JP2022540673A - 動的リフレッシュレート制御 - Google Patents
動的リフレッシュレート制御 Download PDFInfo
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- JP2022540673A JP2022540673A JP2022502424A JP2022502424A JP2022540673A JP 2022540673 A JP2022540673 A JP 2022540673A JP 2022502424 A JP2022502424 A JP 2022502424A JP 2022502424 A JP2022502424 A JP 2022502424A JP 2022540673 A JP2022540673 A JP 2022540673A
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- 230000015654 memory Effects 0.000 claims abstract description 90
- 230000008859 change Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 9
- 238000009529 body temperature measurement Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 6
- 230000006903 response to temperature Effects 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 description 24
- 238000004891 communication Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000004744 fabric Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
Description
Claims (15)
- ダイナミックランダムアクセスメモリ(DRAM)と、
前記DRAMに結合された集積回路であって、
少なくとも1つの温度センサと、
メモリコントローラであって、前記少なくとも1つの温度センサによって感知された温度の変化レートに応じて前記メモリコントローラが前記DRAMをリフレッシュする、リフレッシュレートを判定するように構成されている、メモリコントローラと、を備える、集積回路と、
を備える、システム。 - 前記DRAMは、第1のリフレッシュレートを提供するように構成されており、前記メモリコントローラは、前記変化レートが閾値を超えることに応じて、前記第1のリフレッシュレートを選択するように構成されている、請求項1に記載のシステム。
- 前記DRAMは、第2の温度センサを更に備え、前記DRAMは、前記第2の温度センサによって感知された温度に応じて、前記第1のリフレッシュレートを生成するように構成されている、請求項2に記載のシステム。
- 前記メモリコントローラは、前記変化レートが前記閾値を超えないことに応じて、前記第1のリフレッシュレートよりも低い第2のリフレッシュレートを選択するように構成されている、請求項2又は3のいずれかに記載のシステム。
- 前記第2のリフレッシュレートは、前記少なくとも1つの温度センサによって感知された温度に応じて、前記第1のリフレッシュレートからスケーリングされる、請求項4に記載のシステム。
- 前記集積回路は、前記集積回路内の前記少なくとも1つの温度センサによって感知された温度に応じて、前記集積回路内の温度の前記変化レートを検出するように構成された熱コントローラを備える、請求項1~5のいずれか一項に記載のシステム。
- 前記集積回路内の前記少なくとも1つの温度センサは、複数の温度センサを備え、前記温度は、前記複数の温度センサによって感知された最高温度である、請求項6に記載のシステム。
- 前記DRAMは、前記メモリコントローラに結合された複数のDRAMのうちの1つであり、前記メモリコントローラは、前記複数のDRAMに対して、複数のリフレッシュレートを独立して制御するように構成されている、請求項1~7のいずれか一項に記載のシステム。
- 前記複数のDRAMのうちの所与のDRAMは、前記所与のDRAMに対する第1のリフレッシュレートを生成するように構成されており、前記メモリコントローラは、前記所与のDRAMに対する前記リフレッシュレートに基づいて、前記所与のDRAMをリフレッシュするように構成されている、請求項8に記載のシステム。
- メモリコントローラを含む集積回路内の温度の変化レートを判定することと、
前記温度の前記変化レートに応じて前記メモリコントローラがダイナミックランダムアクセスメモリ(DRAM)をリフレッシュする、リフレッシュレートを判定することと、
を含む、方法。 - 前記リフレッシュレートを判定することは、前記DRAMによって提供される第1のリフレッシュレート、及び前記集積回路内の温度センサによる1つ以上の温度測定値に基づいて判定される第2のリフレッシュレートから、前記リフレッシュレートを選択することを含む、請求項10に記載の方法。
- 前記リフレッシュレートを選択することは、前記変化レートが閾値を超えることに応じて、前記第1のリフレッシュレートを選択することを含む、請求項11に記載の方法。
- 前記リフレッシュレートを選択することは、前記変化レートが前記閾値を超えないことに応じて、前記第2のリフレッシュレートを選択することを含む、請求項11又は12のいずれかに記載の方法。
- 前記1つ以上の温度測定値に応じて前記第2のリフレッシュレートを判定するために、前記第1のリフレッシュレートをスケーリングすることを更に含む、請求項11~13のいずれか一項に記載の方法。
- 前記DRAMは、前記メモリコントローラによって制御される複数のDRAMのうちの1つであり、前記方法は、前記複数のDRAMに対して、前記リフレッシュレートを独立して判定することを更に含む、請求項10~15のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/515,351 | 2019-07-18 | ||
US16/515,351 US10978136B2 (en) | 2019-07-18 | 2019-07-18 | Dynamic refresh rate control |
PCT/US2020/041039 WO2021011236A1 (en) | 2019-07-18 | 2020-07-07 | Dynamic refresh rate control |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2022540673A true JP2022540673A (ja) | 2022-09-16 |
JP7240553B2 JP7240553B2 (ja) | 2023-03-15 |
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JP2022502424A Active JP7240553B2 (ja) | 2019-07-18 | 2020-07-07 | 動的リフレッシュレート制御 |
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US (4) | US10978136B2 (ja) |
JP (1) | JP7240553B2 (ja) |
KR (1) | KR20220019051A (ja) |
CN (1) | CN114127851A (ja) |
DE (1) | DE112020003419T5 (ja) |
TW (1) | TWI743889B (ja) |
WO (1) | WO2021011236A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11049545B2 (en) | 2019-04-23 | 2021-06-29 | Micron Technology, Inc. | Methods for adjusting row hammer refresh rates and related memory devices and systems |
US11031066B2 (en) * | 2019-06-24 | 2021-06-08 | Micron Technology, Inc. | Methods for adjusting memory device refresh operations based on memory device temperature, and related memory devices and systems |
US10978136B2 (en) | 2019-07-18 | 2021-04-13 | Apple Inc. | Dynamic refresh rate control |
US20210200298A1 (en) * | 2019-12-30 | 2021-07-01 | Advanced Micro Devices, Inc. | Long-idle state system and method |
CN114461051B (zh) * | 2021-12-29 | 2023-01-17 | 荣耀终端有限公司 | 帧率切换方法、装置及存储介质 |
Citations (3)
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JPH05501628A (ja) * | 1989-11-18 | 1993-03-25 | イー・オゥ・ヨーロッパ・リミテッド | メモリ装置をリフレッシュする方法 |
JP2015041395A (ja) * | 2013-08-20 | 2015-03-02 | キヤノン株式会社 | 情報処理装置及びその制御方法、並びに、そのプログラムと記憶媒体 |
JP2016048592A (ja) * | 2014-08-27 | 2016-04-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US6438057B1 (en) * | 2001-07-06 | 2002-08-20 | Infineon Technologies Ag | DRAM refresh timing adjustment device, system and method |
KR20050118952A (ko) * | 2004-06-15 | 2005-12-20 | 삼성전자주식회사 | 히스테리리스 특성을 갖는 온도 감지 회로 |
US8122187B2 (en) | 2004-07-02 | 2012-02-21 | Qualcomm Incorporated | Refreshing dynamic volatile memory |
US7214910B2 (en) * | 2004-07-06 | 2007-05-08 | International Business Machines Corporation | On-chip power supply regulator and temperature control system |
KR100564640B1 (ko) | 2005-02-16 | 2006-03-28 | 삼성전자주식회사 | 온도측정기 동작지시신호 발생기 및 이를 구비하는 반도체메모리 장치 |
KR100855578B1 (ko) | 2007-04-30 | 2008-09-01 | 삼성전자주식회사 | 반도체 메모리 소자의 리프레시 주기 제어회로 및 리프레시주기 제어방법 |
JP5501628B2 (ja) | 2009-01-29 | 2014-05-28 | 三菱鉛筆株式会社 | 筆記具用キャップ |
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US9734887B1 (en) * | 2016-03-21 | 2017-08-15 | International Business Machines Corporation | Per-die based memory refresh control based on a master controller |
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US10276228B1 (en) * | 2017-12-22 | 2019-04-30 | Nanya Technology Corporation | DRAM and method of operating the same |
US10978136B2 (en) | 2019-07-18 | 2021-04-13 | Apple Inc. | Dynamic refresh rate control |
-
2019
- 2019-07-18 US US16/515,351 patent/US10978136B2/en active Active
-
2020
- 2020-07-07 WO PCT/US2020/041039 patent/WO2021011236A1/en active Application Filing
- 2020-07-07 KR KR1020227001261A patent/KR20220019051A/ko not_active Application Discontinuation
- 2020-07-07 JP JP2022502424A patent/JP7240553B2/ja active Active
- 2020-07-07 CN CN202080051753.9A patent/CN114127851A/zh active Pending
- 2020-07-07 DE DE112020003419.4T patent/DE112020003419T5/de active Pending
- 2020-07-15 TW TW109123810A patent/TWI743889B/zh active
-
2021
- 2021-02-23 US US17/182,341 patent/US11270753B2/en active Active
-
2022
- 2022-03-04 US US17/687,107 patent/US11823728B2/en active Active
-
2023
- 2023-10-17 US US18/488,656 patent/US20240119991A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05501628A (ja) * | 1989-11-18 | 1993-03-25 | イー・オゥ・ヨーロッパ・リミテッド | メモリ装置をリフレッシュする方法 |
JP2015041395A (ja) * | 2013-08-20 | 2015-03-02 | キヤノン株式会社 | 情報処理装置及びその制御方法、並びに、そのプログラムと記憶媒体 |
JP2016048592A (ja) * | 2014-08-27 | 2016-04-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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TW202105388A (zh) | 2021-02-01 |
US11823728B2 (en) | 2023-11-21 |
US20220254410A1 (en) | 2022-08-11 |
US11270753B2 (en) | 2022-03-08 |
CN114127851A (zh) | 2022-03-01 |
US20210020231A1 (en) | 2021-01-21 |
JP7240553B2 (ja) | 2023-03-15 |
KR20220019051A (ko) | 2022-02-15 |
DE112020003419T5 (de) | 2022-03-31 |
US20210201987A1 (en) | 2021-07-01 |
US20240119991A1 (en) | 2024-04-11 |
US10978136B2 (en) | 2021-04-13 |
TWI743889B (zh) | 2021-10-21 |
WO2021011236A1 (en) | 2021-01-21 |
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