JP2022180409A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the variation in luminance due to fluctuation in value of current flowing in a light-emitting element caused by a change in environment temperature.

SOLUTION: A semiconductor device includes a transistor. The semiconductor device includes a pixel circuit, a monitor circuit, and a correction circuit. The pixel circuit includes a selection transistor, a driving transistor, and a light-emitting element. The monitor circuit includes a monitor light-emitting element and a monitor transistor. The semiconductor device acquires the values of current flowing in the monitor light-emitting element and the monitor transistor. By the correction circuit, the values of current flowing in the light-emitting element and the driving transistor are controlled.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2023,JPO&INPIT

Description

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. A technical field of one embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, the invention relates to a process, machine, manufacture or composition of matter. In particular, one embodiment of the present invention is a semiconductor device, an electroluminescence (Electronic
The present invention relates to a display device having a ro luminescence) element (hereinafter also referred to as an EL display device), a liquid crystal display device, a light-emitting device, a power storage device, a storage device, an imaging device, a driving method thereof, or a manufacturing method thereof.

A technique for forming a transistor (also called a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor materials typified by silicon are widely known as semiconductor thin films that can be applied to transistors, but oxide semiconductors are attracting attention as other materials (for example, Patent Document 1).

Further, a configuration is disclosed in which a monitor circuit is provided in order to correct changes in the characteristics of a transistor and a light-emitting element including an oxide semiconductor provided in each pixel of an EL display device due to ambient temperature (hereinafter referred to as ambient temperature). ing. The monitor circuit is arranged outside the pixel portion and has a configuration in which the potential of the cathode of the light emitting element is corrected according to the environmental temperature (for example, Patent Document 2).

JP 2006-165529 A JP 2012-78798 A

As shown in Patent Document 2, the light emitting element has a property that its resistance value (internal resistance value) changes depending on the environmental temperature. Specifically, when room temperature is normal temperature, the resistance value decreases when the temperature becomes higher than normal, and the resistance value increases when the temperature becomes lower than normal. Therefore, the current-voltage characteristics of the light-emitting element change according to the ambient temperature. Specifically, when the temperature rises, the current value of the light-emitting element increases and the luminance becomes higher than the desired luminance. lower luminance than Therefore, the brightness of the light-emitting element may vary due to fluctuations in the value of the current flowing through the light-emitting element due to changes in the ambient temperature.

In view of the above problem, an object of one embodiment of the present invention is to suppress variations in luminance due to variations in the value of current flowing through a light-emitting element due to changes in environmental temperature. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.

Note that the description of the above problem does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than the above are naturally clarified from the description of the specification, etc., and it is possible to extract problems other than the above from the description of the specification, etc.

One embodiment of the present invention is a semiconductor device including a transistor, the semiconductor device including a pixel circuit, a monitor circuit, and a correction circuit. The pixel circuit includes a selection transistor, a driving transistor, and a light-emitting element. and the monitor circuit has a monitor light emitting element and a monitor transistor, and the semiconductor device acquires a current value flowing through the monitor light emitting element and the monitor transistor, and the correction circuit corrects the light emitting element and the driving transistor. controls the current value flowing through More specifically, it is as follows.

One embodiment of the present invention is a semiconductor device including a transistor, the semiconductor device including a pixel circuit, a monitor circuit, a correction circuit, a first electrode, a second electrode, a third electrode, the pixel circuit has a selection transistor, a driving transistor, and a light-emitting element; the monitor circuit has a monitor light-emitting element and a monitor transistor; the correction circuit includes an amplifier circuit and a switching wherein one of the pair of electrodes of the monitor light emitting element is electrically connected to the first electrode, and the other of the pair of electrodes of the monitor light emitting element is one of the source electrode and the drain electrode of the monitor transistor. The other of the source electrode and the drain electrode of the monitor transistor is electrically connected to the first input terminal of the amplifier circuit, and the gate electrode of the monitor transistor is electrically connected to the output terminal of the amplifier circuit. connected and the second
The electrode of is electrically connected to the second input terminal of the amplifier circuit, the third electrode is electrically connected to the other of the source electrode and the drain electrode of the monitor transistor via the switching element, and the third and the other of the source electrode or the drain electrode of the monitor transistor, a resistor element is connected, and the current flowing through the light emitting element is controlled by a correction circuit.

Further, in the above aspect, it is preferable that the resistance element is provided outside the wiring to which the other of the source electrode and the drain electrode of the monitor transistor and the first input terminal of the amplifier circuit are connected. Further, in the above aspect, it is preferable that the resistive element has an oxide conductor.

Further, in the above aspect, each of the select transistor, the drive transistor, and the monitor transistor preferably has an oxide semiconductor in its channel region.

In the above aspect, the oxide conductor and the oxide semiconductor preferably have at least one same metal element. In the above aspect, one or both of the oxide conductor and the oxide semiconductor may contain In, Zn, and M (M is Ti, Ga, Y, Zr, La
, Ce, Nd, Sn or Hf). Further, in the above aspect, one or both of the oxide conductor and the oxide semiconductor have a crystal part, and the crystal part is c
It is preferable to have axial orientation.

Another embodiment of the present invention is a display device including the semiconductor device according to any one of the above embodiments and a color filter. Another embodiment of the present invention is a display module including the display device and a touch sensor. Another aspect of the present invention is an electronic device including the semiconductor device, the display device, or the display module according to any one of the above aspects, and an operation key or a battery.

According to one embodiment of the present invention, variations in luminance due to variations in current flowing through a light-emitting element due to changes in environmental temperature can be suppressed. Alternatively, one embodiment of the present invention can provide a novel semiconductor device. Alternatively, one embodiment of the present invention can provide a novel display device.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract effects other than these from the descriptions of the specification, drawings, claims, etc. is.

1 is a block diagram illustrating one mode of a semiconductor device; FIG. FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; 1A and 1B are a top view and a cross-sectional view of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; FIG. 10 illustrates a circuit of one embodiment of a semiconductor device; 1A and 1B are a top view and a cross-sectional view of one embodiment of a semiconductor device; 4A and 4B are diagrams for explaining LJ characteristics of a light emitting element and IV characteristics of the light emitting element; 4A and 4B illustrate temperature characteristics of a transistor; FIG. 4 is a diagram for explaining temperature characteristics of resistance of an oxide conductor (OC); 1A and 1B are a top view and a cross-sectional view of one embodiment of a transistor; 1A and 1B are a top view and a cross-sectional view of one embodiment of a transistor; 1A and 1B are a top view and a cross-sectional view of one embodiment of a transistor; 1A and 1B are a top view and a cross-sectional view of one embodiment of a transistor; 1A and 1B are a top view and a cross-sectional view of one embodiment of a transistor; 3A and 3B are cross-sectional views each illustrating one mode of a transistor; 4A and 4B illustrate the band structure of an oxide semiconductor; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 1A and 1B illustrate structural analysis by XRD of a CAAC-OS and a single-crystal oxide semiconductor, and a selected-area electron diffraction pattern of the CAAC-OS; A cross-sectional TEM image of CAAC-OS, a planar TEM image, and its image analysis image. A diagram showing an electron diffraction pattern of an nc-OS and a cross-sectional TEM image of the nc-OS. Cross-sectional TEM image of a-like OS. FIG. 4 is a diagram showing changes in the crystal part of an In--Ga--Zn oxide due to electron irradiation. 1 is a perspective view showing an example of a touch panel; FIG. FIG. 2 is a cross-sectional view showing an example of a display device and a touch sensor; Sectional drawing which shows an example of a touch panel. FIG. 3 is a block diagram and a timing chart of a touch sensor; FIG. Circuit diagram of a touch sensor. 4A and 4B are diagrams for explaining an input/output device; The figure explaining an input device. The figure explaining an input device. 4A and 4B are diagrams for explaining an input/output device; 4A and 4B are diagrams for explaining an input/output device; 1A and 1B are circuit diagrams and timing charts for explaining one embodiment of the present invention; Graphs and circuit diagrams for explaining one embodiment of the present invention. 1A and 1B are circuit diagrams and timing charts for explaining one embodiment of the present invention; 1A and 1B are circuit diagrams and timing charts for explaining one embodiment of the present invention; The figure explaining a display module. 1A and 1B are diagrams for explaining an electronic device; FIG. 4 is a diagram for explaining Ion and Vth of a transistor in an example; 4A and 4B are diagrams for explaining display examples of a semiconductor device in an embodiment; 4A and 4B are diagrams for explaining display examples of a semiconductor device in an embodiment; FIG. 10 is a diagram illustrating a circuit diagram of a semiconductor device in an example; FIG. 10 illustrates power consumption of a semiconductor device in an example. FIG. 3 is a diagram for explaining a circuit configuration according to an example; FIG. 10 is a diagram for explaining luminance-voltage characteristics of a light-emitting element according to an example; FIG. 4 is a diagram for explaining the concept of a correction circuit according to an embodiment; FIG. 10 is a diagram for explaining luminance-gradation characteristics of a light-emitting element according to an example; FIG. 10 is a diagram illustrating a circuit diagram of a semiconductor device in an example; 4A and 4B illustrate the concept of current-voltage characteristics of a light-emitting element and a transistor; FIG. 5 is a diagram for explaining temperature characteristics of luminance of samples B1 and B2;

Hereinafter, embodiments and examples will be described with reference to the drawings. A person skilled in the art will readily recognize, however, that the embodiments and examples can be embodied in many different forms, and that various changes in form and detail can be made therein without departing from the spirit and scope thereof. understood. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples.

Also, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. In addition, in the drawings, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated descriptions thereof will be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In this specification and the like, ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. So, for example, change "first" to "second
It can be explained by appropriately replacing with "of" or "third". Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

In this specification, terms such as "above" and "below" are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

In this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices
may have semiconductor devices.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current flows through the drain, the channel region, and the source. is possible. Note that in this specification and the like, a channel region means a region where current mainly flows.

Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, the terms "source" and "drain" can be used interchangeably in this specification and the like.

Note that in this specification and the like, a silicon oxynitride film has a composition that contains more oxygen than nitrogen, preferably 55 atomic % or more and 65 atomic % or less of oxygen and 1 atom of nitrogen. % or more and 20 atomic % or less, silicon of 25 atomic % or more and 35 atomic % or less, and hydrogen of 0.1 atomic % or more and 20 atomic % or less.
It is contained in a concentration range of 1 atomic % or more and 10 atomic % or less. The silicon oxynitride film has a composition that contains more nitrogen than oxygen, and preferably contains 55 atomic % to 65 atomic % of nitrogen and 1 atomic % to 20 atomic % of oxygen. , silicon is 25
It means that the concentration range of hydrogen is 0.1 atomic % or more and 10 atomic % or less.

In this specification and the like, the terms “film” and “layer” can be used interchangeably. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, the term "insulating film" may be replaced with "insulating layer"
It may be possible to change the term to

In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Also, in this specification and the like, when it is explicitly stated that X and Y are connected,
the case where X and Y are electrically connected, the case where X and Y are functionally connected,
and the case where X and Y are directly connected. Therefore, given connection relations,
For example, it is not limited to the connection relationships shown in the diagrams or text, and includes connections other than those shown in the diagrams or text.

Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.).

An example of the case where X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display elements, light emitting elements, loads, etc.) can be connected between X and Y. Note that the switch has a function of being controlled to be turned on and off. In other words, the switch has a function of controlling whether it is in a conducting state (on state) or a non-conducting state (off state) to allow current to flow. Alternatively, the switch has a function of selecting and switching a path through which current flows.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (eg, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (
Power supply circuit (booster circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier) circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) can be connected between X and Y. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected. do.

Note that when explicitly describing that X and Y are connected, it means that X and Y are electrically connected (that is, another element or another element is connected between X and Y). When X and Y are functionally connected (that is, when X and Y are functionally connected via another circuit) and the case where X and Y are directly connected (that is, the case where X and Y are connected without another element or another circuit between them). In other words, the explicit description of "electrically connected" is the same as the explicit description of "connected".

Note that, for example, the source (or the first terminal, etc.) of the transistor is electrically connected to X via (or not via) Z1, and the drain (or the second terminal, etc.) of the transistor is connected to Z2
is electrically connected to Y through (or not through) or the source of the transistor (
or first terminal, etc.) is directly connected to part of Z1, another part of Z1 is directly connected to X, and the drain (or second terminal, etc.) of the transistor is part of Z2. and another part of Z2 is directly connected to Y, it can be expressed as follows.

For example, "X and Y and source (or first terminal, etc.) and drain (or second
terminals, etc.) are electrically connected to each other, X, the source of the transistor (or the first
terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in that order. ” can be expressed. Or, "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X is the source (or second terminal, etc.) of the transistor. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. Or, "X is the source (or first terminal, etc.) and drain (
or the second terminal, etc.), and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), Y are connected in this connection order. It can be expressed as "provided". By defining the order of connection in the circuit configuration using the same expression method as these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, A technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wiring, electrodes,
terminal, conductive film, etc.).

(Embodiment 1)
In this embodiment, an example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<1-1. About semiconductor devices>
FIG. 1 is a block diagram illustrating an example of a semiconductor device of one embodiment of the present invention.

The semiconductor device shown in FIG. and a correction circuit 30 electrically connected to the monitor circuit 20 . Note that the pixel section 12 has a plurality of pixel circuits 14 .

The semiconductor device shown in FIG. 1 also has a terminal portion 17 and a protection circuit 13 . Note that the terminal portion 17 and the protection circuit 13 may be omitted.

[Pixel portion and pixel circuit]
The pixel portion 12 has circuits (pixel circuits 14) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The drive circuit 16 has a function of outputting a signal (scanning signal) for selecting the pixel circuit 14 , and the signal line drive circuit 18
has a function of supplying a signal (data signal) for driving the display element of the pixel circuit 14 .

Note that FIG. 1 illustrates a configuration in which a plurality of pixel circuits 14 are arranged in a matrix (stripe arrangement), but the present invention is not limited to this, and the pixel circuits 14 may be arranged in a delta arrangement or a pentile arrangement, for example. The color elements controlled by the pixel circuit 14 for color display include three colors of RGB (R for red, G for green, and B for blue). However, the pixel circuit 14
The color elements controlled by are not limited to this, and may be more. For example, RGBW (
W is white), or one or more colors such as Y (yellow), C (cyan), and M (magenta) may be added to RGB. Note that the size of the display area may be different for each dot of the color element.

Further, each of the plurality of pixel circuits 14 has a light emitting element and a driving transistor that controls current flowing through the light emitting element. When a voltage is applied to the light-emitting element, electrons are injected from one of a pair of electrodes of the light-emitting element and holes are injected from the other into the layer containing a light-emitting organic compound, thereby causing a current to flow. Recombination of electrons and holes causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[Gate Line Driver Circuit and Signal Line Driver Circuit]
Either or both of the gate line driving circuit 16 and the signal line driving circuit 18 are included in the pixel section 1.
2 are preferably formed on the same substrate. This makes it possible to reduce the number of components and the number of terminals. If either one or both of the gate line driving circuit 16 and the signal line driving circuit 18 are not formed on the same substrate as the pixel portion 12, either one of the gate line driving circuit 16 and the signal line driving circuit 18 is used. Or both, COG (Chip On Glass)
or TAB (Tape Automated Bonding).

Each of the plurality of pixel circuits 14 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives data through one of the plurality of data lines DL to which the data signal is applied. A signal is input. In each of the plurality of pixel circuits 14 , writing and holding of data of data signals are controlled by the gate line driving circuit 16 . For example, the pixel circuit 14 in the m-th row and the n-th column receives a pulse signal from the gate line driving circuit 16 via the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n is set according to the potential of the scanning line GL_m. A data signal is input from the signal line driving circuit 18 via (n is a natural number equal to or smaller than Y).

The gate line driving circuit 16 has a shift register and the like. The gate line driving circuit 16 receives a signal for driving the shift register via the terminal portion 17 and outputs a signal. For example, the gate line drive circuit 16 receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate line driver circuit 16 has a function of controlling potentials of wirings supplied with scan signals (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate line driver circuits 16 may be provided and the scanning lines GL_<b>1 to GL_X may be divided and controlled by the plurality of gate line driver circuits 16 . Alternatively, the gate line drive circuit 16 has a function of supplying an initialization signal. However, it is not limited to this, and the gate line driving circuit 16 can also supply another signal. For example, as shown in FIG. 1, the gate line driving circuit 16 is electrically connected to wirings (hereinafter referred to as ANODE_1 to ANODE_X) that control the potential of the light emitting elements.

The signal line driving circuit 18 has a shift register and the like. The signal line driving circuit 18 is connected to the terminal section 1
7, a signal for driving the shift register and a signal (image signal) that is the source of the data signal are input. The signal line driving circuit 18 has a function of generating data signals to be written to the pixel circuits 14 based on image signals. The signal line driving circuit 18 also has a function of controlling the output of the data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, and the like. Further, the signal line driver circuit 18 has a function of controlling potentials of wirings supplied with data signals (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the signal line driving circuit 18 has a function of supplying an initialization signal. However, it is not limited to this, and the signal line driving circuit 18 can also supply another signal. For example, the signal line drive circuit 18 is configured using a plurality of analog switches. By sequentially turning on a plurality of analog switches, the signal line driving circuit 18 can output a signal obtained by time-dividing an image signal as a data signal.

[Protection circuit]
The protection circuit 13 is connected to, for example, a scanning line GL which is wiring between the gate line driving circuit 16 and the pixel circuit 14 . Alternatively, the protection circuit 13 is connected to the data line DL, which is wiring between the signal line driving circuit 18 and the pixel circuit 14 . Alternatively, the protection circuit 13 can be connected to wiring between the gate line driving circuit 16 and the terminal section 17 . Alternatively, the protection circuit 13 can be connected to wiring between the signal line driving circuit 18 and the terminal section 17 . The terminal portion 17 has terminals for inputting power, control signals, and image signals from an external circuit to the display device.

The protection circuit 13 has a function of bringing a wiring to which it is connected into electrical continuity with another wiring when a potential outside a certain range is applied to the wiring. By providing the protection circuit 13, the ES
The resistance of the display device to overcurrent generated by D (Electrostatic Discharge) or the like can be increased. A configuration in which the protection circuit 13 is connected to the gate line driving circuit 16 or a configuration in which the protection circuit 13 is connected to the signal line driving circuit 18 may be employed. Alternatively, a configuration in which the protection circuit 13 is connected to the terminal portion 17 may be employed.

[Monitor circuit and correction circuit]
The monitor circuit 20 and the correction circuit 30 have a function of controlling the current flowing through the light emitting element and the driving transistor of the pixel circuit 14 .

Note that FIG. 1 illustrates a configuration in which a plurality of monitor circuits 20 and correction circuits 30 are arranged outside the pixel portion 12;
A configuration in which only one of each 0 is arranged may be used. As shown in FIG. 1, it is preferable to arrange a plurality of monitor circuits 20 and correction circuits 30 outside the pixel section 12 so that a plurality of corrections can be performed within the pixel section 12 . For example, the pixel section 12 is equally divided vertically and horizontally into four areas, and the monitor circuit 20 and the correction circuit 3 in the vicinity of the four divided areas are detected.
0 may be used to independently control the light emitting elements and driving transistors in each divided area.

<1-2. Characteristics of Light Emitting Element>
Next, the characteristics of the light emitting elements included in the pixel circuit 14 will be described below. First, LJ (luminance-current density) characteristics and IV (current-voltage) characteristics, which are one of the characteristics of the light-emitting element, are described with reference to FIGS.

FIG. 11A is a diagram for explaining LJ characteristics of a light emitting element. As shown in FIG. 11A, the luminance of the light-emitting element increases in proportion to the current density. That is, the LJ characteristic of the light emitting element has no or very little change due to environmental temperature (hereinafter sometimes referred to as temperature dependence).

FIG. 11B is a diagram illustrating IV characteristics of a light emitting element. Since the resistance of the light-emitting element changes depending on the temperature, the luminance changes when the temperature changes. For example, FIG.
As shown in (B), when the same voltage is applied, if the temperature of the light-emitting element becomes higher than 25° C., the current flowing through the light-emitting element increases.

Therefore, in the semiconductor device of one embodiment of the present invention, in order to reduce the temperature dependence of the light-emitting element,
It has a monitor circuit 20 and a correction circuit 30 . The monitor circuit 20 has a light emitting element and a transistor having the same functions as the light emitting element and the driving transistor of the pixel circuit 14 . Specifically, the monitor circuit 20 has a monitor light emitting element and a monitor transistor. The correction circuit 30 has a function of controlling the current flowing through the pixel circuit 14 based on the current value data of one or both of the monitor light emitting element and the monitor transistor of the monitor circuit 20 . For example, the correction circuit 30 can control the value of the current flowing through the light emitting element or driving transistor of the pixel circuit 14 .

<1-3. Configuration Example 1 of Monitor Circuit and Correction Circuit>
Next, an example of the monitor circuit 20 and the correction circuit 30 will be described with reference to FIG. FIG. 2 is a circuit diagram illustrating an example of the monitor circuit 20 and the correction circuit 30 included in the semiconductor device of one embodiment of the present invention.

The monitor circuit 20 has a monitor light emitting element 21 and a monitor transistor 22 . Further, the correction circuit 30 has an amplifier circuit 31 and a switching element 32 .

One of the pair of electrodes of the monitor light emitting element 21 is electrically connected to the first electrode (CATHODE), and the other of the pair of electrodes of the monitor light emitting element 21 is connected to one of the source electrode and the drain electrode of the monitor transistor 22. electrically connected. It should be noted that C
ATHODE potential is applied.

The other of the source electrode and the drain electrode of the monitor transistor 22 is electrically connected to the first input terminal of the amplifier circuit 31, and the gate electrode of the monitor transistor 22 is
It is electrically connected to the output terminal of the amplifier circuit 31 . The second electrode (Vnode) is supplied with the ANODE potential and is electrically connected to the second input terminal of the amplifier circuit 31 . A high power supply potential is applied to the third electrode (V2),
The third electrode (V2) is electrically connected to the other of the source electrode and the drain electrode of the monitor transistor 22 via the switching element 32. A resistance element 50 is connected between the third electrode (V2) and the other of the source electrode and the drain electrode of the monitor transistor 22. FIG.

For example, in the configuration of the monitor circuit 20 and the correction circuit 30 shown in FIG. be done.

(V2-Vanode)/R (1)

In equation (1), V2-Vanode is the potential (Vgs) between the gate electrode and the source electrode of the monitor transistor 22 required to flow the current value i, and R is the resistance value of the resistance element 50. be.

Therefore, it is preferable that the resistance element 50 has no temperature dependence and a constant resistance value. For example, the resistance element 50 may be an oxide conductor (OC).
is preferably used. For example, an oxide conductor (OC) is an oxide semiconductor (OS: Oxi
It is obtained by increasing the carrier density of a de Semiconductor) to make it n-type.

Oxide conductors (OC) have little or no change in resistance with ambient temperature. That is, it can be used as a resistance material with low temperature dependence. However, the resistance element 50 is not limited to the oxide conductor (OC), and other resistance materials with low temperature dependence may be used.

In addition, the monitor transistor 22 preferably has an oxide semiconductor (OS) in its active layer. The oxide conductor (OC) and the oxide semiconductor (OS) can be manufactured in the same manufacturing process. Note that when an oxide semiconductor (OS) is applied to the monitor transistor 22 , the characteristics may change depending on the ambient temperature, as in the case of the monitor light emitting element 21 . for example,
As the ambient temperature rises, the potential difference (Vds) between the drain electrode and the source electrode of the monitor transistor 22 having an oxide semiconductor (OS) may increase.

In the monitor circuit 20 shown in FIG. 2, the configuration using an n-channel transistor as the monitor transistor 22 is illustrated, but the configuration is not limited to this, and may be, for example, the configuration shown in FIG. FIG. 3 is a circuit diagram illustrating an example of a monitor circuit and a correction circuit. FIG. 3 shows a circuit in which the monitor transistor 22 shown in FIG. 2 is of p-channel type and the polarity of the amplifier circuit 31 is changed.

Alternatively, the resistive element 50 may be provided on the first electrode (CATHODE) side of the monitor light emitting element 21 . An example of the configuration is shown in FIG. The circuit shown in FIG. 4 is the monitor circuit 2
0B and a correction circuit 30B. In the case of the configuration shown in FIG. 4, the current value i flowing through the monitor light emitting element 21 is represented by the following formula (2).

(V2-CATHODE)/R (2)

In addition, a so-called reverse stacking configuration, in which the stacking order of the monitor light emitting elements 21 is changed, may be employed. An example of the configuration is shown in FIG. The circuit shown in FIG. 5 includes a monitor circuit 20C and a correction circuit 30C.
and have

Further, in the above description, a configuration in which a monitor circuit is used to perform temperature correction on a light emitting element is exemplified, but the present invention is not limited to this. Values may be monitored and temperature corrected.

<1-4. Temperature Characteristics of Transistor Including Oxide Semiconductor>
Here, temperature dependence of a transistor including an oxide semiconductor (OS) will be described below with reference to FIGS.

FIG. 12 shows the results of evaluating the temperature dependence of a bottom-gate-top-contact (BGTC), so-called channel-etch type transistor. An oxide semiconductor was used for an active layer of the transistor. Note that there are two conditions for the oxide semiconductor, and the first condition is
IGZO film (In:Ga:Zn=4:2:4.1 [atomic ratio]) and IGZO film (In:
Ga: Zn = 1: 1: 1.2 [atomic ratio]), and the second condition is
A single-layer structure of an IGZO film (In:Ga:Zn=1:1:1.2 [atomic ratio]) was used. As for the size of the transistor, the channel length L was set to 3 μm, and the channel width W was set to 5 μm.

In addition, the substrate temperature was set to 25° C., 40° C., and 60° C. to evaluate the temperature dependence of the transistor.
, and 80° C., and the on-current (Ion) of the transistor was measured. Note that the drain voltage (Vd) was set to 20V, and the gate voltage (Vg) was set to 15V.

As shown in FIG. 12, regardless of the conditions of the oxide semiconductor, Ion of the transistor increased as the substrate temperature increased. That is, a transistor including an oxide semiconductor has temperature dependence.

<1-5. Temperature Dependence of Oxide Conductor>
Next, temperature dependence of the oxide conductor (OC) will be described with reference to FIG.

FIG. 13 is a diagram for explaining the temperature dependence of the resistance of an oxide conductor (OC). Note that as the oxide conductor (OC), an oxide semiconductor film is formed and a silicon nitride film containing hydrogen is formed over the oxide semiconductor film; It was formed by supplying hydrogen. Note that there are two conditions for the oxide semiconductor film, and the first condition is an IGZO film (In:Ga:Zn=4:2:4.1 [atomic ratio]) Ga: Zn = 1: 1: 1.2 [atomic ratio]), and the second condition is an IGZO film (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]).

In addition, as an evaluation of the temperature dependence of the oxide conductor (OC), the substrate temperature was set to 25°C and 40°C.
, 60° C., and 80° C., and the sheet resistance of the oxide conductor (OC) was measured. note that,
The size of the oxide conductor (OC) was W/L=10 μm/1500 μm.

As shown in FIG. 13, regardless of the conditions of the oxide semiconductor, the sheet resistance of the oxide conductor (OC) does not change or changes very little even when the substrate temperature changes. Thus, it can be seen that the oxide conductor (OC) has no temperature dependence of resistance or extremely small temperature dependence of resistance. In other words, the oxide conductor is a degenerate semiconductor, and the bottom of the conduction band and the Fermi level match or substantially match.

Therefore, the oxide conductor can be suitably used as the resistance element of the correction circuit 30 .

<1-6. Configuration Example 2 of Monitor Circuit and Correction Circuit>
Next, a configuration example different from the monitor circuit 20 and the correction circuit 30 shown in FIG. 2 will be described with reference to FIG.

FIG. 6 is a circuit diagram illustrating an example of a semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 6 has a monitor circuit 20A and a correction circuit 30A.

[Monitor circuit]
The monitor circuit 20A has a monitor light emitting element 21, a monitor transistor 22A, a resistance element 23, a terminal 24, a terminal 25, a terminal 26, and a terminal 27.

As shown in the monitor circuit 20A, by providing a plurality of terminals and changing connection destinations of the terminals, the element characteristics of the monitor light emitting element 21, the monitor transistor 22A, and the resistor element 23 can be measured.

Note that the resistance element 23 can be configured using the oxide conductor (OC) described above. Therefore, in FIG. 6, the resistive element 23 is given the symbol OC. The same applies to subsequent drawings.

The terminal 24 is electrically connected to the gate electrode of the monitor transistor 22A, and the potential of the gate electrode of the monitor transistor 22A can be extracted to the outside. Also, the terminal 25 is electrically connected to the source electrode of the monitor transistor 22A, and the potential of the source electrode of the monitor transistor 22A can be extracted to the outside. Also, terminal 2
6 is electrically connected to the drain electrode of the monitor transistor 22A, and the potential of the drain electrode of the monitor transistor 22A can be extracted to the outside. Also, terminal 2
7 is electrically connected to the other of the pair of electrodes of the monitor light emitting element 21 via the resistance element 23 and the monitor transistor 22A.
For example, the potential of the anode) can be taken out to the outside. Note that the monitor light emitting element 21
A first electrode (CATHODE) is electrically connected to one of the pair of electrodes.

Note that the monitor transistor 22A has a configuration having a plurality of gate electrodes, unlike the monitor transistor 22 described above. Specifically, the monitor transistor 22A is
It has a first gate electrode and a second gate electrode facing the first gate electrode. Also, the second gate electrode is electrically connected to the source electrode of the monitor transistor 22A. The connection destination of the second gate electrode is not limited to this, and may be electrically connected to, for example, the first gate electrode of the monitor transistor 22A or another electrode.
Note that the other electrode includes, for example, an electrode to which a ground (GND) potential is applied, an electrode to which another potential is applied, and the like. Alternatively, the second gate electrode of monitor transistor 22A may be floating.

As shown in the monitor transistor 22A, by adopting a transistor structure having a plurality of gate electrodes, it is possible, for example, to improve the drive capability of the monitor transistor 22A or to control the threshold voltage (Vth) of the monitor transistor 22A. It becomes possible.

Also, the resistance element 23 can have, for example, the configuration shown in FIG.

FIG. 7A is a top view of the semiconductor device 950, and FIG. 7B corresponds to a cross-sectional view taken along the dashed-dotted line MN in FIG. 7A.

A semiconductor device 950 includes a conductive film 904 a over a substrate 902 and a conductive film 904 over the substrate 902 .
b, an insulating film 906 covering the substrate 902 and the conductive films 904a and 904b, an insulating film 907 over the insulating film 906, an oxide conductive film 909 over the insulating film 907, and openings provided in the insulating films 906 and 907. A conductive film 912d connected to the conductive film 904a through a portion 944a; a conductive film 912e connected to the conductive film 904b through openings 944b provided in the insulating films 906 and 907; It has a conductive film 909 and an insulating film 918 which covers the conductive films 912d and 912e.

For example, an oxide semiconductor is used for the oxide conductive film 909 and an insulating film containing hydrogen is used for the insulating film 918 . With such a structure, hydrogen contained in the insulating film 918 enters the oxide semiconductor film, and the carrier density of the oxide semiconductor film is increased, so that the oxide semiconductor film can function as an oxide conductive film.

[Correction circuit]
The correction circuit 30A has an amplifier circuit 31, a switching element 32, a converter circuit 61, and a memory circuit 62.

Note that the memory circuit 62 is electrically connected to the output terminal of the amplifier circuit 31 via the converter circuit 61 . For example, the output signal of the amplifier circuit 31 may be converted from an analog signal to a digital signal using the converter circuit 61 and stored in the memory circuit 62 .

As shown in FIG. 6, circuits having functions different from those of the amplifier circuit 31 and the switching element 32 (here, the converter circuit 61 and the memory circuit 62) may be provided in the correction circuit 30A.

Also, the monitor circuit 20A and the correction circuit 30A shown in FIG. 6 are connected as follows. The terminal 24 and the output terminal of the amplifier circuit 31 are electrically connected, and the terminal 26 and one electrode of the switching element 32 and the first input terminal of the amplifier circuit 31 are electrically connected.

In the configuration shown in FIG. 6, the terminals 25 and 27 are not electrically connected from the correction circuit 30A. In this manner, the correction circuit 30A may be electrically connected to any one of the monitor light emitting element 21, the monitor transistor 22A, and the resistance element 23 included in the monitor circuit 20A.

<1-7. Configuration Example 3 of Monitor Circuit and Correction Circuit>
Next, FIG. 8 shows a configuration example different from the monitor circuit 20 and the correction circuit 30 shown in FIG.
will be used to explain.

FIG. 8 is a circuit diagram illustrating an example of a semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 8 has a monitor circuit 20A and a correction circuit 30A. The semiconductor device shown in FIG. 8 differs from the semiconductor device shown in FIG. 6 in the method of connecting the monitor circuit 20A and the correction circuit 30A.

Specifically, the monitor circuit 20A and the correction circuit 30A shown in FIG. 8 are connected as follows. The terminal 24 and the output terminal of the amplifier circuit 31 are electrically connected, the terminal 26 and the first input terminal of the amplifier circuit 31 are electrically connected, and the terminal 27 and one electrode of the switching element 32 are electrically connected. connected

In the configuration shown in FIG. 8, the resistance element 23 included in the monitor circuit 20A can be used, so the resistance element 50 shown in FIG. 6 can be omitted.

<1-8. Configuration Example 1 of Pixel Circuit>
Next, a specific configuration of the pixel circuit 14 shown in FIG. 1 will be described using FIG. Figure 9
2 is a circuit diagram showing an example of a pixel circuit 14. FIG.

The pixel circuit 14 illustrated in FIG. 9 includes transistors 552 and 554, a capacitor 562, and a light emitting element 572. The pixel circuit 14 illustrated in FIG. Either or both of the transistor 552 and the transistor 554 can be a transistor including an oxide semiconductor.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to the data line DL_Y. Further, a gate electrode of the transistor 552 is electrically connected to the scan line GL_X.

The transistor 552 has a function of controlling data writing of the data signal by turning on or off.

One of the pair of electrodes of the capacitor 562 is electrically connected to the other of the source and drain electrodes of the transistor 552 . The other of the pair of electrodes of the capacitor 562 is electrically connected to a second gate electrode (also referred to as a back gate electrode) of the transistor 554 .
The capacitor 562 functions as a storage capacitor that retains written data.

One of the source and drain electrodes of transistor 554 is connected to the anode line (ANODE
_X).

One of the anode and cathode of the light emitting element 572 is electrically connected to the other of the source and drain electrodes of the transistor 554, and the other is electrically connected to the cathode line (CATHODE). Note that one of the anode and the cathode of the light emitting element 572 is electrically connected to the other of the pair of electrodes of the capacitor 562 .

As the light emitting element 572, for example, an organic EL element can be used. However, the light-emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

For example, in the circuit configuration shown in FIG. 9, the pixel circuits 14 in each row are sequentially selected by the gate line driver circuit 16 shown in FIG. 1, the transistor 552 is turned on, and the data of the data signal is written.

The pixel circuit 14 to which data is written enters a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

Note that the potential of the cathode of the light emitting element 572 is appropriately adjusted to an arbitrary value by the monitor circuit and correction circuit described above.

Note that although the structure in which the light-emitting element 572 is included as a display element of the display device is described in this embodiment mode, the present invention is not limited to this, and the display device may include various elements. Examples of such elements include electroluminescence (EL) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistors (transistors that emit light in response to current), electron-emitting elements, Liquid crystal devices, electronic ink devices, electrophoretic devices, electrowetting devices, plasma displays (PDP), MEMS (micro-electro-mechanical system) displays (e.g. grating light valves (GLV), digital micromirror devices (DMD) , Digital Micro Shutter (DMS) element, Interference Modulation (IMOD)
devices), piezoelectric ceramic displays, etc., which have display media whose contrast, brightness, reflectance, transmittance, etc., change due to electrical or magnetic action. An example of a display device using an EL element is an EL display. Examples of display devices using electron-emitting devices include a field emission display (FED) or an SED flat panel display (SED: Surface-conduction Electro
n-emitter Display) and the like. Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays).
An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. In addition, when realizing a transflective liquid crystal display or a reflective liquid crystal display,
Part or all of the pixel electrode may function as a reflective electrode. For example, part or all of the pixel electrode may comprise aluminum, silver, or the like. Furthermore, in that case, it is also possible to provide a storage circuit such as an SRAM under the reflective electrode. Thereby, power consumption can be further reduced.

Further, as a display method of the display device, a progressive method, an interlace method, or the like can be used. RGB (
R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pentile array, one color element may be composed of two colors of RGB, and two different colors may be selected according to the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device and can also be applied to a monochrome display device.

In addition, backlights (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.)
may be provided with white light (W). Further, a colored layer (also referred to as a color filter) is added to the display device.
may be provided. As the colored layer, for example, red (R), green (G), blue (B
), yellow (Y), etc. can be used in appropriate combination. By using the colored layer, color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, by arranging a region having a colored layer and a region having no colored layer, the white light in the region having no colored layer may be directly used for display. By arranging a region that does not have a colored layer in part, it is possible to reduce the decrease in luminance due to the colored layer during bright display, and reduce power consumption by 2.
In some cases, it can be reduced by about 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having the respective emission colors. . By using a self-luminous element, power consumption can be further reduced in some cases as compared to the case where a colored layer is used.

<1-9. Configuration Example 2 of Pixel Circuit>
Next, a specific configuration of the pixel circuit 14 shown in FIG. 9 will be described using FIG. FIG. 10A is a top view of the pixel circuit 14, and FIG. 10B corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 shown in FIG. 10A. In addition, in FIG. 10A, some of the constituent elements are omitted in order to avoid complication of the drawing.

The pixel circuit 14 shown in FIGS. 10A and 10B includes a conductive film 704 functioning as a first gate electrode over a substrate 702 , insulating films 706 and 707 over the conductive film 704 , and an oxide film over the insulating film 707 . A semiconductor film 708, an insulating film 707, conductive films 712a and 712b functioning as source and drain electrodes over the oxide semiconductor film 708, and a conductive film 712 over the insulating film 707.
and an insulating film 714 covering the oxide semiconductor film 708 and the conductive films 712a, 712b, and 712c.
, 716 , an oxide semiconductor film 720 functioning as a second gate electrode over the insulating film 716 , an insulating film 718 over the insulating films 716 and 720 , and a planarization insulating film over the insulating film 718 . An insulating film 722 that functions, conductive films 724a and 724b that function as pixel electrodes over the insulating film 722, a structure 726 that has a function of suppressing electrical connection between the conductive films 724a and 724b, and a conductive film. EL layer 72 on 724a, 724b and structure 726
8 and a conductive film 730 over the EL layer 728 .

In addition, the conductive film 712 c is electrically connected to the conductive film 704 through openings 752 c provided in the insulating films 706 and 707 . In addition, the oxide semiconductor film 720 functioning as a second gate electrode is connected to the conductive film 712 through the openings 752 a provided in the insulating films 714 and 716 .
b is electrically connected. In addition, the conductive film 724a is formed between the insulating films 714, 716, 718, and 7.
22 is electrically connected to the conductive film 712b through the opening 752b.

In addition, a conductive film 724a functioning as a pixel electrode, an EL layer 728, a conductive film 730,
, a light emitting element 572 is formed. Note that the EL layer 728 can be formed by a sputtering method, a vapor deposition method (including a vacuum vapor deposition method), a printing method (e.g., relief printing method, intaglio printing method, gravure printing method,
lithographic printing method, stencil printing method, etc.), an inkjet method, a coating method, or the like.

As shown in FIGS. 10A and 10B, the pixel circuit 14 includes two transistors and one transistor.
With a structure including one capacitor, the number of wirings can be reduced. for example,
As shown in FIG. 10A, the wirings included in the pixel circuit 14 can be mainly three lines, ie, a gate line, a scanning line, and an anode line. With such a structure, the aperture ratio of the pixel can be increased. In addition, by reducing the number of wirings, a short circuit or the like is less likely to occur between adjacent wirings, so that a semiconductor device with high display quality can be provided.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments, examples, or reference examples.

(Embodiment 2)
In this embodiment, a transistor included in a semiconductor device of one embodiment of the present invention and a method for manufacturing the transistor will be described with reference to FIGS.

<2-1. Configuration Example 1 of Transistor>
14A is a top view of a transistor 100 included in a semiconductor device of one embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 14A. FIG. 14C corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 14A. Note that in FIG. 14A, some components of the transistor 100 (an insulating film functioning as a gate insulating film and the like) are omitted in order to avoid complication. Also, the direction of the dashed line X1-X2 may be referred to as the channel length direction, and the direction of the dashed line Y1-Y2 may be referred to as the channel width direction. Note that in the top views of the transistors, some of the components are omitted in some cases in the following drawings, as in FIG. 14A.

The transistor 100 includes a conductive film 104 functioning as a gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide semiconductor film over the insulating film 107. 108 , a conductive film 112 a functioning as a source electrode electrically connected to the oxide semiconductor film 108 , and a conductive film 112 b functioning as a drain electrode electrically connected to the oxide semiconductor film 108 . Also, on the transistor 100,
More specifically, the insulating film 114 is formed over the conductive films 112 a and 112 b and the oxide semiconductor film 108 .
, 116 and an insulating film 118 are provided. The insulating films 114 , 116 , and 118 function as protective insulating films of the transistor 100 .

When an impurity such as hydrogen or moisture enters the oxide semiconductor film 108, it is combined with oxygen vacancies that may be formed in the oxide semiconductor film 108 to generate electrons as carriers. When carriers are generated due to impurities as described above, the transistor 100 tends to have normally-on characteristics. Therefore, impurities such as hydrogen and moisture in the oxide semiconductor film 108 should be reduced, and the oxide semiconductor film 1
Reducing oxygen vacancies in 08 is also important for obtaining stable transistor characteristics. Therefore, in the transistor 100, from the insulating films 114 and 116 to the oxide semiconductor film 108
Oxygen deficiency in the film is compensated by supplying oxygen to the inside.

Therefore, the insulating films 114 and 116 are regions containing oxygen in excess of the stoichiometric composition (
oxygen excess region). In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. In order to provide the oxygen-excess regions in the insulating films 114 and 116, for example, oxygen is added to the insulating films 114 and 116 after film formation to form the oxygen-excess regions. As a method for adding oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used. Note that as the plasma treatment, it is preferable to use an apparatus (also referred to as a plasma etching apparatus or a plasma ashing apparatus) that turns oxygen gas into plasma with high-frequency power.

In addition, thermal desorption spectrometry (TDS)
By measuring the insulating film using ctroscopy), the amount of released oxygen can be measured. For example, when the insulating films 114 and 116 are measured by thermal desorption spectrometry,
The amount of released oxygen molecules is 8.0×10 ¹⁴ /cm ² or more, preferably 1.0×10 ¹⁵ /cm 2
cm ² or more, more preferably 1.5×10 ¹⁵ /cm ² or more. The surface temperature of the film in thermal desorption spectrometry is 100° C. or higher and 700° C. or lower, preferably 100° C. or higher and 500° C. or lower.

<2-2. Components of Semiconductor Device>
Next, components included in the semiconductor device of this embodiment will be described.

[substrate]
There are no particular restrictions on the material of the substrate 102, but it must have at least heat resistance to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102 . Alternatively, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like made of silicon, silicon carbide, or the like can be used, and a semiconductor element is provided over any of these substrates. The substrate 102 may be used as the substrate 102 . In addition, when using a glass substrate as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2
200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2
800 mm), 10th generation (2950 mm×3400 mm), etc., a large display device can be manufactured.

Further, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate.
0 may be formed. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100 . The release layer can be used to separate from the substrate 102 and transfer to another substrate after partially or wholly completing a semiconductor device thereon. At that time, the transistor 100 can be transferred to a substrate having poor heat resistance or a flexible substrate.

[Conductive film]
As the conductive film 104 functioning as a gate electrode and the conductive films 112a and 112b functioning as source and drain electrodes, chromium (Cr), copper (Cu), aluminum (
Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta
), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (
Fe), cobalt (Co), an alloy containing the above-described metal elements as a component, or an alloy in which the above-described metal elements are combined.

Further, the conductive films 104, 112a, and 112b may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, and a two-layer structure in which a tungsten film is stacked over a titanium nitride film. a layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is laminated, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, and the like. be. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide are used for the conductive films 104, 112a, and 112b. , indium zinc oxide, indium tin oxide containing silicon oxide, or the like can also be used.

Further, the conductive films 104, 112a, and 112b are Cu—X alloy films (X is Mn, Ni,
Cr, Fe, Co, Mo, Ta, or Ti) may be applied. By using a Cu—X alloy film, processing can be performed by a wet etching process, so that manufacturing costs can be suppressed.

[Gate insulating film]
The insulating films 106 and 107 functioning as gate insulating films of the transistor 100 are formed by plasma enhanced chemical vapor deposition (PECVD).
l Vapor Deposition) method, sputtering method, etc., to form a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, An insulating layer containing one or more of a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. Note that the insulating films 106 and 107
A single-layer insulating film or three or more layers of insulating films selected from the above materials may be used instead of the stacked structure.

Note that the insulating film 107 in contact with the oxide semiconductor film 108 of the transistor 100 is preferably an oxide insulating film and may include a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region). more preferred. In other words, the insulating film 107 is an insulating film capable of releasing oxygen. Note that in order to provide the oxygen-excess region in the insulating film 107, the insulating film 107 may be formed in an oxygen atmosphere, for example. Alternatively, an oxygen-excess region may be formed by introducing oxygen into the insulating film 107 after deposition. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

Further, when hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. therefore,
Since the film thickness of the insulating film 107 can be increased as compared with the case of using silicon oxide, leak current due to tunnel current can be reduced. That is, a transistor with low off-state current can be realized. Furthermore, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, hafnium oxide having a crystalline structure is preferably used for a transistor with low off-state current. Examples of crystal structures include monoclinic and cubic systems. However, one embodiment of the present invention is not limited to these.

Note that in this embodiment mode, a silicon nitride film is formed as the insulating film 106 and the insulating film 107 is formed.
A silicon oxide film is formed as a film. A silicon nitride film has a higher relative dielectric constant than a silicon oxide film, and a large film thickness is required to obtain a capacitance equivalent to that of a silicon oxide film. By including the insulating film, the thickness of the insulating film can be increased physically. Therefore, a decrease in the dielectric strength voltage of the transistor 100 can be suppressed, and furthermore, the dielectric strength voltage can be improved, and electrostatic breakdown of the transistor 100 can be suppressed.

[Oxide semiconductor film]
The oxide semiconductor film 108 contains In, Zn, and M (M is Ti, Ga, Y, Zr, La,
Ce, Nd, Sn or Hf). Typically, the oxide semiconductor film 108 is composed of I
n-Ga oxide, In--Zn oxide, and In--M--Zn oxide can be used. In--M--Zn oxide is preferably used for the oxide semiconductor film 108 in particular.

When the oxide semiconductor film 108 is an In--M--Zn oxide, the atomic ratio of metal elements in a sputtering target used for forming the In--M--Zn oxide is In≧M and Zn≧M.
is preferably satisfied. The atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn
=2:1:3, In:M:Zn=3:1:2, and In:M:Zn=4:2:4.1.

For example, when forming the oxide semiconductor film 108 using a sputtering target of In:Ga:Zn=4:2:4.1 [atomic ratio] as an In-M-Zn oxide, the field effect of the transistor It is preferable because it can increase the mobility. By increasing the field effect mobility of the transistor, for example, 4K×2K (the number of pixels in the horizontal direction=3840 pixels, the number of pixels in the vertical direction=
2160 pixels) or 8K x 4K (horizontal direction pixels = 7680 pixels, vertical direction pixels = 4
It can be suitably used as a pixel circuit of a high-definition display device typified by 320 pixels) or a transistor of a driver circuit.

Further, the atomic ratio of the oxide semiconductor film 108 to be formed may vary by plus or minus 40% of the atomic ratio of the metal elements contained in the respective sputtering targets.
For example, a sputtering target having an atomic ratio of In:Ga:Zn=4:2:4.
When 1 is used, the atomic ratio of the oxide semiconductor film 108 to be formed is In:Ga:Zn=4.
: 2:3 in some cases. Also, as a sputtering target, the atomic ratio is I
When n:Ga:Zn=1:1:1.2 is used, the atomic ratio of the oxide semiconductor film 108 to be formed is close to In:Ga:Zn=1:1:1 in some cases.

Note that when the oxide semiconductor film 108 is an In--M--Zn oxide film, the atomic ratio of In and M, excluding Zn and O, is preferably higher than 25 atomic % for In and 75 atomic % for M.
less than atomic %, more preferably more than 34 atomic % of In and 66a of M
less than tomic %.

Further, the oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV.
eV or more, more preferably 3 eV or more. By using an oxide semiconductor with a wide energy gap in this manner, off-state current of the transistor 100 can be reduced.

Further, the thickness of the oxide semiconductor film 108 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably 3 nm.
100 nm or less, more preferably 3 nm or more and 50 nm or less.

Note that the material is not limited to these, and a material having an appropriate composition may be used according to required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In addition, the carrier density, the impurity concentration, the defect density, the atomic ratio of the metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor film 108 are set appropriately in order to obtain required semiconductor characteristics of the transistor. is preferred.

Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). Further, since a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low defect level density, the trap level density may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off current, and even an element with a channel width of 1×10 ⁶ μm and a channel length L of 10 μm can be used as a source electrode. When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, the off current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ^-13 A.
You can get the following properties:

Therefore, a transistor in which a channel region is formed in the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have small variations in electrical characteristics and can have high reliability. Note that the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear and may behave like a fixed charge. for that reason,
A transistor whose channel region is formed in an oxide semiconductor film with a high trap level density might have unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like.

Hydrogen contained in the oxide semiconductor film 108 reacts with oxygen that bonds to a metal atom to form water, and oxygen vacancies are formed in lattices from which oxygen is released (or portions from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier.
Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to have normally-on characteristics. Therefore, hydrogen in the oxide semiconductor film 108 is preferably reduced as much as possible. Specifically, in the oxide semiconductor film 108, SIMS (Secondary
The hydrogen concentration obtained by y Ion Mass Spectrometry) analysis is
×10 ²⁰ atoms/cm ³ or less, preferably 5 × 10 ¹⁹ atoms/cm ³ or less,
More preferably 1×10 ¹⁹ atoms/cm ³ or less, 5×10 ¹⁸ atoms/cm ³
below, preferably 1×10 ¹⁸ atoms/cm ³ or less, more preferably 5×10 ¹⁷ a
toms/cm ³ or less, more preferably 1×10 ¹⁶ atoms/cm ³ or less.

When the oxide semiconductor film 108 contains silicon or carbon, which is one of Group 14 elements, oxygen vacancies increase in the oxide semiconductor film 108 and the oxide semiconductor film 108 becomes n-type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 108 and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor film 108 (concentration obtained by SIMS analysis) are 2×10 ¹⁸ atom.
ms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

Further, in the oxide semiconductor film 108, the concentration of the alkali metal or alkaline earth metal obtained by SIMS analysis is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×1.
0 ¹⁶ atoms/cm ³ or less. Alkali metals and alkaline earth metals may generate carriers when bonded to an oxide semiconductor, which might increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor film 108 is preferably reduced.

Further, when the oxide semiconductor film 108 contains nitrogen, electrons as carriers are generated, the carrier density increases, and the oxide semiconductor film 108 tends to be n-type. As a result, a transistor including an oxide semiconductor film containing nitrogen tends to have normally-on characteristics. Therefore, nitrogen content in the oxide semiconductor film is preferably reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is preferably 5×10 ¹⁸ atoms/cm ³ or less.

For the structure and the like of an oxide semiconductor that can be used for the oxide semiconductor film 108,
A detailed description will be given in a third embodiment.

[Protective insulating film]
The insulating films 114, 116, and 118 function as protective insulating films. insulating film 114,
116 contains oxygen and insulating film 118 contains nitrogen. Further, the insulating film 114 is an insulating film through which oxygen can pass. Note that the insulating film 114 also functions as a film for relieving damage to the oxide semiconductor film 108 when the insulating film 116 is formed later.

The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm.
Sub-nm silicon oxide or silicon oxynitride can be used.

In addition, the insulating film 114 preferably has a small amount of defects.
ctron Spin Resonance) measurement, the spin density of the signal appearing at g=2.001 originating from the dangling bond of silicon is 3×10 ¹⁷ spins/cm.
It is preferably ³ or less. This is because, if the density of defects contained in the insulating film 114 is high, oxygen is bound to the defects, and the amount of oxygen passing through the insulating film 114 is reduced.

In addition, in the insulating film 114 , all of the oxygen entering the insulating film 114 from the outside
Some oxygen remains in the insulating film 114 without moving to the outside of 4 . Further, when oxygen enters the insulating film 114 and oxygen contained in the insulating film 114 moves to the outside of the insulating film 114 , oxygen may move in the insulating film 114 . When an oxide insulating film through which oxygen can pass is formed as the insulating film 114 , oxygen released from the insulating film 116 provided over the insulating film 114 is allowed to pass through the insulating film 114 and reach the oxide semiconductor film 108 . can be moved.

Further, the insulating film 114 can be formed using an oxide insulating film with a low level density due to nitrogen oxide. Note that the level density due to the nitrogen oxide can be formed between the energy (Ev_os) at the top of the valence band of the oxide semiconductor film and the energy (Ec_os) at the bottom of the conduction band of the oxide semiconductor film. Sometimes. As the oxide insulating film, a silicon oxynitride film which releases a small amount of nitrogen oxides, an aluminum oxynitride film which releases a small amount of nitrogen oxides, or the like can be used.

Note that a silicon oxynitride film that releases a small amount of nitrogen oxides is a film that releases a larger amount of ammonia than the amount of nitrogen oxides released in the temperature-programmed desorption spectrometry method. is 1×10 ¹⁸ pieces/cm ³ or more and 5×10 ¹⁹ pieces/cm ³ or less. The amount of ammonia released is determined when the surface temperature of the film is 50° C. or higher and 650° C. or lower, preferably 50° C. or higher and 55° C. or lower.
It is the amount released by heat treatment at 0°C or lower.

Nitrogen oxides (NO _x , where x is more than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO, form levels in the insulating film 114 and the like. The level is located within the energy gap of the oxide semiconductor film 108 . Therefore, when nitrogen oxide diffuses near the interface between the insulating film 114 and the oxide semiconductor film 108 , the level traps electrons on the insulating film 114 side in some cases. As a result, the trapped electrons stay near the interface between the insulating film 114 and the oxide semiconductor film 108, which shifts the threshold voltage of the transistor in the positive direction.

Nitrogen oxides also react with ammonia and oxygen during heat treatment. Insulating film 114
nitrogen oxides contained in the insulating film 114 react with ammonia contained in the insulating film 116 in the heat treatment, so nitrogen oxides contained in the insulating film 114 are reduced. Therefore, electrons are less likely to be trapped near the interface between the insulating film 114 and the oxide semiconductor film 108 .

By using the above oxide insulating film as the insulating film 114, a shift in the threshold voltage of the transistor can be reduced, and a change in electrical characteristics of the transistor can be reduced.

Note that the insulating film 114 has a g value of 2.037 in a spectrum measured with an ESR of 100 K or less by heat treatment in a manufacturing process of a transistor, typically heat treatment at 300° C. or more and less than the substrate strain point. A first signal with a g value of 2.039 or more, a second signal with a g value of 2.001 or more and 2.003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less are observed. The split width between the first signal and the second signal and the split width between the second signal and the third signal are about 5 mT in X-band ESR measurement. In addition, the first signal with a g value of 2.037 or more and 2.039 or less, a g value of 2
. The sum of the spin densities of the second signal of 001 or more and 2.003 or less and the third signal of which the g value is 1.964 or more and 1.966 or less is less than 1 × 10 ¹⁸ spins/cm ³ , representative is 1×10 ¹⁷ spins/cm ³ or more and less than 1×10 ¹⁸ spins/cm ³ .

In the ESR spectrum at 100 K or less, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the g value of 1
. The third signal of 964 or more and 1.966 or less corresponds to a signal due to nitrogen oxides (NO _x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Representative examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, and a g value of 1.964 or more and 1.966 or less It can be said that the smaller the total spin density of the third signal, the smaller the nitrogen oxide content in the oxide insulating film.

Further, the oxide insulating film has a nitrogen concentration of 6×10 ²⁰ atto as measured by SIMS analysis.
ms/cm ³ or less.

The substrate temperature is 220° C. or higher, 280° C. or higher, or 350° C. or higher, and the oxide insulating film is formed by a PECVD method using silane and dinitrogen monoxide, so that the oxide insulating film is dense and A film with high hardness can be formed.

The insulating film 116 is formed using an oxide insulating film containing more oxygen than the stoichiometric composition. An oxide insulating film containing more oxygen than the stoichiometric composition is
Part of the oxygen is released by heating. According to TDS analysis, the amount of oxygen released from the oxide insulating film, which contains more oxygen than the stoichiometric composition, is 8.0×10 ¹ in terms of oxygen molecules.
The oxide insulating film has a density of ⁴ atoms/cm ² or more, preferably 1.0×10 ¹⁵ atoms/cm ² or more. The surface temperature of the film during the TDS analysis is 100° C. or higher.
00° C. or lower, preferably 100° C. or higher and 500° C. or lower.

As the insulating film 116, silicon oxide or silicon oxynitride with a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm can be used.

In addition, it is preferable that the insulating film 116 has a small amount of defects ^. less than 1×10 18 spins/cm ³ or even less than 1×10 ¹⁸ spins/cm ³
The following are preferable. Note that the insulating film 116 may have a higher defect density than the insulating film 114 because the insulating film 116 is farther from the oxide semiconductor film 108 than the insulating film 114 .

In addition, since the insulating films 114 and 116 can be made of the same material, the interface between the insulating films 114 and 116 cannot be clearly confirmed in some cases. Therefore, in this embodiment, the interface between the insulating film 114 and the insulating film 116 is illustrated with a dashed line. Note that although the two-layer structure of the insulating film 114 and the insulating film 116 is described in this embodiment mode, the present invention is not limited to this, and for example, a single-layer structure of either the insulating film 114 or the insulating film 116 may be used. good.

Insulating film 118 contains nitrogen. In addition, the insulating film 118 contains nitrogen and silicon. In addition, the insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the insulating film 118, oxygen from the oxide semiconductor film 108 diffuses to the outside, oxygen contained in the insulating films 114 and 116 diffuses to the outside, hydrogen from the outside enters the oxide semiconductor film 108, Intrusion of water or the like can be prevented. As the insulating film 118, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride. note that,
An oxide insulating film having a blocking effect against oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect against oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of oxide insulating films having an effect of blocking oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

The methods for forming various films such as the conductive film, the insulating film, and the oxide semiconductor film described above include a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, and a pulse laser deposition (P) method.
LD) method and the like. Further, the above-described methods for forming various films such as conductive films, insulating films, and oxide semiconductor films include plasma chemical vapor deposition (PECVD), thermal CVD (Ch
emical Vapor Deposition) method, or ALD (Atomic
Layer Deposition) method may be used. MOCVD as an example of thermal CVD
(Metal Organic Chemical Vapor Deposition
) law. As a method for forming various films such as the conductive film, the insulating film, and the oxide semiconductor film described above, a coating method or a printing method may be used.

The thermal CVD method is a film forming method that does not use plasma, so it has the advantage of not generating defects due to plasma damage.

In the thermal CVD method, a raw material gas and an oxidizing agent are sent into a chamber at the same time, the inside of the chamber is made to be under atmospheric pressure or reduced pressure, and a film is formed by reacting near or on the substrate and depositing it on the substrate. .

Further, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, raw material gases for reaction are sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, by switching the switching valves (also called high-speed valves), two or more source gases are sequentially supplied to the chamber, and the first source gas is supplied simultaneously with or after the first source gas so as not to mix the two or more source gases. Introduce an active gas (argon, nitrogen, etc.),
A second source gas is introduced. When the inert gas is introduced at the same time, the inert gas serves as a carrier gas, and the inert gas may be introduced at the same time as the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the second source gas may be introduced after the first source gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form the first layer, and reacts with the second source gas introduced later to laminate the second layer on the first layer. a thin film is formed. A thin film with excellent step coverage can be formed by repeating this gas introduction sequence several times until a desired thickness is obtained. Since the thickness of the thin film can be adjusted by the number of times the gas introduction order is repeated, precise film thickness adjustment is possible.
It is suitable for manufacturing fine FETs.

The thermal CVD method such as ALD method or MOCVD method can be applied to the conductive film, insulating film,
Various films such as oxide semiconductor films and metal oxide films can be formed.
When forming a -ZnO film, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In(CH ₃ ) ₃ .
Also, the chemical formula of trimethylgallium is Ga(CH ₃ ) ₃ . Also, the chemical formula of dimethylzinc is Zn(CH ₃ ) ₂ . Moreover, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C ₂ H ₅ )) can be used instead of dimethylzinc. ₂ ) can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two kinds of gases, a raw material gas and ozone (O ₃ ) as an oxidant, are used. The chemical formula of tetrakisdimethylamide hafnium is Hf[N(CH ₃ ) ₂ ] ₄ . Other material liquids include tetrakis(ethylmethylamido)hafnium.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA)) containing a solvent and an aluminum precursor compound and H ₂ as an oxidant are used. Two kinds of O gases are used. The chemical formula of trimethylaluminum is Al(CH ₃ ) ₃ . As another material liquid, Tris (
dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2
, 2,6,6-tetramethyl-3,5-heptanedionate).

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, chlorine contained in the adsorbed substance is removed, and an oxidizing gas (O
₂ , dinitrogen monoxide) radicals are supplied to react with the adsorbate.

For example, when forming a tungsten film with a film forming apparatus using ALD, WF ₆
gas and B ₂ H ₆ gas to form an initial tungsten film, then WF ₆ gas and H ₂
A tungsten film is formed using a gas. _SiH4 gas may be used instead of _B2H6 gas _.

For example, an oxide semiconductor film such as In--Ga--ZnO is formed by a film forming apparatus using ALD.
When forming a film, an In--O layer is formed using In(CH ₃ ) ₃ gas and O ₃ gas, and then Ga(CH ₃ ) ₃ gas and O ₃ gas are used to form a Ga layer. A —O layer is formed, and then a Zn—O layer is formed using Zn(CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. In--Ga--O layers and In--Zn-- can be formed by mixing these gases.
A mixed compound layer such as an O layer or a Ga--Zn--O layer may be formed. Although H ₂ O gas obtained by bubbling with an inert gas such as Ar may be used instead of O ₃ gas, it is preferable to use O ₃ gas that does not contain H. Also, instead of the In(CH ₃ ) ₃ gas, In(C ₂
H ₅ ) ₃ gas may also be used. Also, instead of Ga(CH ₃ ) ₃ gas, Ga(C ₂ H ₅
) ₃ gases may be used. Alternatively, Zn(CH ₃ ) ₂ gas may be used.

<2-3. Configuration Example 2 of Transistor>
Next, structural examples different from the transistor 100 illustrated in FIGS.
Description will be made with reference to FIGS.

15A is a top view of a transistor 150 included in a semiconductor device of one embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 15A. FIG. 15C corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 15A.

The transistor 150 includes the conductive film 104 functioning as a gate electrode over the substrate 102, the insulating film 106 over the substrate 102 and the conductive film 104, the insulating film 107 over the insulating film 106, and the oxide semiconductor film over the insulating film 107. 108 , the insulating film 114 over the oxide semiconductor film 108 , the insulating film 116 over the insulating film 114 , and the insulating films 114 and openings 141 provided in the insulating films 116 .
The conductive film 112a functioning as a source electrode and electrically connected to the oxide semiconductor film 108 through the insulating films 114 and 116 is electrically connected to the oxide semiconductor film 108 through the openings 141b provided in the insulating films 114 and 116. and a conductive film 112b functioning as a drain electrode connected to . An insulating film 118 is provided over the transistor 150 , more specifically, over the conductive films 112 a and 112 b and the insulating film 116 . The insulating films 114 and 116 function as protective insulating films for the oxide semiconductor film 108 . The insulating film 118 is the transistor 1
50 has a function as a protective insulating film.

While the transistor 100 shown above has a channel-etch structure,
A transistor 150 illustrated in FIGS. 15A, 15B, and 15C has a channel-protective structure.
Thus, the semiconductor device of one embodiment of the present invention can be applied to both channel-etched and channel-protected transistor structures.

<2-4. Configuration Example 3 of Transistor>
Next, structural examples different from the transistor 150 illustrated in FIGS.
Description will be made with reference to FIGS.

16A is a top view of a transistor 160 which is a semiconductor device of one embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A. FIG. 16(C) corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 16(A).

The transistor 160 includes the conductive film 104 functioning as a gate electrode over the substrate 102, the insulating film 106 over the substrate 102 and the conductive film 104, the insulating film 107 over the insulating film 106, and the oxide semiconductor film over the insulating film 107. , an insulating film 114 over the oxide semiconductor film 108, an insulating film 116 over the insulating film 114, a conductive film 112a functioning as a source electrode electrically connected to the oxide semiconductor film 108, and an oxide semiconductor film. and a conductive film 112 b functioning as a drain electrode electrically connected to the film 108 . An insulating film 118 is provided over the transistor 160 , more specifically, over the conductive films 112 a and 112 b and the insulating film 116 .
The insulating films 114 and 116 function as protective insulating films for the oxide semiconductor film 108 . The insulating film 118 functions as a protective insulating film for the transistor 160 .

The shape of the insulating films 114 and 116 of the transistor 160 is different from that of the transistor 150 illustrated in FIGS. Specifically, the insulating films 114 and 1 of the transistor 160
16 is provided in an island shape over the channel region of the oxide semiconductor film 108 . Other configurations are
It is similar to the transistor 150 and has similar effects.

<2-5. Configuration Example 4 of Transistor>
Next, structural examples different from the transistor 100 illustrated in FIGS.
Description will be made with reference to FIGS.

17A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention, and FIG. 17B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 17A. FIG. 17(C) corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 shown in FIG. 17(A).

The transistor 170 includes the conductive film 104 functioning as a first gate electrode over the substrate 102 .
, the insulating film 106 over the substrate 102 and the conductive film 104 , the insulating film 107 over the insulating film 106 , the oxide semiconductor film 108 over the insulating film 107 , and the source electrically connected to the oxide semiconductor film 108 . A conductive film 112a functioning as an electrode, a conductive film 112b functioning as a drain electrode electrically connected to the oxide semiconductor film 108, the oxide semiconductor film 108, and the conductive film 1
Insulating film 114 on 12a and 112b, insulating film 116 on insulating film 114, and insulating film 116
Upper oxide semiconductor films 120a and 120b, the insulating film 114, and the oxide semiconductor film 120a
, and an insulating film 118 on 120b.

The insulating films 106 and 107 also function as a first gate insulating film of the transistor 170 . In addition, the insulating films 114 and 116 function as second gate insulating films of the transistor 170 . The insulating film 118 also functions as a protective insulating film for the transistor 170 . Further, the oxide semiconductor film 120a functions as, for example, a pixel electrode used for a display device. In addition, the oxide semiconductor film 120a is connected to the conductive film 112b through the openings 142c provided in the insulating films 114 and 116 . Moreover, the oxide semiconductor film 1
20b functions as a second gate electrode (also referred to as a back gate electrode).

Further, as illustrated in FIG. 17C, the oxide semiconductor film 120b includes the insulating films 106, 107,
The openings 142a and 142b provided in 114 and 116 are connected to the conductive film 104 functioning as the first gate electrode. Therefore, the oxide semiconductor film 120b and the conductive film 104
are given the same potential.

Note that in this embodiment, the openings 142a and 142b are provided, and the oxide semiconductor film 1 is formed.
Although the configuration in which 20b and the conductive film 104 are connected has been exemplified, the present invention is not limited to this. For example, either the opening 142a or the opening 142b is formed to connect the oxide semiconductor film 120b and the conductive film 104, or the opening 142a and the opening 142 are connected to each other.
A structure in which the oxide semiconductor film 120b and the conductive film 104 are not connected may be employed without providing b.
Note that in the case where the oxide semiconductor film 120b and the conductive film 104 are not connected, different potentials can be applied to the oxide semiconductor film 120b and the conductive film 104, respectively.

Further, as illustrated in FIG. 17B, the oxide semiconductor film 108 faces the conductive film 104 functioning as the first gate electrode and the oxide semiconductor film 120b functioning as the second gate electrode. and sandwiched between two conductive films functioning as gate electrodes. The length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 120b functioning as the second gate electrode are longer than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 108, respectively. Long, the entire oxide semiconductor film 108 is covered with insulating films 114 and 116
is covered with the oxide semiconductor film 120b with the . The oxide semiconductor film 120b functioning as the second gate electrode and the conductive film 104 functioning as the first gate electrode are connected through openings 142a and 142b provided in the insulating films 106, 107, 114, and 116. Therefore, the side surface of the oxide semiconductor film 108 in the channel width direction faces the oxide semiconductor film 120b functioning as a second gate electrode with the insulating films 114 and 116 interposed therebetween.

In other words, in the channel width direction of the transistor 170, the conductive film 104 functioning as a first gate electrode and the oxide semiconductor film 120b functioning as a second gate electrode are
The insulating films 106 and 107 functioning as the first gate insulating films and the insulating films 114 and 116 functioning as the second gate insulating films are connected in the openings provided, and the insulating films functioning as the first gate insulating films In this structure, the oxide semiconductor film 108 is surrounded with the insulating films 114 and 116 functioning as the second gate insulating films 106 and 107 interposed therebetween.

With such a structure, the oxide semiconductor film 108 included in the transistor 170 can be
can be electrically surrounded by the electric fields of the conductive film 104 functioning as the first gate electrode and the oxide semiconductor film 120b functioning as the second gate electrode. transistor 170
, the device structure of the transistor that electrically surrounds the oxide semiconductor film in which the channel region is formed is surrounded by the electric field of the first gate electrode and the second gate electrode.
It can be called a d channel (s-channel) structure.

Since the transistor 170 has an s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 104 functioning as a first gate electrode. improved current drive capability of
High on-current characteristics can be obtained. In addition, since the on-state current can be increased, the transistor 170 can be miniaturized. In addition, since the transistor 170 has a structure surrounded by the conductive film 104 functioning as the first gate electrode and the oxide semiconductor film 120b functioning as the second gate electrode, the mechanical strength of the transistor 170 can be increased. can.

<2-6. Configuration Example 5 of Transistor>
Next, structural examples different from the transistor 100 illustrated in FIGS.
Description will be made with reference to FIGS.

18A is a top view of a transistor 180, which is a semiconductor device of one embodiment of the present invention, and FIG. 18B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. FIG. 18(C) corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 18(A).

The transistor 180 includes the insulating film 131 formed over the substrate 102, the insulating film 132 over the insulating film 131, the oxide semiconductor film 108 over the insulating film 132, the insulating film 107 over the oxide semiconductor film 108, The insulating film 106 over the insulating film 107, the conductive film 104 overlapping with the oxide semiconductor film 108 with the insulating films 106 and 107 interposed therebetween, and the insulating film 133 covering the oxide semiconductor film 108, the insulating film 132, and the conductive film 104 , the insulating film 116 over the insulating film 133 , the conductive film 112 a connected to the oxide semiconductor film 108 through the opening 140 a provided in the insulating film 133 and the insulating film 116 , and the insulating film 133 and the insulating film 116 . and a conductive film 112b connected to the oxide semiconductor film 108 through the provided opening 140b. Note that the insulating film 116, the conductive film 104, the conductive film 112a, and the conductive film 112b are formed over the transistor 180;
An insulating film 118 may be provided to cover the .

In the transistor 180, the conductive film 104 functions as a gate electrode (also referred to as a top gate electrode), the conductive film 112a functions as one of a source electrode and a drain electrode, and the conductive film 112b functions as , as the other electrode of the source electrode and the drain electrode. In the transistor 180, the insulating films 131 and 132 function as base films for the oxide semiconductor film 108, and the insulating films 107 and 106 function as gate insulating films. Further, as shown in FIGS. 18A, 18B, and 18C, the transistor 1
80 is a top gate type single gate transistor. In this manner, transistors with various structures such as a bottom-gate transistor, a dual-gate transistor, and a top-gate transistor can be applied to the semiconductor device of one embodiment of the present invention.

<2-7. Configuration Example 6 of Transistor>
Next, structural examples different from the transistor 100 illustrated in FIGS.
Description will be made with reference to FIGS.

19A, 19B, 19C, and 19D are cross-sectional views of modifications of the transistor 100 shown in FIGS. 14B and 14C.

In a transistor 100A illustrated in FIGS. 19A and 19B, the oxide semiconductor film 108 included in the transistor 100 illustrated in FIGS. 14B and 14C has a stacked-layer structure of three layers. More specifically, the oxide semiconductor film 108 included in the transistor 100A includes an oxide semiconductor film 108a, an oxide semiconductor film 108b, and an oxide semiconductor film 108c.

A transistor 100B illustrated in FIGS. 19C and 19D has a two-layer structure of the oxide semiconductor film 108 included in the transistor 100 illustrated in FIGS. More specifically, the oxide semiconductor film 108 included in the transistor 100B includes an oxide semiconductor film 108b and an oxide semiconductor film 108c.

Here, band structures of the oxide semiconductor film 108 and the insulating film in contact with the oxide semiconductor film 108 are described with reference to FIGS.

FIG. 20A illustrates an example of a band structure in the thickness direction of a stacked-layer structure including the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and the insulating film 114. FIG. Moreover, FIG.
) is an example of a band structure in the thickness direction of a stacked-layer structure including the insulating film 107, the oxide semiconductor films 108b and 108c, and the insulating film 114. FIG. Note that the band structure shows energy levels (Ec) at the bottom of the conduction band of the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and the insulating film 114 for easy understanding.

In addition, in FIG. 20A, silicon oxide films are used as the insulating films 107 and 114, and a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108a. and the oxide semiconductor film 108b is formed using a metal oxide target in which the atomic ratio of the metal elements is In:Ga:Zn=1:1:1. A semiconductor film is used, and the atomic ratio of the metal element is set to In for the oxide semiconductor film 108c.
1 is a band diagram of a structure using an oxide semiconductor film formed using a metal oxide target of :Ga:Zn=1:3:2; FIG.

In FIG. 20B, a silicon oxide film is used as the insulating films 107 and 114, and a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the oxide semiconductor film 108b. and the oxide semiconductor film 108c is formed using a metal oxide target in which the atomic ratio of the metal elements is In:Ga:Zn=1:3:2. FIG. 4 is a band diagram of a configuration using a membrane;

As shown in FIGS. 20A and 20B, the energy levels at the bottom of the conduction band gradually change in the oxide semiconductor films 108a, 108b, and 108c. In other words, it can be said that it changes continuously or joins continuously. In order to have such a band structure, the interface between the oxide semiconductor films 108a and 108b or the oxide semiconductor film 108b
and the oxide semiconductor film 108c, there is no impurity that forms a defect level such as a trap center or a recombination center.

In order to form continuous junctions in the oxide semiconductor films 108a, 108b, and 108c, a multi-chamber deposition apparatus (sputtering apparatus) equipped with a load-lock chamber is used to continuously form the films without exposure to the air. It is sufficient to stack them together.

With the structures illustrated in FIGS. 20A and 20B, the oxide semiconductor film 108b serves as a well.
Therefore, in the transistor using the above stacked structure, the channel region is the oxide semiconductor film 1
08b.

Note that the oxide semiconductor film 108b is formed when the oxide semiconductor films 108a and 108c are not formed.
The trap levels that can be formed in the oxide semiconductor film 108a,
108c. Therefore, the trap level can be separated from the oxide semiconductor film 108b.

In addition, the trap level might be farther from the vacuum level than the energy level (Ec) at the bottom of the conduction band of the oxide semiconductor film 108b functioning as a channel region, and electrons are likely to be accumulated in the trap level. . When electrons are accumulated in the trap level, they become negative fixed charges, and the threshold voltage of the transistor shifts in the positive direction. therefore,
It is preferable that the trap level is lower than the energy level (Ec) at the bottom of the conduction band of the oxide semiconductor film 108b in the vacuum level. By doing so, it becomes difficult for electrons to be accumulated in the trap level, and it is possible to increase the on-current of the transistor and increase the field effect mobility.

20A and 20B, the energy levels at the bottom of the conduction band of the oxide semiconductor films 108a and 108c are closer to the vacuum level than the oxide semiconductor film 108b. The energy level at the bottom of the conduction band of the film 108b and the oxide semiconductor films 108a and 108
The difference between the energy level at the bottom of the conduction band of c is 0.15 eV or more, or 0.5 eV or more,
and 2 eV or less, or 1 eV or less. That is, the oxide semiconductor films 108a and 108
The difference between the electron affinity of c and the electron affinity of the oxide semiconductor film 108b is 0.15 eV or more,
Alternatively, it is 0.5 eV or more and 2 eV or less, or 1 eV or less.

With such a structure, the oxide semiconductor film 108b serves as a main current path and functions as a channel region. In addition, since the oxide semiconductor films 108a and 108c are oxide semiconductor films including one or more metal elements forming the oxide semiconductor film 108b in which the channel region is formed, the oxide semiconductor film 108a and the oxide semiconductor film 108b Interfacial scattering is less likely to occur at the interface with the semiconductor film 108b or the interface between the oxide semiconductor film 180b and the oxide semiconductor film 108c. Therefore, since the movement of carriers is not hindered at the interface, the field effect mobility of the transistor is increased.

Further, a material with sufficiently low conductivity is used for the oxide semiconductor films 108a and 108c in order to prevent them from functioning as part of the channel region. Alternatively, the oxide semiconductor films 108a and 108c have electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band).
is smaller than that of the oxide semiconductor film 108b, and the energy level of the conduction band bottom is different from that of the oxide semiconductor film 108b (band offset). In order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, the energy levels at the bottoms of the conduction bands of the oxide semiconductor films 108a and 108c should be
It is preferable to use a material whose energy level is closer to the vacuum level than the energy level at the bottom of the conduction band of the oxide semiconductor film 108b. For example, the difference between the energy level of the bottom of the conduction band of the oxide semiconductor film 108b and the energy level of the bottom of the conduction band of the oxide semiconductor films 108a and 108c is set to be 0.2 eV or more, preferably 0.5 eV or more. is preferred.

Further, the oxide semiconductor films 108a and 108c preferably do not have a spinel crystal structure. In the case where the oxide semiconductor films 108a and 108c include a spinel crystal structure, the conductive films 112a and 112a and 112a and 112b are formed at interfaces between the spinel crystal structure and other regions.
The constituent element of 2b might diffuse into the oxide semiconductor film 108b. Note that when the oxide semiconductor films 108a and 108c are CAAC-OS, which will be described later, the conductive films 112a and 112a and 112c are used.
Constituent elements of 2b, such as copper, are preferred because of their high blocking properties.

The thicknesses of the oxide semiconductor films 108a and 108c are greater than or equal to the thickness with which the constituent elements of the conductive films 112a and 112b can be prevented from diffusing into the oxide semiconductor film 108b. The thickness of the film 108b is less than the film thickness that suppresses the supply of oxygen to the film 108b. For example, when the thicknesses of the oxide semiconductor films 108a and 108c are 10 nm or more, the conductive films 112a,
The constituent element 112b can be prevented from diffusing into the oxide semiconductor film 108b. Further, when the thickness of the oxide semiconductor films 108a and 108c is set to 100 nm or less, the insulating film 114
, 116 can effectively supply oxygen to the oxide semiconductor film 108b.

When the oxide semiconductor films 108a and 108c are In--M--Zn oxide, M is Ti
, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf at a higher atomic ratio than In, the oxide semiconductor films 108a and 108c can have a large energy gap and a small electron affinity. Therefore, the difference in electron affinity with the oxide semiconductor film 108b can be controlled by the composition of the element M in some cases. In addition, Ti, Ga, Y, Zr, La, Ce
, Nd, Sn, and Hf are metal elements that have a strong bonding force with oxygen, and oxygen vacancies are less likely to occur when these elements have a higher atomic ratio than In.

Further, when the oxide semiconductor films 108a and 108c are In--M--Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 50 atomic %.
less than 50 atomic % of M, more preferably 25 atomic % of In
less than, M higher than 75 atomic %. In addition, the oxide semiconductor films 108a and 108c
Alternatively, a gallium oxide film may be used.

Further, when the oxide semiconductor films 108a, 108b, and 108c are In--M--Zn oxides, M contained in the oxide semiconductor films 108a and 108c is higher than that in the oxide semiconductor film 108b.
Typically, the atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more that of the above atoms contained in the oxide semiconductor film 108b. be.

In the case where the oxide semiconductor films 108a, 108b, and 108c are In--M--Zn oxide, the oxide semiconductor film 108b is oxidized with In:M:Zn= _x.sub.1 : _y.sub.1 : _z.sub.1 [atomic ratio]. When the material semiconductor films 108a and 108c are In:M:Zn=x ₂ :y ₂ :z ₂ [atomic number ratio],
y ₂ /x ₂ is greater than y ₁ /x ₁ , preferably y ₂ /x ₂ is greater than y ₁ /x ₁ by 1.
5 times or more. More preferably, y ₂ /x ₂ is two times or more larger than y ₁ /x ₁ , and still more preferably y ₂ /x ₂ is three times or more or four times larger than y ₁ /x ₁ . At this time, in the oxide semiconductor film 108b, when _y1 is greater than or equal to _x1 , the oxide semiconductor film 108b
is preferable because stable electrical characteristics can be imparted to a transistor using . However, y ₁ is x
If it is three times or more than ₁ , the field-effect mobility of the transistor including the oxide semiconductor film 108b is reduced; therefore, _y1 is preferably less than three times _x1 .

When the oxide semiconductor film 108b is an In-M-Zn oxide, the atomic ratio of the metal elements in the target used for forming the oxide semiconductor film 108b is In:M:Zn=x ₁ :
When y ₁ : z _{1 ,} x ₁ /y ₁ is 1/3 or more and 6 or less, further 1 or more and 6 or less, and z ₁ /y ₁ is 1/3 or more and 6 or less, further 1 or more It is preferably 6 or less. Note that when z ₁ /y ₁ is set to 1 or more and 6 or less, the oxide semiconductor film 108 b can be a CAA film, which will be described later.
C-OS is easily formed. A representative example of the atomic ratio of the metal elements in the target is I
n:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1
: There are 2nd class.

In the case where the oxide semiconductor films 108a and 108c are In--M--Zn oxides, the atomic ratio of the metal elements in the targets used for forming the oxide semiconductor films 108a and 108c is In:M:Zn. x ₂ : y ₂ : z _{2 ,} then x ₂ /y ₂ <x ₁ /y ₁ and z
₂ / _y2 is preferably ⅓ or more and 6 or less, more preferably 1 or more and 6 or less. Further, by increasing the atomic ratio of M to indium, the oxide semiconductor films 108a and 108
Since it is possible to increase the energy gap of c and decrease the electron affinity, y ₂
/x ₂ is preferably 3 or more, or 4 or more. Typical examples of atomic ratios of metal elements in the target are In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:
M:Zn=1:3:5, In:M:Zn=1:3:6, In:M:Zn=1:4:2, I
n:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:5:5
etc.

Further, in the case where the oxide semiconductor films 108a and 108c are In—M oxides, M does not contain a divalent metal atom (eg, zinc), so that the oxide does not have a spinel crystal structure. Semiconductor films 108a and 108c can be formed. For example, an In—Ga oxide film can be used as the oxide semiconductor films 108a and 108c. As the In--Ga oxide, for example, an In--Ga metal oxide target (In:Ga=7
: 93) and can be formed by a sputtering method. In order to form the oxide semiconductor films 108a and 108c by a sputtering method using DC discharge, In
: When M = x: y [atomic ratio], y / (x + y) is 0.96 or less, preferably 0
. 95 or less, for example, 0.93.

Note that the atomic ratios of the oxide semiconductor films 108a, 108b, and 108c may vary by plus or minus 40% from the above atomic ratio.

Further, each of the above structures can be freely combined with the transistor according to this embodiment.

<2-8. Semiconductor Device Manufacturing Method 1>
Next, a method for manufacturing the transistor 100 is described with reference to FIGS.
21 and 22 are cross-sectional views illustrating a method for manufacturing a semiconductor device.

First, a conductive film is formed over a substrate 102 and processed by a lithography step and an etching step to form a conductive film 104 functioning as a gate electrode (see FIG. 21A).

In this embodiment mode, a glass substrate is used as the substrate 102, and a tungsten film with a thickness of 100 nm is formed by a sputtering method as the conductive film 104 functioning as a gate electrode.

Next, insulating films 106 and 107 functioning as gate insulating films are formed over the conductive film 104 (see FIG. 21B).

In this embodiment mode, a silicon nitride film with a thickness of 400 nm is formed as the insulating film 106 and a silicon oxynitride film with a thickness of 50 nm is formed as the insulating film 107 by a PECVD method.

Note that the insulating film 106 has a stacked structure of silicon nitride films. Specifically, the insulating film 106
can have a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. An example of the three-layer laminated structure can be formed as follows.

As the first silicon nitride film, for example, silane at a flow rate of 200 sccm and a flow rate of 2000 sccm are used.
PE-CV using sccm nitrogen and ammonia gas at a flow rate of 100 sccm as raw material gases
It may be formed to a thickness of 50 nm by supplying power to the reaction chamber of apparatus D, controlling the pressure in the reaction chamber to 100 Pa, and supplying power of 2000 W using a high frequency power supply of 27.12 MHz.

As the second silicon nitride film, silane at a flow rate of 200 sccm and a flow rate of 2000 sccm were used.
of nitrogen and ammonia gas at a flow rate of 2000 sccm are supplied to the reaction chamber of the PECVD apparatus as raw material gases, the pressure in the reaction chamber is controlled at 100 Pa, and power of 2000 W is supplied using a high frequency power supply of 27.12 MHz to increase the thickness. It may be formed so as to have a thickness of 300 nm.

As the third silicon nitride film, silane at a flow rate of 200 sccm and a flow rate of 5000 sccm were used.
cm of nitrogen as a raw material gas is supplied to the reaction chamber of the PECVD apparatus, and the pressure in the reaction chamber is set to 100.
The film may be formed to have a thickness of 50 nm by controlling to Pa and supplying power of 2000 W using a high frequency power source of 27.12 MHz.

Note that the substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be set to 350.degree.

By forming the insulating film 106 to have a laminated structure of three layers of silicon nitride films, for example, the conductive film 10
When a conductive film containing copper (Cu) is used for 4, the following effects are obtained.

The first silicon nitride film can suppress diffusion of copper (Cu) elements from the conductive film 104 . The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film functioning as the gate insulating film. The third silicon nitride film releases less hydrogen from the third silicon nitride film and can suppress the diffusion of hydrogen released from the second silicon nitride film.

The insulating film 107 is preferably formed using an insulating film containing oxygen in order to improve interface characteristics with the oxide semiconductor film 108 which is formed later.

Next, an oxide semiconductor film 108 is formed over the insulating film 107 (see FIG. 21C).

In this embodiment, an In--Ga--Zn metal oxide target (In:Ga:Zn=1:
1:1.2 (atomic ratio)) to form an oxide semiconductor film by a sputtering method,
A mask is formed over the oxide semiconductor film by a lithography process, and the oxide semiconductor film is processed into desired regions, whereby the island-shaped oxide semiconductor film 108 is formed.

After the oxide semiconductor film 108 is formed, the temperature is 150° C. or more and less than the strain point of the substrate, preferably 200° C.
Heat treatment may be performed at 300° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower. The heat treatment here is one of treatments for purifying the oxide semiconductor film, and can reduce hydrogen, water, and the like contained in the oxide semiconductor film 108 . Note that heat treatment for reducing hydrogen, water, and the like may be performed before the oxide semiconductor film 108 is processed into an island shape.

For heat treatment of the oxide semiconductor film 108, a gas baking furnace, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature higher than the strain point of the substrate for a short period of time. Therefore, it becomes possible to shorten the heating time.

Note that the heat treatment of the oxide semiconductor film 108 includes nitrogen gas, oxygen gas, ultra-dry air (Cl
EAN Dry Air: Also called CDA. CDA means that the water content is 20 ppm or less,
The air is preferably 1 ppm or less, preferably 10 ppb or less. ), or noble gases (
argon, helium, etc.) atmosphere. In addition, the above nitrogen gas, oxygen gas, CD
It is preferable that A or the rare gas does not contain hydrogen, water, or the like.

For example, it is preferable to increase the purity of the nitrogen gas, oxygen gas, or CDA. Specifically, the purity of nitrogen gas, oxygen gas, or CDA is 6N (99.9999%) or 7N
(99.99999%). In addition, by using a nitrogen gas, an oxygen gas, or a highly purified gas with a dew point of CDA of −60° C. or lower, preferably −100° C. or lower, moisture or the like can be taken into the oxide semiconductor film 108 . as long as it can be prevented.

Alternatively, the oxide semiconductor film 108 may be heat-treated in a nitrogen or rare gas atmosphere and then heated in an oxygen or CDA atmosphere. As a result, hydrogen, water, and the like contained in the oxide semiconductor film 108 can be released and oxygen can be supplied to the oxide semiconductor film 108 . As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

Further, when an oxide semiconductor film is formed by a sputtering method, the sputtering gas includes
A rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In the case of the mixed gas, it is preferable to increase the gas ratio of oxygen to the rare gas. Also, the sputtering gas must be highly purified. For example, an oxygen gas or an argon gas used as a sputtering gas is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower, so that the oxide semiconductor film 108 does not absorb moisture or the like. prevent as much as possible.

In the case of forming the oxide semiconductor film 108 by a sputtering method, a chamber of a sputtering apparatus is equipped with an adsorption-type vacuum pump such as a cryopump in order to remove water and the like, which are impurities in the oxide semiconductor film 108, as much as possible. is used to evacuate to a high vacuum (5 x 1
0 ⁻⁷ Pa to 1×10 ⁻⁴ Pa). Alternatively, it is preferable to prevent backflow of gas, especially gas containing carbon or hydrogen, from the exhaust system into the chamber by combining a turbomolecular pump and a cold trap.

Next, a conductive film is formed over the insulating film 107 and the oxide semiconductor film 108 and processed into a desired shape, so that the conductive films 112a and 112b are formed (see FIG. 21D).

In this embodiment, as the conductive films 112a and 112b, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are formed in this order. Note that a sputtering method may be used as a method for forming the conductive films 112a and 112b.

Further, a step of cleaning the surface of the oxide semiconductor film 108 may be performed after the conductive films 112a and 112b are formed. As a method for cleaning the surface of the oxide semiconductor film 108, for example, an aqueous phosphoric acid solution or the like may be used. Note that in the step of forming the conductive films 112 a and 112 b or the step of cleaning the surface of the oxide semiconductor film 108 , a depression may be formed in part of the surface of the oxide semiconductor film 108 in some cases.

The transistor 100 is formed through the above steps.

Next, specifically, the oxide semiconductor film 108 and the conductive film 112 are formed over the transistor 100 .
Insulating films 114 and 116 functioning as protective insulating films of the transistor 100 over a and 112b
is formed (see FIG. 22(A)).

Note that the insulating film 116 is preferably formed continuously without exposure to the air after the insulating film 114 is formed. After forming the insulating film 114, the insulating film 114 and the insulating film are continuously formed by adjusting one or more of the source gas flow rate, pressure, high-frequency power, and substrate temperature without exposing to the atmosphere. 116, the concentration of impurities derived from atmospheric components can be reduced, oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, and the amount of oxygen vacancies in the oxide semiconductor film 108 can be increased. can be reduced.

For example, a silicon oxynitride film can be formed as the insulating film 114 by a PECVD method. In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as source gases. Typical examples of deposition gases containing silicon include silane, disilane, trisilane, and fluorinated silane. The oxidizing gas includes dinitrogen monoxide, nitrogen dioxide, and the like. Further, the flow rate of the oxidizing gas is more than 20 times and less than 100 times, preferably 40 times to 80 times, the flow rate of the deposition gas, and the pressure in the processing chamber is less than 100 Pa, preferably 50 Pa or less. By using the PECVD method, the insulating film 114 becomes an insulating film containing nitrogen and having a small number of defects.

In this embodiment, the insulating film 114 holds the substrate 102 at a temperature of 220.degree.
silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm are used as raw material gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 M.
A silicon oxynitride film is formed by PECVD at Hz and 100 W (1.6×10 ⁻² W/cm ² as power density).

As the insulating film 116, a substrate placed in an evacuated treatment chamber of a PECVD apparatus is held at 180° C. to 280° C., preferably 200° C. to 240° C., and a source gas is introduced into the treatment chamber. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less.
/cm ² or more and 0.5 W/cm ² or less, more preferably 0.25 W/cm ² or more and 0.35
A silicon oxide film or a silicon oxynitride film is formed under conditions for supplying high-frequency power of W/cm ² or less.

As a condition for forming the insulating film 116, by supplying high-frequency power with the above-mentioned power density in the reaction chamber with the above-mentioned pressure, the decomposition efficiency of the raw material gas increases in the plasma, oxygen radicals increase, and oxidation of the raw material gas progresses. Therefore, the oxygen content in the insulating film 116 is higher than the stoichiometric composition. On the other hand, since the bonding force between silicon and oxygen is weak in the film formed at the substrate temperature above, part of the oxygen in the film is released by heat treatment in a later step. As a result, an oxide insulating film that contains more oxygen than the stoichiometric composition and from which part of the oxygen is released by heating can be formed.

Note that in the step of forming the insulating film 116 , the insulating film 114 serves as a protective film for the oxide semiconductor film 108 . Therefore, the insulating film 116 can be formed using high-density high-frequency power while reducing damage to the oxide semiconductor film 108 .

Note that the amount of defects in the insulating film 116 can be reduced by increasing the flow rate of the deposition gas containing silicon relative to the oxidizing gas in the deposition conditions of the insulating film 116 . Typically, ESR measurements show that the spin density of the signal appearing at g=2.001 originating from dangling bonds in silicon is less than 6×10 ¹⁷ spins/cm ³ , preferably 3×10 ^{17 .}
An oxide insulating layer can be formed with a small amount of defects, which is spins/cm ³ or less, preferably 1.5×10 ¹⁷ spins/cm ³ or less. As a result, the reliability of the transistor can be improved.

Heat treatment may be performed after the insulating films 114 and 116 are formed. By the heat treatment, nitrogen oxides contained in the insulating films 114 and 116 can be reduced. Further, by the above heat treatment, part of oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, so that the amount of oxygen vacancies contained in the oxide semiconductor film 108 can be reduced.

The temperature of the heat treatment for the insulating films 114 and 116 is typically 150° C. to 400° C., preferably 300° C. to 400° C., and preferably 320° C. to 370° C.
The heat treatment may be performed in an atmosphere of nitrogen, oxygen, CDA, or a rare gas (argon, helium, or the like). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, or the like.

In this embodiment mode, heat treatment is performed at 350° C. for 1 hour in a nitrogen and oxygen atmosphere.

Next, an insulating film 118 is formed over the insulating film 116 (see FIG. 22B).

In the case of forming the insulating film 118 by a PECVD method, a substrate temperature of 300° C. to 400° C., preferably 320° C. to 370° C. is preferable because a dense film can be formed.

For example, when a silicon nitride film is formed as the insulating film 118 by a PECVD method, a deposition gas containing silicon, nitrogen, and ammonia are preferably used as source gases.
By using a small amount of ammonia compared to nitrogen, ammonia is dissociated in the plasma to generate active species. The active species cut the bond between silicon and hydrogen and the triple bond of nitrogen contained in the deposition gas containing silicon. As a result, bonding of silicon and nitrogen is promoted,
A dense silicon nitride film with few bonds between silicon and hydrogen and few defects can be formed. On the other hand, when the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and nitrogen do not decompose, silicon and hydrogen bonds remain, and a rough silicon nitride film with increased defects is formed. put away. For these reasons, the flow ratio of nitrogen to ammonia in the source gas is preferably 5 or more and 50 or less, more preferably 10 or more and 50 or less.

In this embodiment mode, as the insulating film 118, a silicon nitride film with a thickness of 50 nm is formed with a PECVD apparatus using silane, nitrogen, and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia.
sccm. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350° C., and the temperature is 27.12 MH.
1000 W of high frequency power is supplied to the parallel plate electrodes using a z high frequency power source. PECVD
The device is a parallel plate type PECVD device with an electrode area of 6000 cm ² , and the power supplied is converted to power per unit area (power density) of 1.7×10 ⁻¹ W/cm ² .

Further, when the insulating film 118 is formed by heating, it is preferable to eliminate preheating before forming the insulating film 118 . For example, if preheating is performed before forming the insulating film 118, excess oxygen in the insulating films 114 and 116 may be released to the outside. Therefore, when the insulating film 118 is formed, preheating is not performed. By forming the insulating film 118 on the film 116, it is possible to suppress release of excess oxygen in the insulating films 114 and 116 to the outside.

Note that heat treatment is performed before or after the insulating film 118 is formed to diffuse excess oxygen contained in the insulating films 114 and 116 into the oxide semiconductor film 108 and cause oxygen vacancies in the oxide semiconductor film 108 . can be supplemented. Alternatively, when the insulating film 118 is formed by heating, excess oxygen contained in the insulating films 114 and 116 can be diffused into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108 . . Before forming the insulating film 118,
Alternatively, the temperature of the heat treatment that can be performed after the insulating film 118 is formed is typically 15°C.
0° C. or higher and 400° C. or lower, preferably 300° C. or higher and 400° C. or lower, preferably 320° C. or higher and 370° C. or lower.

Through the above steps, the transistor 100 can be manufactured.

<2-9. Semiconductor device manufacturing method 2>
Next, a method for manufacturing the transistor 150 is described with reference to FIGS. In addition, Fig. 2
3 is a cross-sectional view for explaining the manufacturing method of the semiconductor device.

First, the steps up to the step shown in FIG. 21C are performed, and then the insulating films 114 and 116 are formed over the insulating film 107 and the oxide semiconductor film 108 (see FIG. 23A).

Next, a mask is formed over the insulating film 116 by a lithography process, and openings 141 a and 141 b are formed in desired regions of the insulating films 114 and 116 . Note that the opening 141a
, 141b reach the oxide semiconductor film 108 (see FIG. 23B).

Next, the oxide semiconductor film 108 and the insulating film 11 are formed so as to cover the openings 141a and 141b.
A conductive film is formed over 6, a mask is formed over the conductive film by a lithography process, and the conductive film is processed into desired regions, whereby conductive films 112a and 112b are formed. After that, an insulating film 118 is formed over the insulating film 116 and the conductive films 112a and 112b (see FIG. 23C).

Through the above steps, the transistor 150 can be manufactured.

Note that the transistor 160 can be manufactured by leaving the insulating films 114 and 116 over the channel region of the oxide semiconductor film 108 when the openings 141a and 141b are formed.

<2-10. Semiconductor device manufacturing method 3>
Next, a method for manufacturing the transistor 170 is described with reference to FIGS. In addition, Fig. 2
4 is a cross-sectional view for explaining the manufacturing method of the semiconductor device;

First, the process up to the step shown in FIG. 22A is performed (see FIG. 24A).

Next, a mask is formed on the insulating film 116 by a lithography process, and the insulating films 114 and 11 are formed.
6, an opening 142c is formed in the desired region. Also, a mask is formed on the insulating film 116 by a lithography process, and openings 1 are formed in desired regions of the insulating films 106 , 107 , 114 , and 116 .
42a, 142b. Note that the opening 142c is formed to reach the conductive film 112b. The openings 142a and 142b are formed to reach the conductive film 104 (see FIG. 24B).

The openings 142a and 142b and the opening 142c may be formed in the same process.
They may be formed in different steps. When the openings 142a and 142b and the opening 142c are formed in the same process, they may be formed using a gray-tone mask or a halftone mask, for example.

Next, the oxide semiconductor film 120 is formed over the insulating film 116 so as to cover the openings 142a, 142b, and 142c (see FIG. 24C).

The oxide semiconductor film 120 can be formed using a material and a manufacturing method similar to those of the oxide semiconductor film 108 . Note that it is preferable to discharge plasma in an atmosphere containing an oxygen gas when the oxide semiconductor film 120 is formed. In this case, the oxide semiconductor film 120
Oxygen is added to the insulating film 116 which is to be the formation surface of . In addition to the oxygen gas, an inert gas (eg, helium gas, argon gas, xenon gas, or the like) may be mixed when the oxide semiconductor film 120 is formed. For example, using argon gas and oxygen gas,
It is preferable to increase the flow rate of oxygen gas over the flow rate of argon gas.

The substrate temperature at which the oxide semiconductor film 120 is formed is room temperature or higher and lower than 340 °C, preferably room temperature or higher and 300 °C or lower, more preferably 100 °C or higher and 250 °C or lower, further preferably 100 °C or higher and 200 °C or lower. It is below. Crystallinity of the oxide semiconductor film 120 can be improved by heating the oxide semiconductor film 120 for deposition. On the other hand, when a large glass substrate (eg, sixth generation to tenth generation) is used as the substrate 102, and the substrate temperature is 150° C. or more and less than 340° C. when the oxide semiconductor film 120 is formed, The substrate 102 may deform (distort or warp). Therefore, in the case of using a large glass substrate, deformation of the glass substrate can be suppressed by setting the substrate temperature to 100° C. or more and less than 150° C. when the oxide semiconductor film 120 is formed.

In this embodiment, an In--Ga--Zn metal oxide target (In:Ga:Zn=4:
2:4.1 [atomic ratio]), the oxide semiconductor film 120 is formed by a sputtering method. In addition, the substrate temperature is 170° C. when the oxide semiconductor film 120 is formed. As a deposition gas for forming the oxide semiconductor film 120, an oxygen gas with a flow rate of 100 sccm is used.

The composition of the oxide semiconductor film 120 is not limited to the above composition. For example, In:Ga:Zn
= 1:1:1 [atomic ratio], In:Ga:Zn=1:3:2 [atomic ratio], In:Ga:
Zn=1:3:4 [atomic ratio], In:Ga:Zn=1:3:6 [atomic ratio], In:G
Compositions such as a:Zn=3:1:2 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio] may be used.

By forming the oxide semiconductor film 120 in an atmosphere containing oxygen gas, the insulating film 1
Oxygen, or excess oxygen, can be included near the surface of 16 .

Next, a mask is formed over the oxide semiconductor film 120 by a lithography process, the oxide semiconductor film 120 is processed into a desired shape, and oxide semiconductor films 120a and 120b are formed. After that, the insulating film 118 is formed over the insulating films 116 and 118 and the oxide semiconductor films 120a and 120b (see FIG. 24D).

The insulating film 118 contains one or both of hydrogen and nitrogen. Therefore, by forming the insulating film 118, the oxide semiconductor films 120a and 120b in contact with the insulating film 118 are
By adding one or both of hydrogen and nitrogen, the carrier density is increased,
It can function as an oxide conductive film.

As the insulating film 118, for example, a silicon nitride film is preferably used. Alternatively, the insulating film 118 can be formed using a sputtering method or a PECVD method, for example. For example, when the insulating film 118 is formed by a PECVD method, the substrate temperature is lower than 400.degree. C., preferably lower than 375.degree. A dense film can be formed by setting the substrate temperature in the above range when the insulating film 118 is formed, which is preferable. By setting the substrate temperature in the above range when the insulating film 118 is formed, oxygen or excess oxygen in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108 .

Through the above steps, the transistor 170 can be manufactured.

Note that one embodiment of the present invention is described in this embodiment. However, one embodiment of the present invention is not limited to these. In other words, since various aspects of the invention are described in this embodiment and other embodiments, one aspect of the invention is not limited to any particular aspect. For example, the example in which the channel region of the transistor includes an oxide semiconductor is described as one embodiment of the present invention; however, one embodiment of the present invention is not limited thereto. In some cases, different transistors in one aspect of the present invention may have different semiconductors. For example, various transistors in one aspect of the present invention include at least one of, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. may be Alternatively, various transistors in one embodiment of the present invention do not necessarily include an oxide semiconductor.

As described above, the structures and methods described in this embodiment can be used in appropriate combination with the structures and methods described in other embodiments, examples, and reference examples.

(Embodiment 3)
In this embodiment, the structure and the like of an oxide semiconductor will be described with reference to FIGS.

<3-1. Structure of Oxide Semiconductor>
Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-align
d crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
inductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-
like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. As a crystalline oxide semiconductor, a single crystal oxide semiconductor, CAAC
-OS, polycrystalline oxide semiconductor and nc-OS.

Amorphous structures are generally isotropic with no inhomogeneous structures, metastable states with unfixed atomic arrangements, flexible bond angles, and short-range order but long-range order. It is said that it does not have

Conversely, a stable oxide semiconductor can be completely amorphous.
orphous) cannot be called an oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a perfect amorphous oxide semiconductor.
On the other hand, the a-like OS is not isotropic but has an unstable structure with voids. In terms of being unstable, an a-like OS is physically similar to an amorphous oxide semiconductor.

<3-2. CAAC-OS>
First, the CAAC-OS will be explained.

A CAAC-OS is a type of oxide semiconductor including a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, _InGaZnO4 , which is classified in the space group R-3m
When structural analysis is performed on CAAC-OS having crystals of 100 nm by the out-of-plane method, a peak appears near the diffraction angle (2θ) of 31° as shown in FIG. 25(A). Since this peak is assigned to the (009) plane of the _InGaZnO crystal, CAAC-OS
, it can be confirmed that the crystal has c-axis orientation, and the c-axis is oriented substantially perpendicular to the surface on which the CAAC-OS film is formed (also referred to as the formation surface) or the upper surface. Note that 2θ is 31
In addition to the peaks around °, there are cases where peaks appear around 2θ of 36°. 2θ is 36°
A nearby peak is attributed to a crystal structure classified in the space group Fd-3m. Therefore, CAA
C-OS preferably does not show this peak.

On the other hand, the in-pl method, in which X-rays are incident on the CAAC-OS from a direction parallel to the formation surface, is used.
Structural analysis by the ane method reveals a peak near 2θ of 56°. This peak is
It is assigned to the (110) plane of the crystal of _InGaZnO4 . Then, 2θ is fixed around 56°, and analysis is performed while rotating the sample around the normal vector of the sample surface (φ axis) (φ scan).
However, no clear peak appears as shown in FIG. 25(B). On the other hand, single crystal InGa
When φ scanning is performed on ZnO ₄ with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in FIG. 25(C). therefore,
From structural analysis using XRD, CAAC-OS can be confirmed to have irregular orientations of the a-axis and b-axis.

Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGa
When an electron beam with a probe diameter of 300 nm is made incident on the CAAC-OS having ZnO ₄ crystals in parallel with the surface on which the CAAC-OS is formed, a diffraction pattern (
It is also called a selected area electron diffraction pattern. ) may appear. This diffraction pattern has I
A spot due to the (009) plane of the nGaZnO ₄ crystal is included. Therefore, electron diffraction also shows that the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or upper surface. On the other hand, FIG. 25 (E
). A ring-shaped diffraction pattern is confirmed from FIG. Therefore, electron diffraction using an electron beam with a probe diameter of 300 nm also shows that the a-axis and b-axis of the pellet contained in CAAC-OS do not have orientation. The first ring in FIG. 25(E) is considered to be caused by the (010) plane and (100) plane of the InGaZnO ₄ crystal. Also, the second ring in FIG. 25(E) is considered to be caused by the (110) plane or the like.

In addition, a transmission electron microscope (TEM: Transmission Electron M
A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS bright-field image and a diffraction pattern using a microscope. On the other hand, even with a high-resolution TEM image, there are cases where the boundaries between pellets, that is, crystal grain boundaries (also called grain boundaries) cannot be clearly confirmed. Therefore, CAA
It can be said that C—OS is less likely to cause a decrease in electron mobility due to grain boundaries.

FIG. 26A shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of high-resolution TEM images, spherical aberration correction (Spherical A
error correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. A Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 26A, a pellet, which is a region in which metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellets can also be referred to as nanocrystals (nc). In addition, CAAC-OS can be replaced with CANC (C-Axis Aligned na
It can also be referred to as an oxide semiconductor having no crystals. Pellets are CAA
It reflects the unevenness of the surface on which the C-OS is formed or the upper surface, and is parallel to the surface on which the CAAC-OS is formed or the upper surface.

26(B) and 26(C) show CAA observed from a direction substantially perpendicular to the sample surface.
A Cs-corrected high-resolution TEM image of the plane of C-OS is shown. FIGS. 26(D) and 26(E) are images obtained by performing image processing on FIGS. 26(B) and 26(C), respectively. The image processing method will be described below. First, the fast Fourier transform (FFT: Fast
An FFT image is obtained by Fourier Transform) processing. Next, mask processing is performed to leave a range between 2.8 nm ⁻¹ and 5.0 nm ⁻¹ on the basis of the origin in the acquired FFT image. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT).
: Inverse Fast Fourier Transform) processing to obtain an image processed. An image obtained in this way is called an FFT filtered image. FFT
A filtered image is an image obtained by extracting periodic components from a Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 26(D), broken lines indicate portions where the lattice arrangement is disturbed. A region surrounded by a dashed line is one pellet. And the part shown by the broken line is a connection part of a pellet and a pellet. Since the dashed line indicates a hexagonal shape, it can be seen that the pellets have a hexagonal shape. Note that the shape of the pellet is not limited to a regular hexagon, and is often a non-regular hexagon.

In FIG. 26(E), a dotted line indicates a space between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting grid points around the grid point near the dotted line. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is CAA
This is thought to be because the C--OS can tolerate strain due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of the metal element.

As described above, CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, C
AAC-OS to CAA crystal (c-axis-aligned a-b-p
It can also be referred to as an oxide semiconductor having lane-anchored crystals.

CAAC-OS is an oxide semiconductor with high crystallinity. The crystallinity of oxide semiconductors may be degraded by the contamination of impurities and the generation of defects.
S can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurities are elements other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon that has a stronger bonding force with oxygen than a metal element that constitutes an oxide semiconductor deprives the oxide semiconductor of oxygen, thereby disturbing the atomic arrangement of the oxide semiconductor and lowering the crystallinity. be a factor. Heavy metals such as iron and nickel, argon,
Since carbon dioxide or the like has a large atomic radius (or molecular radius), it disturbs the atomic arrangement of the oxide semiconductor and causes deterioration in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, or the like. For example, an impurity contained in an oxide semiconductor may act as a carrier trap or a carrier generation source. For example, oxygen vacancies in an oxide semiconductor may trap carriers or generate carriers by trapping hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8×10 ¹¹ pieces/cm ³ , preferably less than 1×10 ^{11 pieces} /cm ³ , more preferably less than 1×10 ¹⁰ pieces/cm ³ , and 1×10 ⁻⁹ pieces/cm ³ . The oxide semiconductor can have a higher carrier density. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that the oxide semiconductor has stable characteristics.

<3-3. nc-OS>
Next, the nc-OS will be explained.

A case where the nc-OS is analyzed by XRD will be described. For example, when nc-OS is subjected to structural analysis by the out-of-plane method, no peak indicating orientation appears. That is, the crystal of nc-OS has no orientation.

Also, for example, an nc-OS having a crystal of InGaZnO ₄ is thinned to a thickness of 34 n.
When an electron beam with a probe diameter of 50 nm is made incident parallel to the surface to be formed into a region of m, FIG.
A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 7(A) is observed. Also, the diffraction pattern (
Nanobeam electron diffraction pattern) is shown in FIG. 27(B). A plurality of spots are observed in the ring-shaped region from FIG. 27(B). Therefore, nc-OS has a probe diameter of 50 nm
The orderliness is not confirmed when an electron beam of 1 nm is incident, but the orderliness is confirmed when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. 27(C). may occur. Therefore, it can be seen that the nc-OS has highly ordered regions, that is, crystals, in the thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where regular electron diffraction patterns are not observed.

FIG. 27D shows a Cs-corrected high-resolution TEM image of the cross section of the nc-OS observed from a direction substantially parallel to the formation surface. In a high-resolution TEM image, the nc-OS has regions where crystal parts can be confirmed, such as the parts indicated by auxiliary lines, and regions where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, often has a size of 1 nm or more and 3 nm or less. Note that an oxide semiconductor having a crystal part size of more than 10 nm and less than or equal to 100 nm is referred to as a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor).
It is sometimes called an ocrystalline oxide semiconductor). In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed. Note that the nanocrystals may share the same origin as the pellets in CAAC-OS. Therefore, the crystal part of the nc-OS may be called a pellet hereinafter.

Thus, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS
, there is no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

Note that the nc-OS is defined as an oxide semiconductor having random aligned nanocrystals (RANC) or an oxide semiconductor having non-aligned nanocrystals (NANC) because there is no regularity in crystal orientation between pellets (nanocrystals). They can also be called semiconductors.

An nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower defect level density than the a-like OS and the amorphous oxide semiconductor. However, nc-OS shows no regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher defect level density than the CAAC-OS.

<3-4. a-like OS>
An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.

FIG. 28 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG.
is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Figure 28 (
B) is a high-resolution cross-sectional TEM image of the a-like OS after electron (e ⁻ ) irradiation of 4.3×10 ⁸ e ⁻ /nm ² . From FIGS. 28(A) and 28(B), a-like O
From the start of the electron irradiation, it can be seen that stripe-like bright regions extending in the longitudinal direction are observed in S. Also, it can be seen that the shape of the bright region changes after electron irradiation. The bright regions are presumed to be void or low-density regions.

Due to the voids, the a-like OS is an unstable structure. Below, a-lik
Structural changes upon electron irradiation are shown to show that e OS is structurally unstable compared to CAAC-OS and nc-OS.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. All samples are In--Ga--Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. A high-resolution cross-sectional TEM image shows that each sample has a crystal part.

Note that the unit cell of the InGaZnO ₄ crystal has three In—O layers, and the Ga—Zn
It is known to have a structure in which a total of nine layers, including six −O layers, are layered in the c-axis direction. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, which is found to be 0.29 nm from crystal structure analysis. therefore,
In the following, InGaZ
It was regarded as the crystalline part of _nO4 . The lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 29 shows an example of investigating the average size of crystal parts (22 to 30 points) of each sample. The length of the lattice fringes described above is the size of the crystal part. From FIG. 29, a-lik
It can be seen that in the e OS, the crystal part grows in size according to the cumulative dose of electrons used for obtaining a TEM image. From FIG. 29, the crystal part (also referred to as the initial nucleus), which had a size of about 1.2 nm at the initial stage of observation by TEM, was reduced to a cumulative dose of 4.2×10 ⁸ e of electrons (e ⁻ ).
It can be seen that the film grows to a size of about 1.9 nm at ⁻ /nm ² . On the other hand, n
In c-OS and CAAC-OS, the cumulative dose of electrons from the start of electron irradiation is 4.2 × 10
It can be seen that there is no change in the crystal part size in the range up to ⁸ e ⁻ /nm ² . Figure 29
From this, it can be seen that the sizes of the crystal parts of the nc-OS and the CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative dose of electrons. For electron beam irradiation and TEM observation, Hitachi transmission electron microscope H-9000NAR was used. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7×10 ⁵ e ⁻ /(nm ² ·s), and a diameter of the irradiated region of 230 nm.

Thus, in the a-like OS, the growth of the crystal part may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of crystal parts due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and CAAC-OS.

In addition, since it has voids, the a-like OS has a lower density structure than the nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Also, the density of nc-OS and CAA
The density of C—OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor with a density of less than 78% of the single crystal.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio],
The density of single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ³ . . Further, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g/cm 3 or more and 6.3 g/cm ³ or more. cm
less than ³ .

If single crystals with the same composition do not exist, the density corresponding to a single crystal with a desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio.
The density corresponding to a single crystal with a desired composition can be estimated using a weighted average for the ratio of single crystals with different compositions combined. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics.
Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS
, and CAAC-OS.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, or reference examples.

(Embodiment 4)
In this embodiment, a display device including a semiconductor device of one embodiment of the present invention and an electronic device in which an input device is attached to the display device will be described with reference to FIGS.

<4-1. Explanation of the touch panel>
Note that in this embodiment, a touch panel 2000 including a display device and an input device will be described as an example of an electronic device. Also, a case where a touch sensor is used as an example of an input device will be described.

30A and 30B are perspective views of the touch panel 2000. FIG. Note that FIG. 30(A) (
In B), representative components of the touch panel 2000 are shown for clarity.

The touch panel 2000 has a display device 2501 and a touch sensor 2595 (see FIG. 3).
1(B)). The touch panel 2000 also includes a substrate 2510 , a substrate 2570 , and a substrate 2590 . Note that the substrates 2510, 2570, and 2590 are all flexible. However, any one or all of the substrates 2510, 2570, and 2590 may have no flexibility.

The display device 2501 has a plurality of pixels over a substrate 2510 and a plurality of wirings 2511 capable of supplying signals to the pixels. A plurality of wirings 2511 are routed to the outer peripheral portion of the substrate 2510 and some of them constitute terminals 2519 . Terminal 2519 is FPC2509
(1) is electrically connected.

A substrate 2590 has a touch sensor 2595 and a plurality of wirings 2598 electrically connected to the touch sensor 2595 . A plurality of wirings 2598 are routed around the outer peripheral portion of the substrate 2590, and some of them constitute terminals. This terminal is then electrically connected to the FPC 2509(2). Note that in FIG. 30B, for clarity, the back side of the substrate 2590 (the substrate 2510
The electrodes, wirings, and the like of the touch sensor 2595 provided on the surface opposite to ) are indicated by solid lines.

As the touch sensor 2595, for example, a capacitive touch sensor can be applied. The capacitance method includes a surface capacitance method, a projected capacitance method, and the like.

Projected capacitance methods include a self-capacitance method, a mutual capacitance method, and the like, mainly depending on the difference in driving method. It is preferable to use the mutual capacitance method because it enables simultaneous multi-point detection.

Note that the touch sensor 2595 illustrated in FIG. 30B has a structure using a projected capacitive touch sensor.

As the touch sensor 2595, various sensors capable of detecting proximity or contact of a detected object such as a finger can be applied.

A projected capacitive touch sensor 2595 has an electrode 2591 and an electrode 2592 . The electrode 2591 is electrically connected to one of the multiple wirings 2598 , and the electrode 2592 is electrically connected to the other one of the multiple wirings 2598 .

As shown in FIGS. 30A and 30B, the electrode 2592 has a shape in which a plurality of quadrangles arranged repeatedly in one direction are connected at corners.

The electrodes 2591 are quadrangular and are repeatedly arranged in a direction crossing the direction in which the electrodes 2592 extend.

A wiring 2594 is electrically connected to two electrodes 2591 sandwiching the electrode 2592 . At this time, it is preferable to have a shape in which the area of the intersection of the electrode 2592 and the wiring 2594 is as small as possible. As a result, the area of the region where no electrode is provided can be reduced, and variations in transmittance can be reduced. As a result, variations in luminance of light transmitted through the touch sensor 2595 can be reduced.

Note that the shape of the electrode 2591 and the electrode 2592 is not limited to this, and can take various shapes. For example, a plurality of electrodes 2591 may be arranged with as few gaps as possible, and a plurality of electrodes 2592 may be provided with an insulating layer interposed therebetween so as to leave a region that does not overlap with the electrodes 2591 . At this time, it is preferable to provide a dummy electrode electrically insulated between two adjacent electrodes 2592 because the area of the regions with different transmittances can be reduced.

As a material that can be used for the conductive films such as the electrodes 2591, the electrodes 2592, and the wirings 2598, that is, the wirings and electrodes that constitute the touch panel, a transparent conductive film containing indium oxide, tin oxide, zinc oxide, or the like (for example, ITO etc.). In addition, as a material that can be used for wiring and electrodes constituting a touch panel, for example, a material having a low resistance value is preferable. As an example, silver, copper, aluminum, carbon nanotubes, graphene, metal halides (such as silver halide), and the like may be used. In addition, it was made very thin (e.g.,
Metal nanowires, such as those constructed using a plurality of conductors (a few nanometers in diameter), may also be used. Alternatively, a metal mesh in which a conductor is meshed may be used. As an example, Ag
Nanowires, Cu nanowires, Al nanowires, Ag mesh, Cu mesh, Al mesh, etc. may be used. For example, when Ag nanowires are used for wiring and electrodes constituting a touch panel, the visible light transmittance is 89% or more, and the sheet resistance value is 40Ω/□ or more.
It can be 0Ω/□ or less. In addition, metal nanowires, metal meshes, carbon nanotubes, graphene, etc., which are examples of materials that can be used for the wiring and electrodes that constitute the touch panel described above, have high transmittance in visible light.
For example, it may be used as a pixel electrode or a common electrode).

<4-2. Explanation of display device>
Next, details of the display device 2501 are described with reference to FIG. Figure 31 (A
) corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 shown in FIG.

The display device 2501 has a plurality of pixels arranged in matrix. The pixel has a display element and a pixel circuit that drives the display element.

A structure using an EL element as a display element will be described below with reference to FIG. Note that in the following description, the case of applying an EL element that emits white light is described, but the EL element is not limited to this. For example, EL elements emitting light of different colors may be used so that adjacent pixels emit different colors of light.

For example, the substrate 2510 and the substrate 2570 have a water vapor permeability of 10 ⁻⁵ g/(m
² ·day) or less, preferably 10 ⁻⁶ g/(m ² ·day) or less can be suitably used. Alternatively, it is preferable to use a material in which the coefficient of thermal expansion of the substrate 2510 and the coefficient of thermal expansion of the substrate 2570 are approximately the same. For example, if the coefficient of linear expansion is 1×10 ^−
3 /K or less, preferably 5×10 ⁻⁵ /K or less, more preferably 1×10 ⁻⁵ /K or less, can be suitably used.

Note that the substrate 2510 includes an insulating layer 2510a that prevents diffusion of impurities into the EL element, a flexible substrate 2510b, and an adhesive layer 2 that bonds the insulating layer 2510a and the flexible substrate 2510b together.
510c. In addition, the substrate 2570 is a laminate having an insulating layer 2570a that prevents diffusion of impurities into the EL element, a flexible substrate 2570b, and an adhesive layer 2570c that bonds the insulating layer 2570a and the flexible substrate 2570b together. .

As the adhesive layer 2510c and the adhesive layer 2570c, for example, a material containing polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, or resin having a siloxane bond can be used.

A sealing layer 2560 is provided between the substrates 2510 and 2570 . encapsulation layer 2560
preferably has a refractive index greater than that of air. In addition, as shown in FIG. 31A, when light is extracted to the sealing layer 2560 side, the sealing layer 2560 can also serve as an optical element.

In addition, a sealing material may be formed on the outer peripheral portion of the sealing layer 2560 . By using the sealant, the EL element 2550 can be provided in a region surrounded by the substrate 2510, the substrate 2570, the sealing layer 2560, and the sealant. Note that the sealing layer 2560 may be filled with an inert gas (nitrogen, argon, or the like). Also, a drying material may be provided in the inert gas to adsorb moisture or the like. Moreover, it is preferable to use, for example, an epoxy resin or a glass frit as the sealing material. Moreover, as a material used for the sealing material, it is preferable to use a material that does not transmit moisture or oxygen.

A display device 2501 illustrated in FIG. 31A includes pixels 2505 . Also, pixel 2
505 has a light emitting module 2580, an EL element 2550, and a transistor 2502t that can power the EL element 2550. FIG. Note that the transistor 250
2t functions as part of the pixel circuit.

Further, the light-emitting module 2580 has an EL element 2550 and a colored layer 2567 .
In addition, the EL element 2550 includes a lower electrode, an upper electrode, and an EL element between the lower electrode and the upper electrode.
layer.

In addition, when the sealing layer 2560 is provided on the side from which light is extracted, the sealing layer 2560 has an E
It is in contact with the L element 2550 and the coloring layer 2567 .

The colored layer 2567 is positioned so as to overlap with the EL element 2550 . As a result, the EL element 25
Part of the light emitted by 50 is transmitted through the colored layer 2567 and emitted to the outside of the light emitting module 2580 in the direction of the arrow shown in the drawing.

In addition, the display device 2501 is provided with a light-blocking layer 2568 in the direction in which light is emitted. A light shielding layer 2568 is provided so as to surround the colored layer 2567 .

The colored layer 2567 may have a function of transmitting light in a specific wavelength band. For example, a color filter that transmits light in a red wavelength band, a color filter that transmits light in a green wavelength band, A color filter that transmits light in the blue wavelength band, a color filter that transmits light in the yellow wavelength band, or the like can be used. Each color filter can be formed using various materials by a printing method, an inkjet method, an etching method using a photolithographic technique, or the like.

In addition, the display device 2501 is provided with an insulating layer 2521 . An insulating layer 2521 covers the transistor 2502t and the like. Note that the insulating layer 2521 has a function of planarizing unevenness caused by the pixel circuit. Further, the insulating layer 2521 may have a function of suppressing diffusion of impurities. As a result, deterioration in reliability of the transistor 2502t and the like due to impurity diffusion can be suppressed.

Also, the EL element 2550 is formed above the insulating layer 2521 . Also, the EL element 25
The lower electrode of 50 is provided with a partition wall 2528 that overlaps the edge of the lower electrode. Note that a spacer that controls the distance between the substrate 2510 and the substrate 2570 may be formed over the partition wall 2528 .

The scan line driver circuit 2504 also includes a transistor 2503t and a capacitor 2503c. Note that the driver circuit and the pixel circuit can be formed over the same substrate in the same process.

A wiring 2511 capable of supplying a signal is provided over the substrate 2510 .
A terminal 2519 is provided over the wiring 2511 . In addition, the terminal 2519 has an FP
C2509(1) is electrically connected. Also, the FPC 2509 (1) is a video signal,
It has a function of supplying a clock signal, a start signal, a reset signal, and the like. Note that FPC2
A printed wiring board (PWB) may be attached to 509(1).

Note that the transistor described in any of the above embodiments may be applied to either one or both of the transistor 2502t and the transistor 2503t. The transistor used in this embodiment includes a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The transistor can have a low current value in an off state (off current value). Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long in the power-on state. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption. In addition, since the transistor used in this embodiment mode has relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in the display device 2501, a switching transistor of a pixel circuit and a driver transistor used in a driver circuit can be formed over the same substrate.
That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. Also in a pixel circuit, a high-quality image can be provided by using a transistor that can be driven at high speed.

<4-3. Explanation of Touch Sensor>
Next, details of the touch sensor 2595 are described with reference to FIG. Figure 31
(B) corresponds to a cross-sectional view taken along the dashed-dotted line X3-X4 shown in FIG. 30(B).

The touch sensor 2595 includes electrodes 2591 and electrodes 2591 and 2591 staggered on the substrate 2590 .
592, an insulating layer 2593 covering the electrodes 2591 and 2592, and an adjacent electrode 259
1 and a wiring 2594 for electrically connecting 1 to each other.

The electrodes 2591 and 2592 are formed using a light-transmitting conductive material. As the light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or gallium-added zinc oxide can be used. Note that a film containing graphene can also be used. A film containing graphene can be formed, for example, by reducing a film containing graphene oxide. Examples of the method of reduction include a method of applying heat.

For example, after a light-transmitting conductive material is deposited over the substrate 2590 by a sputtering method, unnecessary portions are removed by various patterning techniques such as photolithography to form the electrodes 2591 and 2592. be able to.

As a material used for the insulating layer 2593, for example, an inorganic insulating material such as silicon oxide, silicon oxynitride, or aluminum oxide can be used in addition to a resin such as acrylic or epoxy resin and a resin having a siloxane bond.

An opening reaching the electrode 2591 is provided in the insulating layer 2593 and the wiring 2594 is electrically connected to the adjacent electrode 2591 . A light-transmitting conductive material can increase the aperture ratio of the touch panel, and thus can be preferably used for the wiring 2594 . Also, the electrode 259
1 and the electrode 2592 can be preferably used for the wiring 2594 because the electrical resistance can be reduced.

The electrodes 2592 extend in one direction, and a plurality of electrodes 2592 are provided in stripes. Also, the wiring 2594 is provided to cross the electrode 2592 .

A pair of electrodes 2591 are provided with one electrode 2592 interposed therebetween. A wiring 2594 electrically connects the pair of electrodes 2591 .

It should be noted that the plurality of electrodes 2591 do not necessarily have to be arranged in a direction orthogonal to one electrode 2592, and may be arranged so as to form an angle of more than 0 degrees and less than 90 degrees.

In addition, wiring 2598 is electrically connected to electrode 2591 or electrode 2592 . Part of the wiring 2598 functions as a terminal. As the wiring 2598, for example, a metal material such as aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy material containing the metal material can be used. can.

Note that an insulating layer covering the insulating layer 2593 and the wiring 2594 is provided so that the touch sensor 2595
may be protected.

Also, the connection layer 2599 electrically connects the wiring 2598 and the FPC 2509(2).

As the connection layer 2599, an anisotropic conductive film (ACF: Anisotropic C
inductive Film) and anisotropic conductive paste (ACP: Anisotrop
IC Conductive Paste) or the like can be used.

<4-4. Explanation of the touch panel>
Next, details of the touch panel 2000 will be described with reference to FIG. Figure 32
(A) corresponds to a cross-sectional view taken along the dashed-dotted line X5-X6 shown in FIG. 30(A).

The touch panel 2000 shown in FIG. 32(A) is the display device 250 described in FIG. 31(A).
1 and the touch sensor 2595 described with reference to FIG.

Further, the touch panel 2000 shown in FIG. 32A has an adhesive layer 2597 and an antireflection layer 2569 in addition to the structure described in FIG.

The adhesive layer 2597 is provided in contact with the wiring 2594 . Note that the adhesive layer 2597 bonds the substrate 2590 to the substrate 2570 so that the touch sensor 2595 overlaps with the display device 2501 . Further, the adhesive layer 2597 preferably has a light-transmitting property. Also, the adhesive layer 2
As 597, a thermosetting resin or an ultraviolet curable resin can be used. for example,
Acrylic resin, urethane resin, epoxy resin, or siloxane resin can be used.

The antireflection layer 2569 is provided at a position overlapping with the pixels. As the antireflection layer 2569,
For example, a circularly polarizing plate can be used.

Next, a touch panel having a structure different from that shown in FIG. 32A will be described with reference to FIG.

FIG. 32B is a cross-sectional view of the touch panel 2001. FIG. A touch panel 2001 shown in FIG. 32B differs from the touch panel 2000 shown in FIG. Here, different configurations are described in detail, and the description of the touch panel 2000 is used for portions where the same configurations can be used.

Colored layer 2567 is located below EL element 2550 . Moreover, E shown in FIG.
The L element 2550 emits light to the side where the transistor 2502t is provided. As a result, part of the light emitted by the EL element 2550 is transmitted through the colored layer 2567 and emitted to the outside of the light emitting module 2580 in the direction of the arrow shown in the drawing.

A touch sensor 2595 is provided on the substrate 2510 side of the display device 2501 .

An adhesive layer 2597 is between the substrates 2510 and 2590 and bonds the display device 2501 and the touch sensor 2595 together.

As shown in FIGS. 32A and 32B, light emitted from the light-emitting element may be emitted through one or both of the substrate 2510 and the substrate 2570. FIG.

<4-5. Explanation of Touch Panel Driving Method>
Next, an example of a method for driving the touch panel will be described with reference to FIG. 33 .

FIG. 33A is a block diagram showing a configuration of a mutual capacitance touch sensor. Figure 33
(A) shows a pulse voltage output circuit 2601 and a current detection circuit 2602 . note that,
In FIG. 33A, X1 to X6 are electrodes 2621 to which a pulse voltage is applied, and Y1 to Y6 are electrodes 2622 that detect a change in current, respectively, and six wirings are illustrated. FIG. 33A shows a capacitor 2603 formed by overlapping the electrode 2621 and the electrode 2622. FIG. Note that the functions of the electrodes 2621 and 2622 may be replaced with each other.

The pulse voltage output circuit 2601 is a circuit for sequentially applying a pulse voltage to the wirings of X1 to X6. An electric field is generated between the electrodes 2621 and 2622 forming the capacitor 2603 by applying a pulse voltage to the wiring of X1 to X6. The electric field generated between the electrodes causes a change in the mutual capacitance of the capacitor 2603 due to shielding or the like, and this can be used to detect the proximity or contact of the object to be sensed.

A current detection circuit 2602 is a circuit for detecting a change in current in the wiring Y1-Y6 due to a change in mutual capacitance in the capacitor 2603. FIG. In the wiring of Y1-Y6, the proximity of the object to be detected,
Alternatively, if there is no contact, there is no change in the detected current value, but if the mutual capacitance decreases due to the proximity or contact of the object to be detected, a change in which the current value decreases is detected. Note that current detection may be performed using an integrating circuit or the like.

Next, FIG. 33B shows a timing chart of input/output waveforms in the mutual capacitance touch sensor shown in FIG. In FIG. 33(B), it is assumed that the detected object is detected in each matrix in one frame period. In addition, in FIG. 33B, when the object to be detected is not detected (
Two cases are shown: non-touch) and detection of an object to be detected (touch). For the wiring Y1-Y6, waveforms are shown with voltage values corresponding to the detected current values.

A pulse voltage is sequentially applied to the wirings of X1-X6, and according to the pulse voltage, Y1-
The waveform at the wiring of Y6 changes. When there is no proximity or contact with the object to be detected, X1-X6
The waveforms of Y1-Y6 uniformly change according to the change in the voltage of the wiring. On the other hand, since the current value decreases at the location where the object to be detected approaches or touches, the waveform of the corresponding voltage value also changes.

By detecting the change in mutual capacitance in this manner, the proximity or contact of the object to be detected can be detected.

<4-6. Description of Sensor Circuit>
Although FIG. 33A shows a structure of a passive touch sensor in which only the capacitor 2603 is provided at the intersection of wirings as a touch sensor, an active touch sensor including a transistor and a capacitor may be used. FIG. 34 shows an example of a sensor circuit included in an active touch sensor.

The sensor circuit shown in FIG. 34 has a capacitor 2603 , a transistor 2611 , a transistor 2612 and a transistor 2613 .

A transistor 2613 has a gate to which a signal G2 is applied, a source or a drain to which a voltage VRES is applied, and a transistor 2613 to which one electrode of the capacitor 2603 and the transistor 2611 are connected.
electrically connected to the gate of Transistor 2611 has one of its source and drain electrically connected to one of source and drain of transistor 2612 and the other to voltage VS.
S is given. The transistor 2612 has a gate supplied with a signal G1, and the other of the source and the drain is electrically connected to the wiring ML. Voltage VS is applied to the other electrode of capacitor 2603
S is given.

Next, the operation of the sensor circuit shown in FIG. 34 will be described. First, when a potential for turning on the transistor 2613 is applied as the signal G2, a potential corresponding to the voltage VRES is applied to the node n to which the gate of the transistor 2611 is connected. Next, a potential for turning off the transistor 2613 is applied as the signal G2, so that the potential of the node n is held.

Subsequently, the potential of the node n changes from VRES as the mutual capacitance of the capacitor 2603 changes due to the proximity or contact of an object to be detected such as a finger.

A read operation provides a potential to turn on the transistor 2612 as the signal G1. The current flowing through the transistor 2611, that is, the current flowing through the wiring ML changes according to the potential of the node n. By detecting this current, it is possible to detect the proximity or contact of the object to be detected.

The transistors described in the above embodiments can be applied to the transistors 2611 , 2612 , and 2613 . In particular, by using the transistor described in any of the above embodiments as the transistor 2613, the potential of the node n can be held for a long time, and the frequency of operation (refresh operation) to resupply VRES to the node n can be increased. can be reduced.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments, examples, or reference examples.

(Embodiment 5)
In this embodiment, structural examples of an input/output device (touch panel), an input device (touch sensor), and an output device (display panel) that can be applied to the semiconductor device in the above embodiments will be described.

<5-1. Configuration example of touch panel>
FIG. 35A is a schematic perspective view of the touch panel 600. FIG. Moreover, FIG. 35(B) shows the
5(A) is an exploded perspective schematic view; FIG. For clarity, only representative components are shown. In addition, in FIG. 35B, only the contours of some components (substrate 602, etc.) are indicated by dashed lines.

The touch panel 600 has a substrate 601 and a substrate 602, which are stacked on top of each other.

35A and 35B, the input device 610 includes a substrate 602, a plurality of electrodes 631, a plurality of electrodes 632, a plurality of wirings 652, a plurality of wirings 653, an FPC (flexible printed circuit board).
ted Circuit) 650 and IC 651.

As the input device 610, for example, a capacitive touch sensor can be applied. The capacitance method includes a surface capacitance method, a projected capacitance method, and the like. As for the projected electrostatic capacitance method, there are a self-capacitance method, a mutual capacitance method, and the like, depending mainly on the difference in the driving method. It is preferable to use the mutual capacitance method because it enables simultaneous multi-point detection. A case where a projected capacitive touch sensor is applied will be described below.

Note that the input device 610 is not limited to this, and various sensors capable of detecting the proximity or contact of an object to be detected such as a finger or a stylus can be applied to the input device 610 .

A display portion 662 , a driver circuit 663 , a wiring 664 , and the like are provided over the substrate 601 .
Further, the substrate 601 is provided with an FPC 660 electrically connected to the wiring 664 .
35A and 35B show an example in which an IC 661 is provided on the FPC 660. FIG.

The display portion 662 has at least a plurality of pixels. A pixel has at least one display element. Also, the pixel preferably comprises a transistor and a display element. As the display element, typically, a light-emitting element such as an organic EL element can be used.

For the driver circuit 663, a circuit that functions as a gate line driver circuit, a signal line driver circuit, or the like can be used, for example.

The wiring 664 has a function of supplying signals and power to the display portion 662 and the driver circuit 663 .
The signal and power are input to the wiring 664 from the outside through the FPC 660 or from the IC 661 .

35A and 35B, a COF (Chip On Film) is mounted on the FPC 660
) shows an example in which an IC 661 mounted by the method is provided. For the IC 661, for example, an IC having a function as a gate line driver circuit, a signal line driver circuit, or the like can be applied. Note that in the case where the touch panel 600 includes a circuit that functions as a gate line driver circuit and a signal line driver circuit, or a circuit that functions as a gate line driver circuit and a signal line driver circuit is provided externally,
When a signal for driving the touch panel 600 is input through the FPC 660, the IC 661 may not be provided. Also, the IC661 is a COG (Chip O
n Glass) method or the like may be directly mounted on the substrate 601 .

<5-2. Configuration example of input device>
A configuration example of the input device (touch sensor) will be described below with reference to the drawings.

FIG. 36A shows a schematic top view of the input device 610. FIG. The input device 610 includes a substrate 602
A plurality of electrodes 631, a plurality of electrodes 632, a plurality of wirings 652, and a plurality of wirings 653 are provided thereon. Further, the substrate 602 is provided with an FPC 650 electrically connected to each of the plurality of wirings 652 and the plurality of wirings 653 . Also, in FIG. 36(A), IC65 is connected to FPC650.
1 is shown.

FIG. 36(B) shows an enlarged view of a region surrounded by a dashed line in FIG. 36(A). electrode 631
has a shape in which a plurality of rhombic electrode patterns are arranged in a horizontal direction. The diamond-shaped electrode patterns arranged in a row are electrically connected to each other. Likewise, the electrode 632 has a shape in which a plurality of rhombic electrode patterns are arranged in a vertical direction, and the rhombic electrode patterns arranged in a row are electrically connected to each other. Moreover, the electrode 631 and the electrode 632 partially overlap each other and cross each other. An insulator is sandwiched at this intersection so that the electrodes 631 and 632 are not electrically short-circuited.

Alternatively, as shown in FIG. 36C, the electrode 632 may be composed of a plurality of rhombic electrodes 633 and a bridge electrode 634 . The island-shaped electrodes 633 are arranged side by side in the vertical direction, and two adjacent electrodes 633 are electrically connected by a bridge electrode 634 . With such a structure, the electrodes 633 and 631 can be formed at the same time by processing the same conductive film. Therefore, variations in film thickness of these electrodes can be suppressed, and variation in the resistance value and light transmittance of each electrode depending on location can be suppressed. Although the electrode 632 has the bridge electrode 634 here, the electrode 631 may have such a structure.

Further, as shown in FIG. 36D, the inside of the rhombic electrode pattern of the electrodes 631 and 632 shown in FIG.
At this time, if the widths of the electrodes 631 and 632 are so thin as to be invisible to the user, the electrodes 631 and 632 may be made of a light-shielding material such as a metal or an alloy, as will be described later. Moreover, the electrode 631 or the electrode 632 shown in FIG.
34 may be used.

One electrode 631 is electrically connected to one wiring 652 . Also one electrode 63
2 is electrically connected to one wiring 653 . Here, one of the electrodes 631 and 632 corresponds to the row wiring, and the other corresponds to the column wiring.

The IC 651 has a function of driving the touch sensor. A signal output from the IC 651 is supplied to either the electrode 631 or the electrode 632 via the wiring 652 or 653 . A current (or potential) flowing through either the electrode 631 or the electrode 632 is input to the IC 651 through the wiring 652 or 653 .

Here, in the case where a touch panel is formed by overlapping the input device 610 on the display surface of the display panel, it is preferable to use a light-transmitting conductive material for the electrodes 631 and 632 .
Further, in the case where a light-transmitting conductive material is used for the electrodes 631 and 632 and light from the display panel is extracted through the electrodes 631 and 632, the same conductive material is formed between the electrodes 631 and 632. It is preferable to dispose a conductive film containing a conductive material as a dummy pattern. By partially filling the gap between the electrode 631 and the electrode 632 with the dummy pattern in this manner, variations in light transmittance can be reduced. As a result, it is possible to reduce luminance unevenness of light passing through the input device 610 .

As the light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or gallium-added zinc oxide can be used. Note that a film containing graphene can also be used. A film containing graphene can be formed, for example, by reducing a film containing graphene oxide. Examples of the method of reduction include a method of applying heat.

Alternatively, a metal or alloy thin enough to transmit light can be used. For example, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, and alloy materials containing such metal materials can be used. Alternatively, a nitride (for example, titanium nitride) of the metal material or alloy material may be used. Alternatively, a stacked film in which two or more of the conductive films containing any of the above materials are stacked may be used.

For the electrodes 631 and 632, a conductive film processed to be thin enough to be invisible to the user may be used. For example, by processing such a conductive film into a lattice shape (mesh shape), high conductivity and high visibility of the display device can be obtained. At this time, the conductive film is 30
nm or more and 100 μm or less, preferably 50 nm or more and 50 μm or less, more preferably 50 nm
It is preferable to have a portion with a width of m or more and 20 μm or less. In particular, a conductive film having a pattern width of 10 μm or less is preferable because it is extremely difficult for the user to visually recognize it.

As an example, FIGS. 37A to 37D show enlarged schematic diagrams in the case of using a grid-like (mesh-like) conductive film or nanowires for the electrode 631 or the electrode 632 .

FIG. 37A shows an example in which a grid-like conductive film 635 is used. At this time, it is preferable to arrange the display element included in the display device so that the conductive film 635 does not overlap with the conductive film 635 because light from the display element is not blocked. In this case, it is preferable that the direction of the grating is the same as that of the arrangement of the display elements, and the period of the grating is an integral multiple of the period of the arrangement of the display elements.

Further, FIG. 37B shows an example of a grid-like conductive film 636 processed to form triangular openings. With such a structure, the resistance can be made lower than in the case shown in FIG. 37(A).

Moreover, as shown in FIG. 37C, a conductive film 63 having a non-periodic pattern shape
7 may be used. By adopting such a structure, it is possible to suppress the occurrence of moire when overlapping with the display portion of the display device.

Alternatively, conductive nanowires may be used for the electrodes 631 and 632 . Figure 37 (D
) shows an example in which nanowires 638 are used. By dispersing the nanowires 638 at an appropriate density so that the adjacent nanowires 638 are in contact with each other, a two-dimensional network is formed and can function as a conductive film with extremely high translucency. For example, the average diameter is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, more preferably 5 nm
Nanowires greater than or equal to 25 nm and less than or equal to 25 nm can be used. Ag
Nanowires, metal nanowires such as Cu nanowires and Al nanowires, or carbon nanotubes can be used.

The above is the description of the input device.

<5-3. Example of cross-sectional configuration>
Next, an example of the cross-sectional configuration of the touch panel 600 will be described with reference to the drawings. Figure 3
8 is a schematic cross-sectional view of the touch panel 600. FIG. In FIG. 38, FP in FIG. 35(A)
An area including C660, an area including driver circuit 663, an area including display portion 662, and FPC
Each cross-section of the area containing 650 is shown.

The substrate 601 and the substrate 602 are bonded together by an adhesive layer 603 .

Between the substrate 601 and the substrate 602, a transistor 611, a driving transistor 612,
A selection transistor 613, a display element 614, a capacitor element 615, a connection portion 616, and a wiring 617
etc. are provided.

An insulating layer 621 , an insulating layer 622 , an insulating layer 623 , an insulating layer 624 , an insulating layer 625 , a spacer 626 , and the like are provided over the substrate 601 . Part of the insulating layer 621 functions as a gate insulating layer of each transistor, and another part functions as a dielectric of the capacitor 615 . An insulating layer 622, an insulating layer 623, and an insulating layer 624 are provided to cover each transistor, the capacitor 615, and the like. The insulating layer 624 functions as a planarization layer.
Note that here, the case where three insulating layers, the insulating layer 622, the insulating layer 623, and the insulating layer 624, are provided as the insulating layers that cover the transistor or the like is shown; It may be a single layer or two layers. Further, the insulating layer 624 functioning as a planarization layer may be omitted if unnecessary.

A display element 614 is provided over the insulating layer 624 . Here, an example in which a top emission type organic EL element is applied as the display element 614 is shown. A driving transistor 612 and a selection transistor 61 overlap with the light emitting region of the display element 614 .
3. The aperture ratio of the display portion 662 can be increased by overlapping the capacitor 615 and the wiring.

A display element 614 has an EL layer 642 between a first electrode 641 and a second electrode 643 . An optical adjustment layer 644 is provided between the first electrode 641 and the EL layer 642 . The insulating layer 625 is provided to cover the ends of the first electrode 641 and the optical adjustment layer 644 .

FIG. 38 shows a cross section of one pixel as an example of the display portion 662 . Here, the case where a pixel has a driving transistor 612, a selection transistor 613, and a capacitor 615 is shown. One of the source or drain of the driving transistor 612 and the capacitive element 6
15 is electrically connected to the first electrode 641 through openings provided in the insulating layers 622 , 623 , and 624 .

In addition, FIG. 38 shows a structure in which a transistor 611 is provided as an example of the driver circuit 663 .

FIG. 38 shows an example in which a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gate electrodes is applied to the transistor 611 and the driving transistor 612 .

Note that the transistors provided in the driver circuit 663 and the display portion 662 may have the same structure, or a combination of transistors with different structures.

A spacer 626 is provided over the insulating layer 625 and has a function of adjusting the distance between the substrate 601 and the substrate 602 . Also, a granular spacer may be used instead of the spacer 626 .

A connection portion 616 is provided in a region near the edge of the substrate 601 . The connection portion 616 is electrically connected to the FPC 660 via the connection layer 656 .

Electrodes and the like forming a touch sensor are provided on the substrate 601 side surface of the substrate 602 .
Specifically, an electrode 632 , an electrode 633 , a wiring 652 (not shown), a wiring 653 and the like are provided on the substrate 602 , an insulating layer 674 covering these, and a bridge electrode 634 and the like are provided on the insulating layer 674 . An insulating layer 673 is provided to cover the electrodes and the like that constitute the touch sensor. Further, a colored layer 671 , a light shielding layer 672 , and the like are provided over the insulating layer 673 .
The light shielding layer 672 has an opening and is arranged so that the opening overlaps with the display region of the display element 614 .

Here, an example in which the electrode 631 has an electrode 633 and a bridge electrode 634 is shown. As indicated by intersections 665 in FIG. 38, electrodes 632 and 633 are formed on the same plane. A bridge electrode 634 is provided over an insulating layer 674 that covers the electrodes 632 and 633 . The bridge electrode 634 is electrically connected to two electrodes 633 provided to sandwich the electrode 632 through an opening provided in the insulating layer 674 .

Also, here, an example in which the electrode 633 has a mesh (lattice) shape is shown.
At this time, it is preferable that the opening of the electrode 633 overlaps with the display region of the display element 614 because the electrode 633 does not block light from the display element 614 . Note that the electrodes 632 and the bridge electrodes 634 also preferably have a mesh shape.

A connection portion 654 is provided in a region near the edge of the substrate 602 . The connecting portion 654 is
The FPC 650 is electrically connected via the connection layer 655 .

The touch panel shown in FIG. 39 has a laminated structure of a substrate 681 , an adhesive layer 682 , and an insulating layer 683 instead of the substrate 601 . Further, instead of the substrate 602, a substrate 691 and an adhesive layer 692
, and an insulating layer 694 .

By using a flexible material for the substrates 681 and 691, a bendable touch panel can be realized.

<5-4. Example of manufacturing method>
Here, a method for manufacturing a flexible touch panel will be described.

Here, for the sake of convenience, a structure including pixels and circuits, a structure including optical members such as color filters, a structure including electrodes and wirings forming a touch sensor, and the like are referred to as element layers. The element layer includes, for example, a display element, and in addition to the display element, wiring electrically connected to the display element, and elements such as transistors used for pixels and circuits may be provided.

Also, a support having an insulating surface on which an element layer is formed (for example, the substrate 681 in FIG. 39)
Alternatively, the substrate 691) is called a substrate.

Methods for forming an element layer on a substrate having a flexible insulating surface include a method of forming an element layer directly on the substrate, and a method of forming an element layer on a supporting substrate different from the substrate, and then forming an element layer on the substrate. and detaching the layer from the supporting substrate and transferring the device layer to the substrate.

In the case where the material forming the substrate has heat resistance against the heat applied in the process of forming the element layer, it is preferable to form the element layer directly on the substrate because the process is simplified. At this time, it is preferable to form the element layer in a state where the substrate is fixed to the supporting base material, because it facilitates transportation within and between apparatuses.

In the case of using a method of forming an element layer on a supporting base material and then transferring it to a substrate, first, a release layer and an insulating layer are laminated on the supporting base material, and the element layer is formed on the insulating layer. Subsequently, the support base material and the element layer are peeled off and transferred to the substrate. At this time, a material that causes peeling at the interface between the support substrate and the release layer, at the interface between the release layer and the insulating layer, or within the release layer may be selected.

For example, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are stacked as a separation layer, and a layer in which multiple layers of silicon nitride or silicon oxynitride are stacked is used as an insulating layer over the separation layer. It is preferable to use The use of a high-melting-point metal material is preferable because it increases the degree of freedom in the process of forming the element layer.

The peeling may be performed by applying a mechanical force, etching the peeling layer, or dropping a liquid onto a portion of the peeling interface to permeate the entire peeling interface. Alternatively, separation may be performed by applying heat to the separation interface using the difference in thermal expansion.

Further, if the separation is possible at the interface between the support substrate and the insulating layer, the separation layer may not be provided.
For example, glass may be used as the supporting substrate, and an organic resin such as polyimide may be used as the insulating layer. In this case, by locally heating a part of the organic resin with a laser beam or the like to form a peeling starting point, the peeling can be performed at the interface between the glass and the insulating layer. Alternatively, a metal layer is provided between the supporting base material and the insulating layer made of an organic resin, and the metal layer is heated by passing an electric current through the metal layer, thereby performing separation at the interface between the metal layer and the insulating layer. may Alternatively, a layer of a light-absorbing material (metal, semiconductor, insulator, etc.) is provided between the support substrate and the insulating layer made of an organic resin, and the layer is irradiated with light such as laser light to locally A starting point of peeling may be formed by heating. In the method shown here, an insulating layer made of an organic resin can be used as a substrate.

Examples of flexible substrates include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, polyimide resins, polymethylmethacrylate resins, polycarbonate resins, and polyethersulfone (PES) resins. , polyamide resins, cycloolefin resins, polystyrene resins, polyamideimide resins, polyvinyl chloride resins, and the like. In particular, it is preferable to use a material with a low coefficient of thermal expansion. For example, polyamideimide resin, polyimide resin, PET, etc., having a coefficient of thermal expansion of 30×10 ⁻⁶ /K or less can be preferably used. A substrate (also referred to as a prepreg) in which a fibrous body is impregnated with a resin, or a substrate in which an inorganic filler is mixed with an organic resin to lower the coefficient of thermal expansion can also be used.

When a fibrous body is included in the material, the fibrous body uses high-strength fibers of an organic compound or an inorganic compound. High-strength fibers specifically refer to fibers having a high tensile modulus or Young's modulus, and representative examples include polyvinyl alcohol fibers, polyester fibers, polyamide fibers, polyethylene fibers, aramid fibers, Polyparaphenylenebenzobisoxazole fibers, glass fibers, or carbon fibers may be mentioned. Examples of glass fibers include glass fibers using E glass, S glass, D glass, Q glass, and the like. These may be used in the form of woven fabric or non-woven fabric, and a structure obtained by impregnating this fibrous body with a resin and curing the resin may be used as a flexible substrate. It is preferable to use a structure made of a fibrous body and a resin as the substrate having flexibility, because the reliability against damage due to bending or local pressure is improved.

Alternatively, a thin glass, metal, or the like having flexibility can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded together may be used.

For example, in the case of the structure shown in FIG. 39, after the first peeling layer and the insulating layer 683 are sequentially formed on the first supporting base material, the upper structure is formed. Separately from this, after the second peeling layer and the insulating layer 694 are formed in this order on the second support base material, the upper structure is formed. Subsequently, the first supporting base material and the second supporting base material are bonded with the adhesive layer 603 . After that, the second supporting base material and the second peeling layer are removed by peeling at the interface between the second peeling layer and the insulating layer 694 , and the insulating layer 694 and the substrate 691 are bonded with the adhesive layer 692 . again,
The first support base material and the first peeling layer are removed by peeling at the interface between the first peeling layer and the insulating layer 683 , and the insulating layer 683 and the substrate 681 are bonded with the adhesive layer 682 . Either side may be peeled off or attached first.

The above is the description of the method for manufacturing a flexible touch panel.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments, examples, or reference examples.

(Embodiment 6)
In this embodiment, examples of circuit structures to which the transistors described in the above embodiments can be applied will be described with reference to FIGS.

Note that in this embodiment, the transistor including an oxide semiconductor described in the above embodiment is referred to as an OS transistor in the following description.

<6. Inverter circuit configuration example>
FIG. 40A shows a circuit diagram of an inverter that can be applied to a shift register, a buffer, or the like included in a driver circuit. The inverter 800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN to the output terminal OUT. The inverter 800 has multiple OS transistors. The signal _SBG is a signal that can switch the electrical characteristics of the OS transistor.

FIG. 40B is a circuit diagram of an example of the inverter 800. As shown in FIG. The inverter 800 is
It has an OS transistor 810 and an OS transistor 820 . The inverter 800 can be manufactured as an n-channel type and can have a so-called unipolar circuit configuration. Since the inverter 800 can be manufactured with a unipolar circuit configuration, CMOS (Complementary
ry Metal Oxide Semiconductor) and an inverter (CMOS
Inverter) can be manufactured at low cost.

Note that the inverter 800 having an OS transistor can also be arranged on a CMOS inverter composed of Si transistors. Since the inverter 800 can be arranged so as to overlap the CMOS inverter, an increase in circuit area due to the addition of the inverter 800 can be suppressed.

The OS transistors 810 and 820 each have a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of the source and the drain, and a second terminal functioning as the other of the source and the drain. have

A first gate of the OS transistor 810 is connected to a second terminal of the OS transistor 810 . A second gate of OS transistor 810 is connected to a wiring for transmitting signal _SBG .
A first terminal of the OS transistor 810 is connected to a wiring that supplies voltage VDD. A second terminal of the OS transistor 810 is connected to the output terminal OUT.

A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. A first terminal of the OS transistor 820 is connected to the output terminal OUT. The second terminal of OS transistor 820 is at voltage VSS
is connected to the wiring that provides

FIG. 40C is a timing chart for explaining the operation of inverter 800. In FIG. The timing chart in FIG. 40C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal _SBG , and the threshold voltage of the OS transistor 810 (FET 810).

By applying the signal _SBG to the second gate of the OS transistor 810, the threshold voltage of the OS transistor 810 can be controlled.

For example, the signal S _BG has a voltage V _{BG_A} for negatively shifting the threshold voltage of the OS transistor 810 and a voltage V _{BG_B} for positively shifting the threshold voltage of the OS transistor 810 . By setting the signal S _BG to the voltage V _{BG_A} , OS
Transistor 810 goes to threshold voltage _{VTH_A} . Also, the signal S _BG is changed to the voltage V _{BG
_B} , the OS transistor 810 has the threshold voltage V _{TH_B} .

In order to explain the above concept, FIG. 41A shows a conceptual diagram of a Vg-Id curve of electrical characteristics of the OS transistor 810. FIG.

As shown in FIG. 41A, the signal S _BG is set to the voltage V _{BG_A} , and the OS transistor 81
Taking a threshold voltage of 0 as V _{TH_A} results in the curve represented by dashed line 840 . Further, a curve represented by a solid line 841 can be obtained by setting the signal _SBG to the voltage _{VBG_B} and the threshold voltage of the OS transistor 810 to _{VTH_B} . In other words,
Let _{VBG_B} be the voltage of the signal _SBG , and V be the threshold voltage of the OS transistor 810.
By setting _{TH_B} , a state in which current does not easily flow through the OS transistor 810 can be achieved. By setting the voltage of the signal _SBG to _{VBG_A} and the threshold voltage of the OS transistor 810 to _{VTH_A} , a current can easily flow through the OS transistor 810. FIG.

41B and 41C show circuit diagrams representing the above concept. FIG. 41B shows the case where the voltage of the signal _SBG is _{VBG_B} , and FIG. 41C shows the case where the voltage of the signal _SBG is _{VBG_A} .

As shown in FIG. 41B, the current _IB flowing through the OS transistor 810 can be made extremely small, so that when the signal applied to the input terminal IN is at a high level, the OS transistor 82
When 0 is in the ON state (ON), the voltage of the output terminal OUT can be sharply lowered.
Therefore, the signal waveform 831 of the output terminal OUT in the timing chart shown in FIG. 40(C) can be changed steeply. In addition, a wiring for applying voltage VDD and a wiring for applying voltage VSS
can be reduced, the inverter 800 can operate with low power consumption.

Also, as shown in FIG. 41C, the current _IA flowing through the OS transistor 810 is
Since the current is larger than the current _IB , when the signal applied to the input terminal IN is at low level and the OS transistor 820 is off (OFF), the voltage of the output terminal OUT can be sharply increased. Therefore, the signal waveform 832 of the output terminal OUT in the timing chart shown in FIG. 40(C) can be changed steeply.

Note that the control of the threshold voltage of the OS transistor 810 by the signal _SBG is preferably performed before the state of the OS transistor 820 is switched, that is, before the times T1 and T2. For example, as shown in FIG. 40C, before time T1 at which the signal applied to the input terminal IN switches to high level, the threshold voltage V _{TH_A} changes to the threshold voltage V _TH
It is preferable to switch the threshold voltage of the OS transistor 810 to _{_B} . In addition, Fig. 4
As shown in 0(C), the time T at which the signal applied to the input terminal IN switches to low level
2, it is preferable to switch the threshold voltage of OS transistor 810 from threshold voltage V _{TH_B} to threshold voltage V _{TH_A} .

Note that the timing chart in FIG. 40C shows a structure in which the signal _SBG is switched according to the signal applied to the input terminal IN, but another structure may be employed. For example, a voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 which is in a floating state. FIG. 42 shows an example of a circuit configuration that can realize this configuration.
(A).

In FIG. 42A, in addition to the circuit configuration shown in FIG. 40B, an OS transistor 850
have A first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810 . A second terminal of the OS transistor 850 is connected to a wiring that supplies the voltage V _{BG_B} (or the voltage V _{BG_A} ). A first gate of the OS transistor 850 is connected to a wiring that supplies the signal _SF . The second gate of OS transistor 850 is at voltage V _{BG
_B} (or voltage V _{BG_A} ) is connected to the wiring.

The operation of the circuit configuration shown in FIG. 42A will be described with reference to the timing chart of FIG. 42B.

A voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN switches to high level. The signal _SF is set to a high level to turn on the OS transistor 850, and the voltage _{VBG_B} for controlling the threshold voltage is applied to the node _NBG .

After the node _NBG reaches the voltage _{VBG_B} , the OS transistor 850 is turned off. Since the off-state current of the OS transistor 850 is extremely low, the voltage V _{BG_B} that was once held at the node N _BG can be held by keeping the off state. for that reason,
Since the number of operations for applying the voltage V _{BG_B} to the second gate of the OS transistor 850 is reduced,
The power consumption required for rewriting the voltage _{VBG_B} can be reduced.

Note that although the circuit configurations of FIGS. 40B and 42A show the configurations in which the voltage to be applied to the second gate of the OS transistor 810 is externally controlled, another configuration may be employed. For example, a voltage for controlling the threshold voltage may be generated based on a signal applied to the input terminal IN and applied to the second gate of the OS transistor 810 . FIG. 43A shows an example of a circuit configuration that can realize this configuration.

43A, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit configuration shown in FIG. 40B. The input terminal of CMOS inverter 860 is connected to input terminal IN. The output terminal of CMOS inverter 860 is connected to the second gate of OS transistor 810 .

The operation of the circuit configuration shown in FIG. 43A will be described with reference to the timing chart of FIG. 43B. The timing chart of FIG. 43B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810 (FET 810). .

The output waveform IN_B, which is a signal obtained by inverting the logic of the signal supplied to the input terminal IN, can be a signal that controls the threshold voltage of the OS transistor 810 . Therefore, FIG.
41A to 41C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 43B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_
B goes low. Therefore, the OS transistor 810 can be in a state in which it is difficult for current to flow, and the voltage of the output terminal OUT can be sharply decreased.

At time T5 in FIG. 43B, the signal applied to the input terminal IN is at a low level and the OS transistor 820 is turned off. At this time, the output waveform IN_B becomes high level. Therefore, the OS transistor 810 can be in a state in which current can easily flow, and the voltage of the output terminal OUT can be rapidly increased.

As described above, in the configuration of this embodiment, the voltage of the back gate in the inverter including the OS transistor is switched according to the logic of the signal applied to the input terminal IN. With such a structure, the threshold voltage of the OS transistor can be controlled. O.
By controlling the threshold voltage of the S transistor in correspondence with the signal applied to the input terminal IN, it is possible to sharply change the voltage of the output terminal OUT. In addition, it is possible to reduce the through current between the wirings that supply the power supply voltage. Therefore, low power consumption can be achieved.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments, examples, or reference examples.

(Embodiment 7)
In this embodiment, display modules, electronic devices,
and a display device will be described with reference to FIGS.

<7-1. Explanation of Display Module>
A display module 8000 shown in FIG.
0, with battery 8011;

A semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

As the touch panel 8004 , a resistive or capacitive touch panel can be used by overlapping the display panel 8006 . In addition, it is possible to provide a counter substrate (sealing substrate) of the display panel 8006 with a touch panel function. Also, the display panel 8
An optical sensor can be provided in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008 . Note that FIG. 44 illustrates the configuration in which the light source 8008 is arranged over the backlight 8007, but the configuration is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusion plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function of protecting the display panel 8006 as well as a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 . The frame 8009 may also function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. A power supply for supplying power to the power supply circuit may be an external commercial power supply, or may be a power supply using a battery 8011 provided separately. The battery 8011 can be omitted when a commercial power supply is used.

In addition, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

<7-2. Description of electronic devices>
45A to 45G are diagrams showing electronic devices. These electronic devices include a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, sensors 9007 (force, displacement, position, speed,
Acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, or infrared rays function), microphone 9008, and the like.

The electronic devices illustrated in FIGS. 45A to 45G can have various functions.
For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display the date or time, various software (
A function to control processing by a program), a wireless communication function, a function to connect to various computer networks using a wireless communication function, a function to transmit or receive various data using a wireless communication function, a function recorded on a recording medium It can have a function of reading a program or data stored in the memory and displaying it on a display unit. Note that the functions that the electronic devices illustrated in FIGS. 45A to 45G can have are not limited to these, and can have various functions. In addition, although not shown in FIGS. 45A to 45G, the electronic device includes
A configuration having a plurality of display units may be employed. In addition, a camera or the like is provided in the electronic device to take still images, to take moving images, to save the shot images in a recording medium (external or built into the camera), and to display the shot images on the display unit. and the like.

Details of the electronic devices shown in FIGS. 45A to 45G are described below.

FIG. 45A is a perspective view showing a mobile information terminal 9100. FIG. A display portion 9001 included in the portable information terminal 9100 has flexibility. Therefore, the display portion 9001 can be incorporated along the curved surface of the curved housing 9000 . The display portion 9001 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be activated by touching an icon displayed on the display portion 9001 .

FIG. 45B is a perspective view showing a mobile information terminal 9101. FIG. The mobile information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, notebook, information viewing device, and the like. Specifically, it can be used as a smartphone. In addition, the portable information terminal 9101
Although the speaker 9003, the connection terminal 9006, the sensor 9007, and the like shown in FIG. 45A are omitted, they can be provided at the same positions as the portable information terminal 9100 shown in FIG. In addition, the mobile information terminal 9101 can display characters and image information on its multiple surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001 . In addition, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display portion 9001 . An example of the information 9051 is a display notifying an incoming e-mail, SNS (social networking service), or a phone call, the title of the e-mail, SNS, etc., the name of the sender of the e-mail, SNS, etc., the date and time, and the time. , battery level, and antenna reception strength. or information 90
Instead of the information 9051, an operation button 9050 or the like may be displayed at the position where 51 is displayed.

FIG. 45C is a perspective view showing a mobile information terminal 9102. FIG. The portable information terminal 9102 has a function of displaying information on three or more sides of the display portion 9001 . Here, information 9052,
An example in which information 9053 and information 9054 are displayed on different surfaces is shown. For example, the user of the mobile information terminal 9102 can confirm the display (here, information 9053) while the mobile information terminal 9102 is stored in the breast pocket of the clothes. Specifically, the phone number, name, or the like of the caller of the incoming call is displayed at a position that can be observed from above the portable information terminal 9102 . The user can check the display and determine whether or not to receive the call without taking out the portable information terminal 9102 from the pocket.

FIG. 45D is a perspective view showing a wristwatch-type portable information terminal 9200. FIG. The personal digital assistant 9200 can run various applications such as mobile phone, e-mail, text viewing and writing, music playback, Internet communication, computer games, and the like. Further, the display portion 9001 has a curved display surface, and display can be performed along the curved display surface. In addition, the mobile information terminal 9200 is capable of performing short-range wireless communication according to communication standards. For example, by intercommunicating with a headset capable of wireless communication, hands-free communication is also possible. In addition, the portable information terminal 9200 has a connection terminal 9006 and can directly exchange data with another information terminal through a connector. Also, charging can be performed through the connection terminal 9006 . It should be noted that the charging operation is performed at the connection terminal 900
It may be performed by wireless power feeding without going through 6 .

45(E), (F) and (G) are perspective views showing a foldable portable information terminal 9201. FIG. FIG. 45(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG.
45F is a perspective view of the portable information terminal 9201 in the middle of changing from one of the unfolded state and the folded state to the other, and FIG. 45G is a perspective view of the portable information terminal 9201 in the folded state. be. The portable information terminal 9201 has excellent portability in the folded state, and has excellent display visibility due to a seamless wide display area in the unfolded state. Portable information terminal 92
01 has three housings 9000 connected by hinges 9055 .
supported by By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly transformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments, examples, or reference examples.

In this example, two types of display devices (display device A and display device B) were manufactured, and characteristics of transistors included in the display devices, display examples of the display devices, and power consumption of the display devices were evaluated. gone.

First, Table 1 shows the specifications of the display device A manufactured in this example, and Table 2 shows the specifications of the display device B, respectively.

In both display device A and display device B, the mother glass is 600 mm × 720 m.
A transistor, a display element, and the like were formed on a glass substrate having a size of m. In addition, the display device A
As a first step, a transistor, a display element, and the like were formed on the glass substrate as it was. Further, as the display device B, a so-called flexible type display device was formed by peeling the transistors, display elements, etc. from the glass substrate and transferring them onto a film.

Further, as display elements included in the display device A and the display device B, organic EL elements capable of emitting white light were used. The organic EL element has a top emission type, so-called top emission structure, and a color filter is provided on the side of the EL element from which light is emitted.

Further, the transistors on the back plane side of the display device A and the display device B have the same structure as the transistor 170 described in Embodiment 2. FIG. CAAC-IGZO was used for the active layer of the transistor. In addition, the display device A and the display device B, respectively,
The monitor circuit 20 and the correction circuit 30 described in the first embodiment are provided.

<1-1. Characteristics of Transistor in Display Device>
First, characteristics of transistors included in the display device A are described with reference to FIGS.

FIG. 46A is a graph showing the probability statistics of the transistor on-current (Ion) within the mother glass surface, and FIG. FIG. 10 is a diagram representing the probability statistics at . Also, the Ion of the transistor in FIGS.
, and Vth are the results of measuring a total of 40 transistors within the surface of the mother glass, and the sizes of the transistors were L/W=6 μm/50 μm.

In addition, in FIGS. 46A and 46B, “new CAAC-IGZO” means a structure in which oxide semiconductors in the channel region are stacked.
IGZO” is a structure in which an oxide semiconductor in a channel region is a single layer. Note that the transistors included in the display device A are “new CAAC-IGZO”, “conv
epochal CAAC-IGZO" was used as a display device for comparison.

Note that the transistor included in the display device B is the "new CAAC-IGZO" described above.
is.

As shown in FIGS. 46A and 46B, the transistors included in the display device A and the display device B manufactured in this example have high on-state current and variations in on-state current and threshold voltage across the plane. I was able to confirm that it was small.

<1-2. Display example of the display device>
Next, display examples of the display device A and the display device B will be described with reference to FIGS. 47 and 48. FIG.

47 is a display example of the display device A, and FIGS. 48A and 48B are display examples of the display device B. FIG. Note that FIG. 48A is a display example in which the flexible display device is unfolded, and FIG. 48B is a display example in which the flexible display device is folded into three. .

As shown in FIGS. 47 and 48, the display device A and the display device B manufactured in this example had no problem in practical use, and a good display was obtained.

<1-3. About the power consumption of the display device>
Next, power consumption of the display device A will be described with reference to FIGS. 49 and 50. FIG.

The power consumption of the scan driver mounted on the display device A was measured.

A circuit diagram of a scan driver mounted on the display device A is shown in FIG.

The scan driver 580 shown in FIG. 49 includes a flip-flop circuit F. F. , a transistor M1, and a transistor M2.

Also, the gate electrode of the transistor M2 is connected to the flip-flop circuit F. F. , one of the source electrode and the drain electrode of the transistor M2 is electrically connected to the terminal CLK1 to which the clock signal is input, and the other of the source electrode and the drain electrode of the transistor M2 is electrically connected to the transistor M1. properly connected. Note that the transistor M1
of the flip-flop circuit F. F. is electrically connected to Further, the transistor M1 and the other of the source electrode and the drain electrode of the transistor M2 are electrically connected to the scan line scan line.

Next, FIG. 50 shows the result of evaluating the power consumption of the scan driver shown in FIG.

Note that "new CAAC-IGZO" and "conventiona
l CAAC-IGZO” is the same notation as shown in FIG.

As shown in FIG. 50, by using a transistor having "new CAAC-IGZO", the power consumption of the scan driver can be reduced to "conventional CAAC-I
It was possible to reduce it to about 35% of the transistor with "GZO".

As described above, the structure shown in this embodiment can be used in appropriate combination with the structures shown in the embodiments, other examples, or reference examples.

In this embodiment, the results of performing temperature correction on an actual panel using the circuit shown in FIG. 51 will be described.

The circuit shown in FIG. 51 has a monitor circuit 20A, a correction circuit 90, and a pixel circuit .

Note that the monitor circuit 20A and the pixel circuit 14 have the same configurations as the circuits described above, and therefore descriptions thereof are omitted here.

<2-1. Correction circuit>
The correction circuit 90 shown in FIG. 51 includes a constant current circuit 80, a converter circuit 61, a PC 91, an FPGA 92, a buffer 93, a data signal transmitter 94, a DVI receiver 95, an FPGA 96, a buffer 97, and an IC 98. , has

The converter circuit 61 can have the same configuration as the configuration described above.

PC91 has a function as an interface. For example, the PC 91 can calculate the cathode potential to be output to the monitor circuit 20A or the pixel circuit 14. Alternatively, the PC 91 can program or control the data signals output to the pixel circuits 14 .

The FPGA 92 is a programmable logic device (PLD), and has the function of generating signals according to the contents programmed by the PC 91 and assigning the signals to desired terminals. Also, the buffer 93 has a function of inverting and outputting the signal from the FPGA 92 or outputting the signal from the FPGA 92 as it is.

As the data signal transmitter 94, for example, high-definition video data such as 8K×4K or 4K×2K can be compressed or uncompressed and transmitted. Also, the DVI receiver 95 has a function of receiving data signals from the data signal transmitter 94 . Also, FP
The GA 96 has the function of allocating the data signal from the DVI receiver 95 to desired output terminals. The buffer 97 has a function of inverting and outputting the signal from the FPGA 96 or outputting the signal from the FPGA 96 as it is.

Also, the IC 98 can use a source driver IC. For example, Buffer
A signal output from 97 is output to the data line (DL_Y) of the pixel circuit 14 via the IC 98 .

As a method of driving the circuit shown in FIG. adjust.

<2-2. Luminance of Light-Emitting Element Due to Change in Cathode Potential>
Here, the luminance of the light-emitting element due to the cathode potential will be described. A sample corresponding to the monitor circuit 20A shown in FIG. 51 was prepared below. A monitor light-emitting element 21 and a monitor transistor 22A are formed on a sample corresponding to the monitor circuit 20A.

The luminance-voltage characteristics of the monitor light-emitting element 21 included in the sample prepared above were evaluated. The luminance-voltage characteristics of the monitor light-emitting element 21 were evaluated in a measurement environment of 70.degree.

The evaluation results are shown in FIG. In FIG. 52, the vertical axis indicates luminance, and the horizontal axis indicates cathode potential.

As shown in FIG. 52, the luminance of the monitor light emitting element 21 changes linearly when the cathode voltage is changed, and the luminance change can be approximated by a straight line.

Note that a method of monitoring the anode potential flowing to the monitor light emitting element 21 and changing the anode potential of the light emitting element 572 included in the pixel circuit 14 may be conceived to suppress the change in luminance of the light emitting element 572, but the transistor 554 is saturated. When operating in the region
Even if the anode potential of the light emitting element 572 is changed, there is no change in luminance or there is very little change in luminance. Therefore, the light emission luminance of the light emitting element 572 is roughly determined by the potential difference between the potential of the data signal applied to the data line (DL_Y) and the cathode potential of the light emitting element 572 .

<2-3. Temperature correction method>
Next, a method for temperature correction of the monitor light emitting element 21 will be described with reference to FIG. FIG. 53 is a conceptual diagram for explaining a method of correcting the temperature of the monitor light emitting element 21. FIG.

In FIG. 53, the vertical axis represents the cathode potential of the monitor light emitting element 21, and the horizontal axis represents the gradation of the display device. Note that in FIG. 53, the display device has 256 gradations. Also, the minimum is 0 gradation, the maximum is 255 gradation, n represents the low gradation side, and N represents the high gradation side.

As shown in FIG. 53, the cathode potential of the monitor light emitting element 21 may vary in amount of change between the low gradation side (n) and the high gradation side (N). Therefore, assuming that the room temperature is "temperature RT", the predetermined temperature is "temperature T", and the predetermined gradation is "gradation k", a current corresponding to temperature T and gradation k is passed through the monitor light emitting element 21. Assuming that the monitor potential in the case is Vmon(T, k), the following four monitor potentials are obtained.
・Low gradation side (n), Vmon (RT, n)
・Low gradation side (n), Vmon (T, n)
・High gradation side (N), Vmon (RT, N)
・High gradation side (N), Vmon (T, N)

As shown in FIG. 53, since the amount of correction on the low gradation side is smaller than that on the high gradation side, the cathode potential of the monitor light emitting element 21 may be based on the monitor potential on the low gradation side. Therefore, the cathode potential of the monitor light emitting element 21 should be changed by the amount represented by the following formula (1). Note that, in Equation (1), α is a correction coefficient.

As the gradation increases, the difference in monitor potential between the temperature T and the temperature RT increases. The amount of change in the data signal is given by the following formula (2)
is represented by Note that, in Expression (2), α and β are correction coefficients, respectively.

Therefore, in the circuit configuration shown in FIG. 51, as a temperature correction method, the cathode potential of the monitor light emitting element 21 and the cathode potential of the light emitting element 572 are corrected according to the measurement environment. In order to correct the temperature of the monitor light emitting element 21, the light emitting element 572
By correcting the potential of the data signal to correct the portion where correction of the cathode potential is insufficient, the light emission luminance of the light emitting element 572 can be adjusted.

In this embodiment, the cathode potential of the light-emitting element and the potential of the data signal are corrected, respectively. Alternatively, only the anode potential of the light emitting element may be corrected. However, as described in this embodiment, it is preferable to correct both the cathode potential and the data signal potential.

<2-4. Results of Luminance-Gradation Characteristics of Light-Emitting Element>
Next, the luminance-gradation characteristics of the light-emitting element obtained by using the temperature correction method described above will be described.

Here, three samples (Samples A1 to A3) were produced, and luminance-gradation characteristics of the samples were evaluated. FIG. 54 shows the results of luminance-gradation characteristics of Samples A1 to A3.

Note that sample A1 is the result of measurement at room temperature without temperature correction, sample A2 is the result of measurement at 60° C. with temperature correction, and sample A3 is the result of measurement at 60° C. without temperature correction. It is the result of measuring in °C.

As shown in FIG. 54, in the sample A2 manufactured in this example, it was confirmed that the brightness of the reference sample A1 and the light-emitting element were substantially the same by performing the temperature correction.

As described above, the structure described in this embodiment can be used in combination with any of the embodiments, other embodiments, or reference examples.

(Reference example)
In this reference example, the circuit shown in FIG. 55 was used to evaluate the temperature dependence of the monitor light-emitting element 21 and the monitor transistor 22A included in the monitor circuit 20A, and the results of performing temperature correction on the actual panel. explain.

<3-1. Temperature correction circuit>
FIG. 55 is a circuit diagram for explaining the configuration used in this reference example. The circuit shown in FIG. 55 has a constant current circuit 80 and a monitor circuit 20A.

The constant current circuit 80 has resistance elements 81 to 85 and amplifier circuits 88 and 89 .

One of the pair of electrodes of resistor element 81 is electrically connected to the first input terminal of amplifier circuit 88 , and the other of the pair of electrodes of resistor element 81 is electrically connected to the output terminal of amplifier circuit 89 . be. One of the pair of electrodes of the resistor element 82 is electrically connected to the other of the pair of electrodes of the resistor element 81 and the output terminal of the amplifier circuit 89, and the other of the pair of electrodes of the resistor element 82 is connected to the amplifier circuit. It is electrically connected to the second input terminal of 89 . One of the pair of electrodes of the resistance element 83 is electrically connected to the output terminal of the amplifier circuit 88, and the other of the pair of electrodes of the resistance element 83 is
It is electrically connected to the first input terminal of the amplifier circuit 89 . A second input terminal of the amplifier circuit 88 is electrically connected to the output terminal of the amplifier circuit 88 . A resistor element 84 is electrically connected to the other of the pair of electrodes of the resistor element 83 and the first input terminal of the amplifier circuit 89,
The resistor element 82 is connected to the other of the pair of electrodes of the resistor element 82 and the second input terminal of the amplifier circuit 89 .
5 are electrically connected.

Note that the monitor circuit 20A has the same configuration as the monitor circuit 20A shown in the first embodiment.

One of the pair of electrodes of the resistance element 81 is electrically connected to the terminal 26 of the monitor circuit 20A, and the voltage generated by the constant current circuit 80 is applied to the monitor transistor 22A through the terminal 26. and supplied to the monitor light emitting element 21 .

A converter circuit 61 is connected to a terminal 24 of the monitor circuit 20A.
A memory circuit 62 is connected to the terminal 24 via the converter circuit 61 .

<3-2. Concept of Temperature Compensation Circuit>
Next, the voltage generated when a constant current is applied to the monitor transistor 22A and monitor light emitting element 21 in the circuit shown in FIG. 55 will be described with reference to FIG.

FIG. 56 shows the current-voltage (I
-V) It is a diagram for explaining the concept of characteristics.

In FIG. 56, the vertical axis represents current (I) and the horizontal axis represents voltage (V).

56 corresponds to a conceptual diagram showing the current-voltage (IV) characteristics of the node A shown in FIG. 55, mainly the voltage (Vtotal) characteristics of the node A. FIG. Voltage of node A (Vtotal)
is the sum of the voltage (Vd) generated when a constant current is applied to the monitor transistor 22A and the voltage (Voled) generated when a constant current is applied to the monitor light emitting element 21. FIG. That is, it can be expressed as Vtotal=Vd+Voled. In FIG. 56, the voltage (Vtotal) is measured at two different temperatures (low temperature and high temperature).
The solid line is Vd(L) and Voled(L) at low temperature, and the dashed line is Vd(H) and Vole at high temperature.
d(H) respectively. Iconst shown in FIG. 56 is a reference current.

As shown in FIG. 56, both the monitor transistor 22A and the monitor light emitting element 21 have high threshold values at low temperatures, and Vtotal increases when Iconst flows. Also, as shown in FIG. 56, Vd increases at low temperatures and decreases at high temperatures. That is, the potential of the cathode of the monitor light emitting element 21 should be changed by the amount of change (ΔVd) from Vd(L) to Vd(H).

<3-3. Evaluation of temperature dependence>
Next, samples B1 and B2 were produced, and the temperature dependence of samples B1 and B2 was evaluated. The specifications of the samples B1 and B2 were the same as those of the display device B shown in the previous example. However, in this reference example, a sample formed on a glass substrate was evaluated.
Sample B1 is a sample for comparison and is not subjected to temperature correction. In addition, sample B2 is
This is a temperature-corrected sample.

Note that a circuit corresponding to the pixel circuit 14 shown in FIG. 9 of Embodiment 1 is formed in the samples B1 and B2. Therefore, in the following description, reference numerals shown in FIG. 9 are used.

The threshold voltage (V
th) shifts in the negative direction, the potential applied to the source electrode of the transistor 554 decreases, and the potential (Vgs) between the gate electrode and the drain electrode of the transistor 554 increases. In addition, the threshold voltage (Vth) of the transistor 554 shifts in the negative direction, and the current flowing through the transistor 554 increases.

Therefore, using the monitor circuit 20A shown in FIG. 55, the temperature dependence of Vtotal of the monitor light emitting element 21 and the monitor transistor 22A was measured, and the result of the measurement was fed back to the transistor 554 and the light emitting element 572. FIG. Specifically, this feedback means that the light emitting element 57
2 was corrected so that the voltage (Vgs) applied to the transistor 554 was decreased.

FIG. 57 shows the measurement results of samples B1 and B2. In FIG. 57, the vertical axis is luminance (L)
, and the horizontal axis represents temperature (° C.).

As shown in FIG. 57, the temperature-corrected sample B2 is different from the temperature-corrected sample B1.
It was confirmed that the temperature dependence of brightness was reduced compared to .

As described above, the structure described in this reference example can be used in appropriate combination with the structure described in the embodiment or example.

12 pixel section 13 protection circuit 14 pixel circuit 16 gate line drive circuit 17 terminal section 18 signal line drive circuit 20 monitor circuit 20A monitor circuit 20B monitor circuit 20C monitor circuit 21 monitor light emitting element 22 monitor transistor 22A monitor transistor 23 resistance element 24 terminal 25 Terminal 26 Terminal 27 Terminal 30 Correction circuit 30A Correction circuit 30B Correction circuit 30C Correction circuit 31 Amplifier circuit 32 Switching element 50 Resistance element 61 Converter circuit 62 Memory circuit 80 Constant current circuit 81 Resistance element 82 Resistance element 83 Resistance element 84 Resistance element 85 Resistance Element 88 Amplifier circuit 89 Amplifier circuit 90 Correction circuit 91 PC
92 FPGAs
93 Buffer
94 data signal transmitter 95 DVI receiver 96 FPGA
97 Buffer
98 IC
100 Transistor 100A Transistor 100B Transistor 102 Substrate 104 Conductive film 106 Insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 108c Oxide semiconductor film 112a Conductive film 112b Conductive film 114 Insulating film 116 Insulating film 118 Insulating film 120 Oxide semiconductor film 120a Oxide semiconductor film 120b Oxide semiconductor film 131 Insulating film 132 Insulating film 133 Insulating film 140a Opening 140b Opening 141a Opening 141b Opening 142a Opening 142b Opening 142c Opening 150 Transistor 160 Transistor 170 Transistor 180 Transistor 180b Oxide semiconductor film 552 Transistor 554 Transistor 562 Capacitive element 572 Light-emitting element 580 Scan driver 600 Touch panel 601 Substrate 602 Substrate 603 Adhesive layer 610 Input device 611 Transistor 612 Driving transistor 613 Selection transistor 614 Display element 615 Capacitive element 616 Connection portion 617 Wiring 621 Insulating layer 622 Insulating layer 623 Insulating layer 624 Insulating layer 625 Insulating layer 626 Spacer 631 Electrode 632 Electrode 633 Electrode 634 Bridge electrode 635 Conductive film 636 Conductive film 637 Conductive film 638 Nanowire 641 Electrode 642 EL layer 643 Electrode 644 Optics Adjustment layer 650 FPC
651 IC
652 Wiring 653 Wiring 654 Connection portion 655 Connection layer 656 Connection layer 660 FPC
661 IC
662 display portion 663 drive circuit 664 wiring 665 intersection portion 671 colored layer 672 light shielding layer 673 insulating layer 674 insulating layer 681 substrate 682 adhesive layer 683 insulating layer 691 substrate 692 adhesive layer 694 insulating layer 702 substrate 704 conductive film 706 insulating film 707 insulating film 708 oxide semiconductor film 712a conductive film 712b conductive film 712c conductive film 714 insulating film 716 insulating film 718 insulating film 720 oxide semiconductor film 722 insulating film 724a conductive film 724b conductive film 726 structure 728 EL layer 730 conductive film 752a opening 752b Opening 752c Opening 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 902 Substrate 904a Conductive film 904b Conductive film 906 Insulating film 907 Insulating film 909 Conductive oxide film 912d Film 912e Conductive film 918 Insulating film 944a Opening 944b Opening 950 Semiconductor device 2000 Touch panel 2001 Touch panel 2501 Display device 2502t Transistor 2503c Capacitor element 2503t Transistor 2504 Scan line driver circuit 2505 Pixel 2509 FPC
2510 substrate 2510a insulating layer 2510b flexible substrate 2510c adhesive layer 2511 wiring 2519 terminal 2521 insulating layer 2528 partition wall 2550 EL element 2560 sealing layer 2567 colored layer 2568 light shielding layer 2569 antireflection layer 2570 substrate 2570a insulating layer 2570b flexible substrate 2570c Adhesive layer 2580 Light-emitting module 2590 Substrate 2591 Electrode 2592 Electrode 2593 Insulating layer 2594 Wiring 2595 Touch sensor 2597 Adhesive layer 2598 Wiring 2599 Connection layer 2601 Pulse voltage output circuit 2602 Current detection circuit 2603 Capacitor 2611 Transistor 2612 Transistor 2613 Transistor 2621 Electrode 2622 Electrode 8000 Display module 8001 upper cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 display panel 8007 backlight 8008 light source 8009 frame 8010 printed circuit board 8011 battery 9000 housing 9001 display unit 9003 speaker 9005 operation key 9006 connection terminal 9007 sensor 9008 microphone 9050 operation button 9051 information 9052 information 9053 information 9054 information 9055 hinge 9100 mobile information terminal 9101 Mobile information terminal 9102 Mobile information terminal 9200 Mobile information terminal 9201 Mobile information terminal

Claims (1)

having a first transistor, a second transistor, a capacitive element, and a light emitting element;
one of the source and the drain of the first transistor is electrically connected to a data line;
the other of the source or the drain of the first transistor is electrically connected to the first gate of the second transistor;
the other of the source and the drain of the first transistor is electrically connected to the first electrode of the capacitive element;
a gate of the first transistor electrically connected to a scanning line;
one of the source or drain of the second transistor is electrically connected to an anode line;
the other of the source or the drain of the second transistor is electrically connected to the second gate of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the second electrode of the capacitive element;
the other of the source and the drain of the second transistor is electrically connected to the light emitting element;
the second transistor has a first conductive film having a region functioning as the other of a source electrode and a drain electrode;
The second transistor has an oxide semiconductor film having a region functioning as a second gate electrode,
The light emitting element has a second conductive film having a region functioning as a pixel electrode,
The semiconductor device, wherein the second conductive film is electrically connected to the oxide semiconductor film through the first conductive film.

Images