JP2022164282A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

To provide a manufacturing method of a semiconductor device and a semiconductor device capable of preventing positional displacement on a contact surface and interfacial peeling after sintering while suppressing the generation of voids.SOLUTION: A manufacturing method of a semiconductor device according to the present invention is a method for joining a semiconductor die and a substrate electrode or a lead frame with a sinter layer. The method includes a dry sinter layer forming step including processing of forming a dry sinter layer having a recess in the substrate electrode or lead frame, and processing of forming a dry sinter layer that fits into the recess in the semiconductor die, a stacking step of superimposing the two dry sinter layers and fitting the other dry sinter layer into the recess of the dry sinter layer, and a sintering step of sintering the superimposed two dry sinter layers to join the semiconductor die and the substrate electrode or lead frame. This allows provision of a manufacturing method of a semiconductor device in which there is no misalignment between the substrate electrode or lead frame and the semiconductor die, and a semiconductor device.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which is heat-sintered under no pressure or a low pressure and a semiconductor device manufactured by the method.

With the recent miniaturization and high output of electric power equipment, it is important to improve the heat resistance of power modules and operate them at high temperatures. Sinter bonding is one of the high heat resistance mounting methods for bonding the semiconductor die and the substrate electrode used in the power module.

The sinter bonding is a bonding method in which a paste-like sinter material in which metal particles such as silver, copper, and nickel with a particle size ranging from micro-sized to nano-sized are dispersed in a solvent is applied to the bonding surface and then sintered. be.

When the paste-like sinter material is applied to the bonding surface and the semiconductor die and the substrate electrode are laminated, the discharge path of the volatilizing solvent is blocked, so voids are formed in the sinter layer formed by sinter bonding. This leads to obstruction of the heat dissipation path and reduction in thermal fatigue life.

Patent Literature 1 discloses that the generation of voids can be suppressed by laminating a semiconductor die after volatilizing a solvent from a paste-like coating layer applied to a substrate electrode.

Japanese Patent Publication No. 2012-517704

However, since the sintering material that has volatilized the solvent has lost its tackiness, the semiconductor die laminated on the sintering material cannot be sufficiently fixed, and the contact surface between the sintering material and the semiconductor die cannot be sufficiently fixed due to vibration or the like. Positional deviation is likely to occur. Moreover, even after sintering, interfacial peeling is likely to occur at the bonding surface between the sintering material and the semiconductor die due to thermal stress caused by the difference in thermal expansion coefficient between the semiconductor die and the substrate electrode.

The present invention has been made in view of such problems of the prior art, and the object thereof is to suppress the occurrence of voids and prevent the positional displacement of the contact surface and the interfacial peeling after sintering. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device that can prevent such a problem.

As a result of intensive studies to achieve the above object, the present inventors formed a dry sintered layer having recesses on a substrate electrode or a lead frame, and formed a dry sintered layer fitted in the recesses on a semiconductor die. The present inventors have found that the above problems can be solved by forming and fitting them, and have completed the present invention.

That is, the method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device in which a semiconductor die and a substrate electrode and/or a semiconductor die and a lead frame are bonded by a sintered sinter layer.
a dry sinter layer forming step including a process of forming a dry sinter layer having recesses on the substrate electrode or lead frame, and a process of forming a dry sinter layer on the semiconductor die that fits into the recesses;
a stacking step of superimposing the two dry sinter layers and fitting the other dry sinter layer into the recesses of the dry sinter layer;
and a sintering step of sintering the two superimposed dry sinter layers to join the semiconductor die and the substrate electrode or lead frame.

Also, the semiconductor device of the present invention is a semiconductor device in which a semiconductor die and a substrate electrode or a lead frame are joined with a sintered sinter layer.
Further, the substrate electrode or the lead frame is characterized by having a recess smaller than the range inside the range of the joint surface with the sintered sinter layer provided with the sintered sinter layer.

According to the present invention, the dry sintered layers are formed on both the substrate electrode or lead frame and the semiconductor die, and one dry sintered layer is fitted into the concave portion of the other dry sintered layer. It is possible to provide a method of manufacturing a semiconductor device and a semiconductor device in which the positions of the frame and the semiconductor die do not shift.

1 is a cross-sectional view of a semiconductor device; FIG. FIG. 4 is a cross-sectional view showing the shape of a dry sinter layer before lamination. FIG. 4 is a cross-sectional view showing a state in which dry sinter layers are laminated; FIG. 4 is a cross-sectional view showing a state in which a wet sinter layer having recesses is formed on a planar substrate electrode; FIG. 4 is a diagram showing an example of a printing mask for forming a wet sinter layer having recesses; FIG. 10 is a plan view showing a state in which a wet sinter layer having recesses is formed on a substrate electrode using dispensing; FIG. 4 is a cross-sectional view showing a state in which a wet sinter layer is formed on a substrate electrode having recesses; FIG. 4 is a cross-sectional view showing a state after drying a wet sinter layer formed on a substrate electrode having recesses; FIG. 4 is a cross-sectional view showing a state in which dry sinter layers are laminated; FIG. 4 is a cross-sectional view showing a state in which pelletized solder is placed on a wet sinter layer; FIG. 4 is a cross-sectional view showing a state in which dry sintered layers on which pelletized solder is placed are stacked; 1 is a cross-sectional view of a semiconductor device in which lead frames are stacked; FIG. FIG. 4 is a cross-sectional view showing a wet sinter layer covering the entire surface electrode of a semiconductor die; FIG. 4 is a cross-sectional view showing a state after drying a wet sinter layer covering the entire surface electrode of the semiconductor die;

A method for manufacturing a semiconductor device according to the present invention will be described below.
The manufacturing method described above is a method for manufacturing a semiconductor device in which a semiconductor die and a substrate electrode or a lead frame are joined by a sintered sinter layer.

For example, as shown in FIG. 1, the semiconductor device 1 has a structure in which a sintered sinter layer 3 is sandwiched between a semiconductor die 2 and a substrate electrode 4, and the semiconductor die 2 and the substrate electrode 4 are sintered. They are joined by the sinter layer 3 .

In the manufacturing method of the present invention, a sinter material containing a solvent is applied to both the semiconductor die 2 and the substrate electrode 4 to form a wet sinter layer 5, which is then dried to form two dry sinter layers 6. . Then, the dried sintered layer 6a of the semiconductor die and the dried sintered layer 6b of the substrate electrode are overlapped and sintered to form an integrated sintered sintered layer 3. As shown in FIG.

As described above, in the manufacturing method of the present invention, after drying the wet sinter layer 5 containing the solvent and forming the dry sinter layer 6 by volatilizing the solvent, the substrate electrode 4 and the semiconductor die 2 are laminated. , the upper surface of the wet sinter layer 5 is not covered, and the discharge path of the solvent is not blocked. Therefore, the generation of voids due to volatilization of the solvent is prevented.

In addition, since the generation of voids can be prevented as described above, there is no need to push out the vapor of the volatilized solvent by applying pressure during sintering. It is possible to prevent the occurrence of cracks in the semiconductor die 2, the substrate electrode 4, and the like.

In addition, the thicker the wet sinter layer 5, the less likely the solvent will volatilize and the more likely the solvent will remain in the dry sinter layer 6. Therefore, the wet sinter layer 4 cannot be made too thick.

In the present invention, since the sintering material containing the solvent is applied to both the semiconductor die 2 and the substrate electrode 4, the wet sintering layer 5 is formed only on either the semiconductor die 2 or the substrate electrode 4. A sintered sinter layer 3 with a double thickness can be formed.

Since the sintered sinter layer 3 relaxes the stress due to the difference in thermal expansion coefficient between the semiconductor die 2 and the substrate electrode 4, it is possible to increase the thickness of the sintered sinter layer 3 and improve the thermal fatigue life. be. The thickness of the sintered sinter layer 3 is preferably 50 μm to 200 μm.

As shown in FIG. 2, the dry sintered layer 6b of the substrate electrode has a recess 61, and the dry sintered layer 6a of the semiconductor die is fitted into the recessed portion 61 so as to fit into the recess. Then, as shown in FIG. 3, the dry sinter layer 6b of the substrate electrode and the dry sinter layer 6a of the semiconductor die are overlapped, and the dry sinter layer 6a of the semiconductor die is fitted into the recesses 61 of the dry sinter layer of the substrate electrode. .

Therefore, even if vibrations are applied during transportation or the like, the contact surfaces of the dry sinter layers 6 will not be misaligned.
In addition, since the dry sinter layer before sintering has a high degree of activity, even if there is a gap between these layers to some extent, the gap is filled by sintering and firmly bonded. Since the sintered sinter layer 3 is formed by integrating the 6b, and the substrate electrode 4 and the semiconductor die 2 are firmly bonded, interfacial peeling due to thermal stress caused by heat generated when the semiconductor is driven can be prevented.

Since the wet sinter layer 5 having tackiness is formed on the semiconductor die 2 and the substrate electrode 4, the interface between the semiconductor die 2 and the dry sinter layer 6a and the interface between the substrate electrode 4 and the dry sinter layer 6a remain unchanged even after drying. Tackiness is maintained at the interface with 6b, and interfacial peeling at these interfaces is also prevented.

The depth of the concave portions 61 of the dry sinter layer is preferably 10 μm or more.
When the depth of the concave portion is 10 μm or more, it is possible to prevent positional deviation against external force such as vibration.

The depth of the recesses 61 of the dry sinter layer can be adjusted by adjusting the thickness difference between the recesses 51 of the wet sinter layer 5 applied to the substrate electrode 4 and the surroundings thereof. The difference in thickness between the recesses 51 of the wet sinter layer and its surroundings is preferably 20 μm or more, although it depends on the volume ratio of the metal particles to the solvent.

The volume ratio of the metal particles to the solvent (metal particles/solvent) in the wet sinter material is preferably 35/65 to 65/35, depending on the average particle size of the metal particles and the type of solvent.

Examples of the metal particles include particles of silver, copper, nickel, and the like.
The smaller the particle diameter of the metal particles, the wider the surface area per volume and the more active they are. It is preferable to mix and use nanoparticles with a diameter of 50 to 500 nm.
The metal particles may be surface-treated to prevent oxidation and improve dispersibility.

As the solvent, conventionally known solvents used for sintering materials can be used, for example, alcohol-based organic solvents such as ethylene glycol can be used.

The substrate electrode 4 is a metal substrate made of a metal such as copper on which a film of gold, silver, or the like is formed so that the sintered sinter layer 3 can be bonded to the surface of the substrate, or a substrate having a copper electrode or the like formed on a ceramic substrate. can be used.

In addition, the semiconductor die 2 is an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field effect transistor (IGBT) in which a surface electrode 21 made of gold, silver, or the like is formed on the outermost surface of the surface connected to the sintered sinter layer 3. power semiconductors such as MOS-FETs).

Although the case where the substrate electrode 4 and the semiconductor die 2 are joined has been described as an example, the case where the lead frame 7 and the semiconductor die 2 are joined is the same.

(First embodiment)
A case of bonding the planar substrate electrode 4 and the semiconductor die 2 will be described.
In the first embodiment, as shown in FIG. 4, a sintering material containing a solvent is applied to one surface of the substrate electrode 4 to form a wet sintering layer 5 having recesses 51 .

The wet sinter layer 5 having the concave portions 51 has, for example, a screen printing mesh portion 91 at the locations where the concave portions 51 are formed, and a printing mask 9 having mask openings 92 around it, as shown in FIG. can be formed using

In this printing mask 9, the amount of the solvent-containing sintering material passing through is regulated in the screen printing mesh portion 91, and is not regulated in the mask openings 92. Therefore, the mesh portion 91 and the openings 92 contain the solvent. The wet sinter layer 5 having the concave portions 51 can be formed by causing a difference in the application amount of the sintering material.

Alternatively, as shown in FIG. 6, after coating the portion that will become the bottom portion 52 of the recessed portion 51, the dispenser 10 is used to surround the periphery thereof, and the coating is formed so as to be thicker than the bottom portion 52.

Then, the wet sinter layer 5 is heated and dried to volatilize the solvent in the wet sinter layer, thereby forming the dry sinter layer 6 having the concave portions 61 . The temperature for drying the wet sinter layer 5 is about 130° C. to 180° C., depending on the solvent used.

In addition, the semiconductor die 2 is fitted into the recesses 61 of the dry sinter layer 6b formed on the substrate electrode 4 so that the dry sinter layer 6a is approximately the same depth as the recesses 61 so as not to create gaps. A wet sinter layer 5a having an adjusted film thickness is formed, and dried by heating to form a dry sinter layer 6a fitted in the concave portions 61. As shown in FIG.

Next, as shown in FIG. 3, the dry sinter layer 6b of the substrate electrode and the dry sinter layer 6a of the semiconductor die are placed face to face, and the dry sinter layer 6a of the semiconductor die is placed in the concave portion 61 of the dry sinter layer of the substrate electrode. and sintered to integrate the dried sintered layer 6b of the substrate electrode and the dried sintered layer 6a of the semiconductor die to manufacture the semiconductor device 1 shown in FIG.

(Second embodiment)
A case of bonding the substrate electrode 4 having the recess 41 and the semiconductor die 2 will be described.
The substrate electrode 4 used in the second embodiment has, as shown in FIG. 7, a concave portion 41 smaller than the outer shape of the semiconductor die 2 inside the bonding range with the semiconductor die 2 . This concave portion 41 can be formed by a conventionally known method such as press working or etching.

Then, as shown in FIG. 7, a printing mask or the like is used for the substrate electrode 4 to apply a sintering material containing a solvent to the concave portion 41 of the substrate electrode 4 and its surroundings, and the convex portion is formed on the substrate electrode 4 side. to form a wet sinter layer 5b having

Although FIG. 7 shows the planar wet sinter layer 5b on the bonding surface side with the semiconductor die 2, the concave portion 51 is formed on the bonding surface side with the semiconductor die 2 by the same method as in the first embodiment. You can also By forming the concave portion 51 on the joint surface side with the semiconductor die 2 , the depth of the concave portion 41 formed in the substrate electrode 4 can be made shallow, and the strength of the substrate electrode 4 can be ensured.

By heating and drying the wet sinter layer 5b, a dry sinter layer 6b having recesses 51 on the bonding surface side with the semiconductor die 2 can be formed as shown in FIG.

Then, as shown in FIG. 9, the dry sinter 6b of the substrate electrode and the dry sinter layer 6a of the semiconductor die are placed face to face, and the dry sinter layer 6a of the semiconductor die is fitted into the concave portion 61 of the dry sinter layer of the substrate electrode. , to manufacture the semiconductor device 1 by sintering.

(Third embodiment)
A case of forming an alloy reinforcing layer on the joint surface between the semiconductor die 2 and the sintered sinter layer 3 will be described.

In the third embodiment, the corners of the semiconductor die 2 are reinforced where the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor die 2 and the substrate electrode 4 is most applied.

Sn-based pellet-like solder 8 is applied to the upper surface of the wet sinter layer 5b formed on the substrate electrode 4 in the same manner as in the first and second embodiments so as to cover the corners of the semiconductor die 2 as shown in FIG. put on.

After drying the wet sinter layer 5b by heating, as shown in FIG. 11, the dry sinter layer 6b of the substrate electrode and the dry sinter layer 6a of the semiconductor die are placed face to face, and the recesses 61 of the dry sinter layer of the substrate electrode are formed. Then, the semiconductor device 1 is manufactured by fitting the dry sinter layer 6a of the semiconductor die and sintering it at a temperature higher than the melting point of the Sn-based solder.

Upon sintering _, the _Sn component in the solder forms _Ag3Sn if the sintering material is Ag _, Cu6Sn5 if it is Cu, and _Ni3Sn4 if it is Ni. Since these alloys are strong, they can prevent peeling from the corners of the bonding surface between the semiconductor die 2 and the sintered sinter layer 3 .

As the Sn-based solder, Sn alone, Sn--Ag--Cu-based solder, Sn--Cu-based solder, and Sn--Sb-based solder can be used.

(Fourth embodiment)
A case of joining the semiconductor die 2 and the lead frame 7 will be described.
FIG. 12 shows a cross-sectional view of the semiconductor device 1 in which the semiconductor die 2 and the lead frame 6 are joined.

In this semiconductor device 1 , a semiconductor die 2 has a surface electrode 21 made of Al or Ni on the lead frame side, and the surface electrode 21 forms a projection on the semiconductor die 2 .

A sintering material containing a solvent is applied so as to cover the entire surface electrode 21 of the semiconductor die 2, and as shown in FIG. 5a is formed.

Then, by drying the wet sinter layer 5a, a dry sinter layer 6a having protrusions on the semiconductor die 2 can be formed as shown in FIG.

On the other hand, the lead frame 7 is also formed with a dry sinter layer 6c having recesses 61 in the same manner as in the first and second embodiments.

Then, the dry sinter layer 6c of the lead frame 7 and the dry sinter layer 6a of the semiconductor die are placed face to face, and the protrusions of the dry sinter layer 6a of the semiconductor die are fitted into the recesses of the dry sinter layer 6c of the lead frame, followed by baking. A semiconductor device is manufactured by bonding.

Also, as shown in FIG. 12, the bottom surface of the semiconductor die 2 is bonded to the substrate electrode 4 by the die bonding layer 11 . By forming the die bonding layer 10 according to the first embodiment or the second embodiment, the semiconductor die 2 and the lead frame 7 and the semiconductor die 2 and the substrate electrode 4 are collectively sintered and joined. The semiconductor device 1 can be manufactured.

REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor die 21 surface electrode 3 sintered sinter layer 4 substrate electrode 41 recess 5 wet sinter layer 51 recess 52 bottom 6 dry sinter layer 61 recess 7 lead frame 8 alloy reinforcement layer 81 solder pellet 9 mask for printing 91 mesh Part 92 Mask opening 10 Dispensing 11 Die bonding layer

Claims (9)

A method for manufacturing a semiconductor device in which a semiconductor die and a substrate electrode, and/or a semiconductor die and a lead frame are bonded with a sintered sinter layer,
A process of forming a dry sinter layer having recesses on the substrate electrode or lead frame;
forming a dry sinter layer on the semiconductor die that fits into the recess; and
a stacking step of superimposing the two dry sinter layers and fitting the other dry sinter layer into the recesses of the dry sinter layer;
and a sintering step of sintering the two superimposed dry sinter layers to join the semiconductor die and the substrate electrode or lead frame. The process of forming the dry sinter layer having the recesses includes:
applying a sintering material containing a solvent to one surface of the substrate electrode or the lead frame to form a wet sintering layer having recesses;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of volatilizing a solvent in said wet sinter layer to form recesses. The process of forming the dry sinter layer having the recesses includes:
Using a substrate electrode or a lead frame in which recesses are formed in advance,
applying a sintering material containing a solvent to the recess of the substrate electrode or lead frame and the periphery of the recess to form a wet sinter layer in which the thickness of the recess is thicker than the periphery of the recess;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of volatilizing a solvent in said wet sinter layer to form recesses. The process of forming the dry sinter layer having the recesses includes:
4. The method of manufacturing a semiconductor device according to claim 2, further comprising applying pelletized solder to the corners of said wet sintered layer. The process of forming a dry sintered layer that fits into the recess is
Using a semiconductor die on which convexities are formed in advance,
applying a sintering material containing a solvent to the protrusions of the semiconductor die and the periphery of the protrusions to form a wet sinter layer in which the thickness of the protrusions is thinner than the periphery of the protrusions;
5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of volatilizing a solvent in said wet sinter layer to form protrusions that fit into said recesses. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the convex portion of the semiconductor die is formed of a surface electrode. A semiconductor device in which a semiconductor die and a substrate electrode or a lead frame are joined with a sintered sinter layer,
1. A semiconductor device according to claim 1, wherein said substrate electrode or said lead frame has a recess smaller than said range inside the range of said joint surface with said sintered sinter layer provided with said sintered sinter layer. The semiconductor die has a convex portion formed by a surface electrode,
8. The semiconductor device according to claim 7, wherein the protrusion is entirely covered with the sinter layer and joined. 9. The semiconductor device as set forth in claim 7, wherein the joint surface between the semiconductor die and the sintered sinter layer has a portion joined by soldering at the corner.

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