JP2022139692A - distance sensor - Google Patents

Abstract

To propose a distance sensor that transmits a transmission pulse signal without using a clock signal.SOLUTION: A transmission circuit 30 comprises a comparator 31, a comparator 32, a voltage control circuit 33, and an AND circuit 34. The comparator 31 includes an input terminal 311 to which a constant voltage V1 is input, an input terminal 312 to which a variable voltage is input, a non-inverted output terminal 313, and an inverted output terminal 314. The comparator 32 includes an input terminal 321 to which a constant voltage V2 is input, an input terminal 322 to which a variable voltage is input, a non-inverted output terminal 323, and an inverted output terminal 324. The voltage control circuit 33 changes the variable voltage between the constant voltage V1 and the constant voltage V2. The AND circuit 34 outputs, as a transmission pulse signal, an AND signal of a first output signal from the non-inverted output terminal 313 of the comparator 31 and a second output signal from the inverted output terminal 324 of the comparator 32.SELECTED DRAWING: Figure 2

Description

The present invention relates to distance sensors.

A TOF (Time Of Flight) method, for example, is known as one method of a distance sensor that measures the distance to a target. A pulse signal transmitted from the distance sensor toward the target is called a "transmission pulse signal", and a reflected pulse signal of the transmission pulse signal reflected by the target is called a "reception pulse signal". A pulse signal is a general term for a transmission pulse signal and a reception pulse signal, and the term pulse signal is used when there is no particular need to distinguish between the two. In the TOF method, the distance obtained by multiplying the speed of the pulse signal by the time from when the transmission pulse signal is sent from the distance sensor to when the reception pulse signal is received (the round trip time of the pulse signal) is obtained (the round trip distance of the pulse signal). Measure the distance to the target by dividing by two.

From the viewpoint of preventing malfunction of the distance sensor, the time from when the transmission of the transmission pulse signal is started to when it is stopped (hereinafter referred to as the "transmission pulse width") is set to It should be shorter than the time to return. Assuming that the minimum value of the transmission pulse width is _TWmin , the minimum value of the distance from the distance sensor to the target is _Rmin , and the speed of the pulse signal is V, equation (1) holds.

T _wmin ≤ 2 × R _min ÷ V (1)

In formula (1), for example, if R _min is 10 mm and V is the speed of light, formula (2) holds.

_TWmin ≤ 1/15,000,000,000 (2)

Conventionally, a transmission pulse signal having a transmission pulse width T _Wmin is generated by driving a logic circuit with a square-wave clock pulse signal having a frequency of (1/T _Wmin )/2.

FIG. 12 shows an example of the configuration of a transmission circuit 70 used in a conventional distance sensor. The transmission circuit 70 includes four upper-stage D flip-flops DFF1 to DFF4 to which the clock signal Clock in is supplied, four lower-stage D flip-flops DFF5 to DFF8 to which the clock signal Clock in is supplied through the NOT circuit NOT, and D A negative logical sum circuit NOR for outputting a negative logical sum signal of the output signal A of the flip-flop DFF4 and the output signal B of the D flip-flop DFF8 is provided. Here, the output signal of the NOR circuit NOR is the transmission pulse signal TX pulse out. The clock signal Clock in is a square-wave clock pulse signal having a frequency of (1/T _Wmin )/2.

13 is a timing chart showing an example of the operation of the transmission circuit 70. FIG. When the reset signal Reset in is input to all of the D flip-flops DFF1 to DFF8 and the transmission circuit 70 is initialized, the transmission pulse signal TX pulse out becomes low level. Subsequently, the clock signal Clock in is input to the transmission circuit 70 . At the timing of the fourth rise of the clock signal Clock in, the output signal A of the D flip-flop DFF4 transitions from high level to low level. On the other hand, the output signal B of the D flip-flop DFF8 transitions from low level to high level at the timing of the fourth fall of the clock signal Clock in. The transmission pulse signal TX pulse out is at high level during the period when both the output signals A and B are at low level.

FIG. 14 shows an example of the configuration of a receiver circuit 80 used in a conventional distance sensor. The receiving circuit 80 includes an operational amplifier OP3 and a D flip-flop DFF. The inverting input terminal of the operational amplifier OP3 is connected to the ground through the resistor R6 and to the output terminal of the operational amplifier OP3 through the resistor R7. A received pulse signal RX pulse in is input to the non-inverting input terminal of the operational amplifier OP3. An output signal from the operational amplifier OP3 is input to the D terminal of the D flip-flop DFF. A detection signal DET indicating that reception of the reception pulse signal RX pulse in has been detected is output from the Q terminal of the D flip-flop DFF. When the reception of the reception pulse signal RX pulse in is detected, the detection signal DET becomes high level.

15 is a timing chart showing an example of the operation of the receiving circuit 80. FIG. When the transmission pulse signal TX pulse out is transmitted at time t1 when the clock signal Clock in rises and the reception pulse signal RX pulse in is received at time t2 when the clock signal Clock in rises, the clock signal Clock in rises. The detection signal DET becomes high level at the timing of time t3. As shown in this figure, when the timing at which the clock signal Clock in rises and the timing at which the reception pulse signal RX pulse in is received are the same, reception of the reception pulse signal RX pulse in can be detected. .

However, if the transmission pulse width is narrowed in order to measure the distance between the target at a short distance and the distance sensor, it becomes necessary to increase the clock frequency of the transmission circuit 70 that generates the transmission pulse signal. For example, in order to generate a transmission pulse signal having a transmission pulse width T _Wmin shown in equation (2), it is necessary to set the clock frequency of the transmission circuit 70 to a frequency of 7.5 GHz or higher. When the transmission circuit 70 is driven at such a high frequency, it is necessary to repeat the operation of changing the logic value of the clock signal Clock in between low level and high level more than 7.5 billion times per second. This repetition charges and discharges the capacitive component of the transmission circuit 70, so that the amount of electric power calculated from charge/discharge current*logic level voltage*clock frequency is generated as heat. At 7.5 GHz, the clock frequency of the conventional transmission circuit 70 is almost the highest level, requiring a heat dissipation device for cooling the transmission circuit 70, which is unsuitable for miniaturization of the distance sensor. In addition, increasing the frequency of such a clock signal causes an increase in cost of the distance sensor and an increase in radiated noise to the outside, so improvement has been desired.

Further, as shown in FIG. 15, when the timing at which the clock signal Clock in rises and the timing at which the reception pulse signal RX pulse in is received are the same, the reception circuit 80 receives the reception pulse signal RX pulse in. However, since the timing at which the received pulse signal RX pulse in is received depends on the distance between the distance sensor and the target, the timing at which the clock signal Clock in rises and the received pulse signal RX pulse The timing at which in is received is not necessarily the same.

16 is a timing chart showing an example of the operation of the receiving circuit 80. FIG. In this example, the reception pulse signal RX pulse in is received between time t2 when the clock signal Clock in rises and time t3 when the clock signal Clock in next rises. If the transmission pulse width is narrowed in order to measure the distance between a short distance target and the distance sensor, the time width of the reception pulse signal is also narrowed. may be shorter than the time from time t2 to time t3. In this case, the reception timing of the reception pulse signal RX pulse in is not synchronized with the rising times t2 and t3 of the clock signal Clock in, and the detection signal DET remains at low level. As a result, the reception circuit 80 cannot detect the reception of the reception pulse signal RX pulse in even though it receives the reception pulse signal RX pulse in. Such a problem becomes more pronounced as the transmission pulse width is narrowed in order to measure the distance to a target at a short distance.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve such problems and to propose a distance sensor including a transmission circuit that transmits a transmission pulse signal without using a clock signal. Another object of the present invention is to propose a distance sensor that includes a receiving circuit that detects reception of a received pulse signal without using a clock signal.

In order to solve the above-described problems, a distance sensor according to the present invention is a distance sensor including a transmission circuit for transmitting a transmission pulse signal to a target, the transmission circuit receiving a first constant voltage and a variable voltage. a first comparator outputting a first logic signal indicating a true value when the variable voltage is lower than the first constant voltage; a second constant voltage different from the first constant voltage; and a variable voltage; and a second comparator that outputs a second logic signal indicating a true value when the variable voltage is higher than the second constant voltage; , a first logic signal indicating the true value output from the first comparator, and a second logic signal indicating the true value output from the second comparator are input. and a logical product circuit for outputting a logical product signal of the first logic signal and the second logic signal as a transmission pulse signal. With such a configuration, a transmission pulse signal with an extremely narrow transmission pulse width can be generated without using a clock signal. Solvable.

A distance sensor according to the present invention is a distance sensor comprising a receiving circuit for receiving a received pulse signal, which is a reflected pulse signal of a transmitted pulse signal reflected by a target, wherein the receiving circuit detects the received pulse signal. A holding circuit is provided to temporarily hold the signal. Detection of the received pulse signal even if the time width of the received pulse signal is narrowed due to narrowing of the transmitted pulse width in order to measure the distance between the target at a short distance and the distance sensor. is temporarily held, the reception of the received pulse signal can be reliably detected regardless of the timing at which the received pulse signal is received by the receiving circuit.

A distance sensor according to the present invention is a distance sensor comprising a transmission circuit for transmitting a transmission pulse signal and a reception circuit for receiving a reception pulse signal, which is a reflection pulse signal of the transmission pulse signal reflected by a target, wherein the transmission circuit inputs a first constant voltage and a variable voltage, and outputs a first logic signal indicating a true value when the variable voltage is lower than the first constant voltage; a second comparator that inputs a second constant voltage different from the voltage and a variable voltage, and outputs a second logic signal indicating a true value when the variable voltage is higher than the second constant voltage; to straddle the first constant voltage and the second constant voltage, the first logic signal output from the first comparator indicating the true value, and the output from the second comparator a second logic signal indicating the true value of the first logic signal and the second logic signal, and outputting a logic product signal of the first logic signal and the second logic signal as a transmission pulse signal; A holding circuit is provided for temporarily holding a detection signal indicating detection of a pulse signal. With such a configuration, a transmission pulse signal with an extremely narrow transmission pulse width can be generated without using a clock signal. Solvable. In addition, even if the time width of the received pulse signal is narrowed due to the narrowing of the transmission pulse width in order to measure the distance between the target at a short distance and the distance sensor, the received pulse signal Since the detection signal indicating the detection of is temporarily held, the reception of the received pulse signal can be reliably detected regardless of the timing at which the received pulse signal is received by the receiving circuit.

The transmit circuitry and receive circuitry may operate asynchronously. Asynchronous operation eliminates the need for a clock signal.

A distance sensor according to the present invention starts outputting current in response to an activation signal that instructs activation of a voltage control circuit to transmit a transmission pulse, and stops outputting current in response to a detection signal. A circuit, a charging element that charges the current output from the constant current circuit, and a control circuit that obtains the distance between the distance sensor and the target from the charging voltage of the charging element. With such a circuit configuration, both the transmission circuit and the reception circuit can be operated without using a clock signal.

According to the present invention, a transmission pulse signal can be transmitted without using a clock signal. Also, the reception pulse signal can be received without using the clock signal.

It is a block diagram showing the configuration of a distance sensor according to the embodiment of the present invention. 1 is a block diagram showing the configuration of a transmission circuit according to an embodiment of the present invention; FIG. 1 is a block diagram showing the configuration of a receiver circuit according to an embodiment of the present invention; FIG. 1 is a diagram showing a first circuit configuration example of a transmission circuit according to an embodiment of the present invention; FIG. 4 is a graph showing temporal changes in voltages of the transmission circuit according to the embodiment of the present invention; FIG. 5 is a diagram showing a second circuit configuration example of the transmission circuit according to the embodiment of the present invention; FIG. 5 is a diagram showing a third circuit configuration example of a transmission circuit according to the embodiment of the present invention; 4 is a graph showing temporal changes in voltages of the transmission circuit according to the embodiment of the present invention; It is a figure which shows the structural example of the receiving circuit in connection with embodiment of this invention. 4 is a timing chart showing an example of operation of the receiving circuit of the receiving circuit according to the embodiment of the present invention; It is a figure which shows the modification of the distance sensor in connection with embodiment of this invention. FIG. 2 is a diagram showing an example of a configuration of a transmission circuit used in a conventional distance sensor; 4 is a timing chart showing an example of operation of a transmission circuit used in a conventional distance sensor; 1 is a diagram showing an example of a configuration of a receiving circuit used in a conventional distance sensor; FIG. 4 is a timing chart showing an example of operation of a receiving circuit used in a conventional distance sensor; 4 is a timing chart showing an example of operation of a receiving circuit used in a conventional distance sensor;

Hereinafter, embodiments related to one aspect of the present invention will be described based on the drawings. The embodiments of the present invention are for facilitating understanding of the present invention, and are not for limiting interpretation of the present invention. The present invention may be modified or improved without departing from its spirit, and the present invention also includes equivalents thereof. In addition, the same reference numerals denote the same components, and duplicate descriptions are omitted.

[Application example]
FIG. 1 is a block diagram showing the configuration of a distance sensor 10 according to an embodiment of the invention. The distance sensor 10 includes a control circuit 20, a transmission circuit 30, and a reception circuit 40. The control circuit 20 is a microcomputer having a processor, memory, and an input/output interface. The transmission circuit 30 transmits a transmission pulse signal TX pulse out toward the target 100 in response to the activation signal Trig input from the control circuit 20 . The transmitted pulse signal TX pulse out is reflected by the target 100 . A received pulse signal RX pulse in, which is a reflected pulse signal of the transmitted pulse signal TX pulse out, returns to the distance sensor 10 . Upon receiving the reception pulse signal RX pulse in, the reception circuit 40 outputs to the control circuit 20 a detection signal EXPAND out indicating that reception of the reception pulse signal RX pulse in has been detected. The control circuit 20 obtains the distance between the distance sensor 10 and the target 100 from the time when the start signal Trig input is output to the transmission circuit 30 and the time when the detection signal EXPAND out is input from the reception circuit 40 .

FIG. 2 is a block diagram showing the configuration of the transmission circuit 30 according to the embodiment of the invention. The transmission circuit 30 includes a comparator 31 , a comparator 32 , a voltage control circuit 33 and an AND circuit 34 . The comparator 31 has an input terminal 311 to which a constant voltage V1 is input, an input terminal 312 to which a variable voltage is input, a non-inverting output terminal 313, and an inverting output terminal 314. A comparator 31 inputs a constant voltage V1 and a variable voltage, and outputs a first logic signal indicating a true value when the variable voltage is lower than the constant voltage V1. The comparator 32 has an input terminal 321 to which a constant voltage V2 is input, an input terminal 322 to which a variable voltage is input, a non-inverting output terminal 323, and an inverting output terminal 324. The comparator 32 inputs a constant voltage V2 different from the constant voltage V1 and a variable voltage, and outputs a second logic signal indicating a true value when the variable voltage is higher than the constant voltage V2. The voltage control circuit 33 changes the variable voltage across the constant voltage V1 and the constant voltage V2 in response to the activation signal Trig input from the control circuit 20 . The AND circuit 34 inputs the first output signal from the non-inverting output terminal 313 of the comparator 31 and the second output signal from the inverting output terminal 324 of the comparator 32, and outputs the first output signal and the second output signal. outputs a logical AND signal of the output signals of TX pulse out as a transmission pulse signal TX pulse out. That is, the AND circuit 34 inputs the first logic signal indicating the true value output from the comparator 31 and the second logic signal indicating the true value output from the comparator 32, and outputs the first logic signal and the second logical signal as the transmission pulse signal TX pulse out. Note that the constant voltage V1 may be higher than the constant voltage V2.

The polarity of the input terminal 311 of the comparator 31 and the polarity of the input terminal 321 of the comparator 32 are the same. For example, if the input terminal 311 of the comparator 31 is a non-inverting input terminal, the input terminal 321 of the comparator 32 is also a non-inverting input terminal. Further, for example, when the input terminal 311 of the comparator 31 is an inverting input terminal, the input terminal 321 of the comparator 32 is also an inverting input terminal.

When the variable voltage input to the input terminal 312 of the comparator 31 and the input terminal 322 of the comparator 32 is changed so as to straddle the constant voltage V1 and the constant voltage V2, the first voltage from the non-inverting output terminal 313 of the comparator 31 and the second output signal from the inverted output terminal 324 of the comparator 32 are both at high level, the AND signal output from the AND circuit 34 as the transmission pulse signal TX pulse out is at high level. become a level. As a result, the transmission pulse signal TX pulse out is output from the transmission circuit 30 . With such a configuration, a transmission pulse signal with an extremely narrow transmission pulse width can be generated without using a clock signal. Solvable.

FIG. 3 is a block diagram showing the configuration of the receiving circuit 40 according to the embodiment of the invention. The receiving circuit 40 includes an amplifier circuit 41 that amplifies the received pulse signal RX pulse in, and a holding circuit 42 that temporarily holds a detection signal EXPAND out indicating detection of the received pulse signal RX pulse in. Even if the time width of the reception pulse signal RX pulse in is narrowed due to narrowing the transmission pulse width in order to measure the distance between the target at a short distance and the distance sensor 10, the reception Since the detection signal EXPAND out indicating the detection of the pulse signal RX pulse in is temporarily held, the reception pulse signal RX pulse in is received regardless of the timing at which the reception pulse signal RX pulse in is received by the reception circuit 40. can be reliably detected.

Both the transmission circuit 30 and the reception circuit 40 can operate asynchronously without using a clock signal.

[Example of circuit configuration]
FIG. 4 is a diagram showing a first circuit configuration example of the transmission circuit 30. As shown in FIG. The comparator 31 includes a comparator Comp1 and resistors R _I1 and R _NI1 . A constant voltage V1 is input to the non-inverting input terminal of the comparator Comp1, and a variable voltage is input to the inverting input terminal of the comparator Comp1. A resistor R _NI1 is connected between the signal path connecting the non-inverted output terminal of the comparator Comp1 and the AND circuit 34 and the ground. _A resistor RI is connected between the inverting output terminal of the comparator Comp1 and the ground.

The comparator 32 has a comparator Comp2 and resistors R _I2 and R _NI2 . A constant voltage V2 is input to the non-inverting input terminal of the comparator Comp2, and a variable voltage is input to the inverting input terminal of the comparator Comp2. A resistor R _I2 is connected between the signal path connecting the inverted output terminal of the comparator Comp2 and the AND circuit 34 and the ground. A resistor R _NI2 is connected between the non-inverting output terminal of the comparator Comp2 and the ground.

The voltage control circuit 33 includes a transistor TR, resistors R, R _b1 , R _b2 and a capacitor C. A start signal Trig input is input from the control circuit 20 to the base terminal of the transistor TR through the resistor R _b1 . The base terminal of transistor TR is connected to ground through resistor R _b2 . The emitter terminal of transistor TR is connected to the ground. A collector terminal of the transistor TR is connected to the ground through a capacitor C, and receives a constant voltage Vcc through a resistor R. The charged voltage of the capacitor C is input to the inverting input terminals of the comparators Comp1 and Comp2 as a variable voltage that changes according to the ON/OFF operation of the transistor TR.

The logical product circuit 34 has a logical product gate AND. The AND gate AND receives the first output signal from the non-inverting output terminal of the comparator Comp1 and the second output signal from the inverting output terminal of the comparator Comp2, and outputs the first output signal and the second output A logical AND signal of the signals is output as a transmission pulse signal TX pulse out.

In this example, it is assumed that the relationship 0<V2<V1<Vcc is satisfied.

Next, operation of the transmission circuit 30 will be described. In the standby state, the voltage of the start-up signal Trig input output from the control circuit 20 is adjusted to such a voltage that the emitter-collector of the transistor TR becomes conductive. In this standby state, the capacitor C is short-circuited to the ground through the transistor TR, so the amount of charge charged in the capacitor C is almost zero, and the charging voltage of the capacitor C is also almost zero. As a result, the voltages input to the inverting input terminals of the comparators Comp1 and Comp2 are also substantially zero. Since both the constant voltages V1 and V2 are set to positive voltages, the first output signal from the non-inverting output terminal of the comparator Comp1 becomes high level, and the second output signal from the inverting output terminal of the comparator Comp2 becomes high. The output signal becomes low level. A logical product signal of the first output signal and the second output signal becomes low level. In this manner, in the standby state, the transmission pulse signal TX pulse out is maintained at the low level, and the transmission pulse signal TX pulse out is not transmitted from the transmission circuit 30 .

When the transmission circuit 30 is caused to transition from the standby state to the activation state, the voltage of the activation signal Trig input output from the control circuit 20 decreases until the emitter-collector of the transistor TR becomes non-conductive. When the transistor TR is turned off, the constant voltage Vcc is applied to the capacitor C through the resistor R, and the charged voltage of the capacitor C increases. The charging voltage of the capacitor C rises from a voltage value of approximately zero toward the constant voltage Vcc according to the time constant determined by the capacitance of the capacitor C and the resistance value of the resistor R.

During the period when the charged voltage of the capacitor C is lower than the constant voltage V2, the first output signal from the non-inverting output terminal of the comparator Comp1 becomes high level, and the second output signal from the inverting output terminal of the comparator Comp2 becomes low level. be the level. A logical product signal of the first output signal and the second output signal becomes low level. In this way, during the period in which the charged voltage of the capacitor C is lower than the constant voltage V2, the transmission pulse signal TX pulse out is maintained at the low level, and the transmission pulse signal TX pulse out is transmitted from the transmission circuit 30. remain untouched.

During the period when the charged voltage of the capacitor C exceeds the constant voltage V2 and falls below the constant voltage V1, the first output signal from the non-inverting output terminal of the comparator Comp1 becomes high level, and the first output signal from the inverting output terminal of the comparator Comp2 becomes high. 2 also goes high. A logical AND signal of the first output signal and the second output signal becomes high level. In this way, during the period when the charged voltage of the capacitor C exceeds the constant voltage V2 and falls below the constant voltage V1, the transmission pulse signal TX pulse out is high level, and the transmission pulse signal TX pulse out is transmitted from the transmission circuit 30. be done.

During the period when the charged voltage of the capacitor C exceeds the constant voltage V1, the first output signal from the non-inverting output terminal of the comparator Comp1 becomes low level, and the second output signal from the inverting output terminal of the comparator Comp2 becomes high level. be the level. A logical product signal of the first output signal and the second output signal becomes low level. In this way, during the period when the charged voltage of the capacitor C exceeds the constant voltage V1 and falls below the constant voltage Vcc, the transmission pulse signal TX pulse out is low level, and the transmission pulse signal TX pulse out is transmitted from the transmission circuit 30. not.

To summarize the above operation, the transmission pulse signal TX pulse out is transmitted from the transmission circuit 30 during the period when the charging voltage of the capacitor C exceeds the constant voltage V2 and falls below the constant voltage V1. As a result, a transmission pulse signal TX pulse out having an extremely narrow transmission pulse width can be generated without using a clock signal.

FIG. 5 is a graph showing the time change of each voltage. Reference numeral 501 indicates the time change of the charging voltage of the capacitor C. FIG. Reference numeral 502 indicates the time change of the constant voltage V1. Reference numeral 503 indicates the time change of the constant voltage V2. Reference numeral 504 indicates the time change of the transmission pulse signal TX pulse out.

Assuming that the charging voltage of the capacitor C is Vc, the formula (3) holds.

Vc=Vcc×(1-exp(-t/RC)) (3)

Here, t indicates the elapsed time after the activation signal Trig input is input so that the transistor TR is turned off. R indicates the resistance value of the resistor R; C indicates the capacitance value of the capacitor C; Here, for example, V1=1V, V2=0.8V, Vcc=3.3V, R=470Ω, C=3.3pF, and the time t at which Vc=V2 is calculated from equation (3), t= It is 430.6 psec. Also, the time t at which Vc=V1 is calculated from the equation (3) is t=559.9 psec. The period during which the charging voltage Vc of the capacitor C exceeds the constant voltage V2 and falls below the constant voltage V1 is 559.9 psec−430.6 psec≈130 psec. From this calculation result, the transmission pulse width is 130 psec. In order to generate a transmission pulse signal having a transmission pulse width of 130 psec using the conventional transmission circuit 70 that generates a transmission pulse signal using a clock signal, it is necessary to set the clock frequency to a high frequency of 7.7 GHz. be. In contrast, according to the transmission circuit 30 according to the embodiment of the present invention, a transmission pulse signal having a transmission pulse width of 130 psec can be generated without using a clock signal. Problems such as radiation noise countermeasures and price increases can be solved.

FIG. 6 is a diagram showing a second circuit configuration example of the transmission circuit 30. As shown in FIG. The configuration of the transmission circuit 30 shown in FIG. 4 in that a constant voltage V2 is input to the terminal and a variable voltage is input to the non-inverting input terminal of the comparator Comp2. are common. The principle of operation of the transmission circuit 30 shown in FIG. 6 is the same as the principle of operation of the transmission circuit 30 shown in FIG.

FIG. 7 is a diagram showing a third circuit configuration example of the transmission circuit 30. As shown in FIG. The voltage control circuit 33 of the transmission circuit 30 shown in FIG. 7 has a different circuit configuration from the voltage control circuit 33 of the transmission circuit 30 shown in FIG. ) are common. The voltage control circuit 33 of the transmission circuit 30 shown in FIG. 7 includes an operational amplifier OP1, a transistor TR, a logical NOT gate INV, a feedback capacitor C, and resistors R1, R2, R3, _Rb1 and _Rb2 . A start signal Trig input is input from the control circuit 20 to the base terminal of the transistor TR through a logic NOT gate INV and a resistor R _b1 . The base terminal of transistor TR is connected to ground through resistor R _b2 . The collector terminal of the transistor TR is connected to the inverting input terminals of the comparators Comp1 and Comp2.

A start signal Trig input is input from the control circuit 20 to the non-inverting input terminal of the operational amplifier OP1 through the resistor R3. A non-inverting input terminal of the operational amplifier OP1 is grounded through a resistor R2. The inverting input terminal of the operational amplifier OP1 is connected to the ground through the resistor R1 and to the output terminal of the operational amplifier OP1 through the feedback capacitor C. The output terminal of the operational amplifier OP1 is connected to the inverting input terminals of the comparators Comp1 and Comp2. The operational amplifier OP1 constitutes an integration circuit, and by integrating the activation signal Trig input, generates a variable voltage that increases with the lapse of time. This variable voltage is input to the inverting input terminals of the comparators Comp1 and Comp2.

Next, operation of the transmission circuit 30 will be described. In the standby state, the voltage of the activation signal Trig input is zero. Since the logical NOT gate INV inverts the logic value of the start signal Trig input, its output signal becomes high level, and the collector-emitter of the transistor TR becomes conductive. Since the emitter of the transistor TR is grounded, the potential of the collector of the transistor TR is also substantially zero, and the voltages input to the inverting input terminals of the comparators Comp1 and Comp2 are also substantially zero. At the same time, the voltage at the output terminal of the operational amplifier OP1 also becomes almost zero. Further, when the voltage of the activation signal Trig input becomes zero, the voltage input to the non-inverting input terminal of the operational amplifier OP1 also becomes zero. Since the voltage at the output terminal of the operational amplifier OP1 is stable at almost zero, no current flows through the feedback capacitor C connected to the output terminal of the operational amplifier OP1. Therefore, the voltage of the inverting input terminal of the operational amplifier OP1 is stabilized at almost zero.

In the standby state, the first output signal from the non-inverting output terminal of the comparator Comp1 is at high level, and the second output signal from the inverting output terminal of the comparator Comp2 is at low level. A logical product signal of the first output signal and the second output signal becomes low level. In this manner, in the standby state, the transmission pulse signal TX pulse out is maintained at the low level, and the transmission pulse signal TX pulse out is not transmitted from the transmission circuit 30 .

When the transmission circuit 30 is caused to transition from the standby state to the activation state, the voltage of the activation signal Trig input output from the control circuit 20 transitions from low level (zero voltage) to high level. Since the logical NOT gate INV inverts the logic value of the start signal Trig input, its output signal becomes low level, and the collector-emitter of the transistor TR becomes non-conductive. Assuming that the voltage of the start signal Trig input is Vtrig and the voltage of the non-inverting input terminal of the operational amplifier OP1 is Vin+, Equation (4) holds.

Vin+=Vtrig×R2/(R2+R3) (4)

Here, R2 and R3 are resistance values of resistors R2 and R3, respectively. Immediately after the voltage of the activation signal Trig input output from the control circuit 20 transitions from low level (zero voltage) to high level, the voltage applied to the inverting input terminal of the operational amplifier OP1 remains substantially zero. Since the voltage at the non-inverting input terminal of operational amplifier OP1 is higher than the voltage at its inverting input terminal, the voltage at its output terminal starts to ramp up from near zero. In the standby state, since the charge in the feedback capacitor C is almost zero, when the voltage at one of the two terminals of the feedback capacitor C (the terminal connected to the output terminal of the operational amplifier OP1) rises sharply, the voltage at the other terminal ( The voltage at the terminal connected to the inverting input terminal of the operational amplifier OP1 also rises sharply, trying to keep the charge in the feedback capacitor C at approximately zero. In this way, the voltage at the inverting input terminal of the operational amplifier OP1 rises, and when the voltage at the inverting input terminal of the operational amplifier OP1 approaches the voltage at the non-inverting input terminal of the operational amplifier OP1, the voltage at the output terminal of the operational amplifier OP1 gradually rises. become. When the rise in voltage at the output terminal of the operational amplifier OP1 slows down, the rise in voltage at the inverting input terminal of the operational amplifier OP1 also stops, and discharge starts from the inverting input terminal of the operational amplifier OP1 through the resistor R1.

Here, assuming that the voltage of the inverting input terminal of the operational amplifier OP1 is Vin- and the resistance value of the resistor R1 is R1, the current discharged from the inverting input terminal of the operational amplifier OP1 is Vin-/R1. When the voltage of the inverting input terminal of the operational amplifier OP1 drops due to this discharge, Vin-<Vin+. The voltage at the output terminal of the operational amplifier OP1 starts to rise again in order to raise the voltage Vin- so that the voltage Vin-, which drops due to the current discharge, becomes the same voltage as the voltage Vin+. Assuming that the charging current of the feedback capacitor C is Icharge, the voltage of the output terminal of the operational amplifier OP1 changes so that the charging current of Icharge=Vin-/R1 flows through the feedback capacitor C.

Assuming that the voltage at the output terminal of the operational amplifier OP1 is Vout, the voltage Vout changes according to equation (5) in order to generate the charging current Icharge over time t.

Icharge×t=C×(Vout−Vin) (5)

Here, C is the capacitance value of the feedback capacitor C. Vin=Vin+-Vin-. Transforming the formula (5) gives the formula (6).

Vout=(Icharge/C)×t+Vin (6)

Since both Icharge/C and Vin are constants, the voltage Vout is a variable voltage that monotonically increases with time t. This variable voltage is input to the inverting input terminals of the comparators Comp1 and Comp2. Due to a change over time in the variable voltages input to the inverting input terminals of the comparators Comp1 and Comp2, a transmission pulse is generated from the transmission circuit 30 according to an operation principle similar to that of the first circuit configuration example of the transmission circuit 30. A signal TX pulse out is sent.

FIG. 8 is a graph showing the time change of each voltage. Reference numeral 801 indicates the time change of the voltage Vout. Reference numeral 802 indicates the time change of the transmission pulse signal TX pulse out.

For example, when Vin=0.1 V, C=4.7 pF, and R=100 Ω, the voltage Vout is calculated from the equation (6), resulting in Vout=212765957.4×t+0.1 [V].

In the transmission circuit 30 shown in FIG. 7, variable voltages are input to the inverting input terminals of the comparators Comp1 and Comp2, and voltages V1 and V2 are input to the non-inverting input terminals of the comparators Comp1 and Comp2. A variable voltage may be input to the non-inverting input terminals of the comparators Comp1 and Comp2, and the voltages V1 and V2 may be input to the inverting input terminals of the comparators Comp1 and Comp2.

FIG. 9 is a diagram showing a circuit configuration example of the receiving circuit 40. As shown in FIG. The amplifier circuit 41 includes an operational amplifier OP2 and resistors R4 and R5. The inverting input terminal of the operational amplifier OP2 is connected to the ground through the resistor R4 and to the output terminal of the operational amplifier OP2 through the resistor R5. A received pulse signal RX pulse in is input to the non-inverting input terminal of the operational amplifier OP2. The holding circuit 42 includes logic NOT gates NOT1, NOT2 and AND gates NAND1, NAND2. One input of the logical NOT gate NAND1 is connected to the output terminal of the operational amplifier OP2 through the logical NOT gate NOT1, and the other input of the logical NOT gate NAND1 is connected to the output of the logical NOT gate NAND2. A reset signal is input to one input of the logical NOT gate NAND2 through the logical NOT gate NOT2, and the other input of the logical NOT gate NAND2 is connected to the output of the logical NOT gate NAND1. A detection signal EXPAND out indicating detection of the received pulse signal RX pulse in is output from the logical NOT gate NOT1. When the reception pulse signal RX pulse in is received by the reception circuit 40, the detection signal EXPAND out transitions from low level to high level. The holding circuit 42 temporarily holds the detection signal EXPAND out until the reset signal is input to the logic NOT gate NOT2 after the detection signal EXPAND out transitions from low level to high level.

10 is a timing chart showing an example of the operation of the receiving circuit 80. FIG. Although the receiving circuit 40 operates without using the clock signal Clock, for the purpose of comparing the operation of the receiving circuit 40 with the operation of the conventional receiving circuit 80 shown in FIGS. A signal Clock in is described. When the reset signal input to the logical NOT gate NOT2 becomes high level, the detection signal EXPAND out becomes low level and enters a standby state. After that, the transmission pulse signal TX pulse out is transmitted at the timing of time t1 when the clock signal Clock in rises. When the reception pulse signal RX pulse in is received between time t2 when the clock signal Clock in rises and time t3 when the clock signal Clock in next rises, the detection signal is generated simultaneously with the reception of the reception pulse signal RX pulse in. EXPAND out transitions from low to high. The detection signal EXPAND out is maintained at high level until the reset signal is input at the timing of time t4. As a result, although the conventional receiving circuit 80 receives the received pulse signal RX pulse in, it is possible to detect the reception of the received pulse signal RX pulse in depending on the reception timing of the received pulse signal RX pulse in. It is possible to solve the problem of not being able to

FIG. 11 is a block diagram showing a modification of the distance sensor 10 according to the embodiment of the invention. The distance sensor 10 includes a control circuit 20 , a transmission circuit 30 , a reception circuit 40 , a constant current circuit 50 and a charging element 60 . The constant current circuit 50 starts outputting current to the charging element 60 in response to the start signal Trig input instructing the start of the voltage control circuit 33 to transmit the transmission pulse signal TX pulse out, and the reception pulse signal TX pulse out. In response to the detection signal EXPAND out indicating detection of RX pulse in, current output to charging element 60 is stopped. Charging element 60 charges the current output from constant current circuit 50 . The timing at which the activation signal Trig input is output matches the timing at which the transmission pulse signal is sent, and the timing at which the detection signal EXPAND out is output matches the timing at which the reception pulse signal is received. is proportional to the time difference between the timing at which the detection signal EXPAND out is output and the timing at which the detection signal EXPAND out is output (that is, the distance between the distance sensor 10 and the target 100). . Control circuit 20 determines the distance between distance sensor 10 and target 100 from the charging voltage of charging element 60 . With such a circuit configuration, both the transmission circuit 30 and the reception circuit 40 can be operated without using a clock signal.

The embodiment of the present invention is not limited to the example of determining the distance between the distance sensor 10 and the target object 100 from the charging voltage of the charging element 60 . A distance to the object 100 may be determined. In this example, charging element 60 is precharged with a predetermined amount of charge. The constant current circuit 50 starts outputting current from the charging element 60 in response to the start signal Trig input instructing the start of the voltage control circuit 33 to transmit the transmission pulse signal TX pulse out, and the reception pulse signal RX. The current output from the charging element 60 is stopped in response to the detection signal EXPAND out indicating the detection of pulse in. Since the amount of change (amount of discharge) in the charging voltage of the charging element 60 is proportional to the distance between the distance sensor 10 and the target 100, the control circuit 20 detects the change in the charging voltage of the charging element 60 from the distance sensor 10. A distance to the target 100 can be determined.

Some or all of the above-described embodiments may be described as in the following appendices, but are not limited to the following.
(Appendix 1)
A distance sensor 10 including a transmission circuit 30 that transmits a transmission pulse signal to a target 100,
The transmission circuit 30 is
A first comparator having a first input terminal 311 to which a first constant voltage V1 is input, a second input terminal 312 to which a variable voltage is input, a non-inverting output terminal 313, and an inverting output terminal 314 31 and
A third input terminal 321 to which the second constant voltage V2 is input, the third input terminal 321 having the same polarity as the polarity of the first input terminal 311, and a fourth input terminal 321 to which the variable voltage is input. a second comparator 32 having an input terminal 322 of, a non-inverting output terminal 324, and an inverting output terminal 323;
a voltage control circuit 33 that changes the variable voltage in a voltage range between the first constant voltage V1 and the second constant voltage V2;
A first output signal from the non-inverting output terminal 313 of the first comparator 31 and a second output signal from the inverting output terminal 324 of the second comparator 32 are inputted, and the first output signal and the second a logical product circuit 34 for outputting a logical product signal of the output signals of as a transmission pulse signal;
A distance sensor 10 comprising:
(Appendix 2)
A distance sensor 10 comprising a receiving circuit 40 for receiving a received pulse signal, which is a reflected pulse signal of a transmitted pulse signal reflected by a target 100,
The distance sensor 10, wherein the receiving circuit 40 includes a holding circuit 42 that temporarily holds a detection signal indicating detection of the received pulse signal.
(Appendix 3)
A distance sensor 10 comprising a transmission circuit 30 for transmitting a transmission pulse signal and a reception circuit 40 for receiving a reception pulse signal which is a reflection pulse signal of the transmission pulse signal reflected by a target 100,
The transmission circuit 30 is
A first comparator having a first input terminal 311 to which a first constant voltage V1 is input, a second input terminal 312 to which a variable voltage is input, a non-inverting output terminal 313, and an inverting output terminal 314 31 and
A third input terminal 321 to which the second constant voltage V2 is input, the third input terminal 321 having the same polarity as the polarity of the first input terminal 311, and a fourth input terminal 321 to which the variable voltage is input. a second comparator 32 having an input terminal 322 of, a non-inverting output terminal 324, and an inverting output terminal 323;
a voltage control circuit 33 that changes the variable voltage in a voltage range between the first constant voltage V1 and the second constant voltage V2;
A first output signal from the non-inverting output terminal 313 of the first comparator 31 and a second output signal from the inverting output terminal 324 of the second comparator 32 are inputted, and the first output signal and the second and a logical product circuit 34 that outputs a logical product signal of the output signals of as a transmission pulse signal,
The distance sensor 10, wherein the receiving circuit 40 includes a holding circuit 42 that temporarily holds a detection signal indicating detection of the received pulse signal.
(Appendix 4)
The distance sensor 10 according to Appendix 3,
The distance sensor 10, wherein the transmitting circuit 30 and the receiving circuit 40 operate asynchronously.

DESCRIPTION OF SYMBOLS 10... Distance sensor 20... Control circuit 30... Transmission circuit 31... Comparator 32... Comparator 33... Voltage control circuit 34... AND circuit 40... Receiving circuit 41... Amplifier circuit 42... Holding circuit

Claims (6)

A distance sensor comprising a transmission circuit for transmitting a transmission pulse signal to a target,
The transmission circuit is
a first comparator that inputs a first constant voltage and a variable voltage and outputs a first logic signal indicating a true value when the variable voltage is lower than the first constant voltage;
A second constant voltage different from the first constant voltage and the variable voltage are input, and a second logic signal indicating a true value is output when the variable voltage is higher than the second constant voltage. a second comparator;
a voltage control circuit that changes the variable voltage across the first constant voltage and the second constant voltage;
inputting a first logic signal indicating the true value output from the first comparator and a second logic signal indicating the true value output from the second comparator; a logical product circuit that outputs a logical product signal of the signal and the second logic signal as the transmission pulse signal;
A distance sensor. A distance sensor comprising a receiving circuit for receiving a received pulse signal, which is a reflected pulse signal in which the transmitted pulse signal is reflected by a target,
The distance sensor, wherein the receiving circuit includes a holding circuit that temporarily holds a detection signal indicating detection of the received pulse signal. A distance sensor comprising: a transmission circuit for transmitting a transmission pulse signal; and a reception circuit for receiving a reception pulse signal, which is a reflection pulse signal of the transmission pulse signal reflected by a target,
The transmission circuit is
a first comparator that inputs a first constant voltage and a variable voltage and outputs a first logic signal indicating a true value when the variable voltage is lower than the first constant voltage;
A second constant voltage different from the first constant voltage and the variable voltage are input, and a second logic signal indicating a true value is output when the variable voltage is higher than the second constant voltage. a second comparator;
a voltage control circuit that changes the variable voltage across the first constant voltage and the second constant voltage;
inputting a first logic signal indicating the true value output from the first comparator and a second logic signal indicating the true value output from the second comparator; a logical product circuit that outputs a logical product signal of the signal and the second logic signal as the transmission pulse signal,
The distance sensor, wherein the receiving circuit includes a holding circuit that temporarily holds a detection signal indicating detection of the received pulse signal. A distance sensor according to claim 3,
The distance sensor, wherein the transmitting circuit and the receiving circuit operate asynchronously. The distance sensor according to claim 3 or 4,
a constant current circuit that starts outputting current in response to an activation signal instructing activation of the voltage control circuit to transmit the transmission pulse, and stops outputting current in response to the detection signal;
a charging element that charges the current output from the constant current circuit;
a control circuit for determining the distance between the distance sensor and the target from the charging voltage of the charging element;
distance sensor. The distance sensor according to claim 3 or 4,
a charging element for charging an electric charge;
Output of current from the charging element is started in response to an activation signal instructing activation of the voltage control circuit to transmit the transmission pulse, and output of current from the charging element is responded to the detection signal. a constant current circuit that stops
a control circuit that determines the distance between the distance sensor and the target from changes in the charging voltage of the charging element;
distance sensor.

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