JP2022133756A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device capable of easily associating a position on an observation image with a position on design data.SOLUTION: A semiconductor device according to an embodiment includes a circuit pattern including a plurality of unit patterns repeatedly arranged in at least one direction, and a determination pattern provided in the circuit pattern and capable of determining the unit pattern.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.

Semiconductor device manufacturing methods include processes such as etching and deposition processes for forming semiconductor devices, observation of interlayer insulating films in which grooves and holes for wiring, vias, contacts, etc. are formed, and formation of wiring, etc. An observation step of observing the wiring layer formed by the wiring layer is included. In the observation step, for example, an optical microscope or a scanning electron microscope (SEM) is used to confirm the presence or absence of manufacturing problems such as the presence or absence of unintended scattering of particles. If a manufacturing problem is found, its positional information becomes important information for yield improvement and the like. However, when the same pattern is repeatedly formed on the substrate, it may be difficult to determine which part of the design data the image obtained by observation corresponds to.

JP 2012-227283 A

One embodiment provides a semiconductor device and a method of manufacturing the same that can easily associate a position on an observation image with a position on design data.

According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns repeatedly arranged in at least one direction, and a discrimination pattern provided in the circuit pattern and capable of discriminating the unit pattern. is provided.

FIG. 1 is a diagram for explaining a circuit pattern formed by repeatedly arranging unit patterns provided in a semiconductor device according to an embodiment. FIG. 2 is a diagram for explaining the effect of the circuit pattern of the semiconductor device of this embodiment. FIG. 3 is a top view schematically showing a circuit pattern of a modification. FIG. 4 is a top view schematically showing a circuit pattern of another modified example. FIG. 5 is a top view schematically showing a circuit pattern of another modification. FIG. 6 is a top view schematically showing a circuit pattern of another modified example. FIG. 7 is a top view schematically showing a circuit pattern of another modified example. FIG. 8 is an explanatory diagram for explaining a circuit pattern of a further modified example. FIG. 9 is a block diagram schematically showing the configuration of a NAND memory. FIG. 10 is a block diagram schematically showing the structure of a DRAM memory. FIG. 11 is a block diagram schematically showing the configuration of an imaging device.

Non-limiting exemplary embodiments of the invention will now be described with reference to the accompanying drawings. In all the attached drawings, the same or corresponding members or parts are denoted by the same or corresponding reference numerals, and overlapping descriptions are omitted. Also, the drawings are not intended to show the relative proportions between members or parts, so specific thicknesses and dimensions may be determined by one of ordinary skill in the art in light of the following non-limiting embodiments.

An example of a circuit pattern included in the semiconductor device according to the embodiment will be described with reference to FIG. The semiconductor device in this embodiment may be, but not limited to, a semiconductor memory device. As the circuit pattern, a circuit pattern formed by repeatedly arranging a plurality of unit patterns having the same shape in one direction is exemplified. The circuit pattern in this embodiment is intended for a figure appearing in an observed image obtained in the manufacturing process of a semiconductor device. Therefore, an observation image is assumed to be an image obtained from the upper surface of the semiconductor substrate. In addition, since the shape of the wiring connected to the element on the circuit diagram and the shape of the wiring not connected to the element on the circuit diagram also appear in the observation image, they are the target of the circuit pattern. Further, as will be described later, the circuit pattern is not limited to wiring, and may be grooves or holes appearing in the observed image. Examples of circuits and semiconductor devices in which such circuit patterns are formed will be described later.

FIG. 1(a) is a top view schematically showing a unit pattern, FIG. 1(b) is a top view schematically showing a circuit pattern formed by a plurality of unit patterns, and FIG. ) is a top view schematically showing a circuit pattern of the semiconductor device 1 according to the present embodiment. The unit pattern, the circuit pattern, and the discrimination pattern include, for example, wiring formed of a conductive material such as metal or conductive polycrystalline silicon on an insulating film. In other words, the unit pattern, circuit pattern, and discrimination pattern may be wiring formed in the same layer in the semiconductor device 1 .

As shown in FIG. 1B, a circuit pattern 12 is formed by repeatedly arranging the unit patterns 10 shown in FIG. 1A in the X direction. The unit pattern 10 may be a wiring pattern formed for, for example, one column (or row) of the semiconductor device 1 according to this embodiment as a semiconductor memory device. In the illustrated example, the unit pattern 10 includes a plurality of lines 10A extending in the Y direction, lines 10B extending in the Y direction but shorter than the lines 10A, and connecting portions 10C connecting the lines 10B to the lines 10A. there is The unit pattern 10 is formed, for example, for one column (or row), and the columns (or rows) are provided repeatedly. A circuit pattern 12 is formed by repeatedly arranging the unit patterns 10 .

The circuit pattern 120 in this embodiment has a discrimination pattern 14 in addition to the circuit pattern 12, as shown in FIG. 1(c). In the illustrated example, the discrimination pattern 14 has four types of discrimination figures 14A, 14B, 14C, and 14D. The distinguishing figure 14A is a line continuously extending in the Y direction, and the distinguishing figures 14B to 14D are a combination of a plurality of lines with different lengths in the Y direction. In this way, the discriminating figures 14A to 14D have shapes different from each other, so that they can be discriminated from each other. Further, the discrimination figures 14A to 14D are sequentially provided in the blank area BA (FIG. 1(a)) of each of the four unit patterns 10, and therefore are arranged in this order along the X direction. Here, the blank area BA is not formed with circuit elements such as lines, and is a relatively wide range of a base layer of the wiring layer forming the circuit pattern or an insulating film of the same layer as the wiring layer forming the circuit pattern. exposed area. Although not shown, the unit patterns 10 are repeatedly arranged on the left and right sides of the figure, and the discrimination figures 14A to 14D are arranged along the X direction for these unit patterns 10 as well. They are arranged periodically in this order.

The circuit pattern 120 is generated in advance from design data, and the positions of each unit pattern 10 and discrimination figures 14A to 14D can be specified by coordinates with a predetermined coordinate reference point (eg, alignment mark) as the origin on the design data. In addition, the circuit pattern 120 is formed by, for example, forming a trench or the like in an insulating film by a photolithography process using a photomask manufactured based on design data, filling the trench or the like with a conductive material such as metal, and performing chemical mechanical polishing. It may be formed by a damascene method that removes the conductive material on the insulating film by a (CMP) method. In addition, a reaction for forming the circuit pattern 120 through a process of depositing a thin film of a conductive material such as metal or conductive polycrystalline silicon, a photolithography process using a photomask manufactured based on design data, and an etching process. A reactive ion etching (RIE) method may be used.

It should be noted that the unit patterns 10 in the circuit pattern 12 do not have the same shape by including the discrimination figures 14A to 14D, respectively. Therefore, there is no circuit pattern in which unit patterns of the same shape are repeatedly arranged. Therefore, here, the circuit pattern in which the unit patterns of the same shape are repeatedly arranged means a pattern in which the unit patterns cannot be individually discriminated by the surface observation means unless there is a discriminating pattern that enables discrimination of the unit patterns. do.

Moreover, the shape of the unit pattern 10 in the circuit pattern 12 may be the same within the range of error in the manufacturing process. In the drawings, for example, the discrimination figures 14A-14D have right-angled corners, but in reality they may have rounded corners depending on the manufacturing process (etching).

Next, the effect produced by the circuit pattern 120 will be described with reference to FIG. FIG. 2 is a diagram for explaining the effect of the circuit pattern 120 of the semiconductor device 1 according to this embodiment. Specifically, FIG. 2A is a top view schematically showing a semiconductor substrate having a circuit pattern 12 as a comparative example, and FIG. is a top view shown in FIG. FIGS. 2A and 2B show an imaging range (field of view) IR when the circuit patterns 12 and 120 are imaged by a scanning electron microscope (SEM) as surface observation means. That is, the shape within the imaging range IR is obtained as one piece of image data.

When particle PCL is detected as a result of observing the circuit pattern 12 by a so-called die-to-die method using an SEM, as shown in FIG. 12 images are displayed. At this time, although the particle PCL is actually at the position Pt, the die-to-die method may show coordinate information that "the particle PCL is at the position Pf." Such a deviation can occur, for example, due to an error associated with movement of a stage that holds the substrate to be measured within the SEM. In this case, even if an attempt is made to specify the position on the design data of the position Pt where the particle PCL actually exists, since the unit patterns 10 are repeated in the circuit pattern 12, the position Pt exists in the vicinity of which unit pattern 10. It is not easy to decide whether to

However, according to this embodiment, as shown in FIG. 2B, the circuit pattern 120 has the identification pattern 14, and the identification figures 14A to 14D have different shapes. Therefore, it is understood from the SEM image data that the discriminant figure 14B exists in the vicinity of the position Pt of the particle PCL. Therefore, even if the coordinates of the particle position Pf indicated by the die-to-die method deviate from the design data coordinates of the position Pt where the particles PCL actually exist, can be corrected by Then, it becomes possible to identify the position of the particle PCL on the design data. That is, since there is the discrimination pattern 14, matching between the image data acquired by the SEM and the design data becomes easy, and the position of the particle PCL can be obtained on the design data.

It should be noted that the number of types of discrimination figures does not have to be equal to the number of repetitions of the unit pattern 10 . For example, instead of providing a distinguishing figure to each of the unit patterns 10, the distinguishing figure may be provided at intervals of one, two, or more. This makes it possible to reduce the number of types of discrimination figures to be prepared, and furthermore to make it possible to clearly differentiate the shapes of the discrimination figures.

Also, the number of types of discrimination figures to be prepared may be determined based on the number of unit patterns that can be captured in the entire SEM image in a predetermined imaging range and imaging magnification. For example, when the width (repetition pitch) of each unit pattern repeatedly arranged in the X direction is 400 nm and the width of the imaging range IR of the SEM corresponds to 9 μm on the substrate, 22 unit patterns 10 are shown in the SEM image. can be captured. At this time, 22 kinds of identification figures having different shapes may be prepared and given to the 22 unit patterns 10 respectively. In this case, 22 types of discrimination figures having different shapes are arranged periodically, and all the unit patterns 10 have discrimination figures. Further, 11 types of distinguishing figures having different shapes may be prepared, given to every other unit pattern 10, and 22 unit patterns 10 to which the distinguishing figure is given every other may be arranged periodically. . In addition, for example, eight types of different discrimination figures having different shapes are prepared, and assigned to every two unit patterns 10, and the 22 unit patterns 10 to which the discrimination figures are assigned every two are arranged periodically. may Furthermore, the discrimination figure may be provided for every three or more unit patterns 10 .

Also, the number of types of discriminant patterns to be prepared may be determined in consideration of the positional error that may occur in the die-to-die system (the difference between the position Pt and the position Pf in the above example). The position error that can occur in the die-to-die method is considered to be, for example, 0.5 μm to 2 μm, but if it is 1.5 μm and the width of the unit pattern 10 is 400 nm, three types of discrimination figures are prepared. I wish I could. According to this, the position of the discriminant figure in the vicinity of the position Pf indicated by the die-to-die method can be known, and therefore the actual position Pt can be specified. Similarly, when the positional error is 1.5 μm and the repetition pitch is 80 nm, 13 types of discriminant patterns should be prepared, and when the repetition pitch is 40 nm, 25 types of discriminant patterns are prepared. All you have to do is Also, if the positional error is 1.5 μm, the position Pf of the particle PCL indicated by the die-to-die method is smaller than that value and larger than half of that value, for example, if discrimination figures are arranged every 1 μm. It is possible to correct and specify the actual position Pt.

Note that the imaging magnification of the SEM is considered to vary depending on the width of the circuit pattern 12, the line width, and the pitch. If the imaging magnification of the SEM differs, the imaging range IR, possible positional errors, and the number of unit patterns 10 observed within the imaging range IR will differ. (Resolution) may be considered.

(Modification)
Next, a modification of the circuit pattern will be described with reference to FIG. FIG. 3 is a top view schematically showing a circuit pattern of a modification.

Referring to FIG. 3A, the circuit pattern 121 has unit patterns 10 and discrimination patterns 16 repeatedly arranged in the X direction. The discrimination pattern 16 has discrimination figures 16A, 16B, 16C, and 16D. The discrimination figures 16A to 16D each have a line shape with a different length, and are arranged apart from the lines 10A and 10B of the unit pattern 10 in the blank area BA (see FIG. 1(a)) of the unit pattern 10. there is Since the lengths are different, it is possible to distinguish the identification figures 16A to 16D, thereby enabling identification of the unit pattern 10 in which the identification figures 16A to 16D are respectively arranged.

Referring to FIG. 3B, the circuit pattern 130 has unit patterns 10 and discrimination patterns 160 that are repeatedly arranged in the X direction. The discrimination pattern 16 has discrimination figures 160A, 160B, 160C and 160D, and these discrimination figures 160A to 160D are provided corresponding to the unit pattern 10. Similar to the discrimination figures 16A to 16D shown in FIG. 3(a), the discrimination figures 160A to 160D have line shapes with different lengths, and the blank areas BA (FIG. 1(a) ) are located. However, the distinguishing figures 160A-160D differ from the distinguishing figures 16A-16D in that they are connected to the line 10B of the unit pattern 10. FIG. Even if the discrimination figures 16A to 16D are connected to the unit pattern 10 in this way, it is possible to distinguish the discrimination figures 16A to 16D from the difference in length. is also possible. Incidentally, if the identification figures 160A to 160D are connected to the unit pattern 10, which is a wiring pattern, there is a possibility that circuit constants such as floating capacitance may vary, and the operation of the semiconductor device may also vary. Therefore, it is desirable to use discrimination figures 160A to 160D when there is little influence due to variations in circuit constants and the like.

As shown in FIG. 3C, the circuit pattern 131 has unit patterns 10 and discrimination patterns 140 that are repeatedly arranged in the X direction. The discrimination pattern 140 has discrimination figures 140A, 140B, 140C, and 140D, which have the same shapes as the discrimination figures 14A to 14D shown in FIG. 1(c). However, the discrimination figures 14A to 14D are separated from the unit pattern 10, whereas the discrimination figures 140A to 140D are connected to the unit pattern 10. FIG. Even in this case, the discriminating figures 140A to 140D have different shapes, so that they can be discriminated. Therefore, the unit pattern 10 to which these are given can also be discriminated. Further, similar to the discrimination figures 160A to 160D shown in FIG. 3(b), the discrimination figures 140A to 140D are useful when there is little influence due to variations in circuit constants and the like.

Next, another modification of the circuit pattern will be described with reference to FIGS. 4 to 6. FIG. In the circuit patterns 120, 121, 130, and 131 described so far, discrimination patterns 14, 16, 140, and 160, which are separate from the unit patterns 10 arranged repeatedly, are provided, respectively. In the subsequent modifications, the unit pattern 10 is modified to form the discrimination pattern.

As shown in FIG. 4A, the unit pattern 100 has a plurality of lines 100A extending in the Y direction and lines 100B having a wider width (length in the X direction) than the lines 100A. Furthermore, the unit pattern 100 is provided with a connecting portion C, and the connecting portion C connects the two lines 100A. That is, these two lines 100A are electrically connected to each other. When such unit patterns 100 are simply arranged repeatedly, a circuit pattern 110 shown in FIG. 4B is formed. As shown, in the circuit pattern 110, the connecting portions C of the unit patterns 100 are arranged at the same position in the Y direction, as indicated by broken lines L1 and L2.

On the other hand, in the circuit pattern 114 according to the modification, as shown in FIG. 4C, connection portions C, C1, C2, and C3 are provided. Although the connecting portions C1 and C2 have substantially the same shape as the connecting portion C, they are arranged at different positions in the Y direction with respect to the connecting portion C, as can be seen from the relative positions with respect to the broken lines L1 and L2 in the figure. ing. Also, the connection portion C3 is longer in the Y direction than the connection portions C, C1, and C2. Furthermore, two connecting portions C3 are formed in the rightmost unit pattern 100 in the figure. The connection portions C to C3 in the circuit pattern 114 are different in position and/or shape, and thus can be distinguished from each other. Therefore, these connection portions C to C3 can have the same function as the discrimination graphic 14A and the like described above. In other words, the connection portions C to C3 constitute a discrimination pattern. In other words, by changing the position and shape of a portion of the unit pattern 100 (in the illustrated example, the connecting portion), a discrimination pattern can also be obtained. Needless to say, such changes should be made so as not to affect the characteristics of the semiconductor device.

Subsequently, referring to FIG. 5A, the unit pattern 101 has a plurality of lines 101A extending in the Y direction and lines 101B having a width wider than that of the lines 100A. Two openings OPL and OPU are formed in the line 101B. When such unit patterns 101 are simply arranged repeatedly, a circuit pattern 111 shown in FIG. 5B is formed. As shown, in the circuit pattern 111, the two openings OPL and OPU of each unit pattern 101 are arranged at the same position in the Y direction, as indicated by dashed lines L3 and L4.

On the other hand, in the circuit pattern 150 according to the modification, openings OPL and OPU are arranged in one unit pattern 101 (left end in the figure), while different openings are arranged in the other unit pattern 101. . Specifically, openings OPL1 and OPU1 are arranged in the line 101B of the second unit pattern 101 from the left in the figure, and openings OPL2 and OPU2 are arranged in the line 101B of the third unit pattern 101 from the left. Openings OPL3 and OPU3 are arranged in the line 101B of the fourth unit pattern 101 from the left, and openings OPL4 and OPU4 are arranged in the line 101B of the fifth unit pattern 101 from the left. , the openings OPL5 and OPU5 are arranged in the line 101B of the sixth unit pattern 101 from the left, and the openings OPL6, OPM and OPU6 are arranged in the line 101B of the rightmost unit pattern 101.

As can be seen from the dashed line L3, the openings OPU1 and OPU2 are arranged at the same position in the Y direction with respect to the opening OPU, while the openings OPL1 and OPL2 are arranged at the lower side of the drawing with respect to the opening OPL. are staggered. Moreover, the opening OPL2 is largely shifted downward from the opening OPL1. Further, as can be seen from the dashed line L4, the openings OPL3 and OPL4 are arranged at the same position in the Y direction with respect to the opening OPL, while the openings OPU3 and OPU4 are arranged at the upper side in the drawing with respect to the opening OPU. are placed out of alignment. Moreover, the opening OPU4 is largely shifted upward from the opening OPU3. Due to the difference in arrangement as described above, combinations of apertures OPL and apertures OPU and combinations of apertures OPLx and apertures OPUx (where x is an integer of 1 to 4) can be distinguished.

Also, the position of the lower end of the opening OPU5 is the same as the position of the lower end of the opening OPU in the Y direction, but the position of the upper end is shifted downward in the figure from the position of the upper end of the opening OPU. That is, the opening OPU5 is shorter in the Y direction than the opening OPU. This also makes it possible to distinguish the combination of the apertures OPL5 and OPU5 from the combination of apertures described above. The combination of aperture OPL6, aperture OPM, and aperture OPU6 is also distinguishable from other combinations. That is, due to the difference in shape and/or position, the combination of these openings can have the same function as the discrimination graphic 14A, etc., and these constitute the discrimination pattern.

Also, referring to FIG. 6A, the unit pattern 102 has a plurality of lines 102A extending in the Y direction and two lines 102B. The lines 102B face each other across the dividing portion DP and both extend in the Y direction. When such unit patterns 102 are simply arranged repeatedly, a circuit pattern 112 shown in FIG. 6B is formed. As shown, in the circuit pattern 112, the dividing portions DP of each unit pattern 102 are arranged at the same position in the Y direction, as indicated by dashed lines L5 and L6.

On the other hand, in the circuit pattern 161 according to the modification, as shown in FIG. 6(c), dividing portions DP, DP1, DP2, DP3, and DP4 are provided. Although the dividing portions DP1 and DP2 have substantially the same length as the dividing portion DP along the Y direction, as can be seen from the relative positions with the dashed lines L5 and L6 in the figure, the dividing portions DP1 and DP2 extend in the Y direction with respect to the dividing portion DP. placed in different positions. Moreover, the dividing portion DP3 is longer in the Y direction than the dividing portions DP, DP1, and DP2. Furthermore, in the rightmost unit pattern 100 in the drawing, two dividing portions DP4 are formed. The dividing portions DP to DP4 in the circuit pattern 161 are different in position and/or shape, and thus can be distinguished from each other. Therefore, these dividing portions DP to DP4 can have the same function as the discrimination graphic 14A and the like described above, and the dividing portions DP to DP4 constitute a discrimination pattern.

Although attention has been focused on the repeated arrangement of unit patterns in the X direction, there are cases where unit patterns elongated in the Y direction are repeatedly arranged in the X direction. In such a case, as shown in FIG. 7, a series of discrimination patterns may be arranged at predetermined intervals in the Y direction. FIG. 7 is a top view schematically showing a circuit pattern when the unit pattern 100 shown in FIG. 4A extends relatively long in the Y direction. As shown, the circuit pattern 170 is provided with two rows of connection portions C, C1, C2, and C3 that are periodically arranged substantially along dashed lines L7 and L8 extending in the X direction. Here, the interval between the two rows (interval between dashed lines L7 and L8) may be determined in consideration of, for example, the imaging range IR of the SEM and the positional error of the die-to-die system.

(Other modifications)
So far, the case where unit patterns formed by wiring are repeatedly arranged has been described, but the present embodiment is not limited to this, and can also be applied to the case where unit patterns formed by vias and through contacts are repeatedly arranged. It is possible. Hereinafter, with reference to FIG. 8, a further modified example will be described, taking as an example a case where unit patterns are formed by vias and through-contact holes provided in an insulating film and arranged repeatedly, for example. FIG. 8 is an explanatory diagram for explaining a circuit pattern of a further modified example.

Referring to FIG. 8(a), a wiring pattern 104 is formed which includes a wiring 104A and a wiring 104B having a wider width than the wiring 104A. The wirings 104A and 104B can be made of metal such as Cu or conductive polysilicon. As shown in FIG. 8B, which is a cross-sectional view taken along the line AA of FIG. 8A, the wiring 104B (similar to the wiring 104A) is formed on the insulating film 51 to cover them. An insulating film 53 is formed as shown in FIG. That is, the wirings 104A and 104B are lower layer wirings, and FIG. 8A shows the wirings 104A and 104B whose shape can be visually recognized through the insulating film 53 depending on the material and thickness of the insulating film 53. FIG.

As shown in FIGS. 8A and 8B, a plurality of holes H are formed through the insulating film 53 to reach the wiring 104B, and the wiring 104B is exposed at the bottom of these holes. These holes H can be formed by, for example, a photolithography process and an etching process. Further, by embedding a metal such as Cu in the hole H later, a via (or contact) connected to the wiring 104B is formed.

As shown in FIG. 8A, the plurality of holes H are grouped into two hole groups GH1 and GH2. The hole group GH1 has five holes H, which are arranged in a substantially pentagonal shape. Specifically, three of the five holes H are arranged at the vertices of an isosceles triangle whose base extends in the X direction. The remaining two are arranged at positions shifted in the Y direction with respect to the two holes H arranged at the vertices of both ends of the base. The hole group GH2 also has five holes H, which are also arranged in a substantially pentagonal shape similar to the holes H of the hole group GH1. However, in the illustrated example, the holes H of the hole group GH1 and the holes H of the hole group GH2 are arranged symmetrically with respect to the X-axis.

Such a pair of hole groups GH1 and GH2 is used as a unit pattern GH (FIG. 8(a)). , a circuit pattern 141 is formed. In this case, since the unit patterns GH in which the holes H are arranged in the same manner are repeatedly arranged, defects such as particles were observed on the insulating film 53 in the same manner as the circuit pattern 12 described with reference to FIG. However, it is not easy to specify the position on the design data.

When observing defects such as particles on the insulating film 53, depending on the material and thickness of the insulating film 53, the wirings 104A and 104B may also be recognized through the insulating film 53, but the wiring pattern 104 including these may also be recognized. In addition, it is not easy to specify the position of the defect such as particles on the design data from the positions of the wirings 104A and 104B because they are arranged repeatedly. Also, when the insulating film 53 is thick, the shapes of the wirings 104A and 104B cannot be recognized.

On the other hand, referring to FIG. 8D, in the circuit pattern 151 of this modification, the hole groups GH21, GH22, GH23, GH24, and GH25 replace the hole group GH2 in FIG. It is provided so as to make a pair with. The hole groups GH21 to GH25 have five holes H similarly to the hole group HG2, but their arrangement is different. Specifically, in the hole groups GH21 to GH25, the holes H are not arranged in a substantially pentagonal shape, but are arranged at five positions, excluding one position, out of six arrangement positions of a matrix of two rows and three columns on the XY plane. H is placed. The position of that one point is different in each of the hole groups GH21 to GH25. More specifically, the one place where the hole H is not arranged is 1st row 3rd column, 1st row 2nd column, 1st row 1st column, 2nd row 1st column, It corresponds to the position of 2 rows and 2 columns. Due to such a difference in arrangement, the hole groups GH21 to GH25 can have the same function as the discrimination figure 14A and the like, and it can be said that the discrimination pattern is formed by deformation of the unit pattern GH.

Further, as described above, it is not easy to clearly recognize the wirings 104A and 104B through the insulating film 53. Therefore, even if a predetermined discrimination pattern is given to the wirings 104A and 104B, the discrimination pattern can be used to distinguish between the insulating films. It is also not easy to locate defects on 53 on the design data. On the other hand, in the case of the hole H, since the wirings 104A and 104B exposed on the bottom surface thereof can be clearly recognized by SEM or the like, it is easy to specify the position of the defect on the design data.

Even if the hole groups GH21 to GH25 are arranged differently, the number of holes H is the same. can be substantially the same in any arrangement. Further, although the hole groups GH1 and GH2 each having five holes H are illustrated, the number of holes H is not limited to five, and the imaging range, imaging magnification, die-to-die It may be determined appropriately in consideration of the positional error due to the method. Furthermore, instead of the hole group GH2 shown in FIG. A group of holes may be used. Furthermore, in FIG. 8D, for example, the hole group GH21 and the hole group GH1 may be interchanged in the Y direction (vertical direction in the drawing), and the hole group GH24 and the hole group GH1 may be interchanged in the Y direction. That is, the arrangement of the holes H may be changed in either one (or both) of the hole group GH1 and the hole group GH2 included in the unit pattern GH in FIG. 8(c).

Also, the case of observing (inspecting) defects and the like after the holes H are formed on the insulating film 53 has been described, but after filling the holes H with metal (for example, Cu) and forming vias and the like, defects and the like are observed (inspected). may be observed. Even in this case, as described above, the defect positions on the substrate can be specified on the design data based on the hole groups GH21 to GH25. In addition, as described above, the circuit pattern 120 and the like are formed by embedding a trench or the like with a conductive material such as metal. You may That is, the circuit pattern to be observed is not limited to wiring, vias, and the like, and may be holes and grooves. In addition, in FIG. 8, the case where the bottom surface of the hole is made of a material different from that of the interlayer insulating film has been described. However, since SEM images are excellent for observing surface unevenness, even if the bottom surface of holes and grooves is the same as the material of other regions, it is possible to recognize the positions of holes and holes on SEM images. be.

Next, a semiconductor device provided with a circuit pattern formed by repeatedly arranging a plurality of unit patterns having the same shape in one direction will be described. 9 is a block diagram schematically showing the configuration of a NAND memory, FIG. 10 is a block diagram schematically showing the configuration of a DRAM memory, and FIG. 11 is a block diagram schematically showing the configuration of an imaging element. It is a diagram.

Referring to FIG. 9, a NAND memory NM as a semiconductor memory device includes a core section COR, an input/output section IO, and a peripheral circuit PER. A memory cell array MCA, a row decoder RD, and a sense amplifier SA are provided in the core section COR, and a plurality of blocks BLK (BLK0, BLK1, BLK2, . . . ) each including a plurality of memory cells are provided in the memory cell array MCA. It is Specifically, each block BLK has a plurality of string units SU (SU0, SU1, SU2, . It is

A plurality of word lines WL and a plurality of bit lines BL are provided in the memory cell array MCA (one word line and one bit line are shown in the figure). A plurality of word lines WL extend in the X direction and are connected to row decoders RD. Also, each of the plurality of word lines WL is commonly connected to the n-th memory cell of the plurality of NAND strings NS of each string unit SU in the corresponding block BLK. On the other hand, a plurality of bit lines BL extend in the Y direction and are connected to sense amplifiers SA. Also, one bit line BL among the plurality of bit lines BL is commonly connected to the m-th NAND string NS between the plurality of blocks BLK. Memory cells are arranged at intersections of a plurality of word lines WL and a plurality of bit lines BL.

The row decoder RD decodes a block address received from a predetermined control section outside the NAND memory NM, and selects a block BLK and a word line WL within that block BLK. The sense amplifier SA senses and amplifies the data read from the memory cell when reading data. Then, it outputs the read data to a predetermined control unit as needed. When programming data, write data received from a predetermined control unit is transferred to the memory cells.

The input/output unit IO transmits and receives various commands and data to and from a predetermined control unit. The input/output unit IO has, for example, data input/output terminals DQ0 to DQ7, toggle signal input/output terminals DQS, /DQS, and external control terminals /CEn, CLE, ALE, /WE, RE, /RE. A signal corresponding to is received from an external controller. The peripheral circuit PER has a sequencer SEQ, a charge pump CHP, a register REG, and a driver DRV. The driver DRV supplies voltages necessary for programming, reading and erasing data to the row decoder RD and the sense amplifier SA. This voltage is applied to various wirings in the memory cell array MCA. The charge pump CHP boosts an externally applied power supply voltage to supply a necessary voltage to the driver DRV. A register REG holds various signals. For example, it holds the status of data program or erase operation, and thereby notifies a predetermined control unit whether the operation has been completed normally. The sequencer SEQ controls the operation of the entire NAND memory NM.

In the NAND memory NM as described above, various circuit elements such as transistors constituting memory cells, word lines WL, and bit lines BL are periodically arranged in the same circuit layout in the memory cell array MCA. there is Therefore, in the row decoder RD to which each word line WL is connected, unit patterns having the same shape are repeatedly arranged in one direction by a plurality of word lines WL and other wirings. The same applies to sense amplifier SA to which a plurality of bit lines BL are connected. The circuit pattern 120 and the like described above can be applied to such row decoder RD and sense amplifier SA.

Next, referring to FIG. 10, a DRAM memory 80 as a semiconductor memory device includes a memory cell array MA. The memory cell array MA has a plurality of word lines WL and a plurality of bit lines BL, and memory cells MC are arranged at intersections of these lines. A word line WL is selected by a row decoder 83R, and a bit line BL is selected by a column decoder 83C. The DRAM memory 80 is also provided with a command address terminal T1, a clock terminal T2, a data terminal T3, and power supply terminals T4 and T5. Clock signals CK and /CK are input to the clock terminal T2. A power supply voltage is supplied to the power supply terminal T5, and the power supply voltage is further supplied to the internal voltage generating circuit 88. FIG. The internal voltage generating circuit 88 generates various internal voltages based on the power supply voltage, and outputs them from the terminal IT to each section. For convenience of explanation, FIG. 10 omits a refresh circuit and the like provided in the DRAM memory.

An address signal and a command signal are input from the outside to the command address terminal T1. The address signal input to the command address terminal T1 is supplied to the address decoder 82A through the command address input circuit 81. FIG. The address decoder 82A supplies the address signal AS to the row decoder 83R or the column decoder 83C. On the other hand, the command signal input to the command address terminal T1 is supplied via the command address input circuit 81 to the command decoder 82C. Command decoder 82C generates various internal command signals by decoding input command signals. The internal command signals include an active signal ATS, a column signal CS, and the like.

Active signal ATS is activated when the command signal is an active command. When the active signal ATS is activated, the address signal AS is supplied from the address decoder 82A to the row decoder 83R. As a result, the word line WL designated by the address signal AS is selected. A column signal CS is activated when the command signal is a read command or a write command. When the column signal CS is activated, the address signal AS is supplied from the address decoder 82A to the column decoder 83C. As a result, the bit line BL specified by the address signal AS is selected.

Therefore, when an active command and a read command are input, read data is read from the memory cell MC specified by the word line WL and bit line BL specified by the address signal AS. The read data is output to the outside from the data terminal T3 via the read/write amplifier 84, the input/output circuit 85 and the data terminal T3. On the other hand, when an active command and a write command are input and write data is input to the data terminal T3, the data terminal T3 is applied to the memory cell array MA specified by the word line WL and bit line BL designated by the address signal AS. Write data is supplied and written via T3, input/output circuit 85 and read/write amplifier 15 .

In the DRAM memory 80 as described above, various circuit elements such as transistors constituting memory cells, word lines WL, and bit lines BL are periodically arranged in the same circuit layout in the memory cell array MA. there is Therefore, in the row decoder 83R to which each word line WL is connected, unit patterns having the same shape are repeatedly arranged in one direction by a plurality of word lines WL and other wiring. The same applies to a plurality of bit line BL column decoders 83C. The circuit pattern 120 and the like described above can be applied to such row decoder 83R and column decoder 83C.

Next, referring to FIG. 11, the image sensor 90 has a pixel array PA and peripheral circuits, which include a row scanning circuit 91, a column processing circuit 92, a column scanning circuit 93, a system controller 94, and a A processing unit 96 is included.

The pixel array PA has multiple pixels PXL. These pixels PXL are arranged in a two-dimensional lattice in the row direction and the column direction. Here, the row direction refers to the horizontal direction in the drawing, and the column direction refers to the vertical direction in the drawing. Each pixel PXL has a photoelectric conversion element that generates and accumulates charges according to the amount of light received. A predetermined filter may be provided on the light incident surface of each pixel PXL. Such a filter may for example be a Bayer filter.

In the pixel array PA, the pixels PXL arranged in the row direction are commonly connected to the pixel drive line PDL, and the pixels PXL arranged in the column direction are commonly connected to the vertical signal line VSL. One end of the pixel drive line PDL is connected to the row scanning circuit 91 . The row scanning circuit 91 generates drive signals for performing signal readout drive from the pixels, and drives all the pixels PDL of the pixel array PA simultaneously or row by row through the pixel drive lines PDL.

A signal output from the pixel PDL driven by the row scanning circuit 91 is input to the column processing circuit 92 through each vertical signal line VSL for each pixel PDS arranged in the row direction. The column processing circuit 92 can perform predetermined signal processing on the signal input through the vertical signal line VSL to generate a pixel signal and temporarily hold the pixel signal. For example, the column processing circuit 92 performs noise removal processing, analog-digital conversion (AD conversion) processing, and the like. A digital signal obtained by AD conversion is output to the signal processing unit 96 . The column scanning circuit 93 sequentially selects readout circuits corresponding to the pixel columns of the column processing circuit 92 . By selective scanning by the column scanning circuit 93, pixel signals that have undergone signal processing for each pixel circuit in the column processing circuit 92 are sequentially output.

A system control unit 94 receives a system clock SYSCLK signal and the like via an external controller. The system control unit 94 includes a timing generator and the like, and drives the row scanning circuit 91, the column processing circuit 92, the column scanning circuit 93 and the like based on various timing signals generated thereby. The signal processing unit 96 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signals output from the column processing circuit 92 . The digital signal output from the signal processing section 96 is output to the image processing section where predetermined processing is performed to generate an image signal for displaying an image on a predetermined display.

In the image sensor 90 configured as described above, in the pixel array PA, various circuit elements such as photodiodes constituting photoelectric conversion elements, pixel drive lines PDL, and vertical signal lines VSL are formed in the same circuit. Arranged periodically in the layout. Therefore, in the row scanning circuit 91 to which each pixel drive line PDL is connected, unit patterns having the same shape are repeatedly arranged in one direction by a plurality of pixel drive lines PDL and other wiring. becomes. The same applies to the column processing circuit 92 to which a plurality of vertical signal lines VSL are connected. The circuit pattern 120 and the like described above can be applied to the row scanning circuit 91 and the column processing circuit 92 as well as the column scanning circuit 93 connected to the column processing circuit 92 .

Note that unit patterns having the same shape are repeatedly arranged in one direction not only in the above-described NAND memory, DRAM, and image sensor, but also in FPGA (Field Programmable Gate Array), cross-point memory, and the like. circuit patterns may be provided. Further, even in a semiconductor device having a circuit corresponding to one of the row decoder RD and the sense amplifier SA in the NAND memory NM, the circuit pattern 120 and the like can be applied to the circuit. be.

Although several embodiments (variations) of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

In this specification, the particle PCL is exemplified as a defect, but the present invention is not limited to this, and is used to identify defects such as wiring disconnection and short circuit that may occur during etching in a circuit pattern in which unit patterns are repeatedly arranged. Circuit patterns according to embodiments are useful.

Reference Signs List 1 semiconductor device 10, 100, 101, 102 unit pattern 114, 120, 121, 130, 131, 150, 161, 170 circuit pattern 14, 16, 140, 160 discrimination pattern C, C1, C2, C3... connection part, OPL, OPL1 to OPL6, OPU, OPU1 to OPU6, OPM... opening, DP, DP1, DP2, DP3... cutting part.

Claims (12)

a circuit pattern including a plurality of unit patterns repeatedly arranged in at least one direction;
and a discrimination pattern provided in the circuit pattern to enable discrimination of the unit pattern. 2. The semiconductor device according to claim 1, wherein said discrimination pattern includes a plurality of types of discrimination figures different from each other, and said plurality of types of discrimination figures are given to said unit pattern one by one. 2. The identification pattern according to claim 1, wherein the identification pattern includes a plurality of types of identification figures that are different from each other, and the plurality of types of identification figures are provided at a rate of one for each of the plurality of unit patterns that are repeatedly arranged in the circuit pattern. semiconductor equipment. 4. The semiconductor device according to claim 2, wherein said plurality of types of discrimination figures are respectively arranged in gap regions within said unit pattern. 5. The semiconductor device according to claim 2, wherein said plurality of types of discrimination figures are separated from said unit pattern. 6. The semiconductor device according to any one of claims 2 to 5, wherein said plurality of types of discrimination figures are connected to said unit pattern. 7. The semiconductor device according to claim 1, wherein said circuit pattern and said discrimination pattern are provided in the same layer. 8. The semiconductor device according to claim 1, wherein said circuit pattern is defined by wiring, and said discrimination pattern is made of the same material as said wiring. 2. The semiconductor device according to claim 1, wherein said circuit pattern is defined by wiring, and said discrimination pattern is provided by deformation of said unit pattern. 2. The semiconductor device according to claim 1, wherein said circuit pattern is defined by grooves or holes, and said discrimination pattern is provided by deformation of said unit pattern. 10. The method according to any one of claims 1 to 9, further comprising an additional discrimination pattern, wherein the additional discrimination pattern and the discrimination pattern are arranged in the one direction while being separated by a predetermined interval. semiconductor equipment. forming a circuit pattern including a plurality of unit patterns repeatedly arranged in at least one direction and provided with a discrimination pattern that enables discrimination of the unit pattern;
A method of manufacturing a semiconductor device, comprising: observing the circuit pattern.

Images