JP2010009656A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device for equalizing capacity generated in data lines of a bank including an extension block and a bank including no extension block and preventing the generation of dead space. <P>SOLUTION: The semiconductor memory device includes a first bank 11 including a regular block 11A having memory cells arrayed therein, a redundancy block 11B having memory cells arrayed therein which are replaced by defective memory cells in the regular block 11A , and an extension block 11C having a storage capacity smaller than that of the regular block 11A, and a second bank 12 including a regular block 11A and a redundancy block 11B. The storage capacity of the redundancy block 11B included in the first bank 11 is smaller than that of the redundancy block 11B included in the second bank 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a semiconductor memory device including an expansion block.

  2. Description of the Related Art Conventionally, a semiconductor memory device is provided with a small-scale cell array (hereinafter referred to as an expansion block) having a smaller storage capacity than a cell array (hereinafter referred to as a regular block) in which a plurality of normally used memory cells are arranged. The extension block is used for storing information for executing a predetermined operation such as an initial operation when the power is turned on.

  A semiconductor memory device usually has a plurality of banks. A bank is the minimum unit that constitutes a storage device, and is installed and added in units of this bank. When accessing the storage device, it is possible to access in parallel in units of banks.

  When an expansion block is disposed in a semiconductor memory device having a plurality of banks, only the bank in which the expansion block is disposed has a special shape. For this reason, the capacity generated in the read data line arranged in the bank differs between the bank including the extension block and the bank not including the extension block, and the capacity generated in the read data line between these banks becomes uneven. This is a cause of reducing a read voltage margin at the time of reading. In addition, since only the bank including the extension block has a special shape, when a bank including the extension block and a bank not including the extension block are arranged, there is a problem that a dead space is generated in the chip area.

Further, as a prior art related to the present invention, for example, an extended memory area is provided inside a ferroelectric memory device, and a conventional control circuit can be used as it is, and another control circuit is arranged only for a special function. Thus, an apparatus has been proposed in which the size of the chip layout is not excessively increased (see Patent Document 1).
JP 2004-185790 A

  According to the present invention, it is possible to equalize the capacitance generated in the data line of the bank including the expansion block and the data line of the bank not including the expansion block, and further, it is possible to eliminate the occurrence of dead space in the area where these banks are arranged. A semiconductor memory device is provided.

  A semiconductor memory device according to an embodiment of the present invention includes a first regular block in which a plurality of normally used memory cells are arranged, a defective memory cell when the memory cell in the first regular block is defective, A first bank including a first redundancy block in which a plurality of memory cells to be used in replacement are arranged; and an expansion block in which a plurality of memory cells are arranged and has a storage capacity smaller than that of the first regular block; A second regular block in which a plurality of normally used memory cells are arranged, and a plurality of memory cells to be used in place of the defective memory cells when the memory cells in the second regular block are defective. A second bank including a second redundancy block, and the first bank included in the first bank. Storage capacitance of the down Dan Sea block, wherein the smaller than the storage capacity of the second redundancy block has to have second banks.

  According to the present invention, it is possible to equalize the capacity generated in the data line of the bank including the extension block and the data line of the bank not including the extension block, and further, the dead space is generated in the area where these banks are arranged. It is possible to provide a semiconductor memory device that can be eliminated.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  FIG. 1 is a layout diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device includes a bank group 10 having a plurality of banks and a sense amplifier 20. Each bank in the bank group 10 constitutes a minimum unit that can be written and read simultaneously in parallel (RWW: Read While Write).

  An arbitrary bank (first bank) 11 among the plurality of banks 10 includes a plurality of regular blocks 11A, a plurality of redundancy blocks 11B, a plurality of extension blocks 11C, a block decoder 11D, and a decoder group 11E. . The regular block 11A is a block in which a plurality of normally used memory cells (regular memory cells) are arranged.

  The redundancy block 11B is a block in which when a memory cell in the regular block 11A is defective and cannot be used, a plurality of memory cells (redundancy memory cells) used instead of the defective memory cell are arranged. For example, the regular block 11A including the defective memory cell is replaced with a redundancy block 11B in the same bank.

  The expansion block 11C is a block in which a plurality of memory cells (expansion memory cells) are arranged, has a smaller storage capacity than the regular block 11A, and can be written / erased at a high speed. Information necessary for operation is stored. The decoder group 11E will be described in detail later.

  In the first bank 11, a plurality of regular blocks 11 </ b> A are divided into left and right within one rectangular area, and a decoder group 11 </ b> E is arranged between them. At one end of the rectangular area, a redundancy block 11B, an extension block 11C, and a decoder group 11E are arranged. Further, a block decoder 11D is arranged on the region side where the regular block 11A of the redundancy block 11B and the extension block 11C is not arranged.

  In addition, any other one bank (second bank) 12 in the plurality of banks includes a plurality of regular blocks 11A, a plurality of redundancy blocks 11B, a block decoder 11D, and a decoder group 11E. In the second bank 12, a plurality of regular blocks 11A are arranged on the left and right sides in one rectangular area, and a decoder group 11E is arranged between them. At one end of this rectangular area, a redundancy block 11B and a decoder group 11E are arranged. Further, a block decoder 11D is arranged on the side of the redundancy block 11B where the regular block 11A is not arranged. That is, the difference from the first bank 11 is that in the second bank 12, only the redundancy block 11B and the decoder group 11E are arranged, and the extension block 11C is not arranged between the regular block 11A and the block decoder 11D. It is. In other words, in the first bank 11, the expansion block 11 </ b> C is arranged by replacing some of the plurality of redundancy blocks 11 </ b> B in the second bank 12.

  The area of the smallest rectangular area including the first bank 11 in which the extended block 11C is disposed is the same as the area of the smallest rectangular area including the second bank 12 in which the expanded block 11C is not disposed.

  2 is a layout diagram of the regular block 11A in the layout diagram shown in FIG. 1, and is an enlarged view of a portion indicated by X in FIG. As shown in FIG. 2, a row main decoder 11E-1 is arranged in the central decoder group 11E, and a row sub-decoder 11E-2 is arranged on both sides thereof. A column decoder 11E-3 is arranged on the row main decoder 11E-1 and the row sub-decoder 11E-2. A regular block 11A is arranged so as to sandwich the decoder group 11E. In the regular block 11A, a cell array 11A-1 in which a plurality of memory cells are arranged is arranged, and a column gate 11A-2 is arranged on the cell array 11A-1. Further, in the cell array 11A-1 and the column gate 11A-2, a data line 11A-3 formed in the wiring layer above the memory cell is arranged.

  FIG. 3 is a layout diagram of the redundancy block 11B and the expansion block 11C in the layout diagram shown in FIG. 1, and is an enlarged view of a portion indicated by Y in FIG. As shown in FIG. 3, a row main decoder 11E-1, a row sub decoder 11E-2, and a column decoder 11E-3 are arranged in the central decoder group 11E. A redundancy block 11B and a plurality of extension blocks 11C are arranged so as to sandwich the decoder group 11E. FIG. 3 shows an example in which the redundancy block 11B is arranged on the left side and the extension block 11C is arranged on the right side. However, the extension block may be arranged on the left side and the redundancy block may be arranged on the right side. .

  In the redundancy block 11B, a cell array 11B-1 in which a plurality of redundancy memory cells are arranged is arranged, and a column gate 11B-2 is arranged on the cell array 11B-1. Further, in the cell array 11B-1 and the column gate 11B-2, a data line 11B-3 formed in the upper wiring layer of the redundancy memory cell is arranged. In the extension block 11C, a plurality of cell arrays 11C-1 in which a plurality of memory cells are arranged are arranged, and a column gate 11C-2 is arranged in each of the plurality of cell arrays 11C-1. A dummy area 11C-4 is formed in a region where the cell array 11C-1 and the column gate 11C-2 are not arranged in the extension block 11C. Further, in the cell array 11C-1, the column gate 11C-2, and the dummy area 11C-4, the data line 11C-3 formed in the upper wiring layer of the memory cell is arranged.

  More specifically, a row main decoder 11E-1 is arranged at the center, and a cell array 11B-1 is arranged on the left side via a row subdecoder 11E-2. On the other hand, on the right side of the row main decoder 11E-1, a plurality of cell arrays 11C-1 and column gates 11C-2 corresponding to the cell arrays 11C-1 are arranged via a row sub decoder 11E-2 and a column decoder 11E-3. Has been. The row sub decoder 11E-2 and the column decoder 11E-3 are provided so as to correspond to the cell array 11C-1 and the column gate 11C-2. Further, a dummy area 11C-4 is formed between the cell array 11C-1 and the column gate 11C-2 and the other cell array 11C-1 and the column gate 11C-2. The dummy area 11C-4 will be described in detail later.

  4 and 5 are diagrams showing details of the cell array, column gates, and decoder group in the layout diagrams shown in FIGS. Here, the details of the regular block 11A and the decoder group 11E will be described, but the details of the other blocks and the decoder group are also the same.

  As shown in FIG. 4, in the cell array 11A-1 including the regular block 11A, memory cells MC are arranged in a matrix. Word lines WLn, WLn + 1, WLn + 2,..., WLn + 510, WLn + 511 connected to the memory cells MC are arranged in the row direction of the cell array 11A-1, and in the column direction of the cell array 11A-1. Bit lines BL0, BL1, BL2,..., BL7 connected to the memory cell MC are arranged. Column bits C0, C1, C2,..., C7 are connected to the bit lines, respectively. A column decoder 11E-3 including a logical product negation (NAND) circuit CND and a negation (NOT) circuit CNT is connected to each gate of the column gate. A column address C <7: 0> is input to the first input terminal of the logical product negation circuit CND, and a column selection signal CR0 is input to the second input terminal.

  Next, details of the decoder group 11E are shown in FIG. The block address BLKadd is input to the first input terminals of the logical product negation circuits RND0, RND1,..., RND7 in the row main decoder 11E-1 via the logical product negation circuit ND and the negation circuit NT. OUT6, OUT7, and OUT8, which are output signals of an address fixing circuit and an address switching circuit, which will be described later, are input to the second, third, and fourth input terminals of the logical product negation circuits RND0 to RND7, respectively.

  Further, the output terminals of the logical product negation circuits RND0 to RND7 are respectively input to the pass transistors PT0, PT1,..., PT7 in the row subdecoder 11E-2 via the negation circuits RNT0, RNT1,. . Then, the word line selection signal BLKFR <7: 0> or BLKFL <7: 0> is output to the word lines WLn to WLn + 511 in accordance with the output signal from the row main decoder 11E-1.

  Next, the dummy area 11C-4 arranged in the extension block 11C will be described. First, details of a part of the cell array 11B-1 in the redundancy block 11B will be described, and then details of a part of the dummy area 11C-4 in the expansion block 11C will be described.

  FIG. 6 is an enlarged plan view of a part R of the cell array 11B-1 in the redundancy block 11B in the layout diagram shown in FIG. A plurality of word lines WL are arranged in the row direction, and a plurality of data lines DL formed via an interlayer insulating film are arranged in the column direction above the word lines WL.

  FIG. 7 is an enlarged plan view of a portion D of the dummy area 11C-4 in the extension block 11C in the layout diagram shown in FIG. In the row direction, dummy wirings DM similar to the plurality of word lines WL shown in FIG. 6 are arranged. These dummy wirings DM are connected to a reference voltage Vss (for example, ground potential). A plurality of data lines DL formed via an interlayer insulating film are arranged in the column direction above the dummy wiring DM.

  FIG. 8 is a cross-sectional view schematically showing capacitance generated in the data line DL when the word line WL is arranged under the data line DL and when the word line WL is not arranged under the data line DL. FIG. A word line WL is formed on the semiconductor substrate 30, and a data line DL is formed on the word line WL via an interlayer insulating film 31. In such a structure, a capacitance generated between the data line DL and the word line WL is C1, and a capacitance generated in the data line DL when the word line WL is not arranged is C2. Then, C1> C2 is established between the capacitors C1 and C2.

  For example, when the dummy area 11C-4 is not formed in the extension block 11C, there is a portion where the capacity of the data line arranged in the extension block is C2. However, the capacity of the data line arranged in the redundancy block (or regular block) is almost C1. For this reason, the capacity of the data line arranged in the expansion block is smaller than the capacity of the data line arranged in the redundancy block, and the data line capacity of the expansion block and the data line capacity of the regular block (or redundancy block) are reduced. It becomes non-uniform and the margin at the time of reading becomes small.

  Therefore, as in the dummy area 11C-4 described above, by forming a dummy wiring in an area where no word line is arranged in the extension block, the capacity of the data line arranged in the extension block and the redundancy block (or The capacity of data arranged in the regular block is made uniform. As a result, it is possible to prevent a read voltage margin from being reduced during reading.

  As described above, according to the present embodiment, the expansion block is arranged in place of the redundancy block in the bank, so that the expansion block is not disposed so as to protrude from the rectangular bank. An expansion block can be arranged in Thereby, when the first bank including the extension block and the second bank not including the extension block are arranged on the chip, it is possible to eliminate the occurrence of dead space in the chip area.

  Further, dummy areas are formed in areas where the memory cell array is not formed in the extension block, and dummy wirings similar to the word lines in the redundancy block (or regular block) are formed in these dummy areas. Thereby, the capacity of the data lines in the expansion block and the capacity of the data lines in the redundancy block are made uniform. That is, the capacity of the data line arranged in the first bank including the extension block and the capacity of the data line arranged in the second bank not including the extension block are made uniform. Thereby, the margin of the read voltage at the time of reading can be improved.

  Next, an address fixing circuit and an address switching circuit used for selecting the row main decoder when accessing the extension block 11C will be described. In the extended block, small-capacity cell arrays are arranged in a distributed manner, so that there are unused row main decoders. In disposing the expansion block 11C in the bank, the row main decoder to be used is limited depending on the size of the memory cell and the block size of the column gate for reading data. Since the row main decoder is also used to select the coexisting redundancy block 11B, if the address is turned from the lower order, a blank address space is created when the memory cell in the expansion block is selected.

  FIGS. 9A and 9B are diagrams showing a blank address space generated in the extension block 11C of the first bank. FIG. 9A shows a state in which the row main decoder 11E-1 is sequentially selected from the lower address side to access the left cell array 11B-1, and FIG. 9B shows a blank space in the right extension block 11C. A state in which the cell array 11C-1 is accessed by skipping the row main decoder 11E-1 corresponding to the address space is shown.

  FIG. 10 is a diagram showing an address map when the row main decoder 11E-1 is sequentially selected from the lower order side of the address to access the cell array 11B-1 as shown in FIG. 9A. As shown in FIG. 10, among the row addresses, the row main decoders 0 to 7 are selected by the addresses of OUT (ADD) 6, OUT (ADD) 7 and OUT (ADD) 8 indicated by Row B.

  FIG. 11 is a diagram showing an address map when the cell array 11C-1 is accessed by skipping the row main decoder 11E-1 corresponding to the blank address space, as shown in FIG. 9B. As shown in FIG. 11, after selecting the 0th row main decoder by the addresses of OUT6, OUT7, and OUT8 indicated by RowB, the 1st row main decoder is skipped and the 4th row main decoder is selected. . That is, if the row main decoder to which the cell array 11C-1 is not connected and then the row main decoder to which the cell array 11C-1 is connected after selecting the row number 0 main decoder is selected, the cell array 11C-1 is connected. Only the row main decoder can be selected continuously.

  A circuit in which the row main decoder corresponding to the blank address space is skipped and the cell array 11C-1 in the expansion block 11C can be continuously selected is shown in FIGS. 12, 13, and 14A. FIG. 14B is a circuit shown in FIG. It is not always necessary to provide an address fixing circuit and an address switching circuit, which will be described later, for a row main decoder that is not used for selecting an extension block. In this case, the row main decoder may be directly selected by ADD6, ADD7, and ADD8.

  A plurality of address circuits shown in FIG. 12 are arranged. Row addresses ADD6, ADD7, and ADD8 are input to the first input terminals of these address circuits, respectively, and the power supply voltage VDD is input to the second input terminal, and addresses ADD6 <0>, ADD6 <1>, and address ADD7 <0. >, ADD7 <1>, and addresses ADD8 <0> and ADD8 <1> are output.

  The address fixing circuit shown in FIG. 13 receives the address ADD6 <0>, ADD6 <1>, or the address ADD7 <0>, ADD7 <1>, and the signal EFAEN output from the address circuit, and the signal OUT6 <0. >, OUT6 <1>, or signals OUT7 <0>, OUT7 <1> are output.

  In the address switching circuit shown in FIG. 14A, the addresses ADD6 <0> and ADD8 <0> and the signal EFAEN output from the address circuit are input, and the signal OUT8 <0> is output. In the address switching circuit shown in FIG. 14B, the addresses ADD6 <1> and ADD8 <1> and the signal EFAEN output from the address circuit are input, and the signal OUT8 <1> is output. The signal EFAEN normally becomes “L”, and becomes “H” when the address is fixed or switched, that is, when an extension block is accessed.

  FIG. 15A shows the outputs of the row address ADD6 and ADD7 in the address circuit and the address fixing circuit. When the signal EFAEN is “L”, the signals OUT <0> and OUT <1> are determined according to the values of the row addresses ADD6 and ADD7. When the signal EFAEN is “H”, the signal OUT <0> is fixed to “H” and the signal OUT <1> is “L” regardless of whether the row address ADD6, ADD7 is “L” or “H”. To be fixed.

  FIG. 15B shows the outputs of the address circuit and the address switching circuit of the row addresses ADD6 and ADD8. When the row addresses ADD6 and ADD8 are “L” or “H”, processing is performed as shown in FIG. When the signal EFAEN is “H”, the signals OUT <0> and OUT <1> of the row address ADD6 are switched to the signal of the row address ADD8.

  As a result, unnecessary addresses can be fixed, the first to third row main decoders can be skipped, and the cell array in the expansion block can be selected linearly.

  As described above, in the present embodiment, by replacing a small cell array (expansion block) with a redundancy block in a specific bank, the occurrence of dead space is eliminated, and the data line of the regular block or redundancy block is further eliminated. The capacity and the capacity of the data line of the extension block can be made equivalent. Thereby, the margin of the read voltage at the time of reading can be increased.

  The embodiment described above is not the only embodiment, and various embodiments can be formed by changing the configuration or adding various configurations.

1 is a layout diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a layout diagram of regular blocks in the layout diagram shown in FIG. 1. FIG. 2 is a layout diagram of a redundancy block and an extension block in the layout diagram shown in FIG. 1. FIG. 4 is a diagram showing details of a cell array, a column gate, and a column decoder in the layout diagrams shown in FIGS. 2 and 3. FIG. 4 is a diagram showing details of a row main decoder and a row sub-decoder in the layout diagrams shown in FIGS. 2 and 3. FIG. 4 is an enlarged plan view of a part of a cell array in a redundancy block in the layout diagram shown in FIG. 3. FIG. 4 is an enlarged plan view of a part D of a dummy area in an extension block in the layout diagram shown in FIG. 3. It is sectional drawing which shows typically the capacity | capacitance which arises in the data line DL. It is a figure which shows the blank address space which arises in the expansion block of a 1st bank. It is a figure which shows an address map in the case of selecting a row main decoder sequentially from the low-order side of an address and accessing a cell array. FIG. 10 is a diagram showing an address map when a cell array is accessed by skipping a row main decoder corresponding to a blank address space. It is a circuit diagram which shows the structure of the address circuit of this embodiment. It is a circuit diagram which shows the structure of the address fixing circuit of this embodiment. It is a circuit diagram which shows the structure of the address switching circuit of this embodiment. It is a figure which shows the output in the address circuit of this embodiment, an address fixing circuit, and an address switching circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Bank group, 11 ... 1st bank, 11A ... Regular block, 11A-1 ... Cell array, 11A-2 ... Column gate, 11A-3 ... Data line, 11B ... Redundancy block, 11B-1 ... Cell array, 11B-2 ... column gate, 11C ... expansion block, 11C-1 ... cell array, 11C-2 ... column gate, 11C-3 ... data line, 11C-4 ... dummy area, 11D ... block decoder, 11E ... decoder group, 11E-1 ... Row main decoder, 11E-2 ... row sub decoder, 11E-3 ... column decoder, 20 ... sense amplifier.

Claims (5)

A first regular block in which a plurality of normally used memory cells are arranged;
A first redundancy block in which a plurality of memory cells used in place of a defective memory cell are arranged when the memory cell in the first regular block is defective;
A first bank including a plurality of memory cells and an expansion block having a storage capacity smaller than that of the first regular block;
A second regular block in which a plurality of normally used memory cells are arranged;
A second bank including a second redundancy block in which a plurality of memory cells used in place of the defective memory cells are arranged when the memory cells in the second regular block are defective;
A semiconductor memory device, wherein a storage capacity of the first redundancy block of the first bank is smaller than a storage capacity of a second redundancy block of the second bank.   2. The semiconductor memory device according to claim 1, wherein a row decoder used for the first redundancy block and a row decoder used for the extension block are shared.   A plurality of cell arrays having a plurality of memory cells are arranged in the extension block, and dummy wirings similar to the word lines formed in the first regular block are formed in a region where the cell array is not arranged. The semiconductor memory device according to claim 1, wherein: An address fixing circuit for fixing unnecessary addresses when selecting the extension block;
An address switching circuit for skipping addresses when selecting the extension block;
The semiconductor memory device according to claim 1, further comprising:   5. The semiconductor memory device according to claim 1, wherein the smallest rectangular area including the first bank and the smallest rectangular area including the second bank have the same size.

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