JP2022082113A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

To provide a semiconductor device in which the integration effect can be increased in a case where diodes are disposed on the same chip, and a manufacturing method for the same.SOLUTION: A semiconductor device 100 according to the present invention includes an insulating substrate 3, an N-type drift region 5 formed on the insulating substrate 3, a P-type drift region 7 formed adjacent to the N-type drift region 5, an anode electrode 9 electrically connected to the N-type drift region 5 while forming an energy barrier, a cathode electrode 11 electrically connected to the P-type drift region 7 while forming the energy barrier, and a connection electrode 13 formed at a position where the N-type drift region 5 and the P-type drift region 7 are adjacent to each other and disposed in ohmic junction with each of the N-type drift region 5 and the P-type drift region 7.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

Conventionally, Patent Document 1 is disclosed as a semiconductor device having a plurality of channels including upper and lower arms. In the semiconductor device disclosed in Patent Document 1, the diode on the positive potential side and the diode on the ground potential side of the high withstand voltage device are each surrounded by a groove and separated from each other.

Japanese Unexamined Patent Publication No. 2010-80803

However, in the above-mentioned conventional semiconductor device, since the diode on the positive potential side and the diode on the ground potential side are completely separated, there is a problem that the integration effect becomes low when the diode is arranged on the same chip. was there.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of enhancing the integration effect when a diode is arranged on the same chip and a method for manufacturing the same.

The semiconductor device according to one aspect of the present invention forms a first conductive type drift region and a second conductive type drift region adjacent to each other on an insulating substrate. Then, the first electrode that forms an energy barrier with the first conductive type drift region and is electrically connected to each other, and the second electrode that forms an energy barrier and is electrically connected to the second conductive type drift region are connected to each other. Have. Further, a third electrode is formed at a position where the first conductive type drift region and the second conductive type drift region are adjacent to each other, and the third electrode is ohmic-bonded to the first conductive type drift region and the second conductive type drift region, respectively. ing.

According to the present invention, the integration effect can be enhanced when the diodes are arranged on the same chip.

FIG. 1 is a cross-sectional perspective view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2A is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 1). FIG. 2B is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 2). FIG. 2C is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 3). FIG. 2D is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 4). FIG. 2E is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 5). FIG. 2F is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 6). FIG. 2G is a schematic process diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention (No. 7). FIG. 3 is a cross-sectional perspective view showing the structure of the semiconductor device according to the second embodiment of the present invention. FIG. 4 is a cross-sectional perspective view showing the structure of the semiconductor device according to the third embodiment of the present invention. FIG. 5 is a cross-sectional perspective view showing the structure of the semiconductor device according to the modified example of the third embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. include parts that are different from the actual ones. In addition, there are parts where the relationships and ratios of the dimensions of the drawings are different from each other.

Further, in the present specification and the like, "electrically connected" includes the case where they are connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements, resistance elements, inductors, capacitive elements, and other elements having various functions.

[First Embodiment]
[Structure of semiconductor device]
FIG. 1 is a diagram showing a structure of a semiconductor device according to the present embodiment. As shown in FIG. 1, the semiconductor device 100 according to the present embodiment includes a first diode 1A and a second diode 1B. The semiconductor device 100 is connected to an insulating substrate 3, a first conductive type drift region 5, a second conductive type drift region 7, an anode electrode (first electrode) 9, and a cathode electrode (second electrode) 11. It has an electrode (third electrode) 13. The first diode 1A and the second diode 1B are connected by a connection electrode 13, and the semiconductor device 100 functions as a whole as if two diodes are connected in series.

The first conductive type and the second conductive type are different conductive types from each other. That is, if the first conductive type is P type, the second conductive type is N type, and if the first conductive type is N type, the second conductive type is P type. In the present embodiment, the case where the first conductive type is N type and the second conductive type is P type will be described. Therefore, in the following, the first conductive type drift region 5 will be described as the N type drift region 5, and the second conductive type will be described. The type drift region 7 will be described as a P type drift region 7.

The insulating substrate 3 is an insulating semiconductor substrate. This makes it possible to simplify the element separation process when integrating a plurality of semiconductor devices on the same insulating substrate 3. Further, when mounting the semiconductor device on the cooler, it is possible to omit the insulating board installed between the insulating board 3 and the cooler. Here, the insulating substrate means that the resistivity of the substrate is several kΩ · cm or more.

For example, a silicon carbide substrate (SiC substrate) can be used as the insulating substrate 3. Since SiC is a wide bandgap semiconductor and has a small number of intrinsic carriers, it is easy to obtain high insulation and a semiconductor device having high withstand voltage can be realized. Although there are several polymorphs (polymorphs of crystals) in SiC, a typical 4H SiC substrate can be used as the insulating substrate 3. By using a SiC substrate for the insulating substrate 3, the insulating property of the insulating substrate 3 can be made high and the thermal conductivity can be made high. Therefore, the back surface of the insulating substrate 3 can be directly attached to the cooling mechanism to efficiently cool the semiconductor device. According to this structure, since the thermal conductivity of the SiC substrate is large, heat generation due to the main current when the semiconductor device is on can be efficiently dissipated.

Further, the insulating substrate 3 is not limited to the SiC substrate, and a semiconductor substrate made of a semiconductor material having a wide bandgap may be used. Examples of the semiconductor material having a wide bandgap include GaN, diamond, ZnO, AlGaN and the like.

The N-type drift region 5 is formed on the insulating substrate 3 and is formed adjacent to the P-type drift region 7. In the present embodiment, the N-type drift region 5 is in contact with the P-type drift region 7. The impurity concentration in the N-type drift region 5 is, for example, about 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁹ / cm ³ . Since it is possible to achieve both a low on-resistance and a high dielectric breakdown electric field, it is preferable that the N-type drift region 5 is formed of a wide bandgap semiconductor. Further, if the insulating substrate 3 and the N-type drift region 5 are formed of the same material, it is possible to prevent performance deterioration such as lattice mismatch that occurs when different materials are used.

Further, an N-type cathode region 15 is formed in a part of the N-type drift region 5. The impurity concentration of the N-type cathode region 15 is higher than that of the N-type drift region 5, and is, for example, about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ . The connection electrode 13 is ohmic-bonded to the surface of the N-type cathode region 15, and the anode electrode 9 is bonded to the surface of the N-type drift region 5.

The P-type drift region 7 is formed on the insulating substrate 3 and is formed adjacent to the N-type drift region 5. In the present embodiment, the P-type drift region 7 is in contact with the N-type drift region 5. The impurity concentration in the P-type drift region 7 is, for example, about 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁹ / cm ³ . Since it is possible to achieve both a low on-resistance and a high dielectric breakdown electric field, it is preferable that the P-type drift region 7 is formed of a wide bandgap semiconductor. Further, if the insulating substrate 3 and the P-type drift region 7 are formed of the same material, it is possible to prevent performance deterioration such as lattice mismatch that occurs when different materials are used.

Further, a P-type anode region 17 is formed in a part of the P-type drift region 7. The impurity concentration of the P-type anode region 17 is higher than that of the P-type drift region 7, and is, for example, about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ . The connection electrode 13 is ohmic-bonded to the surface of the P-type anode region 17, and the cathode electrode 11 is bonded to the surface of the P-type drift region 7.

The anode electrode 9 is electrically connected to the N-type drift region 5 by forming an energy barrier. For example, the anode electrode 9 may be formed of a metal that forms a Schottky barrier with the N-type drift region 5, or may be formed of a polysilicon material that forms a heterojunction with the N-type drift region 5. .. The anode electrode 9 thus formed functions as an anode electrode of the first diode 1A and also functions as an anode electrode of the semiconductor device 100.

The cathode electrode 11 is electrically connected to the P-shaped drift region 7 by forming an energy barrier. For example, the cathode electrode 11 may be formed of a metal that forms a Schottky barrier with the P-type drift region 7, or may be formed of a polysilicon material that forms a heterojunction with the P-type drift region 7. .. The cathode electrode 11 thus formed functions as a cathode electrode of the second diode 1B and also functions as a cathode electrode of the semiconductor device 100.

The connection electrode 13 is formed at a position where the N-type drift region 5 and the P-type drift region 7 are adjacent to each other, and is ohmic-bonded to the N-type drift region 5 and the P-type drift region 7, respectively. In particular, the connection electrode 13 is ohmic-bonded to the N-type cathode region 15 formed in a part of the N-type drift region 5 and to the P-type anode region 17 formed in a part of the P-type drift region 7. ing.

The connection electrode 13 is separately bonded to the N-type drift region 5 and the P-type drift region 7. Therefore, as shown in FIG. 1, in the connection electrode 13, the electrode portion 13a bonded to the N-type cathode region 15 and the electrode portion 13b bonded to the P-type anode region 17 are separately formed, and the electrode portion 13a is formed. , 13b have a structure connected by the upper connecting portion 13c.

The connection electrode 13 having such a structure connects the first diode 1A and the second diode 1B, and functions as a cathode electrode of the first diode 1A and also as an anode electrode of the second diode 1B.

[Operation of semiconductor devices]
Next, an example of the basic operation of the semiconductor device 100 according to the present embodiment will be described.

In the first diode 1A of the semiconductor device 100 having the configuration shown in FIG. 1, when a low voltage (forward voltage) is applied to the connection electrode 13 with the anode electrode 9 as a reference potential, the anode electrode 9 and the N-type drift region 5 are formed. The barrier height between them is lowered. As a result, electrons flow from the N-type drift region 5 to the anode electrode 9, and a current (forward current) flows from the anode electrode 9 to the connection electrode 13.

On the other hand, when a high voltage (reverse voltage) is applied to the connection electrode 13 with the anode electrode 9 as a reference potential, the barrier height between the anode electrode 9 and the N-type drift region 5 becomes high, and the barrier height is increased from the anode electrode 9. The empty layer spreads inside the N-type drift region 5. As a result, electrons do not flow from the N-type drift region 5 to the anode electrode 9, and no current flows from the anode electrode 9 to the connection electrode 13.

Further, in the second diode 1B, when a high voltage (forward voltage) is applied to the connection electrode 13 with the cathode electrode 11 as a reference potential, the barrier height between the cathode electrode 11 and the P-type drift region 7 is low. Become. As a result, holes flow from the P-type drift region 7 to the cathode electrode 11, and a current (forward current) flows from the connection electrode 13 to the cathode electrode 11.

On the other hand, when a low voltage (reverse voltage) is applied to the connection electrode 13 with the cathode electrode 11 as a reference potential, the barrier height between the cathode electrode 11 and the P-type drift region 7 increases, and the cathode electrode 11 A depleted layer spreads inside the P-type drift region 7. As a result, the hole does not flow from the P-type drift region 7 to the cathode electrode 11, and the current from the connection electrode 13 to the cathode electrode 11 does not flow.

[Manufacturing method of semiconductor devices]
Next, an example of the manufacturing method of the semiconductor device 100 according to the present embodiment will be described with reference to FIGS. 2A to 2G.

First, the insulating substrate 3 to which impurities are not added is prepared. Next, as shown in FIG. 2A, the mask material 31 formed on the insulating substrate 3 is patterned to expose the region forming the N-type drift region 5. Then, using the mask material 31 as a mask, ion implantation is performed to selectively add N-type impurities to the insulating substrate 3 to form the N-type drift region 5.

As a general mask material, a silicon oxide film can be used, and as a deposition method, a thermal CVD method or a plasma CVD method can be used. As a patterning method, a photolithography method can be used. That is, the mask material is etched using the patterned photoresist film as a mask. As the etching method, dry etching such as wet etching using hydrofluoric acid or reactive ion etching can be used. After etching the mask material, the photoresist film is removed with oxygen plasma, sulfuric acid, or the like. In this way, the mask material 31 is patterned.

Next, as shown in FIG. 2B, the mask material 33 formed on the insulating substrate 3 and the N-type drift region 5 is patterned to expose the region forming the P-type drift region 7. Then, using the mask material 33 as a mask, ion implantation is performed to selectively add P-type impurities to the insulating substrate 3 to form the P-type drift region 7.

Next, as shown in FIG. 2C, the mask material 35 formed on the insulating substrate 3, the N-type drift region 5, and the P-type drift region 7 is patterned to expose the region forming the N-type cathode region 15. Let me. Then, using the mask material 35 as a mask, ion implantation is performed to selectively add N-type impurities to the N-type drift region 5 to form a high-concentration N-type cathode region 15.

Next, as shown in FIG. 2D, the mask material 37 formed on the insulating substrate 3, the N-type drift region 5, the P-type drift region 7, and the N-type cathode region 15 is patterned, and the P-type anode region 17 is formed. The area that forms the Then, using the mask material 37 as a mask, ion implantation is performed in which P-type impurities are selectively added to the P-type drift region 7, to form a high-concentration P-type anode region 17.

As the N-type impurity in this embodiment, for example, nitrogen (N) can be used, and as the P-type impurity, for example, aluminum (Al) or boron (B) can be used. Further, by implanting ions in a state where the temperature of the substrate is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the ion-implanted region.

Further, the impurities ion-implanted in each of the above steps can be activated by heat treatment. For example, heat treatment at about 1700 ° C. is performed in an argon atmosphere or a nitrogen atmosphere.

Further, even if the ion implantation condition of adding impurities with high injection energy to form a high-concentration impurity region and the ion implantation condition of adding impurities with low injection energy to form a low-concentration impurity region are appropriately switched. good. As a result, a high-concentration impurity region and a low-concentration impurity region can be continuously formed by one continuous ion implantation. For example, the N-type drift region 5 and the P-type drift region 7, which are low-concentration impurity regions, and the N-type cathode region 15 and the P-type anode region 17, which are high-concentration impurity regions, can be continuously formed.

By forming the N-type drift region 5 and the P-type drift region 7 while changing the ion implantation conditions in the middle of ion implantation to change the impurity concentration in the depth direction as described above, the impurity concentration in the depth direction can be increased. Can be designed freely. As a result, the concentration of the electric field can be relaxed and the maximum applied voltage of the semiconductor device can be improved.

In the present embodiment, the case where the N-type drift region 5 and the P-type drift region 7 are formed by ion implantation has been specifically described, but the N-type drift region 5 and the P-type drift region 7 are formed by epitaxial growth. May be good.

Next, as shown in FIG. 2E, the interlayer insulating film 39 is formed. As the interlayer insulating film 39, for example, a silicon oxide film can be used. As a method for depositing the silicon oxide film, a thermal CVD method or a plasma CVD method can be used. Further, a silicon nitride film may be used for the interlayer insulating film 39.

Then, the interlayer insulating film 39 is selectively etched using the patterned photoresist film (not shown) as a mask to form a contact hole so that the upper surface of the N-type drift region 5 is exposed. As the etching method, for example, dry etching such as wet etching using hydrofluoric acid or reactive ion etching is used.

Next, the electrode film formed so as to embed the contact hole is patterned to form the anode electrode 9. As the material of the anode electrode 9, a metal material such as nickel (Ni) or molybdenum (Mo) that forms a Schottky junction with the N-type semiconductor can be preferably used. Further, a laminated film such as nickel / silver (Ni / Ag) may be used for the anode electrode 9. The anode electrode 9 is formed by depositing a metal material on the entire surface by a sputtering method, an electron beam (EB) vapor deposition method, or the like, and then etching the metal material. Further, the contact hole may be embedded with a metal material by a plating process to form the anode electrode 9. Further, the anode electrode 9 may be formed by using a polysilicon material that forms a heterojunction with the N-type semiconductor.

Next, as shown in FIG. 2F, the interlayer insulating film 39 is selectively etched using the patterned photoresist film (not shown) as a mask, and a contact hole is formed so that the upper surface of the P-type drift region 7 is exposed. Form. As the etching method, for example, dry etching such as wet etching using hydrofluoric acid or reactive ion etching is used.

Next, the electrode film formed so as to embed the contact hole is patterned to form the cathode electrode 11. As the material of the cathode electrode 11, a metal material such as titanium (Ti) forming a Schottky junction with the P-type semiconductor can be preferably used. Further, a laminated film such as titanium / silver (Ti / Ag) may be used for the cathode electrode 11. The cathode electrode 11 is formed by depositing a metal material on the entire surface by a sputtering method, an electron beam (EB) vapor deposition method, or the like, and then etching the metal material. Further, the contact hole may be embedded with a metal material by a plating process to form the cathode electrode 11. Further, the cathode electrode 11 may be formed by using a polysilicon material that forms a heterojunction with the P-type semiconductor.

Next, as shown in FIG. 2G, the interlayer insulating film 39 is selectively etched using the patterned photoresist film (not shown) as a mask, and the upper surfaces of the N-type cathode region 15 and the P-type anode region 17 are exposed. A contact hole is formed so as to be. As the etching method, for example, dry etching such as wet etching using hydrofluoric acid or reactive ion etching is used.

Next, the electrode film formed so as to embed the contact hole is patterned to form the connection electrode 13. As the material of the connection electrode 13, a metal material such as nickel (Ni) that forms an ohmic contact with high-concentration N-type and P-type semiconductors can be preferably used. The connection electrode 13 is formed by depositing a metal material on the entire surface by a sputtering method, an electron beam (EB) vapor deposition method, or the like, and then etching the metal material. Further, the contact hole may be embedded with a metal material by a plating process to form the connection electrode 13. When the connection electrode 13 is formed in this way, the semiconductor device 100 according to the present embodiment is completed.

[Effect of the first embodiment]
As described in detail above, the semiconductor device 100 according to the present embodiment has an anode electrode 9 electrically connected to the N-type drift region 5 by forming an energy barrier, and a P-type drift region 7 and an energy barrier. It has a cathode electrode 11 which is electrically connected to form the above. Further, the connection electrode 13 is formed at a position where the N-type drift region 5 and the P-type drift region 7 are adjacent to each other, and the connection electrode 13 is ohmic-bonded to the N-type drift region 5 and the P-type drift region 7, respectively. As a result, the N-type drift region 5 and the P-type drift region 7 formed adjacent to each other can be used as diodes, so that the integration effect can be enhanced when the diodes are arranged on the same chip. In particular, in an inverter circuit having an upper arm and a lower arm, an integrated freewheel diode is formed by utilizing a semiconductor region formed for the upper arm and a semiconductor region formed for the lower arm. Can be done.

Further, in the semiconductor device 100 according to the present embodiment, the anode electrode 9 is formed of the metal forming the N-type drift region 5 and the Schottky barrier, and the cathode electrode 11 is formed of the metal forming the P-type drift region 7 and the Schottky barrier. Is formed of. As a result, the N-type drift region 5 and the P-type drift region 7 can be used as Schottky barrier diodes, so that the integration effect can be enhanced when the diodes are arranged on the same chip.

Further, in the semiconductor device 100 according to the present embodiment, the anode electrode 9 is formed of a polysilicon material that forms a heterojunction with the N-type drift region 5, and the cathode electrode 11 is a poly that forms a heterojunction with the P-type drift region 7. It is made of a silicon material. As a result, the N-type drift region 5 and the P-type drift region 7 can be used as the heterojunction diode, so that the integration effect can be enhanced when the diodes are arranged on the same chip.

Further, in the semiconductor device 100 according to the present embodiment, the N-type drift region 5 and the P-type drift region 7 are formed of a wide bandgap semiconductor. This makes it possible to achieve both a low on-resistance and a high dielectric breakdown electric field.

Further, in the semiconductor device 100 according to the present embodiment, the insulating substrate 3, the N-type drift region 5, and the P-type drift region 7 are formed of the same material. This makes it possible to prevent performance deterioration such as lattice mismatch that occurs when different materials are used.

Further, in the semiconductor device 100 according to the present embodiment, the insulating substrate 3 is made of silicon carbide. As a result, the cooling performance can be improved by utilizing the high thermal conductivity characteristics of silicon carbide.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, impurities are added to the insulating substrate 3 by ion implantation to form an N-type drift region 5 and a P-type drift region 7. As a result, the manufacturing cost can be significantly reduced as compared with the case of forming by epitaxial growth.

Further, in the semiconductor device 100 according to the present embodiment, the N-type drift region 5 and the P-type drift region 7 are formed by changing the impurity concentration in the depth direction at the time of ion implantation. This makes it possible to freely design the dope concentration in the depth direction and further improve the maximum applied voltage.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, the N-type drift region 5 and the P-type drift region 7 are formed by epitaxial growth. This makes it possible to improve the characteristics of the diode.

[Second Embodiment]
Hereinafter, a second embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[Structure of semiconductor device]
FIG. 3 is a diagram showing the structure of the semiconductor device according to the present embodiment. As shown in FIG. 3, the semiconductor device 100 according to the present embodiment is different from the first embodiment in that the insulating region 19 is formed between the N-type drift region 5 and the P-type drift region 7.

The insulating region 19 is masked between the region where the N-type drift region 5 is formed and the region where the P-type drift region 7 is formed when the N-type drift region 5 and the P-type drift region 7 are formed by ion implantation. It can be formed by providing a material so that impurities are not added. Therefore, the insulating region 19 is formed to the depth of the insulating substrate 3 and is made of the same material as the insulating substrate 3. Further, the insulating region 19 is in contact with the N-type drift region 5 and the P-type drift region 7.

[Effect of the second embodiment]
As described above in detail, in the semiconductor device 100 according to the present embodiment, the insulating region 19 is formed between the N-type drift region 5 and the P-type drift region 7. As a result, it is possible to suppress the injection of holes from the P-type anode region 17 into the first diode 1A during the operation of the first diode 1A. Further, it is possible to suppress the injection of electrons from the N-type cathode region 15 into the second diode 1B during the operation of the second diode 1B. Further, it is possible to suppress the recovery current when the first and second diodes 1A and 1B turn off.

[Third Embodiment]
Hereinafter, a third embodiment to which the present invention is applied will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[Structure of semiconductor device]
FIG. 4 is a diagram showing the structure of the semiconductor device according to the present embodiment. As shown in FIG. 4, in the semiconductor device 100 according to the present embodiment, the anode electrode 9 is connected to the N-type drift region 5 via the P-type semiconductor region 21, and the cathode electrode 11 is connected to the N-type drift region 5 via the N-type semiconductor region 23. It is different from the second embodiment that it is connected to the P-type drift region 7. Although FIG. 4 shows an example in which the P-type semiconductor region 21 and the N-type semiconductor region 23 are formed in the semiconductor device 100 of the second embodiment, the P-type semiconductor is shown in the semiconductor device 100 of the first embodiment. It is also possible to form the region 21 and the N-type semiconductor region 23.

The P-type semiconductor region 21 is formed on the insulating substrate 3 and is in contact with the N-type drift region 5. An anode electrode 9 is ohmic-bonded to the surface of the P-type semiconductor region 21. Therefore, the P-type semiconductor region 21 and the N-type drift region 5 form a PN junction and function as the first diode 1A.

The P-type semiconductor region 21 may be formed at the same time when the P-type drift region 7 is formed by ion implantation. That is, when the mask material is patterned, if the region where the P-type drift region 7 is formed is exposed and the region where the P-type semiconductor region 21 is formed is also exposed and ion implantation is performed, the P-type drift region 7 is exposed. And the P-type semiconductor region 21 can be formed at the same time. Further, the anode electrode 9 may be formed by using a metal material such as nickel (Ni) that forms an ohmic contact with the P-type semiconductor.

The N-type semiconductor region 23 is formed on the insulating substrate 3 and is in contact with the P-type drift region 7. A cathode electrode 11 is ohmic-bonded to the surface of the N-type semiconductor region 23. Therefore, the N-type semiconductor region 23 and the P-type drift region 7 form a PN junction and function as the second diode 1B.

The N-type semiconductor region 23 may be formed at the same time when the N-type drift region 5 is formed by ion implantation. That is, when the mask material is patterned, if the region where the N-type drift region 5 is formed is exposed and the region where the N-type semiconductor region 23 is formed is also exposed and ion implantation is performed, the N-type drift region 5 is performed. And the N-type semiconductor region 23 can be formed at the same time. Further, the cathode electrode 11 may be formed by using a metal material such as nickel (Ni) that forms an ohmic contact with the N-type semiconductor.

Further, in the present embodiment, a column region may be provided in a part of the N-type drift region 5 and the P-type drift region 7, respectively, to form a super junction structure. As shown in FIG. 5, in the semiconductor device 100 according to the present embodiment, the P-type column region 25 is formed in a part of the N-type drift region 5, and the N-type column region 27 is formed in a part of the P-type drift region 7. Formed to form a superjunction structure.

The P-type column region 25 is formed on the insulating substrate 3 and is in contact with the N-type drift region 5, the P-type semiconductor region 21, and the N-type cathode region 15. The P-type column region 25 can be formed by ion implantation, and the mask material may be patterned to expose the region where the P-type column region 25 is formed and ion implantation may be performed.

The N-type column region 27 is formed on the insulating substrate 3 and is in contact with the P-type drift region 7, the N-type semiconductor region 23, and the P-type anode region 17. The N-type column region 27 can be formed by ion implantation, and the mask material may be patterned to expose the region where the N-type column region 27 is formed and ion implantation may be performed.

[Effect of the third embodiment]
As described in detail above, in the semiconductor device 100 according to the present embodiment, the anode electrode 9 is connected to the N-type drift region 5 via the P-type semiconductor region 21, and the cathode electrode 11 connects the N-type semiconductor region 23. It is connected to the P-type drift region 7 via. As a result, the P-type semiconductor region 21, the N-type drift region 5, the N-type semiconductor region 23, and the P-type drift region 7 can each function as a PN junction diode, and the withstand voltage can be increased.

Further, in the semiconductor device 100 according to the present embodiment, the P-type column region 25 is formed in a part of the N-type drift region 5, and the N-type column region 27 is formed in a part of the P-type drift region 7. Form a structure. As a result, it is possible to obtain high withstand voltage and low on-resistance performance.

The above embodiment is an example of the present invention. Therefore, the present invention is not limited to the above-described embodiment, and even if the embodiment is other than this embodiment, as long as it does not deviate from the technical idea of the present invention, it depends on the design and the like. Of course, various changes are possible.

1A 1st diode 1B 2nd diode 3 Insulated substrate 5 N-type drift region 7 P-type drift region 9 Anode electrode 11 cathode electrode 13 Connection electrode 15 N-type cathode region 17 P-type anode region 19 Insulation region 21 P-type semiconductor region 23 N Type semiconductor area 25 P-type column area 27 N-type column area 31, 33, 35, 37 Mask material 39 Interlayer insulating film 100 Semiconductor device

Claims (12)

Insulated board and
The first conductive type drift region formed on the insulating substrate and
A second conductive drift region formed on the insulating substrate and adjacent to the first conductive drift region, and a second conductive drift region.
The first electrode, which forms an energy barrier and is electrically connected to the first conductive drift region,
The second electrode, which forms an energy barrier and is electrically connected to the second conductive drift region,
The first conductive type drift region and the second conductive type drift region are formed at adjacent positions, and have a third electrode ohmic-bonded to the first conductive type drift region and the second conductive type drift region, respectively. A semiconductor device characterized by this. The first electrode is formed of a metal forming a Schottky barrier with the first conductive drift region.
The semiconductor device according to claim 1, wherein the second electrode is formed of a metal forming a Schottky barrier with the second conductive drift region. The first electrode is formed of a polysilicon material that forms a heterojunction with the first conductive drift region.
The semiconductor device according to claim 1, wherein the second electrode is made of a polysilicon material that forms a heterojunction with the second conductive drift region. A second conductive semiconductor region formed on the insulating substrate and in contact with the first conductive drift region,
It further has a first conductive semiconductor region formed on the insulating substrate and in contact with the second conductive drift region.
The first electrode is connected to the first conductive drift region via the second conductive semiconductor region.
The semiconductor device according to claim 1, wherein the second electrode is connected to the second conductive drift region via the first conductive semiconductor region. A second conductive column region is formed in a part of the first conductive drift region, and a first conductive column region is formed in a part of the second conductive drift region to form a super junction structure. The semiconductor device according to claim 4. The semiconductor device according to any one of claims 1 to 5, wherein an insulating region is formed between the first conductive type drift region and the second conductive type drift region. The semiconductor device according to any one of claims 1 to 6, wherein the first conductive type drift region and the second conductive type drift region are made of a wide bandgap semiconductor. The semiconductor device according to any one of claims 1 to 7, wherein the insulating substrate, the first conductive type drift region, and the second conductive type drift region are made of the same material. The semiconductor device according to any one of claims 1 to 8, wherein the insulating substrate is made of silicon carbide. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is manufactured.
A method for manufacturing a semiconductor device, which comprises adding impurities to the insulating substrate by ion implantation to form the first conductive type drift region and the second conductive type drift region. The semiconductor device according to claim 10, wherein the first conductive type drift region and the second conductive type drift region are formed by changing the impurity concentration in the depth direction at the time of ion implantation. Production method. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is manufactured.
A method for manufacturing a semiconductor device, characterized in that the first conductive type drift region and the second conductive type drift region are formed by epitaxial growth.

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