JP2022079407A5 - - Google Patents

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Publication number
JP2022079407A5
JP2022079407A5 JP2021103681A JP2021103681A JP2022079407A5 JP 2022079407 A5 JP2022079407 A5 JP 2022079407A5 JP 2021103681 A JP2021103681 A JP 2021103681A JP 2021103681 A JP2021103681 A JP 2021103681A JP 2022079407 A5 JP2022079407 A5 JP 2022079407A5
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JP
Japan
Prior art keywords
error rate
bit error
encoded data
data
threshold
Prior art date
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Pending
Application number
JP2021103681A
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English (en)
Japanese (ja)
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JP2022079407A (ja
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Publication date
Priority claimed from US17/171,657 external-priority patent/US11379305B2/en
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Publication of JP2022079407A publication Critical patent/JP2022079407A/ja
Publication of JP2022079407A5 publication Critical patent/JP2022079407A5/ja
Pending legal-status Critical Current

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JP2021103681A 2020-11-16 2021-06-22 不揮発性データ完全性の高速検証 Pending JP2022079407A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063114103P 2020-11-16 2020-11-16
US63/114,103 2020-11-16
US17/171,657 US11379305B2 (en) 2020-11-16 2021-02-09 Fast verification of non-volatile data integrity
US17/171,657 2021-02-09

Publications (2)

Publication Number Publication Date
JP2022079407A JP2022079407A (ja) 2022-05-26
JP2022079407A5 true JP2022079407A5 (enExample) 2022-08-12

Family

ID=81587721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021103681A Pending JP2022079407A (ja) 2020-11-16 2021-06-22 不揮発性データ完全性の高速検証

Country Status (3)

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US (1) US11379305B2 (enExample)
JP (1) JP2022079407A (enExample)
KR (1) KR102715393B1 (enExample)

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JP2024041466A (ja) 2022-09-14 2024-03-27 キオクシア株式会社 メモリシステムおよび制御方法
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CN121153020A (zh) * 2023-04-24 2025-12-16 美光科技公司 具有数据验证的受管理非易失性存储器装置
US12488854B2 (en) * 2023-06-14 2025-12-02 Western Digital Technologies, Inc. Data storage device and method for host-managed data integrity
US20250095765A1 (en) * 2023-09-15 2025-03-20 SK Hynix Inc. Error condition monitoring in memory systems
US20250104789A1 (en) * 2023-09-22 2025-03-27 Micron Technology, Inc. Dual-read data integrity scan in a memory sub-system

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