JP2022079407A - 不揮発性データ完全性の高速検証 - Google Patents

不揮発性データ完全性の高速検証 Download PDF

Info

Publication number
JP2022079407A
JP2022079407A JP2021103681A JP2021103681A JP2022079407A JP 2022079407 A JP2022079407 A JP 2022079407A JP 2021103681 A JP2021103681 A JP 2021103681A JP 2021103681 A JP2021103681 A JP 2021103681A JP 2022079407 A JP2022079407 A JP 2022079407A
Authority
JP
Japan
Prior art keywords
data
error rate
bit error
threshold
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021103681A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022079407A5 (enExample
Inventor
ラン・ザミール
Zamir Ran
デヴィット・アブラハム
Avraham David
エラン・シャロン
Sharon Eran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Western Digital Technologies Inc
Original Assignee
Western Digital Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Digital Technologies Inc filed Critical Western Digital Technologies Inc
Publication of JP2022079407A publication Critical patent/JP2022079407A/ja
Publication of JP2022079407A5 publication Critical patent/JP2022079407A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2021103681A 2020-11-16 2021-06-22 不揮発性データ完全性の高速検証 Pending JP2022079407A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063114103P 2020-11-16 2020-11-16
US63/114,103 2020-11-16
US17/171,657 US11379305B2 (en) 2020-11-16 2021-02-09 Fast verification of non-volatile data integrity
US17/171,657 2021-02-09

Publications (2)

Publication Number Publication Date
JP2022079407A true JP2022079407A (ja) 2022-05-26
JP2022079407A5 JP2022079407A5 (enExample) 2022-08-12

Family

ID=81587721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021103681A Pending JP2022079407A (ja) 2020-11-16 2021-06-22 不揮発性データ完全性の高速検証

Country Status (3)

Country Link
US (1) US11379305B2 (enExample)
JP (1) JP2022079407A (enExample)
KR (1) KR102715393B1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024041466A (ja) 2022-09-14 2024-03-27 キオクシア株式会社 メモリシステムおよび制御方法
US20240289056A1 (en) * 2023-02-27 2024-08-29 Micron Technology Inc. Verifying chunks of data based on read-verify commands
CN121153020A (zh) * 2023-04-24 2025-12-16 美光科技公司 具有数据验证的受管理非易失性存储器装置
US12488854B2 (en) * 2023-06-14 2025-12-02 Western Digital Technologies, Inc. Data storage device and method for host-managed data integrity
US20250095765A1 (en) * 2023-09-15 2025-03-20 SK Hynix Inc. Error condition monitoring in memory systems
US20250104789A1 (en) * 2023-09-22 2025-03-27 Micron Technology, Inc. Dual-read data integrity scan in a memory sub-system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327690A (ja) * 1992-05-21 1993-12-10 Hitachi Ltd 通信方法および装置
JPH09508990A (ja) * 1993-11-12 1997-09-09 コナー ペリフェラルズ インコーポレイテッド Ｓｃｓｉ接続のｒａｉｄバンク及びバンク環境を監視しそして制御するためのｓｃｓｉ接続モジュール
US20010002086A1 (en) * 1998-06-12 2001-05-31 Webb Sterling E. Dual mode stabilizer for backhoe loaders and backhoe attachments
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
US20170236592A1 (en) * 2016-02-11 2017-08-17 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
US20180173655A1 (en) * 2016-12-20 2018-06-21 Sandisk Technologies Llc Multi-channel memory operations based on bit error rates

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7490263B2 (en) 2006-01-17 2009-02-10 Allen King Apparatus, system, and method for a storage device's enforcing write recovery of erroneous data
KR20090042951A (ko) * 2006-08-08 2009-05-04 지멘스 에너지 앤드 오토메이션 인코포레이티드 Ｐｌｃ에 관한 장치들, 시스템들, 및 방법들
US8307271B1 (en) 2009-09-17 2012-11-06 Emc Corporation Fast verification of data block cycle redundancy checks
US8631281B1 (en) 2009-12-16 2014-01-14 Kip Cr P1 Lp System and method for archive verification using multiple attempts
US8910031B1 (en) 2011-03-29 2014-12-09 Emc Corporation DIF-CRC based fast hashing
US8726104B2 (en) 2011-07-28 2014-05-13 Sandisk Technologies Inc. Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages
US20130031431A1 (en) * 2011-07-28 2013-01-31 Eran Sharon Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats
US8939056B1 (en) * 2012-04-20 2015-01-27 Barron Associates, Inc. Systems, devices, and/or methods for managing targeted payload descent
US8984190B2 (en) * 2013-05-23 2015-03-17 Western Digital Technologies, Inc. Methods and devices for booting a network attached storage with two logical units
US10475523B2 (en) 2013-05-31 2019-11-12 Western Digital Technologies, Inc. Updating read voltages triggered by the rate of temperature change
US9697905B2 (en) 2013-05-31 2017-07-04 Sandisk Technologies Llc Updating read voltages using syndrome weight comparisons
US9818488B2 (en) * 2015-10-30 2017-11-14 Seagate Technology Llc Read threshold voltage adaptation using bit error rates based on decoded data
US9411683B2 (en) * 2013-12-26 2016-08-09 Intel Corporation Error correction in memory
US10089177B2 (en) 2014-06-30 2018-10-02 Sandisk Technologies Llc Multi-stage decoder
US9817752B2 (en) 2014-11-21 2017-11-14 Sandisk Technologies Llc Data integrity enhancement to protect against returning old versions of data
US9886342B2 (en) * 2015-10-28 2018-02-06 Sandisk Technologies Llc Storage device operations based on bit error rate (BER) estimate
US10536172B2 (en) * 2016-03-04 2020-01-14 Western Digital Technologies, Inc. ECC and raid-type decoding
EP3504814B1 (en) * 2016-10-31 2021-05-26 Huawei Technologies Duesseldorf GmbH Error detection using symbol distribution in a system with distribution matching and probabilistic amplitude shaping
US10418097B2 (en) * 2017-11-27 2019-09-17 Western Digital Technologies, Inc. Non-volatile storage system with read calibration
US10534738B2 (en) * 2018-01-17 2020-01-14 Western Digital Technologies, Inc. Host bus adaptor with configurable interface
WO2019221650A1 (en) * 2018-05-17 2019-11-21 Telefonaktiebolaget Lm Ericsson (Publ) Measurement reporting for radio access network

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327690A (ja) * 1992-05-21 1993-12-10 Hitachi Ltd 通信方法および装置
JPH09508990A (ja) * 1993-11-12 1997-09-09 コナー ペリフェラルズ インコーポレイテッド Ｓｃｓｉ接続のｒａｉｄバンク及びバンク環境を監視しそして制御するためのｓｃｓｉ接続モジュール
US20010002086A1 (en) * 1998-06-12 2001-05-31 Webb Sterling E. Dual mode stabilizer for backhoe loaders and backhoe attachments
US20150358036A1 (en) * 2014-06-10 2015-12-10 Phison Electronics Corp. Decoding method, memory storage device and memory control circuit unit
US20170236592A1 (en) * 2016-02-11 2017-08-17 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
US20180173655A1 (en) * 2016-12-20 2018-06-21 Sandisk Technologies Llc Multi-channel memory operations based on bit error rates

Also Published As

Publication number Publication date
US20220156143A1 (en) 2022-05-19
KR20220066815A (ko) 2022-05-24
KR102715393B1 (ko) 2024-10-08
US11379305B2 (en) 2022-07-05

Similar Documents

Publication Publication Date Title
KR102621497B1 (ko) 비휘발성 스토리지에 대한 판독 적분 시간 교정
KR102715393B1 (ko) 비휘발성 데이터 무결성의 고속 검증
CN113744784B (zh) 分层读取参考校准
JP7179127B2 (ja) ソフトビット基準レベル較正
US11482296B2 (en) ECC in integrated memory assembly
KR102684016B1 (ko) 디코딩된 데이터를 사용한 소프트 비트 기준 레벨 교정
US11321167B2 (en) Adaptive folding for integrated memory assembly
US11763911B2 (en) On-chip-copy for integrated memory assembly
KR102600877B1 (ko) 인접 메모리 셀 간섭 완화
US11579812B2 (en) Local data compaction for integrated memory assembly
US11977915B2 (en) Non-volatile memory with intelligent compute task distribution
US11068342B1 (en) Redundancy data in integrated memory assembly
US11650932B2 (en) Integrated non-volatile memory assembly with address translation

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210622

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20210706

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20211027

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220803

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20220803

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220823

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221004

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20221227

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20230725