JP2022050683A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of alleviating electric field concentration in a withstand voltage structure region and improving a withstand voltage.

SOLUTION: A semiconductor device includes an active region 101 and a breakdown voltage structure region 102 having an opposite conductivity type electric field relaxation region (4, 5, 21, and 22) provided around the active region 101 and disposed above a drift layer 32 included in the active region 101, and the depth of the electric field relaxation region (4, 5, 21, and 22) becomes shallower toward the outside, and a space modulation portion is provided at the outer end of the electric field relaxation region (4, 5, 21, and 22).

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a technique for relaxing an electric field concentration in a withstand voltage structure region of the semiconductor device.

In order to alleviate the electric field concentration in the withstand voltage structure region of the conventional semiconductor device, a structure having a resurf layer composed of a plurality of p-type injection layers in the withstand voltage structure region has been proposed (see Patent Document 1). Further, a structure in which a p ⁺ type layer, a p ^- type layer and a p ^- type layer are provided outward in the pressure resistant structure region has been proposed (see Patent Document 2).

However, in the semiconductor devices described in Patent Documents 1 and 2, the electric field concentration in the withstand voltage structure region cannot be sufficiently relaxed, and the withstand voltage may decrease.

International Publication No. 2012/049872 Japanese Unexamined Patent Publication No. 1-138759

In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of alleviating electric field concentration in a withstand voltage structure region and improving withstand voltage.

One aspect of the present invention is provided in (a) an active region and (b) an electric field relaxation region of a conductive type opposite to the drift layer, which is provided above the drift layer included in the active region and is arranged around the active region. The gist of the present invention is that the semiconductor device is provided with a withstand voltage structure region having a pressure resistant structure region, and the depth of the electric field relaxation region becomes shallower toward the outside, and a space modulation unit is provided at the outer end portion of the electric field relaxation region.

According to the present invention, it is possible to provide a semiconductor device capable of relaxing the electric field concentration in the withstand voltage structure region and improving the withstand voltage.

It is sectional drawing of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process sectional view for demonstrating an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 3 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 4 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 5 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 6 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 7 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 8 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. It is a process sectional view for demonstrating an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 11 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. It is a process sectional view for demonstrating another example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. It is a process cross-sectional view following FIG. 13 for explaining another example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process sectional view for demonstrating an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 17 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 18 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 19 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 20 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is a process sectional view for demonstrating an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 23 for explaining an example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is a process sectional view for demonstrating another example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is a process cross-sectional view following FIG. 25 for explaining another example of the manufacturing method of the pressure-resistant structure region of the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is sectional drawing of the pressure-resistant structure region of the semiconductor device which concerns on a comparative example.

Hereinafter, the first and second embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals, and duplicate description will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. may differ from the actual ones. In addition, parts having different dimensional relationships and ratios may be included between the drawings. Further, the first and second embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is based on the material of a component. The shape, structure, arrangement, etc. are not specified to the following.

As used herein, the "first main electrode region" means a semiconductor region that is either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), it means a semiconductor region that is either an emitter region or a collector region. Further, in an electrostatic induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO), it means a semiconductor region which is either an anode region or a cathode region. The “second main electrode region” means a semiconductor region that is either a source region or a drain region that does not become the first main electrode region in the FET or SIT. In the IGBT, it means a region that is either an emitter region or a collector region that is not the first main electrode region. In SI thyristor and GTO, it means a region which is either an anode region or a cathode region which is not the first main electrode region. As described above, when the "first main electrode region" is the source region, the "second main electrode region" means the drain region. When the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. When the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region. By exchanging the bias relationship, in many cases, the function of the "first main electrode region" and the function of the "second main electrode region" can be exchanged.

Further, the definition of the direction such as up and down in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present invention. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read. Further, in the following description, the case where the first conductive type is n type and the second conductive type opposite to the first conductive type is p type will be exemplified. However, the conductive type may be selected in the opposite relationship, the first conductive type may be the p type, and the second conductive type opposite to the first conductive type may be the n type. Further, + and-attached to n and p mean that they are semiconductor regions having a relatively high or low impurity density, respectively, as compared with the semiconductor regions to which + and-are not added. However, even if the semiconductor regions have the same n and n, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same.

(First Embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an active region 101 and a pressure-resistant structure region 102 arranged around the active region 101. FIG. 1 illustrates a case where the active region 101 includes a MISFET having a trench gate structure provided above the drift layer 2 of the first conductive type (n ⁻ type) as an active element.

A second conductive type (p type) base region 6 is arranged on the upper surface of the drift layer 2. The drift layer 2 and the base region 6 are each composed of an epitaxial growth layer made of SiC (hereinafter, abbreviated as "epitaxial layer"). Above the base region 6, p ⁺ type base contact regions 7a, 7b, 7c having a higher impurity density than the base region 6 are selectively provided. An n ⁺ type first main electrode region (source region) 8 having a higher impurity density than the drift layer 2 is selectively provided on the upper portion of the base region 6 so as to be in contact with the base contact region 7a.

A trench 25 is provided so as to penetrate the base region 6 from the upper surfaces of the source region 8 and the base region 6. A gate insulating film 9 is provided on the bottom surface and the side surface of the trench 25. The gate insulating film 9 includes a silicon oxide film (SiO ₂ film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si _{3N 4 )} film, and an aluminum oxide (Al). ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO ₂ ) film, zirconium oxide (ZrO ₂ ) film, tantalum oxide (Ta ₂ O) film ₅ ) A single-layer film of any one of a film and a bismuth oxide (Bi ₂ O ₃ ) film, or a composite film in which a plurality of these is laminated can be adopted.

A gate electrode 10 is embedded in the trench 25 via a gate insulating film 9. As the material of the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) in which impurities such as phosphorus (P) are added to a high impurity density can be used.

An n-type current diffusion layer (CSL) 3 having a higher impurity density than the drift layer 2 is selectively provided on the upper part of the drift layer 2. The bottom of the trench 25 reaches the current diffusion layer 3. Inside the current diffusion layer 3, a p ⁺ type gate bottom protection region 4y is provided so as to be in contact with the bottom of the trench 25. Inside the current diffusion layer 3, a first base bottom embedded region 4x is provided below the base contact region 7a at the same depth as the gate bottom protection region 4y and away from the gate bottom protection region 4y. .. A second base bottom embedded region 5x is provided on the upper portion of the current diffusion layer 3 so as to be sandwiched between the upper surface of the first base bottom embedded region 4x and the lower surface of the base region 6.

Inside the drift layer 2, a first base bottom embedded region 4 is provided below the base contact region 7c at the same depth as the gate bottom protection region 4y and away from the gate bottom protection region 4y. A second base bottom embedded region 5 is provided on the upper portion of the drift layer 2 so as to be sandwiched between the upper surface of the first base bottom embedded region 4 and the lower surface of the base region 6. The left end of the first base bottom embedded region 4 and the second base bottom embedded region 5 is in contact with the current diffusion layer 3.

A first main electrode (source electrode) 14 is arranged on the upper surface of the gate electrode 10 separately from a gate surface electrode (not shown) located at the back of the paper surface via an interlayer insulating film 11. As the interlayer insulating film 11, a non-doped silicon oxide film (SiO ₂ film) containing no phosphorus (P) or boron (B), which is called "NSG", can be adopted. However, as the interlayer insulating film 11, a silicon oxide film (PSG) to which phosphorus is added, a silicon oxide film (BSG) to which boron is added, a silicon oxide film (BPSG) to which boron and phosphorus are added, and a silicon nitride (Si ₃ ) are used. N ₄ ) A film or the like may be used. The source electrode 14 is electrically connected to the source region 8 and the base contact regions 7a and 7b. A barrier metal layer 13 is arranged on the lower layer of the source electrode 14. The barrier metal layer 13 is arranged so as to be in metallic contact with the source region 8 and the base contact regions 7a and 7b, respectively. For example, the barrier metal layer 13 is made of a nickel (Ni) film, and the source electrode 14 is made of an aluminum (Al) film. As the gate surface electrode, the same material as the source electrode 14 can be used.

The wiring layer 15 is arranged on the upper surface of the base contact region 7c via the interlayer insulating film 11, and the gate electrode pad 16 is arranged on the upper surface of the wiring layer 15. Although not shown, the gate electrode pad 16 is electrically connected to the gate electrode 10 via the wiring layer 15. A protective film 12 is arranged around the gate electrode pad 16. The interlayer insulating film 11 and the protective film 12 extend to the pressure-resistant structure region 102 side.

An n ⁺ type second main electrode region (drain region) 1 is arranged on the lower surface of the drift layer 2. The drain region 1 is composed of a semiconductor substrate (SiC substrate) made of SiC. A second main electrode (drain electrode) 17 is arranged on the lower surface of the drain region 1. As the drain electrode 17, for example, a single-layer film made of gold (Au) or a metal film in which Al, nickel (Ni), and Au are laminated in this order can be used, and molybdenum (Mo) is used as the lowermost layer thereof. A metal film such as tungsten (W) may be laminated.

During operation of the semiconductor device according to the first embodiment of the present invention, when a positive voltage is applied to the drain electrode 17 and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 10, it is inverted to the side surface side of the trench 25 of the base region 6. A layer (channel) is formed and turned on. The inversion layer is formed on the surface of the base region 6 exposed on the side surface of the trench 25 which is the interface between the gate insulating film 9 sandwiched at the position where the base region 6 faces the gate electrode 10 and the base region 6. In the on state, a current flows from the drain electrode 17 to the source electrode 14 via the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layer of the base region 6, and the source region 8. On the other hand, when the voltage applied to the gate electrode 10 is less than the threshold value, the inversion layer is not formed in the base region 6, so that the state is turned off and no current flows from the drain electrode 17 to the source electrode 14.

As shown in FIG. 1, the first base bottom embedded region 4 extends from the active region 101 side on the left side to the withstand voltage structure region 102, and functions as the first electric field relaxation layer 4 on the withstand voltage structure region 102 side. Further, the second base bottom embedded region 5 extends from the active region 101 side on the left side to the withstand voltage structure region 102, and functions as the second electric field relaxation layer 5 on the withstand voltage structure region 102 side.

A partially enlarged view of the upper part of the drift layer 2 on the pressure resistant structure region 102 side shown in FIG. 1 is shown in FIG. In FIG. 2, the interlayer insulating film 11, the protective film 12, the wiring layer 15, and the gate electrode pad 16 shown in FIG. 1 are not shown.

The pressure-resistant structure region 102 has a p-type electric field relaxation region (4,5,21,22) provided above the drift layer 2. In the withstand voltage structure region 102, the depth of the electric field relaxation region (4,5,21,22) becomes shallower toward the outside, and a spatial modulation unit is provided at the outer end of the electric field relaxation region (4,5,21,22). It is provided. The electric field relaxation region (4,5,21,22) includes a first electric field relaxation layer 4, a second electric field relaxation layer 5, and a junction termination structure portion (21,22). The second electric field relaxation layer 5 extends to the outside of the first electric field relaxation layer 4 so as to be in contact with the upper surface of the first electric field relaxation layer 4. The joint termination structure portion (21, 22) extends to the outside of the second electric field relaxation layer 5 so as to be in contact with the upper surface of the second electric field relaxation layer 5.

The first electric field relaxation layer 4 is a p + type main body portion 4a extending continuously from the active region 101 side, and a p ⁺ type main body portion 4a provided on the outside of the main body portion 4a with the same impurity density as the main body portion 4a ^. It has spatial modulation units 4b, 4c, 4d, 4e. The spatial modulation units 4b, 4c, 4d, and 4e are provided in a concentric ring shape so as to be separated from each other. For example, the spatial modulation units 4b, 4c, 4d, and 4e form a spatial modulation pattern in which the width becomes narrower and the interval becomes wider toward the outside. By having the patterns of the spatial modulation units 4b, 4c, 4d, and 4e in the shape of a concentric ring, the amount of p-type impurities added (absent amount) effectively decreases toward the outside, so that the electric field concentration is relaxed. be able to.

The second electric field relaxation layer 5 extends to the outside of the first electric field relaxation layer 4 so as to be in contact with the upper surface of the first electric field relaxation layer 4. The second electric field relaxation layer 5 may have the same impurity density as the first electric field relaxation layer 4, or may have a lower impurity density than the first electric field relaxation layer 4. For example, the impurity density of the first electric field relaxation layer 4 is 5 × 10 ¹⁷ cm ^-3 to 2 × 10 ¹⁹ cm ^-3 , and the impurity density of the second electric field relaxation layer 5 is 3 × 10 ¹⁷ cm ^-3 to 1 × 10 ¹⁹ . It may be cm ^-3 . The second electric field relaxation layer 5 has a main body portion 5a extending continuously from the active region 101 side and spatial modulation portions 5b, 5c, 5d provided outside the main body portion 5a with the same impurity density as the main body portion 5a. , 5e. The spatial modulation units 5b, 5c, 5d, and 5e are provided in a concentric ring shape so as to be separated from each other. For example, the spatial modulation units 5b, 5c, 5d, 5e form a spatial modulation pattern that is shallower than the spatial modulation units 4b, 4c, 4d, 4e, narrows in width toward the outside, and widens in spacing. There is. By having the spatial modulation units 5b, 5c, 5d, and 5e having a concentric ring shape, the amount of p-type impurities added decreases effectively toward the outside, so that the electric field concentration can be relaxed.

The base region 6 has a step portion 6x. A junction termination structure (21, 22) called a "junction termination extension (JTE)" is provided from the base contact region 7c to the vicinity of the outer end of the upper part of the drift layer 2 over the upper part of the base region 6. ing. The joint termination structure portion (21, 22) extends to the outside of the second electric field relaxation layer 5. The junction termination structure portion (21, 22) is provided outside the p ^- type first junction termination region (first JTE region) 21 and the first JTE region 21 having a lower impurity density than the base region 6, and is a first JTE region. It has a p ^- type second junction termination region (second JTE region) 22 having a lower impurity density than 21. For example, the impurity density of the base region 6 is 2 × 10 ¹⁶ cm ^-3 to 2 × 10 ¹⁸ cm ^-3 , and the impurity density of the first JTE region 21 is 2 × 10 ¹⁶ cm ^-3 to 2 × 10 ¹⁸ cm ^-3 . The impurity density of the 2JTE region 22 may be 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .

The first JTE region 21 has a main body portion 21a extending from the base contact region 7c to the upper part of the drift layer 2 to the outside of the second electric field relaxation layer 5, and a spatial modulation section provided outside the main body portion 21a. It has 21b, 21c, 21d, 21e. The spatial modulation units 21b, 21c, 21d, 21e are provided in a concentric ring shape so as to be separated from each other. For example, the spatial modulation units 21b, 21c, 21d, 21e form a spatial modulation pattern that is shallower than the spatial modulation units 5b, 5c, 5d, 5e, narrows in width toward the outside, and widens in spacing. There is.

The second JTE region 22 has spatial modulation units 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h provided concentrically with the same impurity density and separated from each other. Of these, the spatial modulation units 22a, 22b, 22c, 22d located inside are alternately provided with the spatial modulation portions 21b, 21c, 21d, 21e of the first JTE region 21. Further, the spatial modulation units 22e, 22f, 22g, and 22h located on the outside form, for example, a spatial modulation pattern in which the width becomes narrower and the interval becomes wider toward the outside.

By having the spatial modulation units 21b, 21c, 21d, 21e of the first JTE region 21 and the spatial modulation portions 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h of the second JTE region 22, p-type toward the outside. Since the amount of impurities added is effectively reduced, the electric field concentration can be alleviated.

At the outer end of the pressure resistant structure region 102, an n ⁺ type channel stopper 23 is provided in a concentric ring shape on the upper part of the drift layer 2. A p ⁺ type channel stopper may be provided instead of the n ⁺ type channel stopper 23.

Here, a comparative example of the semiconductor device according to the first embodiment of the present invention will be described. As shown in FIG. 27, the semiconductor device according to the comparative example has a p ⁺ type first base bottom embedded region 71 and a p ⁺ type second on the upper part of the drift layer 70 in the pressure resistant structure region provided in the peripheral portion. The base bottom embedded region 72 extends continuously from the active region. A p-shaped base region 73 is arranged on the upper surface of the drift layer 70. A p ⁺ type base contact region 74 is provided above the base region 73. An n ⁺ type channel stopper 77 is provided at the outer end of the drift layer 70.

A joint termination structure portion (75,76) is provided from the base contact region 74 to the vicinity of the outer end portion of the drift layer 70. The joint termination structure portion (75,76) is composed of a p ^- type first JTE region 75 and a p ^- type second JTE region 76 provided outside the first JTE region 75.

In the semiconductor device according to the comparative example, the first base bottom embedded region 71 and the second base bottom embedded region 72 are provided as a continuous pattern from the active region, but the space modulation portion is not provided and the electric field is not provided. Does not function as a mitigation area. Therefore, electric field concentration occurs at the outer ends of the first base bottom embedded region 71 and the second base bottom embedded region 72.

On the other hand, according to the semiconductor device according to the first embodiment, as shown in FIGS. 1 and 2, the first base bottom embedded region 4 and the second base continuously extend from the active region 101 side. The bottom embedded region 5 is effectively utilized as the first electric field relaxation layer 4 and the second electric field relaxation layer 5. Then, the depth of each layer constituting the electric field relaxation region (4,5,21,22) becomes shallower toward the outside, and the outer end side of each layer of the electric field relaxation region (4,5,21,22) becomes shallower. Since the spatial modulation pattern is provided in, the electric field concentration can be relaxed also in the depth direction. Therefore, the withstand voltage of the withstand voltage structure region 102 can be improved, a device with a high withstand voltage can be realized, and the margin between the active withstand voltage and the edge withstand voltage can be widened.

Further, the deeper the electric field relaxation region (4,5,21,22) is, the higher the impurity density in the electric field relaxation region (4,5,21,22) is, and the electric field relaxation region (4,5,21,22) is increased. By lowering the impurity density of) toward the outside, the effect of relaxing the electric field concentration can be improved.

Next, using FIGS. 3 to 9, the method of manufacturing the semiconductor device according to the embodiment of the present invention will be described with a focus on the pressure-resistant structure region 102 provided in the peripheral portion of the chip. It should be noted that the manufacturing method described below is an example, and it is needless to say that it can be realized by various manufacturing methods other than this, including this modification, as long as it is within the scope of the claims. ..

First, an n ⁺ type semiconductor substrate (SiC substrate) to which an n-type impurity such as nitrogen (N) is added is prepared. Using this n ⁺ type SiC substrate as the drain region 1, an n ⁻ type first drift layer 2a is epitaxially grown on the upper surface of the drain region 1. Next, a photoresist film is applied to the upper surface of the first drift layer 2a, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as aluminum (Al) are implanted in multiple stages. After removing the photoresist film, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 3, a p ⁺ type first electric field relaxation layer (first base bottom embedded region) 4 is formed on the upper part of the first drift layer 2a. The first electric field relaxation layer 4 has a main body portion 4a extending continuously from the active region 101 side and a spatial modulation section 4b provided on the outside of the main body portion 4a so as to form a concentric ring-shaped spatial modulation pattern. , 4c, 4d, 4e. At the same time, on the active region 101 side shown in FIG. 1, a p ⁺ type gate bottom protection region 4y and a p ⁺ type first base bottom embedded region 4x are formed on the upper part of the first drift layer 2a.

Next, as shown in FIG. 4 ^, an n− type second drift layer 2b is epitaxially grown on the upper surface of the first drift layer 2a. The drift layer 2 is formed by the first drift layer 2a and the second drift layer 2b, and the first electric field relaxation layer 4 is embedded inside the drift layer 2. Next, a photoresist film is applied to the upper surface of the drift layer 2, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the photoresist film, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 5, a p ⁺ type second electric field relaxation layer (second base bottom embedded region) 5 is provided above the drift layer 2 so as to be in contact with the upper surface of the first electric field relaxation layer 4. Form. The second electric field relaxation layer 5 has a main body portion 5a extending continuously from the active region 101 side and a spatial modulation section 5b provided on the outside of the main body portion 5a so as to form a concentric ring-shaped spatial modulation pattern. , 5c, 5d, 5e. At the same time, on the active region 101 side shown in FIG. 1, a second base bottom embedded region 5x is formed on the upper part of the drift layer 2.

Next, as shown in FIG. 6, a p-type base region 6 is epitaxially grown on the upper surface of the drift layer 2. Then, a photoresist film is applied to the upper surface of the base region 6, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the photoresist film, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 7, a p ⁺ type base contact region 7c is formed on the upper portion of the base region 6. At the same time, on the active region 101 side shown in FIG. 1, p ⁺ type base contact regions 7a and 7b are formed on the upper part of the drift layer 2.

Next, a photoresist film is applied to the upper surface of the base region 6, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an etching mask, a part of the outer periphery of the base region 6 is selectively removed by wet etching or the like. After that, the photoresist film is removed by a wet treatment or the like. As a result, as shown in FIG. 8, a stepped portion 6x having an inclination is formed in the base region 6, and the upper surface of the drift layer 2 is exposed to the outside of the pressure-resistant structure region 102.

Next, as shown in FIG. 9, a p ^- type first JTE is performed by a photolithography technique in which mask alignment is performed twice, ion implantation in each of the two mask alignments, and then heat treatment. The region 21 is formed. The p ^- type first JTE region 21 is formed so as to extend above the base contact region 7c, the base region 6, the second electric field relaxation layer 5, and the drift layer 2. For example, when forming the first JTE region 21, a first ion implantation mask patterned by a photolithography technique is used for the central (inner) region. Using this first ion implantation mask, n-type impurity ions such as N are selectively added to the p ⁺ type base contact region 7c, the p-type base region 6, and the p ⁺ type second electric field relaxation layer 5. Multi-stage ion implantation. Further, a second ion implantation mask patterned by photolithography technology is used to selectively implant p-type impurity ions such as Al into the n ^- type drift layer 2 on the outer end side. .. Then, by performing a heat treatment, a part of the p-type impurities on the upper part of the base contact region 7c, the base region 6, and the second electric field relaxation layer 5 is compensated with the activated n-type impurities, and the p ^- type first JTE is compensated. The region 21 is formed. The order may be such that the injection of the p-type impurity ion using the second ion implantation mask is performed before the injection of the n-type impurity ion using the first ion implantation mask.

On the other hand, when a p ^- type second JTE region 22 having a lower impurity density than the first JTE region 21 is formed outside the first JTE region 21, the drift layer has a smaller dose amount than when the first JTE region 21 is ion-implanted. P-type impurity ions such as Al are implanted into 2 in multiple stages. The heat treatment after ion implantation may be performed together with the heat treatment for forming the first JTE region 21.

According to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the occurrence of electric field concentration in the withstand voltage structure region can be efficiently prevented by a plurality of spatial modulation patterns having different depths at the lower ends, and the withstand voltage is improved. It becomes possible to realize a semiconductor device that can be made to.

(Variation example of the first embodiment)
FIG. 10 shows a pressure resistant structure region of the semiconductor device according to the modified example of the first embodiment of the present invention. As shown in FIG. 10, in the withstand voltage structure region of the semiconductor device according to the modified example of the first embodiment of the present invention, the p-type base region 6 provided on the upper surface of the drift layer 2 does not have a stepped portion. It extends to the vicinity of the outer end of the pressure resistant structure region and functions as the third electric field relaxation layer 6.

In the withstand voltage structure region of the semiconductor device according to the modified example of the first embodiment of the present invention, a first electric field relaxation layer 4, a second electric field relaxation layer 5, and a third space modulation unit 6a, 6b, 6c are provided. The electric field relaxation layer 6 constitutes an electric field relaxation region (4,5,6,6a, 6b, 6c). The third electric field relaxation layer 6 extends to the outside of the second electric field relaxation layer 5 so as to be in contact with the upper surface of the second electric field relaxation layer 5. On the outside of the third electric field relaxation layer 6, p-type spatial modulation units 6a, 6b, 6c are provided in a concentric ring shape. The spatial modulation units 6a, 6b, 6c are provided alternately with the n-type regions 24a, 24b, 24c, 24d. A channel stopper 23 is provided on the upper portion of the n-type region 24d located at the outer end of the pressure-resistant structure region.

According to the semiconductor device according to the modification of the first embodiment of the present invention, the first electric field relaxation layer 4, the second electric field relaxation layer 5, and the third electric field relaxation portion 6a, 6b, 6c provided are provided. By providing the electric field relaxation region (4,5,6,6a, 6b, 6c) by the layer 6, the generation of electric field concentration in the withstand voltage structure region can be efficiently prevented by a plurality of spatial modulation patterns having different depths at the lower ends. And the withstand voltage can be improved. Further, the third electric field relaxation layer 6 provided with the spatial modulation sections 6a, 6b, 6c can replace the structure of the junction termination structure section (21, 22) shown in FIGS. 1 and 2, and the number of layers can be replaced. And the number of processes can be reduced.

As an example of the method for manufacturing a semiconductor device according to the modified example of the first embodiment of the present invention, the first electric field relaxation layer 4 and the second electric field relaxation layer 5 are formed by the same procedure as in FIGS. 3 to 5. Then, as shown in FIG. 11, a p-type base region (third electric field relaxation layer) 6 is epitaxially grown on the upper surface of the drift layer 2. Then, a photoresist film is applied to the upper surface of the base region 6, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) for forming the n-type regions 24a, 24b, 24c, and 24d are implanted in multiple stages.

Then, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 12, the polarities of the p-type base region 6 are reversed (backed up) to form n-type regions 24a, 24b, 24c, 24d. Further, the base region 6 is sandwiched between the n-type regions 24a, 24b, 24c, 24d, and the p-type spatial modulation portions 6a, 6b, 6c are formed. Since the other procedure is the same as the method for manufacturing the semiconductor device according to the first embodiment of the present invention, duplicate description will be omitted.

Alternatively, as another example of the method for manufacturing a semiconductor device according to the modified example of the first embodiment of the present invention, the n-type region 24 may be epitaxially grown on the upper surface of the drift layer 2 as shown in FIG. Then, a photoresist film is applied to the upper surface of the n-type region 24, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. At this time, multi-stage ion implantation of p-type impurity ions such as Al is also performed in the region of the active region 101 shown in FIG. 1, which is the p-type base region 6.

Then, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 14, the polarity of the n-type region 24 is reversed (backed up) to form the p-type third electric field relaxation layer 6 and the spatial modulation portions 6a, 6b, 6c. Further, n-type regions 24a, 24b, 24c, 24d consisting of the rest of the n-type region 24 are formed. At the same time, the p-type base region 6 on the active region 101 side shown in FIG. 1 is also formed.

(Second Embodiment)
As shown in FIG. 15, the semiconductor device according to the second embodiment of the present invention includes an active region 201 and a pressure resistant structure region 202 arranged around the active region 201. FIG. 15 illustrates a case where the active region 201 includes a MISFET having a planar gate structure provided on the upper portion of the first conductive type (n ⁻ type) drift layer 32 as an active element.

Second conductive type (p type) base regions 34x, 34y, 34 are arranged on the upper surface of the drift layer 32. The drift layer 32 and the base regions 34x, 34y, 34 are each composed of an epitaxial layer made of SiC. The base regions 34x, 34y, 34 are provided with n ⁺ type first main electrode regions (source regions) 36a, 36b having a higher impurity density than the drift layer 32. The base regions 34x, 34y, 34 are provided with p ⁺ type base contact regions 35a, 35b having a higher impurity density than the base regions 34x, 34y, 34 so as to be in contact with the source regions 36a, 36b.

Note that FIG. 15 illustrates a structure in which the source regions 36a, 36b and the base contact regions 35a, 35b are provided so as to divide the base regions 34x, 34y, 34 at the same depth as the base regions 34x, 34y, 34. However, it is not limited to this. For example, the source regions 36a, 36b and the base contact regions 35a, 35b may be provided above the base regions 34x, 34y, 34.

An n-type junction field effect transistor (JFET) region 37 is arranged at a position sandwiched between the base regions 34x and 34y. At the upper part of the drift layer 32, p ⁺ type base bottom embedded regions 33x and 33 are provided so as to be separated from each other. The base bottom embedded region 33x is in contact with the lower surfaces of the base contact region 35a, the source region 36a, and the base region 34x. The base bottom embedded region 33 is in contact with the lower surfaces of the base region 34y, the source region 36b, the base contact region 35b, and the base region 34. The JFET region 37 is in contact with the upper surface of the convex portion of the drift layer 32 sandwiched between the base bottom embedded regions 33x and 33.

The gate electrode 39 is arranged via the gate insulating film 38 from the upper surface of the base region 34x, 34y and the JFET region 37 to a part of the upper surface of the source regions 36a, 36b. A first main electrode (source electrode) 41 is arranged on the upper surface of the gate electrode 39 separately from a gate surface electrode (not shown) located at the back of the paper surface via an interlayer insulating film 40. The source electrode 41 is electrically connected to the source regions 36a and 36b and the base contact regions 35a and 35b. A protective film 42 is arranged on the upper surface of the source electrode 41. The protective films 43 and 44 are arranged on the lower layer of the protective film 42 on the pressure resistant structure region 202 side.

An n ⁺ type second main electrode region (drain region) 31 is arranged on the lower surface of the drift layer 32. The drain region 31 is composed of a semiconductor substrate (SiC substrate) made of SiC. A second main electrode (drain electrode) 45 is arranged on the lower surface of the drain region 31.

During operation of the semiconductor device according to the second embodiment of the present invention, when a positive voltage is applied to the drain electrode 45 and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 39, the surface of the base regions 34x and 34y on the gate electrode 39 side is applied. An inverted layer (channel) is formed in and turned on. In the on state, a current flows from the drain electrode 45 to the source electrode 41 via the drain region 31, the drift layer 32, the JFET region 37, the inversion layer of the base regions 34x and 34y, and the source regions 36a and 36b. On the other hand, when the voltage applied to the gate electrode 39 is less than the threshold value, the inversion layer is not formed in the base regions 34x and 34y, so that the state is turned off and no current flows from the drain electrode 45 to the source electrode 41.

As shown in FIG. 15, the base bottom embedded region 33 extends from the active region 201 to the pressure-resistant structure region 202, and functions as the electric field relaxation layer 33 in the pressure-resistant structure region 202. The pressure-resistant structure region 202 has a p-type electric field relaxation region (33, 51, 52) provided above the drift layer 32. The depth of the outer end of each layer constituting the electric field relaxation region (33, 51, 52) becomes shallower toward the outside, and the outer end side of each layer of the electric field relaxation region (33, 51, 52) becomes shallower. Each is provided with a spatial modulation pattern.

A partially enlarged view of the upper part of the drift layer 32 on the pressure resistant structure region 202 side shown in FIG. 15 is shown in FIG. In FIG. 16, the protective films 42, 43, and 44 shown in FIG. 15 are not shown. As shown in FIG. 16, the electric field relaxation region (33, 51, 52) is a joint termination structure portion provided to the outside of the electric field relaxation layer 33 so as to be in contact with the electric field relaxation layer 33 and the upper surface of the electric field relaxation layer 33. (51, 52) is provided.

The electric field relaxation layer 33 has a main body portion 33a continuous from the active region 201, and spatial modulation portions 33b, 33c, 33d, 33e provided outside the main body portion 33a. The spatial modulation units 33b, 33c, 33d, 33e are provided in a concentric ring shape so as to be separated from each other. For example, the spatial modulation units 33b, 33c, 33d, 33e form a spatial modulation pattern in which the width becomes narrower and the interval becomes wider toward the outside.

The base region 34 has a stepped portion 34z. A joint termination structure portion (51, 52) is provided from the base contact region 35b to the vicinity of the outer end portion of the drift layer 32. The junction termination structure portion (51, 52) is provided outside the p ^- type first JTE region 51 and the first JTE region 51, ^and has a lower impurity density than the first JTE region 51. Has.

The first JTE region 51 has a main body 51a and spatial modulation sections 51b, 51c, 51d, 51e provided outside the main body 51a at a horizontal level shallower than the spatial modulation sections 33b, 33c, 33d, 33e. The second JTE region 52 includes spatial modulation units 52a, 52b, 52c, 52d provided alternately with the spatial modulation units 51b, 51c, 51d, 51e of the first JTE region 51, and spatial modulation units 52e, 52f provided on the outside. , 52g, 52h. Since the joint terminal structure portion (51, 52) has the same configuration as the joint terminal structure portion (21, 22) shown in FIGS. 1 and 2, duplicate description will be omitted.

At the outer end of the pressure resistant structure region 202, an n ⁺ type channel stopper 53 is provided above the drift layer 32. A p ⁺ type channel stopper may be provided instead of the n ⁺ type channel stopper 53.

According to the semiconductor device according to the second embodiment of the present invention, the depth of the outer end portion of each layer constituting the electric field relaxation region (33, 51, 52) becomes shallower toward the outside, and the electric field relaxation region (33, 51, 52) becomes shallower. 33, 51, 52) are provided with a plurality of spatial modulation patterns having different depths at the lower ends. As a result, the electric field concentration in the withstand voltage structure region 202 can be relaxed, and the withstand voltage can be improved. Therefore, a device with a higher withstand voltage can be realized, and the margin between the active withstand voltage and the edge withstand voltage can be widened.

Next, using FIGS. 17 to 21, a method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described with a focus on the pressure resistant structure region 202. It should be noted that the manufacturing method described below is an example, and it is needless to say that it can be realized by various manufacturing methods other than this, including this modification, as long as it is within the scope of the claims. ..

First, an n ⁺ type semiconductor substrate (SiC substrate) to which an n-type impurity such as nitrogen (N) is added is prepared. Using this n ⁺ type SiC substrate as the drain region 31 ^, an n− type drift layer 32 is epitaxially grown on the upper surface of the drain region 31. Next, a photoresist film is applied to the upper surface of the drift layer 32, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the photoresist film, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 17, a p ⁺ type base bottom embedded region (electric field relaxation layer) 33 is formed on the upper part of the drift layer 32. The electric field relaxation layer 33 has a main body portion 33a continuous from the active region 201, and spatial modulation portions 33b, 33c, 33d, 33e provided outside the main body portion 33a. At the same time, on the active region 201 side shown in FIG. 15, a p ⁺ type base bottom embedded region 33x is formed on the upper part of the drift layer 32.

Next, as shown in FIG. 18, a p-type base region 34 is epitaxially grown on the upper surface of the drift layer 32. Then, a photoresist film is applied to the upper surface of the base region 34, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the photoresist film, heat treatment is performed to activate p-type impurity ions, and as shown in FIG. 19, a p ⁺ -type base contact region 35b is formed in the base region 34. At the same time, on the active region 201 side shown in FIG. 15, a p ⁺ type base contact region 35a is formed in the base region 34.

Next, a photoresist film is applied to the upper surface of the base region 34, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an etching mask, a part of the base region 34 is selectively removed by wet etching or the like. After that, the photoresist film is removed by a wet treatment or the like. As a result, as shown in FIG. 20, an inclined step portion 34z is formed in the base region 34, and the upper surface of the drift layer 32 is exposed.

Next, as shown in FIG. 21, a p ^- type first JTE is performed by a photolithography technique in which mask alignment is performed twice, ion implantation in response to the two mask alignment, and then heat treatment. The region 51 is formed. The p ^- type first JTE region 51 is formed so as to extend above the base contact region 35b, the base region 34, the electric field relaxation layer 33, and the drift layer 32. For example, when forming the first JTE region 51, a first ion implantation mask patterned by a photolithography technique is used for the central (inner) region. Using this first ion implantation mask, n-type impurity ions such as N are selectively multi-stage ions in the p ⁺ type base contact region 35b, the p-type base region 34, and the p ⁺ type electric field relaxation layer 33. inject. On the other hand, further, p-type impurity ions such as Al are selectively implanted into the n ^- type drift layer 32 by using a second ion implantation mask patterned by photolithography technology on the outer end side. do. Then, by performing a heat treatment, a part of the p-type impurities on the base contact region 35b, the base region 34, and the upper part of the electric field relaxation layer 33 is compensated with the activated n-type impurities, and the p ^- type first JTE region 51 To form. The order may be such that the injection of the p-type impurity ion using the second ion implantation mask is performed before the injection of the n-type impurity ion using the first ion implantation mask.

On the other hand, when a p ^- type second JTE region 52 having a lower impurity density than the first JTE region 51 is formed outside the first JTE region 51, the drift layer has a smaller dose amount than when the first JTE region 51 is ion-implanted. P-type impurity ions such as Al are implanted into 32 in multiple stages. The heat treatment after ion implantation may be performed together with the heat treatment for forming the first JTE region 51.

According to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, the occurrence of electric field concentration in the withstand voltage structure region can be efficiently prevented by a plurality of spatial modulation patterns having different depths at the lower ends, and the withstand voltage is improved. It becomes possible to realize a semiconductor device that can be made to.

(Modified example of the second embodiment)
FIG. 22 shows a pressure-resistant structure region of the semiconductor device according to the modified example of the second embodiment of the present invention. As shown in FIG. 22, in the withstand voltage structure region of the semiconductor device according to the modified example of the second embodiment of the present invention, the p-type base region 34 provided on the upper surface of the drift layer 32 does not have a stepped portion. It extends to the vicinity of the outer end of the pressure-resistant structure region and functions as an electric field relaxation layer 34.

In the withstand voltage structure region of the semiconductor device according to the modified example of the second embodiment of the present invention, the electric field relaxation region is formed by the first electric field relaxation layer 33 and the second electric field relaxation layer 34 provided with the space modulation units 34a, 34b, 34c. (33, 34, 34a, 34b, 34c) is configured. The second electric field relaxation layer 34 extends to the outside of the first electric field relaxation layer 33 so as to be in contact with the upper surface of the first electric field relaxation layer 33. On the outside of the second electric field relaxation layer 34, p-type spatial modulation units 34a, 34b, 34cc are provided in a concentric ring shape. Spatial modulation units 34a, 34b, 34c are provided alternately with n-type regions 54a, 54b, 54c, 54d. A channel stopper 53 is provided on the upper portion of the n-type region 54d located at the outer end of the pressure-resistant structure region.

According to the semiconductor device according to the modification of the second embodiment of the present invention, the electric field relaxation region (33) is formed by the first electric field relaxation layer 33 and the second electric field relaxation layer 34 provided with the spatial modulation units 34a, 34b, 34c. , 34, 34a, 34b, 34c), it is possible to relax the electric field concentration in the withstand voltage structure region.

As an example of the method for manufacturing a semiconductor device according to the modified example of the second embodiment of the present invention, a p ⁺ type base bottom embedded region (first electric field relaxation layer) is formed on the upper part of the drift layer 32 by the same procedure as in FIG. ) 33 is formed. Then, as shown in FIG. 23, a p-type base region (second electric field relaxation layer) 34 is epitaxially grown on the upper surface of the drift layer 32. Then, a photoresist film is applied to the upper surface of the second electric field relaxation layer 34, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as nitrogen (N) for forming n-type regions 54a, 54b, 54c, 54d are implanted in multiple stages. At this time, multi-stage ion implantation of n-type impurity ions such as nitrogen (N) is also performed in the region of the active region 201 shown in FIG. 15, which is the n-type JFET region 37.

Then, heat treatment is performed to activate the n-type impurity ion. As a result, as shown in FIG. 24, n-type regions 54a, 54b, 54c, 54d are formed in the second electric field relaxation layer 34. Further, the second electric field relaxation layer 34 is sandwiched between the n-type regions 54a, 54b, 54c, 54d to form the p-type spatial modulation portions 34a, 34b, 34c. At the same time, the n-type JFET region 37 on the active region 201 side shown in FIG. 15 is also formed.

Alternatively, as another example of the method for manufacturing a semiconductor device according to the modified example of the second embodiment of the present invention, as shown in FIG. 25, the n-type region 54 may be epitaxially grown on the upper surface of the drift layer 32. Then, a photoresist film is applied to the upper surface of the n-type region 54, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. At this time, multi-stage ion implantation of p-type impurity ions such as Al is also performed in the p-type base regions 34x and 34y of the active region 201 shown in FIG.

Then, heat treatment is performed to activate p-type impurity ions. As a result, as shown in FIG. 26, the p-type second electric field relaxation layer 34 and the spatial modulation portions 34a, 34b, and 34c are formed by reversing (reversing) the polarity of the n-type region 54. Further, n-type regions 54a, 54b, 54c, 54d consisting of the rest of the n-type region 54 are formed. At the same time, the p-type base regions 34x and 34y of the active region 201 shown in FIG. 15 are also formed.

(Other embodiments)
As mentioned above, the invention has been described by embodiment, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

In the first embodiment, the MISFET having a trench structure has been exemplified, but the invention is not limited to this, and the MOSFET device can be applied to a semiconductor device having various trench structures such as an IGBT having a trench structure. As the trench gate type IGBT, the n ⁺ type source region 8 of the MISFET shown in FIG. 1 is used as the emitter region, and the p ⁺ type collector region is provided on the lower surface side of the drift layer 2 instead of the n ⁺ type drain region 1. The structure may be provided.

In the embodiment of the present invention, the semiconductor device using SiC has been exemplified, but it can also be applied to a semiconductor device using another wide bandgap semiconductor such as gallium nitride (GaN) or diamond. Further, the present invention is not limited to wide bandgap semiconductors, and can be applied to semiconductor devices using silicon (Si).

1,31 ... Drain region 2,2a, 2b, 32,70 ... Drift layer 3 ... Current diffusion layer 4 ... First base bottom embedded region (electric field relaxation layer)
4a, 5a, 21a, 33a, 51a ... Main body 4b, 4c, 4d, 4e, 5b, 5c, 5d, 5e, 6a, 6b, 6c, 21b, 21c, 21d, 21e, 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h, 33b, 33c, 33d, 33e, 34a, 34b, 34c, 51b, 51c, 51d, 51e, 52a, 52b, 52c, 52d, 52e, 52f, 52g, 52h ... Spatial modulation unit 4x , 71 ... 1st base bottom embedded region 4y ... Gate bottom protected region 5 ... 2nd base bottom embedded region (electric field relaxation layer)
5x, 72 ... Second base bottom embedded region 6 ... Base region (electric field relaxation layer)
6x, 34z ... Stepped portions 7a, 7b, 7c, 35a, 35b, 74 ... Base contact region 8, 36a, 36b ... Source region 9, 38 ... Gate insulating film 10, 39 ... Gate electrode 11, 40 ... Interlayer insulating film 12 , 42, 43, 44 ... Protective film 13 ... Barrier metal layer 14, 41 ... Source electrode 15 ... Wiring layer 16 ... Gate electrode pad 17, 45 ... Drain electrode 21, 51, 75 ... First JTE region 22, 52, 76 ... 2nd JTE region 23, 53, 77 ... Channel stopper 24, 24a, 24b, 24c, 24d, 54, 54a, 54b, 54c, 54d ... n-type region 25 ... Trench 33 ... Base bottom embedded region (electric field relaxation layer)
33x ... Base bottom embedded region 34 ... Base region (electric field relaxation layer)
34x, 34y, 73 ... Base region 37 ... JFET region 101, 201 ... Active region 102, 202 ... Withstand voltage structure region

Claims (9)

The active region and
A pressure-resistant structure region having a second conductive type electric field relaxation region provided above the first conductive type drift layer included in the active region, which is arranged around the active region.
Equipped with
The depth of the electric field relaxation region becomes shallower toward the outside, a spatial modulation section is provided at the outer end of the electric field relaxation region, and the electric field relaxation region is continuously provided from the active region side. A featured semiconductor device. The electric field relaxation region
A second conductive type first electric field relaxation layer which is continuously provided inside the drift layer from the active region side and has a first spatial modulation section at the outer end portion.
A second space modulation section is provided on the upper part of the drift layer continuously from the active region side to the outside of the first electric field relaxation layer so as to be in contact with the upper surface of the first electric field relaxation layer. The second conductive type second electric field relaxation layer having,
The semiconductor device according to claim 1, wherein the semiconductor device comprises. The active region is
The second conductive type first base bottom embedded region provided in the upper part of the drift layer, and
The second conductive type second base bottom embedded region provided on the upper surface of the first base bottom embedded region, and the second base bottom embedded region.
Equipped with
The first electric field relaxation layer has a first main body portion continuously provided from the first base bottom embedded region on the active region side.
The semiconductor device according to claim 2, wherein the second electric field relaxation layer has a second main body portion continuously provided from the second base bottom embedded region on the active region side. The electric field relaxation region is provided on the upper surface of the drift layer continuously from the active region side to the outside of the second electric field relaxation layer so that the electric field relaxation region is in contact with the upper surface of the second electric field relaxation layer, and is provided at the outer end portion. The semiconductor device according to claim 2, further comprising a third electric field relaxation layer having a third spatial modulation unit. The active region is
The second conductive type first base bottom embedded region provided in the upper part of the drift layer, and
The second conductive type second base bottom embedded region provided on the upper surface of the first base bottom embedded region, and the second base bottom embedded region.
The second conductive type base region provided on the upper surface of the second base bottom embedded region and the second base region.
Equipped with
The first electric field relaxation layer has a first main body portion continuously provided from the first base bottom embedded region on the active region side.
The second electric field relaxation layer has a second main body portion continuously provided from the second base bottom embedded region on the active region side.
The semiconductor device according to claim 4, wherein the third electric field relaxation layer has a portion continuously provided from the base region on the active region side. The active region is
The second conductive type base bottom embedded region provided in the upper part of the drift layer, and
A second conductive type base region provided on the upper surface of the base bottom embedded region and
Equipped with
The first electric field relaxation layer has a main body portion continuously provided from the base bottom embedded region on the active region side.
The semiconductor device according to claim 2, wherein the second electric field relaxation layer has a portion continuously provided from the base region on the active region side. The electric field relaxation region
A second conductive type electric field relaxation layer which is continuously provided on the upper part of the drift layer from the active region side and has a space modulation portion at the outer end portion.
A second conductive type junction terminal structure portion provided to the outside of the electric field relaxation layer so as to be in contact with the upper surface of the electric field relaxation layer and having a spatial modulation portion at the outer end portion.
The semiconductor device according to claim 1, wherein the semiconductor device comprises. The active region is
The second conductive type base bottom embedded region provided in the upper part of the drift layer, and
A second conductive type base region provided on the upper surface of the base bottom embedded region and
Equipped with
The semiconductor device according to claim 7, wherein the electric field relaxation layer has a main body portion continuously provided from the base bottom embedded region on the active region side. The semiconductor device according to claim 2, wherein the outer peripheral end portion of the first space modulation section is closer to the active region side than the inner peripheral end portion of the second space modulation section.

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