JP7331914B2 - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to an insulated gate semiconductor device having an insulated gate electrode structure in trenches and a method of manufacturing the same.

A trench gate type MOS field effect transistor (MOSFET) is expected to have a reduced on-resistance compared to a planar gate type due to a smaller cell pitch. In a trench gate type MOSFET made of a wide bandgap semiconductor such as silicon carbide (SiC), a structure using the a-plane (11-20) on the side wall surface of the trench has been proposed (see Patent Documents 1 to 3). ). In Patent Documents 1 to 3, an n-type source region and a p-type base region are provided on one side wall of a trench, and the side wall is used as a current path.

Insulated gate semiconductor devices such as trench gate MOSFETs made of wide bandgap semiconductors are required to have further improvements in their structures and manufacturing methods.

U.S. Patent Application Publication No. 2017/0077251 Patent No. 6105032 JP 2016-163047 A

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device and a method of manufacturing the same, which can further improve the insulated gate semiconductor device.

According to one aspect of the present invention, a first side wall surface forming a first inclination angle with respect to a reference plane of a chip structure, and a second side wall surface facing the first side wall surface and having a different first inclination angle with respect to the reference plane. An insulated gate semiconductor device in which a plurality of trenches having side walls defined by inclined second side walls are arranged in a chip structure, comprising: (a) an insulated gate electrode in a first trench included in the plurality of trenches; A first unit cell having a structure comprising: a main electrode region of a first conductivity type in contact with a first sidewall surface of the first trench; a conductive type base region, a first conductive type drift layer with a lower impurity density than the main electrode region in contact with the lower surface of the base region and the first side wall surface, the first conductive type drift layer in contact with the second side wall surface and the bottom surface of the first trench, and the base (b) a second unit cell having an insulated gate electrode structure in a second trench included in the plurality of trenches; The second cell includes an operation suppression region of the second conductivity type, which is embedded in the upper part of the drift layer and is in contact with the first sidewall surface and the second sidewall surface of the second trench and has a higher impurity density than the base region. 2 unit cells, wherein the second unit cell is arranged to include a second trench positioned at one end of the array of the plurality of trenches.

Another aspect of the present invention includes (a) a first sidewall surface forming a first inclination angle with respect to a reference surface of a chip structure, and a first sidewall surface facing the first sidewall surface and having the first inclination angle with respect to the reference surface. (b) an insulated gate electrode structure disposed inside a trench having sidewalls defined by second sidewall surfaces having different second inclination angles; (c) a base region of the second conductivity type in contact with the lower surface of the main electrode region and the first side wall surface; and (d) lower impurity than the main electrode region in contact with the lower surface of the base region and the first side wall surface. (e) a gate protection region having a higher impurity density than the base region and being in contact with the second side wall surface and the bottom surface of the trench and having a second conductivity type; and (f) a main electrode region. The gist of the present invention is an insulated gate semiconductor device including a plurality of unit cells having main electrodes in contact with each other, and incorporating a Schottky barrier diode composed of a main electrode and a drift layer positioned between adjacent unit cells.

Another aspect of the present invention includes (a) a first sidewall surface forming a first inclination angle with respect to a reference surface of a chip structure, and a first sidewall surface facing the first sidewall surface and having the first inclination angle with respect to the reference surface. (b) an insulated gate electrode structure disposed inside a trench having both sidewalls defined by second sidewall surfaces having different second inclination angles; (c) a second conductivity type base region in contact with the lower surface of the main electrode region and the first sidewall surface; and (d) the main electrode in contact with the lower surface of the base region and the first sidewall surface. (e) a gate protection region of the second conductivity type with a higher impurity density than the base region and in contact with the second side wall surface and the bottom surface of the trench; The gist of the present invention is an insulated gate semiconductor device including a base contact region spaced apart from a trench and in contact with a gate protection region and having a higher impurity density than the base region and a second conductivity type.

Another aspect of the present invention includes (a) a drift layer of a first conductivity type, (b) a base region of a second conductivity type provided on the drift layer, (c) provided on top of the base region, (d) an insulated gate type provided inside a striped trench so that one side wall surface is in contact with the first conductivity type main electrode region having a higher impurity density than the drift layer; and (d) the main electrode region and the base region. and (e) a stripe-shaped gate protection region provided on the drift layer so as to be in contact with the bottom surface and the other side wall surface of the trench and having a higher impurity density than the base region and the second conductivity type. A structure in which a common base region is sandwiched between trenches of adjacent unit cells and a structure in which a common gate protection region is sandwiched between trenches of adjacent unit cells are alternately repeated to form a gate protection region. are arranged intermittently along the longitudinal direction of the trench.

Another aspect of the present invention comprises the steps of: (a) forming a second conductivity type base region on a first conductivity type drift layer; forming a main electrode region of a first conductivity type; A trench having side walls defined by second side wall surfaces facing each other and forming a second inclination angle different from the first inclination angle with respect to the reference plane is formed until it reaches the drift layer, and the main electrode region and the base region are formed in the second direction. (d) obliquely implanting ions into the bottom surface of the trench and the first sidewall surface to form a gate protection region of the second conductivity type in contact with the bottom surface of the trench and the first sidewall surface; and (e) forming an insulated gate electrode structure inside the trench.

According to the present invention, it is possible to provide an insulated gate semiconductor device capable of further improving the insulated gate semiconductor device and a method of manufacturing the same.

1 is a plan view showing an example of an insulated gate semiconductor device according to a first embodiment; FIG. FIG. 2 is a vertical cross-sectional view of the insulated gate semiconductor device according to the first embodiment viewed from the AA direction of FIG. 1; FIG. 2 is a vertical cross-sectional view of the insulated gate semiconductor device according to the first embodiment viewed from the BB direction of FIG. 1; FIG. 4 is a schematic diagram for explaining the plane orientation of sidewall surfaces of a trench; FIG. 4 is a schematic diagram for explaining the plane orientation of sidewall surfaces of a trench; 4 is a graph showing the relationship between the plane orientation of the side wall surface of the trench and the gate voltage and mobility. FIG. 3 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the first embodiment; FIG. 10 is a cross-sectional view of a main part showing an example of an insulated gate semiconductor device according to a second embodiment; FIG. 10 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the second embodiment; FIG. 10 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the second embodiment; FIG. 10 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the second embodiment; FIG. 11 is a cross-sectional view of a main part showing an example of an insulated gate semiconductor device according to a third embodiment; It is process sectional drawing for demonstrating an example of the manufacturing method of the insulated gate-type semiconductor device which concerns on 3rd Embodiment. FIG. 16 is a process cross-sectional view continued from FIG. 15 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 17 is a process cross-sectional view subsequent to FIG. 16 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 18 is a process cross-sectional view subsequent to FIG. 17 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 19 is a process cross-sectional view subsequent to FIG. 18 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; 20 is a process cross-sectional view subsequent to FIG. 19 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. FIG. 21 is a process cross-sectional view subsequent to FIG. 20 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 22 is a process cross-sectional view continued from FIG. 21 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 23 is a process cross-sectional view continued from FIG. 22 for explaining the example of the method of manufacturing the insulated gate semiconductor device according to the third embodiment; FIG. 11 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the third embodiment; FIG. 11 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the third embodiment; FIG. 11 is a cross-sectional view of a main part showing another example of the insulated gate semiconductor device according to the third embodiment; FIG. 11 is a cross-sectional view of a main part showing an example of an insulated gate semiconductor device according to a fourth embodiment; FIG. 28 is a horizontal cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment viewed from the AA direction of FIG. 27; FIG. 29 is a vertical cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment viewed from the CC direction of FIG. 28; 28 is another horizontal cross-sectional view of the insulated gate semiconductor device according to the comparative example viewed from the AA direction of FIG. 27; FIG. 28 is another horizontal cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment viewed from the AA direction of FIG. 27; FIG. 28 is another horizontal cross-sectional view of the insulated gate semiconductor device according to the fourth embodiment viewed from the AA direction of FIG. 27; FIG.

First to fourth embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and overlapping descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may differ from the actual ones. In addition, portions having different dimensional relationships and ratios may also be included between drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not specified below.

As used herein, the term "first main electrode region" means a semiconductor region that serves as either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), it means a semiconductor region which is either an emitter region or a collector region. Also, in static induction thyristors (SI thyristors) and gate turn-off thyristors (GTO), it means a semiconductor region that is either an anode region or a cathode region. "Second main electrode region" means a semiconductor region that is either a source region or a drain region that does not become the first main electrode region in an FET or SIT. In an IGBT, it means a region that is either an emitter region or a collector region that is not the first main electrode region. In SI thyristors and GTOs, it means a region that is either an anode region or a cathode region that is not the first main electrode region. Thus, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. If the "first main electrode area" is the anode area, then the "second main electrode area" means the cathode area. By exchanging the bias relationship, it is possible to exchange the function of the "first main electrode region" and the function of the "second main electrode region" in an FET or the like. Furthermore, simply referring to the "main electrode region" in this specification means either the first main electrode region or the second main electrode region comprehensively.

Further, the definitions of directions such as up and down in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. For example, if an object is observed after being rotated by 90°, it will be read with its top and bottom converted to left and right, and if it is observed after being rotated by 180°, it will of course be read with its top and bottom reversed. Further, in the following description, a case where the first conductivity type is the n-type and the second conductivity type is the p-type will be exemplified. However, the conductivity types may be selected in an inverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively high or low impurity densities, respectively, compared to semiconductor regions not marked with "+" and "-". means that However, even if the same "n" is attached to the semiconductor regions, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same. Further, in the following description, the members and regions to which the “first conductivity type” and “second conductivity type” are limited mean the members and regions made of semiconductor materials even if there is no explicit limitation. is technically and logically obvious. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

1, the insulated gate semiconductor device (MISFET) according to the first embodiment includes a plurality of unit cells C1 to C3, . . . each having a plurality of trenches 10a to 10c, . , C4 to C6. In addition, in the insulated gate semiconductor device according to the first embodiment, the number of trenches and the number of unit cells are not particularly limited. By further arranging a plurality of unit cells to form a multi-channel structure, the insulated gate semiconductor device according to the first embodiment can be used as a power semiconductor device (power device) that allows a large current to flow.

In FIG. 1, the planar patterns of the trenches 10a to 10c, . The trenches 10a-10c, . . . , 10d-10f form stripes and extend parallel to each other. , 10d to 10f (parallel direction of the trenches 10a to 10c, . , the unit cell C1 is located at one end of the array structure. Also, the unit cells C4 to C6 are located at the right peripheral portion of the array structure, and the unit cell C6 is located at the other end of the array structure.

FIG. 2 corresponds to a vertical sectional view of the unit cells C1 to C3 in the left peripheral portion shown in FIG. 1 as seen from the AA direction. The insulated gate semiconductor device according to the first embodiment, as shown in FIG. base regions 3a and 3b. The drift layer 1 and the base regions 3a and 3b are respectively composed of epitaxial growth layers made of SiC.

Above the base regions 3a and 3b, n ⁺ -type first main electrode regions (source regions) 4a to 4d having a higher impurity density than the drift layer 1 are selectively provided. Source regions 4a and 4c contact base regions 3a and 3b, respectively. Since the source regions 4b and 4d are not used as current paths, they may be omitted. On drift layer 1, p ⁺ -type gate protection regions 2a and 2b having a higher impurity density than base regions 3a and 3b are selectively provided. The upper surfaces of gate protection regions 2a and 2b are positioned at the same horizontal level as the upper surfaces of source regions 4a-4d. Gate protection region 2a is in contact with source regions 4b and 4c and base region 3b.

Trenches 10a-10c are provided to reach drift layer 1 from the upper surfaces of source regions 4a-4d. Although FIG. 2 illustrates the case where both sidewall surfaces of the trenches 10a to 10c are parallel to the vertical direction, the present invention is not limited to this. For example, both sidewall surfaces of trenches 10a to 10c may be tapered downward. Further, although the case where the bottoms of the trenches 10a to 10c are flat is exemplified, they may be curved, and the corners of the bottoms may have curvature.

One sidewall surface (first sidewall surface described later) of trench 10b contacts source region 4a and base region 3a, and the other sidewall surface (second sidewall surface described later) contacts source region 4b and gate protection region 2b. One side wall surface of trench 10d is in contact with source region 4c and base region 3b, and the other side wall surface is in contact with source region 4d and gate protection region 2b. The bottom surfaces of the trenches 10b and 10d are in contact with the drift layer 1 and the gate protection regions 2a and 2b, respectively, but the bottom surfaces of the trenches 10b and 10d may be entirely covered with the gate protection regions 2a and 2b, respectively. . On the other hand, both side wall surfaces and the bottom surface of the trench 10a are covered with p ⁺ -type operation suppression regions 2x. The operation suppression region 2x is in contact with the source region 4a and the base region 3a. The operation suppression region 2x is provided at the same depth as the gate protection regions 2a and 2b.

Gate insulating films 5a to 5c are provided on the bottom and sidewall surfaces of trenches 10a to 10c. As the gate insulating _films 5a to 5c, in addition to a silicon oxide film ( _SiO.sub.2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride ( _{Si.sub.3N.sub.4} ) film, and an aluminum oxide film are used. (Al ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO ₂ ) film, zirconium oxide (ZrO ₂ ) film, tantalum oxide (Ta ₂ O ₅ ) film or bismuth oxide (Bi ₂ O ₃ ) film, or a composite film obtained by laminating a plurality of these films.

Gate electrodes 6a to 6c are buried inside trenches 10a to 10c via gate insulating films 5a to 5c to form insulated gate electrode structures (5a, 6a), (5b, 6b), (5c, 6c). are doing. As a material for the gate electrodes 6a to 6c, a polysilicon layer (doped polysilicon layer) in which an impurity such as phosphorus (P) is added at a high impurity density can be used.

A first main electrode (source electrode) 8 is arranged on the gate electrodes 6a to 6c with an interlayer insulating film 7 interposed therebetween. As the interlayer insulating film 7, a non-doped silicon oxide film ( _SiO.sub.2 film) called "NSG" which does not contain phosphorus (P) or boron (B) can be used. However, as the interlayer insulating film 7, a phosphorus-added silicon oxide film (PSG), a boron-added silicon oxide film (BSG), a boron- and phosphorus-added silicon oxide film (BPSG), a silicon nitride film (Si ₃ N ₄ ) or the like. The source electrode 8 is electrically connected to the source regions 4a, 4c and the gate protection regions 2a, 2b. The source electrode 8 is arranged separately from the gate surface electrode (not shown) located at the back of the paper.

For example, the source electrode 8 can be composed of an aluminum (Al) film. The same material as the source electrode 8 can be used for the gate surface electrode. Although not shown, under the source electrode 8, a source contact layer and a barrier metal layer serving as a base metal may be arranged. For example, the source contact layer can be composed of a nickel silicide (NiSi _x ) film, and the barrier metal layer can be composed of a titanium nitride (TiN) film.

An n ⁺ -type second main electrode region (drain region) 9 is arranged on the lower surface of the drift layer 1 so as to be in contact with the drift layer 1 . The drain region 9 is composed of a semiconductor substrate (SiC substrate) made of SiC. A second main electrode (drain electrode) 11 is arranged on the lower surface of the drain region 9 . As the drain electrode 11, for example, a single layer film made of gold (Au) or a metal film in which Al, nickel (Ni) and Au are laminated in this order can be used. A metal film such as tungsten (W) or an alloy layer in which nickel (Ni) and titanium (Ti) are deposited and reacted with SiC may be laminated.

On the other hand, FIG. 3 corresponds to a vertical cross-sectional view of the unit cells C4 to C6 located in the right peripheral portion shown in FIG. 1 as seen from the BB direction. As shown in FIG. 3, p-type base regions 3c to 3e are arranged on the n-type drift layer 1. As shown in FIG. N ⁺ -type source regions 4e to 4j are selectively provided above the base regions 3c to 3e. Source regions 4e, 4g and 4h are in contact with base regions 3c-3e, respectively. Since the source regions 4f, 4h, and 4j are not used as current paths, they may be omitted. On the drift layer 1, p ⁺ -type gate protection regions 2c to 2e are selectively provided. The upper surfaces of gate protection regions 2c-2e are positioned at the same horizontal level as the upper surfaces of source regions 4e-4j. Gate protection region 2c is in contact with source region 4g and base region 3d. Gate protection region 2d is in contact with source region 4i and base region 3e.

Trenches 10d-10f are provided to reach drift layer 1 from the upper surfaces of source regions 4e-4j. One side wall surface of trench 10d is in contact with source region 4e and base region 3c, and the other side wall surface is in contact with source region 4f and gate protection region 2c. One side wall surface of trench 10e is in contact with source region 4g and base region 3d, and the other side wall surface is in contact with source region 4h and gate protection region 2d. One side wall surface of trench 10f is in contact with source region 4i and base region 3e, and the other side wall surface is in contact with source region 4j and gate protection region 2e. The bottoms of the trenches 10d to 10f contact the drift layer 1 and the gate protection regions 2c to 2e, respectively, but the bottoms of the trenches 10d to 10f may all be covered with the gate protection regions 2c to 2e, respectively. .

Gate electrodes 6d to 6f are buried inside the trenches 10d to 10f via gate insulating films 5d to 5f to form insulated gate electrode structures (5d, 6d), (5e, 6e), (5f, 6f). are doing. A source electrode 8 is arranged on the gate electrodes 6d to 6f with an interlayer insulating film 7 interposed therebetween. The source electrode 8 is electrically connected to the source regions 4e, 4g, 4h and the gate protection regions 2c-2e. An n ⁺ -type drain region 9 is arranged on the lower surface of the drift layer 1 so as to be in contact with the drift layer 1 . A drain electrode 11 is arranged on the lower surface of the drain region 9 .

Here, with reference to FIGS. 4 to 6, plane orientations used for sidewall surfaces of the trenches 10a to 10c, . . . , 10d to 10f shown in FIGS. 1 to 3 will be described. The chip structure in which the trenches 10a to 10c, . . . , 10d to 10f shown in FIGS. > direction has an off angle θ1 of about 4° to 8°. The off-angle θ1 is an angle formed between a plane (basal plane) perpendicular to the c-axis, which is the (0001) plane (Si plane) or the (000-1) plane (C plane), and the reference plane of the chip structure. A plurality of straight lines L1 indicated by solid lines on the side surface of the chip structure schematically indicates the Si surface. Consider providing the chip structure with a trench T1 and a trench T2 orthogonal to the trench T1. The sidewall surfaces S1 and S2 of the trench T1 use the m-plane, which is the (1-100) plane perpendicular to the (0001) plane. Since the sidewall surfaces S1 and S2 of the trench T1 are actually tapered, both the sidewall surfaces S1 and S2 of the trench T1 are m-planes inclined by about 9° toward the Si surface.

FIG. 5 shows the case where a trench T2 is provided in the chip structure. As shown in FIG. 5, the opposing sidewall surfaces S3 and S4 of the trench T2 both use the (11-20) a-plane. In FIG. 5, dashed lines L2 and L3 parallel to the plane a are schematically shown. In this case, since the semiconductor wafer has an off angle θ1, the inclination angle θ2 of one side wall surface S3 of the trench T2 with respect to the a-plane and the inclination angle θ3 of the other side wall surface S4 with respect to the a-plane are different. For example, when the off angle θ1 is 4°, the sidewall surface S3 of the trench T2 has an inclination angle θ2 of 5° on the Si surface side with respect to the a-plane, and the sidewall surface S4 of the trench T2 has an inclination angle θ2 on the Si surface side with respect to the a-plane. θ4 becomes 13°. FIG. 6 shows the relationship between gate voltage and electron mobility for the m-plane inclined 9° toward the Si surface, the a-plane inclined 5° toward the Si-plane, and the a-plane inclined 13° toward the Si-plane. From FIG. 6, the electron mobility is higher in the order of the a-plane inclined by 5° toward the Si surface, the m-plane inclined by 9° toward the Si-plane, and the a-plane inclined by 13° toward the Si-plane.

In the insulated gate semiconductor device according to the first embodiment, the source regions 4a, 4c, 4e, 4g, and 4i and the base regions 3a to 3e of the trenches 10b to 10c, . . . , 10d to 10f shown in FIGS. As the side wall surface on the side in contact with the Si surface, the a-plane, which has a relatively small inclination angle θ2 toward the Si surface and has high electron mobility, is used as a current path. This a-plane is defined as a "first side wall surface" forming a first inclination angle θ2 with respect to the reference plane (a-plane) of the chip structure.

On the other hand, the side walls of the trenches 10b to 10c, . . . , 10d to 10f shown in FIGS. First, the a-plane having a large tilt angle θ3 and low electron mobility is used on the Si-plane side. This a-plane faces the first side wall surface, forms a second inclination angle θ3 different from the first inclination angle θ2 with respect to the reference plane (a-plane), and has a higher electron mobility than the first sidewall surface. Define a low "second sidewall surface". Thus, both sidewalls of the trenches 10b-10c, .

During operation of the insulated gate semiconductor device according to the first embodiment, a positive voltage is applied to the drain electrode 11 and a positive voltage equal to or higher than the threshold is applied to the gate electrodes 6a to 6f. As a result, in the unit cells C2 to C6 excluding the unit cell C1 located at one end of the arrangement structure of the unit cells C1 to C3, . . . C4 to 6, the inversion layers ( channel) is formed and turned on. In the ON state, current flows from the drain electrode 11 to the source electrode 8 via the drain region 9, the drift layer 1, the inversion layers of the base regions 3a to 3e, and the source regions 4a, 4c, 4e, 4g, and 4i. On the other hand, when the voltage applied to the gate electrodes 6a to 6f is less than the threshold, no inversion layer is formed in the base regions 3a to 3e. On the other hand, in the unit cell C1 located at one end of the arrangement structure of the unit cells C1 to C3, . Therefore, the operation of the unit cell C1 is suppressed during operation of the insulated gate semiconductor device according to the first embodiment.

In the unit cell C1 positioned at the end of the arrangement structure of the unit cells C1 to C3, . In contrast, according to the insulated gate semiconductor device according to the first embodiment, in the unit cell C1 located at the end of the arrangement structure of the unit cells C1 to C3, . The wall surface is covered with a p ⁺ -type motion suppression region 2x. As a result, even if the pattern of the trench 10a is destroyed, the operation of the unit cell C1 is suppressed, so reliability can be improved.

Further, as shown in FIG. 7, in the unit cell C6 located at the other end of the arrangement structure ^of the unit cells C1 to C3, . may be coated with The operation suppression region 2y is in contact with the bottom and side wall surfaces of the trench 10e of the unit cell C5 adjacent to the unit cell C6. The operation suppression region 2y is a semiconductor region common to the gate protection region of the unit cell C5, and functions also as the gate protection region of the unit cell C5. According to the structure shown in FIG. 7, even if the patterns of the trenches 10a and 10f of the unit cells C1 and C6 located at both ends of the arrangement structure of the unit cells C1 to C3, . operation is suppressed, reliability can be improved.

Further, as shown in FIG. 8, in the two unit cells C1 and C2 positioned at the ends of the arrangement structure of the unit ^cells C1 to C3, . may be covered with the motion suppressing region 2x. This suppresses the operation of the unit cells C1 and C2 even when the patterns of the trenches 10a and 10b of the two unit cells C1 and C2 located at the ends of the arrangement structure of the unit cells C1 to C3, . . . C4 to 6 are destroyed. reliability can be improved.

Furthermore, as shown in FIG. 9, in the two unit cells C5 and C6 located at the other end of the arrangement structure of the unit cells C1 to C3 ^{, .} It may be covered with the movement suppression region 2y of the mold. The operation suppression region 2y is in contact with the bottom and side wall surfaces of the trench 10d of the unit cell C4 adjacent to the unit cell C5. The operation suppression region 2y is a semiconductor region common to the gate protection region of the unit cell C4, and functions also as the gate protection region of the unit cell C4. According to the structure shown in FIGS. 8 and 9, the trenches 10a and 10b and the trenches 10a and 10b and the trenches 10a and 10b in the unit cells C1 and C2 and the unit cells C5 and C6 located at both ends of the arrangement structure of the unit cells C1 to C3, . Even if the patterns of 10e and 10f are broken, the operations of the unit cells C1 and C2 and the unit cells C5 and C6 are suppressed, so reliability can be improved.

Note that the trench 10a of one unit cell C0 at one end of the arrangement structure of the unit cells C1 to C3, . . . C4 ^to 6 shown in FIG. ^Even if the arrangement structure of the shown unit cells C1 to C3, . good. Furthermore, the trenches 10a and 10b of the two unit cells C0 at one end of the arrangement structure of the unit cells C1 to C3, . . . C4 ^to 6 shown in FIG. 7 may be combined with a structure in which the trench 10f of one unit cell C6 at the other end is covered with the p ⁺ -type operation suppressing region 2y.

(Second embodiment)
As shown in FIG. 10, the insulated gate semiconductor device according to the second embodiment is provided selectively on a first conductivity type (n-type) drift layer 1 and a second conductivity type (n-type) drift layer 1. p ⁺ -type) base regions 3a and 3b. Above the base regions 3a and 3b, main electrode regions (source regions) 4a to 4d having a higher impurity density than the drift layer 1 and of the first conductivity type are provided. Since 4b and 4d are not used as current paths, they may not be provided.

Trenches 10a and 10b are provided to penetrate source regions 4a-4d. One side wall surface of trench 10a is in contact with source region 4a and base region 3a, and the other side wall surface is in contact with source region 4b. One side wall surface of trench 10b is in contact with source region 4c and base region 3b, and the other side wall surface is in contact with source region 4d.

In the insulated gate semiconductor device according to the second embodiment, the a-plane having relatively high electron mobility is used as the side wall surfaces of the trenches 10a and 10b on the side of the source regions 4a and 4c and the base regions 3a and 3b. On the other hand, the side walls of the trenches 10a and 10b on the side of the source regions 4b and 4d are the a-planes with relatively low electron mobility. That is, the sidewall surfaces of the trenches 10a and 10b on the side of the source regions 4a and 4c and the base regions 3a and 3b are the first sidewall surfaces, and the sidewall surfaces of the trenches 10a and 10b on the side of the source regions 4b and 4d are the second sidewall surfaces. .

Insulated gate electrode structures (5a, 6a), (5b, 6b) comprising gate insulating films 5a, 5b and gate electrodes 6a, 6b are provided inside the trenches 10a, 10b. Gate protection regions 2a to 2c of the second conductivity type (p ⁺ type) having a higher impurity density than base regions 3a and 3b are selectively provided on drift layer 1. FIG. The gate protection region 2a is in contact with the source region 4a and the base region 3a. The gate protection region 2b is in contact with the bottom and sidewall surfaces of the trench 10a and the source region 4b. Gate protection region 2c is in contact with the bottom surface and side wall surfaces of trench 10b, and is in contact with source region 4d.

A first main electrode (source electrode) 8 is arranged on the gate electrodes 6a and 6b with an interlayer insulating film 7 interposed therebetween. The source electrode 8 is in contact with the source regions 4a, 4c and the gate protection regions 2a-2c. An n ⁺ -type second main electrode region (drain region) 9 is arranged on the lower surface of the drift layer 1 so as to be in contact with the drift layer 1 . A second main electrode (drain electrode) 11 is arranged on the lower surface of the drain region 9 .

In the insulated gate semiconductor device according to the second embodiment, a Schottky barrier diode D1 (schematically represented by a circuit symbol in ) is built in. The Schottky barrier diode D1 functions as a freewheeling diode (FWD). In the structure shown in FIG. 10, a Schottky junction of Schottky barrier diode D1 is formed by the upper surface of drift layer 1 and source electrode 8 located at the same horizontal level as the upper surfaces of source regions 4a-4d. Other configurations and basic operations of the insulated gate semiconductor device according to the second embodiment are the same as those of the insulated gate semiconductor device according to the first embodiment, and redundant descriptions will be omitted.

According to the insulated gate semiconductor device according to the second embodiment, by incorporating the Schottky barrier diode D1, an external FWD becomes unnecessary and the number of parts can be reduced.

11 differs from the insulated gate semiconductor device according to the second embodiment shown in FIG. 10 in the configuration of the Schottky barrier diode D2. On the drift layer 1, p ⁺ -type gate protection regions 2a to 2c and a p ⁺ -type base contact region 2f are selectively provided. The source electrode 8 has a protrusion 8a embedded to the same depth as the bottom surfaces of the trenches 10a and 10b so as to be sandwiched between the gate protection region 2b and the base contact region 2f. A Schottky junction is formed by the bottom surface of the convex portion 8a of the source electrode 8 and the drift layer 1 to form a Schottky barrier diode D2.

12 differs from the insulated gate semiconductor device according to the second embodiment shown in FIG. 10 in the configuration of the Schottky barrier diode D3. P ⁺ -type gate protection regions 2 a to 2 c are selectively provided on the drift layer 1 . The source electrode 8 has a protrusion 8a embedded to the same depth as the bottom surfaces of the trenches 10a and 10b so as to be sandwiched between the gate protection region 2b and the base region 3b. A Schottky junction is formed by the side surface of the convex portion 8a of the source electrode 8 and the drift layer 1 to form a Schottky barrier diode D3. According to the modification of the insulated gate semiconductor device according to the second embodiment shown in FIG. 12, the side surface of the projection 8a of the source electrode 8 and the drift layer 1 form a Schottky junction. Therefore, the width W1 of the gate protection region 2b can be reduced while maintaining the area of the Schottky barrier diode D3, and the chip size can be reduced.

13 differs from the insulated gate semiconductor device according to the second embodiment shown in FIG. 10 in the configuration of the Schottky barrier diode D3. On the drift layer 1, p ⁺ -type gate protection regions 2a to 2c and a p ⁺ -type base contact region 2f are selectively provided. The source electrode 8 has a convex portion 8a embedded in the drift layer 1 to the same depth as the bottom surfaces of the trenches 10a and 10b so as to be sandwiched between the drift layer 1 and the base contact region 2f. The bottom surface of the protrusion 8a is in contact with the drift layer 1 and the base contact region 2f. A stepped Schottky junction is formed by the region from the lower surface of the source electrode 8 to the side and bottom surfaces of the projection 8a of the source electrode 8 and the drift layer 1 . According to the modification of the insulated gate semiconductor device according to the second embodiment shown in FIG. 13, the area of the Schottky barrier diode D4 can be increased, and the forward voltage can be reduced.

(Third Embodiment)
As shown in FIG. 14, the insulated gate semiconductor device according to the third embodiment is provided selectively on a first conductivity type (n-type) drift layer 1 and a second conductivity type (n-type) drift layer 1. p-type) base regions 3a and 3b. Above the base regions 3a and 3b, main electrode regions (source regions) 4a to 4c having a higher impurity density than the drift layer 1 and of the first conductivity type (n ⁺ type) are provided. Since the source region 4b is not used as a current path, it may not be provided. A trench 10 extending from the upper surface of the source regions 4a to 4c to the drift layer 1 is provided through the source regions 4a and 4b. One side wall surface of trench 10 is in contact with source region 4a and base region 3a, and the other side wall surface is in contact with source region 4b.

In the insulated gate semiconductor device according to the third embodiment, the side wall surfaces of the trench 10 on the source region 4a and base region 3a sides are the a-planes with relatively high electron mobility. That is, the side wall surfaces of the trench 10 on the source region 4a and base region 3a side are the first side wall surfaces, and the side wall surfaces of the trench 10 on the source region 4b side are the second side wall surfaces.

An insulated gate electrode structure (5, 6) is provided inside the trench 10 . A first main electrode (source electrode) 8 is arranged on the gate electrode 6 with an interlayer insulating film 7 interposed therebetween. Source electrode 8 is in contact with source regions 4a and 4c. An n ⁺ -type second main electrode region (drain region) 9 is arranged on the lower surface of the drift layer 1 so as to be in contact with the drift layer 1 . A second main electrode (drain electrode) 11 is arranged on the lower surface of the drain region 9 .

A gate protection region 2 of the second conductivity type (p ⁺ type) having a higher impurity density than base regions 3a and 3b is selectively provided on drift layer 1 . The gate protection region 2 is a region formed in a self-aligned manner by obliquely ion-implanting p-type impurities into the side wall surfaces and the bottom surface of the trench 10 when manufacturing the insulated gate semiconductor device according to the third embodiment. . The gate protection region 2 has an L-shaped cross-sectional pattern and is in contact with the bottom and sidewall surfaces of the trench 10 .

On the drift layer 1, base contact regions 2h and 2i of the second conductivity type (p ⁺ type) having a higher impurity density than the base regions 3a and 3b are selectively provided. The base contact region 2h is in contact with the source region 4a and the base region 3a. The base contact region 2i is in contact with the source regions 4b and 4c, the base region 3b and the gate protection region 2. As shown in FIG. For example, the impurity density of the gate protection region 2 may be higher than that of the base contact regions 2h and 2i, or may be the same as that of the base contact regions 2h and 2i. Other configurations and basic operations of the insulated gate semiconductor device according to the third embodiment are the same as those of the insulated gate semiconductor device according to the first embodiment, and redundant descriptions will be omitted.

According to the insulated gate semiconductor device according to the third embodiment, by providing the gate protection region 2 so as to be in contact with the bottom surface and side wall surfaces of the trench 10, electric field concentration at the bottom of the trench 10 can be suppressed, and the bottom of the trench 10 can be of the gate insulating film 5 can be protected.

Next, referring to FIGS. 15 to 23, a method for manufacturing an insulated gate semiconductor device according to the third embodiment will be described with a trench gate MISFET as an example. It should be noted that the method for manufacturing a trench gate type MISFET described below is merely an example, and other various manufacturing methods, including modifications, can be implemented within the scope of the scope of the claims. Of course.

First, an n ⁺ -type semiconductor substrate (SiC substrate) doped with an n-type impurity such as nitrogen (N) is prepared. For example, the SiC substrate is a 4H—SiC substrate and has an off angle of 4°. Using this n ⁺ -type SiC substrate as a drain region 9, an n-type drift layer 1 and a p-type base region 3 are epitaxially grown in sequence on the upper surface of the drain region 9, as shown in FIG.

Next, a photoresist film is applied to the upper surface of the base region 3, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, n-type impurity ions such as N are implanted in multiple stages. After removing the ion implantation mask, a new photoresist film is applied onto the base region 3 using the photolithography technique, and the photoresist film is patterned using the photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurity ions such as Al are implanted in multiple stages. After removing the ion implantation mask, heat treatment is performed to activate the implanted n-type impurity ions and p-type impurity ions. As a result, as shown in FIG. 16, p ⁺ -type base contact regions 2h and 2i are selectively formed on drift layer 1 so as to be exposed on the upper surfaces of base regions 3a and 3b. Also, n ⁺ -type source regions 4 and 4c are selectively formed above base regions 3a and 3b.

Next, a photoresist film 31 is applied to the upper surfaces of the source regions 4, 4c and the base contact regions 2h, 2i, and the photoresist film 31 is patterned using photolithography. Part of the source region 4, the base region 3a, the base contact region 2i and the drift layer 1 is selected by dry etching such as reactive ion etching (RIE) using the patterned photoresist film 31 as an etching mask. effectively remove. As a result, trenches 10 are selectively formed to reach the top of drift layer 1, as shown in FIG. One sidewall surface of trench 10 is a first sidewall surface and exposes source region 4a and base region 3a. The other sidewall surface of trench 10 is the second sidewall surface and exposes base contact region 2i. The bottom of trench 10 exposes drift layer 1 and base contact region 2i.

Next, as shown in FIG. 18, using the photoresist film 31 as an ion implantation mask, p-type impurity ions are obliquely implanted into the side wall and bottom of the trench 10 on the side of the base contact region 2i. After removing the photoresist film 31 as an ion implantation mask, heat treatment is performed to activate the implanted p-type impurity ions. As a result, as shown in FIG. 19, gate protection regions 2 having an L-shaped cross-sectional pattern are formed in a self-aligned manner so as to be exposed on the side walls and bottom of trenches 10 .

Next, as shown in FIG. 20, SiO 2 is deposited on the bottom surface and side wall surfaces of the trenches 10 and the top surfaces of the source regions 4a to 4c and the base contact regions 2h and 2i by thermal oxidation, chemical vapor deposition (CVD), or the like. A gate insulating film 5 such as ₂ films is formed. Next, a polysilicon layer (doped polysilicon layer) doped with impurities such as phosphorus (P) at a high impurity density is deposited by CVD or the like so as to fill the trenches 10 . After that, the polysilicon layer and the gate insulating film 5 on the upper surfaces of the source regions 4a to 4c and the base contact regions 2h and 2i are removed by etchback, chemical mechanical polishing (CMP), or the like. As a result, as shown in FIG. 21, gate electrode 6 made of a polysilicon layer is embedded in trench 10 to form an insulated gate type electrode structure (5, 6).

Next, an interlayer insulating film 7 is deposited on the upper surfaces of the insulated gate electrode structures (5, 6) by CVD or the like. Then, by photolithography and dry etching, as shown in FIG. 22, part of the interlayer insulating film 7 is selectively removed. As a result, a source contact hole is opened in interlayer insulating film 7 . Although not shown, a gate contact hole is also formed in the interlayer insulating film 7 so that a portion of the gate surface electrode connected to the gate electrode 6 is exposed at a location different from the source contact hole.

Next, a metal layer such as an Al film is deposited by sputtering or the like. A metal layer such as an Al film is patterned using a photolithographic technique and RIE or the like to form a pattern of a source electrode 8 and a gate surface electrode (not shown) as shown in FIG. As a result, the source electrode 8 and gate surface electrode patterns are separated. Next, as shown in FIG. 14, a drain electrode 11 made of Au or the like is formed on the entire lower surface of the drain region 9 by sputtering, vapor deposition, or the like. Thus, the insulated gate semiconductor device according to the embodiment of the present invention is completed.

According to the method of manufacturing an insulated gate semiconductor device according to the third embodiment, after the trenches 10 are formed, p-type impurity ions are obliquely implanted to form the gate protection regions 2 in contact with the bottom and side wall surfaces of the trenches 10. It can be formed in a self-aligned manner. Therefore, the insulated gate semiconductor device shown in FIG. 14 can be easily realized.

In addition, the modified example of the insulated gate semiconductor device according to the third embodiment shown in FIG. 24 is characterized in that the side surface of the end portion of the gate protection region 2 in contact with the bottom surface of the trench 10 is inclined with respect to the vertical direction. , is different from the insulated gate semiconductor device according to the third embodiment shown in FIG. The edge of gate protection region 2 in contact with the bottom surface of trench 10 is inclined parallel to a straight line connecting position P1 of the upper end of trench 10 and position P2 of the edge of gate protection region 2 in contact with the bottom surface of trench 10 .

As a manufacturing method of the modification of the insulated gate semiconductor device according to the third embodiment shown in FIG. form 10; After that, ions are implanted obliquely into the sidewall and bottom surfaces of the trench 10 so that the region where the edge of the gate protection region 2 is formed does not overlap with the base contact region 2i. As a result, the gate protection region 2 can be formed in a self-aligned manner with the inclined side surfaces of the ends in contact with the bottom surface of the trench 10 .

25, the bottom surface of the gate protection region 2 is shallower than the bottom surface of the base contact region 2i. Different from semiconductor devices. As a manufacturing method of the modification of the insulated gate semiconductor device according to the third embodiment shown in FIG. form 10; After that, by obliquely implanting ions into the side wall surfaces and the bottom surface of the trench 10, the gate protection region 2 can be formed in a self-aligned manner at a position shallower than the bottom surface of the base contact region 2i.

Also, FIG. 26 shows a modification of the insulated gate semiconductor device according to the third embodiment. The insulated gate semiconductor device shown in FIG ^. 26 is different from the insulated gate shown in FIG. It is different from a type semiconductor device. The on-resistance can be reduced by providing the current diffusion layers 12a and 12b. The current diffusion layers 12 a and 12 b can be formed by ion-implanting an n-type impurity such as nitrogen (N) into the drift layer 1 . A current diffusion layer may be provided only on the lower surfaces of the base contact regions 2h and 2i.

(Fourth embodiment)
As shown in FIG. 27, the insulated gate semiconductor device according to the fourth embodiment has an arrangement structure of a plurality of striped unit cells C1 to C4 each having four striped trenches 10a to 10d. The insulated gate semiconductor device according to the fourth embodiment includes a drift layer 1 of a first conductivity type (n-type) and base regions 3a and 3b of a second conductivity type (p-type) arranged on the drift layer 1. Prepare. Above the base regions 3a and 3b, main electrode regions (source regions) 41 and 43 having a higher impurity density than the drift layer 1 and having a first conductivity type (n ⁺ type) are provided.

Trenches 10 a - 10 d are provided to reach drift layer 1 from the upper surfaces of source regions 41 and 43 . The trenches 10a and 10b are in contact with both ends of the source region 41 and the base region 3a, respectively, with the source region 41 and the base region 3a interposed therebetween. The trenches 10c and 10d are in contact with both ends of the source region 43 and the base region 3b, respectively, with the source region 43 and the base region 3b interposed therebetween.

Insulated gate electrode structures (5a, 6a), (5b, 6b), (5c, 6c), (5d, 6d) consisting of gate insulating films 5a to 5d and gate electrodes 6a to 6d are provided inside the trenches 10a to 10d. ) is provided. A first main electrode (source electrode) 8 is arranged on the gate electrodes 6a to 6d with an interlayer insulating film 7 interposed therebetween. An n ⁺ -type second main electrode region (drain region) 9 is arranged on the lower surface of the drift layer 1 so as to be in contact with the drift layer 1 . A second main electrode (drain electrode) 11 is arranged on the lower surface of the drain region 9 .

Gate protection regions 21, 22a and 23 of the second conductivity type (p ⁺ -type) are selectively provided on the drift layer 1 with a higher impurity density than the base regions 3a and 3b. The gate protection region 21 is in contact with the bottom and sidewall surfaces of the trench 10a. The gate protection region 22a is in contact with the bottom surface and side wall surfaces of the trench 10b and the bottom surface and side wall surfaces of the trench 10c. The gate protection region 23 is in contact with the bottom surface and side wall surfaces of the trench 10d.

In the insulated gate semiconductor device according to the fourth embodiment, the a-plane is used as both side wall surfaces of the trenches 10a to 10d. For example, the sidewall surface of the trench 10a on the side of the gate protection region 21, the sidewall surface of the trench 10b on the side of the source region 41 and the base region 3a, the sidewall surface of the trench 10c on the side of the gate protection region 22a, the source region 42 and the base region of the trench 10d. As the sidewall surface on the 3b side, the a-plane having relatively high electron mobility is used as the first sidewall surface. On the other hand, the sidewall surface of the trench 10a on the side of the source region 41 and the base region 3a, the sidewall surface of the trench 10b on the side of the gate protection region 22a, the sidewall surface of the trench 10c on the side of the source region 42 and the base region 3b, and the gate protection region of the trench 10d. As the sidewall surface on the 23 side, the a-plane having relatively low electron mobility is used as the second sidewall surface. Alternatively, the first sidewall surface and the second sidewall surface may be reversed as both side wall surfaces of the trenches 10a to 10d.

In addition, in the insulated gate semiconductor device according to the fourth embodiment, the m-plane, which is the (1-100) plane, may be used as both side wall surfaces of the trenches 10a to 10d. When the m-plane is used, the inclination angles of both side wall surfaces of the trenches 10a to 10d with respect to the reference plane (m-plane) are the same, so the electron mobilities on both side wall surfaces of the trenches 10a to 10d are the same.

In the insulated gate semiconductor device according to the fourth embodiment, common base regions 3a and source regions are provided between trenches 10a and 10b of adjacent unit cells C1 and C2 and between trenches 10c and 10d of adjacent unit cells C3 and C4. The structure in which 41 and 43 are sandwiched and the structure in which common gate protection region 22a is sandwiched between trenches 10b and 10c of adjacent unit cells C2 and C3 are alternately repeated. Other configurations of the insulated gate type semiconductor device according to the fourth embodiment are similar to those of the insulated gate type semiconductor device according to the first embodiment, so redundant description will be omitted.

During operation of the insulated gate semiconductor device according to the fourth embodiment, a positive voltage is applied to the drain electrode 11 and a positive voltage equal to or higher than the threshold is applied to the gate electrodes 6a to 6d. As a result, inversion layers (channels) are formed on both side surfaces of the base regions 3a and 3b to turn on. In the ON state, current flows from the drain electrode 11 to the source electrode 8 via the drain region 9, the drift layer 1, the inversion layers on both side surfaces of the base regions 3a and 3b, and the source regions 41 and 43. FIG. On the other hand, when the voltage applied to the gate electrodes 6a to 6d is less than the threshold, no inversion layer is formed on both side surfaces of the base regions 3a and 3b, so that the state is turned off and current flows from the drain electrode 11 to the source electrode 8. do not have.

FIG. 28 shows a planar layout of the source regions 41 and 43 of FIG. 27 viewed in the AA direction horizontally. FIG. 27 corresponds to a cross-sectional view seen from the BB direction of FIG. As shown in FIG. 28, the planar patterns of the source regions 41 and 43 and the gate electrodes 6a to 6d are striped and extend parallel to each other. The gate protection regions 22a and 22b are intermittently provided at predetermined intervals along the longitudinal direction of the source regions 41 and 43 and the gate electrodes 6a to 6d. Source regions 42a and 42b are provided between the gate protection regions 22a and 22b. The interval W3 between the gate protection regions 22a and 22b is equal to or smaller than (same or narrower than) the interval (JFT width) W2 between the junction field effect transistor (JFET) regions sandwiched between the gate protection regions 21 and 22a shown in FIG. is preferred. FIG. 29 corresponds to a cross-sectional view seen from the CC direction of FIG. As shown in FIG. 29, a base region 3c is provided on the lower surface of the source region 42a.

Here, an insulated gate semiconductor device according to a comparative example will be described. In the insulated gate semiconductor device according to the comparative example, as shown in FIG. 30, gate protection region 22 forms a planar pattern extending along the longitudinal direction of trenches 10a-10d. On the other hand, according to the insulated gate semiconductor device according to the fourth embodiment, by intermittently providing the gate protection regions 22a and 22b, the space between the gate protection regions 22a and 22b can be used as the source regions 42a and 42b. can. Therefore, the channel can be increased and the on-resistance can be reduced.

In the structure shown in FIG. 29, a Schottky barrier diode is configured by the source region 42a and the source electrode 8 in the planar pattern region of the source region 42a without providing the base region 3c on the lower surface of the source region 42a. good too. That is, a Schottky barrier diode can be provided in each region between the gate protection regions 22a and 22b.

Further, as shown in FIG. 31, gate protection regions 21a and 21b sandwiched between trenches 10a and 10b (see FIG. 27) may be provided intermittently along the longitudinal direction of trenches 10a and 10b. . The gate protection regions 21a and 21b are provided alternately with the source regions 41a and 41b. Further, gate protection regions 23a and 23b sandwiched between trenches 10c and 10d (see FIG. 27) may be provided intermittently along the longitudinal direction of trenches 10c and 10d. The gate protection regions 23a, 23b are provided alternately with the source regions 43a, 43b.

Further, as shown in FIG. 31, the arrangement of the gate protection regions 21a and 21b, the arrangement of the gate protection regions 22a and 22b, and the arrangement of the gate protection regions 23a and 23b are aligned in the longitudinal direction of the trenches 10a to 10d (see FIG. 27). may be provided at the same position in the direction orthogonal to the trenches 10a to 10d (parallel direction of the trenches 10a to 10d). The gate protection regions 21a, 22a, 23a and the gate protection regions 21a, 22a, 23a are arranged at the same position in the parallel direction of the trenches 10a to 10d. In addition, the source regions 41a, 42a, 43a and the source regions 41b, 42b, 43b are arranged at the same position in the parallel direction of the trenches 10a to 10d.

Further, as shown in FIG. 32, the arrangement of the gate protection regions 21a and 21b, the arrangement of the gate protection regions 22a and 22b, and the arrangement of the gate protection regions 23a and 23b are shifted in the parallel direction of the trenches 10a to 10d. may The gate protection regions 21a, 22a, 23a and the gate protection regions 21b, 22b, 23b are arranged to be shifted in the parallel direction of the trenches 10a to 10d. In addition, the source regions 41a, 42a, 43a and the source regions 41b, 42b, 43b are arranged to be shifted in the parallel direction of the trenches 10a to 10d.

(Other embodiments)
As described above, the present invention has been described by the first to fourth embodiments, but the statements and drawings forming part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

In the first to fourth embodiments of the present invention, the MISFET having the insulating gate electrode structure in the trench was exemplified. It can be applied to an insulated gate semiconductor device having an insulated gate electrode structure. As ^a trench gate type IGBT, the n ⁺ -type source regions 4a to 4j of the MISFET shown in FIGS ^. A structure in which a collector region of the type is provided may be employed.

In addition, in the embodiments of the present invention, the insulated gate semiconductor device using SiC was exemplified. It can also be applied to an insulated gate semiconductor device using a semiconductor (wide bandgap semiconductor) with a wider bandgap than the above.

Reference Signs List 1: drift layers 2, 2a, 2b, 2c, 2d, 2e, 21, 21a, 21b, 22a, 22b, 23, 23a, 23b: gate protection regions 2g, 2h, 2i: base contact regions 2x, 2y: operation suppression Regions 3, 3a, 3b, 3c, 3d, 3e, . , 43b... source regions 5, 5a, 5b, 5c, 5d, 5e, 5f... gate insulating films 6, 6a, 6b, 6c, 6d, 6e, 6f... gate electrodes 7... interlayer insulating films 8... source electrodes 8a... convex Part 9... Drain regions 10a, 10b, 10c, 10d, 10e, 10f... Trench 11... Drain electrodes 12a, 12b... Current diffusion layer 31... Photoresist film

Claims (5)

forming a second conductivity type base region on the first conductivity type drift layer;
forming a main electrode region of a first conductivity type above the base region with an impurity density higher than that of the drift layer;
a first sidewall surface forming a first inclination angle with respect to a reference surface of the chip structure on which the main electrode region is formed; forming a trench having sidewalls defined by second sidewalls having a second inclination angle to reach the drift layer to expose the main electrode region and the base region on the first sidewalls;
forming a second conductivity type gate protection region in contact with the bottom surface and the second sidewall surface of the trench by obliquely implanting ions into the bottom surface and the second sidewall surface of the trench;
forming an insulated gate electrode structure inside the trench ;
forming a base contact region of a second conductivity type on the drift layer, the base contact region being in contact with the bottom surface and side surfaces of the gate protection region and having a bottom surface deeper than the bottom surface of the gate protection region;
including
An insulated gate, wherein an end portion of the gate protection region in contact with the bottom surface of the trench is located closer to the first side wall surface than an end portion of the base contact region in contact with the bottom surface of the gate protection region. method of manufacturing a semiconductor device. 2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the first side wall surface is a hexagonal a-plane. 3. The method according to claim 1, wherein the first sidewall surface and the second sidewall surface are made of SiC, and the first sidewall surface has a smaller inclination angle toward the Si surface than the second sidewall surface. A method for manufacturing an insulated gate semiconductor device. 4. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein the method is a method for manufacturing an insulated gate semiconductor device using SiC. a first conductivity type drift layer;
a second conductivity type base region provided on the first conductivity type drift layer;
a main electrode region having a higher impurity density than the drift layer and having a first conductivity type provided above the base region;
a first sidewall surface forming a first inclination angle with respect to a reference surface of the chip structure on which the main electrode region is formed; a bottom and second sidewalls of a trench defining both side walls with second sidewalls having a second inclination angle, reaching the drift layer, and contacting the main electrode region and the base region with the first sidewalls; a gate protection region of the second conductivity type in contact with the
an insulated gate electrode structure provided inside the trench;
a second conductivity type base contact region provided on the upper part of the drift layer, in contact with the bottom surface and side surfaces of the gate protection region, and having a bottom surface deeper than the bottom surface of the gate protection region;
with
An insulated gate, wherein an end portion of the gate protection region in contact with the bottom surface of the trench is positioned closer to the first side wall surface than an end portion of the base contact region in contact with the bottom surface of the gate protection region. type semiconductor device.

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