JP2019102557A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which the avalanche withstanding capability is not decreased even when ptype regions are misaligned.SOLUTION: A trench-gate vertical MOSFET comprises an ntype drift layer 2 and a p type base layer 6 which are epitaxially grown. In the ntype drift layer 2, a first ptype base region 3 and a second ptype base region 4 are provided. Each of the first ptype base region 3, the second ptype base region 4 and trenches 18 has a stripe shape; and an angle formed by a depth direction of either one of the first ptype base region 3 or the second ptype base region 4 and a depth direction of the trench 18 is larger than 0° and smaller than 90°.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  Conventionally, in a power semiconductor device, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench structure is manufactured (manufactured) in order to reduce the on-resistance of the device. In a vertical MOSFET, since the trench structure formed perpendicular to the substrate surface can increase the cell density per unit area rather than the planar structure in which the channel is formed parallel to the substrate surface, the unit The current density per area can be increased, which is advantageous in cost.

  However, when the trench structure is formed in the vertical MOSFET, the entire inner wall of the trench is covered with the gate insulating film in order to form the channel in the vertical direction, and the trench bottom portion of the gate insulating film approaches the drain electrode. A high electric field is likely to be applied to the bottom portion of the trench. In particular, a wide band gap semiconductor (a semiconductor having a wider band gap than silicon, for example, silicon carbide (SiC)) produces an ultra-high breakdown voltage element, so the adverse effect on the gate insulating film at the bottom of the trench greatly reduces the reliability. Let

As a method of solving such problems, in a vertical MOSFET having a trench structure having a stripe-shaped flat pattern, a p ⁺ -type base region is provided in a stripe between the trench and the trench in parallel with the trench, and the trench bottom In addition, a technique has been proposed in which p ⁺ -type base regions are provided in stripes in parallel with the trenches (for example, see Patent Document 1 below). Further, a technique has been proposed in which p ⁺ -type base regions are provided in a stripe shape in parallel with the trenches between the trenches (for example, see Patent Document 2 below). In addition, there is a technology in which an electric field relaxation layer deeper than a trench is provided, and a low impurity concentration region and a high concentration region at a deep position are formed (see, for example, Patent Document 3 below).

When the cell pitch is reduced to 4 μm or less, a structure resistant to misalignment can be obtained by making the p ⁺ -type base region orthogonal to the trench. Note that alignment misalignment means that when the p ⁺ -type base region is formed of a plurality of layers, the formation position of the p ⁺ -type base region is shifted in each layer. Below, sectional drawing and a top view of the conventional silicon carbide semiconductor device are shown. FIG. 21 is a cross-sectional view of a portion AA 'of FIG. 23 showing a structure of a conventional silicon carbide semiconductor device. FIG. 22 is a cross-sectional view of a portion BB ′ of FIG. 24 showing a structure of a conventional silicon carbide semiconductor device. FIG. 23 is a top view showing the structure of a conventional silicon carbide semiconductor device. FIG. 24 is another top view showing the structure of a conventional silicon carbide semiconductor device.

The conventional silicon carbide semiconductor device shown in FIGS. 21 to 24 is generally on the front surface (surface on the p-type base layer 6 side) side of a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate). A MOS gate with a trench gate structure is provided. The silicon carbide substrate (semiconductor chip) comprises an n ^-- type drift layer 2 and an n-type region 5 as a current diffusion region on an n ⁺ -type support substrate (hereinafter referred to as n ⁺ -type silicon carbide substrate) 1 made of silicon carbide. Each silicon carbide layer to be the p-type base layer 6 is epitaxially grown in order.

In the n-type region 5, as shown in FIGS. 21 and 22, a first p ⁺ -type base region 3 which partially covers the bottom of the trench 18 and which is orthogonal to the trench 18 is selectively provided. The first p ⁺ -type base region 3 is provided at a depth not reaching the n ⁻ -type drift layer 2. Further, in the n-type region 5, as shown in FIG. 22, the second p ⁺ -type base region 4 is selectively provided between the adjacent trenches 18 (mesa portions). The second p ⁺ -type base region 4 and the first p ⁺ -type base region 3 may be formed simultaneously. The second p ⁺ -type base region 4 is provided in contact with the p-type base layer 6. Reference numerals 7 to 14 denote an n ⁺ -type source region, a p ⁺ -type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a barrier metal, a source electrode and a source electrode pad, respectively. In FIGS. 21 and 22, CP (Cell Pitch) is a cell pitch, which is a distance between the trenches 18 and is, for example, 2 μm. More precisely, the cell pitch is the distance between the left side wall, the right side wall or the center of the adjacent trench 18 (in FIG. 21, CP is indicated by the distance between the left side walls). In addition, x, y and z are, for example, 0.8 μm, 0.3 μm and 0.6 μm, respectively, for the width of the trench 18, the width of the n ⁺ -type source region 7 and the width of the p ⁺ -type contact region 8. In FIG. 21, a plurality of 4 to 16 are continuously provided in parallel between the trenches 18 where the second p ⁺ -type base region 4 is not provided. The structure in which the plurality of inter-trench intervals 18 in FIG. 21 are continuously provided in parallel with one another between the trenches 18 in FIG.

23 and 24 are top views of conventional silicon carbide semiconductor devices. 23 is a top view of a portion CC 'in FIG. 22, and FIG. 24 is a top view of a portion DD' in FIG. As shown in FIGS. 23 and 24, the second p ⁺ -type base region 4 is provided in the surface layer of the first p ⁺ -type base region 3 and is partially provided between the trenches 18. Also, in FIGS. 23 and 24, CP, x, y, z are the same as CP, x, y, z in FIGS. w1, w2, respectively third 1p ⁺ -type base region 3 having a width, a distance between the first and 1p ⁺ -type base region 3, for example, respectively 1.0 .mu.m, 1.0 .mu.m. The distance between the first p ⁺ -type base regions 3 may be referred to as a JFET (Junction FET) width in the following description.

In the vertical MOSFETs configured as shown in FIGS. 21 to 24, the pn junction between the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 and the n-type region 5 is at a deeper position than the trench 18. Therefore, the electric field is concentrated at the boundary between the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 and the n-type region 5, and the electric field concentration at the bottom of the trench 18 can be relaxed. Further, by making the second p ⁺ -type base region 4 orthogonal to the trench, a structure resistant to misalignment can be obtained, and the cell pitch can be 4 μm or less.

JP, 2015-72999, A JP, 2015-192028, A JP, 2016-066780, A

Here, in the orthogonal structure in which the second p ⁺ -type base region 4 is orthogonal to the trench, the characteristics of the vertical MOSFET vary due to the processing accuracy of the first p ⁺ -type base region 3. Therefore, in order to improve the processing accuracy of the first p ⁺ -type base region 3, it is preferable to widen the JFET width w2.

25 to 27 are cross-sectional views showing a state in the middle of manufacturing the conventional silicon carbide semiconductor device. FIG. 28 is a top view showing a state in the middle of the production of the conventional silicon carbide semiconductor device in the case where there is a misalignment. In the silicon carbide semiconductor device, as shown in FIG. 25, n ^- type drift layer 2 is epitaxially grown on the front surface of n ⁺ silicon carbide substrate 1 (not shown), and then lower n type region 5a is epitaxially grown. Let The lower n-type region 5 a is a part of the n-type region 5. Next, the first p ⁺ -type base region 3 is selectively formed on the surface of the lower n-type region 5a by ion implantation of p-type impurities.

Next, as shown in FIG. 26, upper n-type region 5b is epitaxially grown. The upper n-type region 5 b and the lower n-type region 5 a are combined to form an n-type region 5. Next, the second p ⁺ -type base region 4 is selectively formed on the surface of the upper n-type region 5b by ion implantation of p-type impurities. At this time, if there is no misalignment, as shown in FIG. 27A, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are in contact with each other. On the other hand, if there is a misalignment, Figure 27B, as shown in FIG. 28, the 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4 is not in contact, the first 1p ⁺ -type base region 3 floating (floating) It becomes a state.

Since the conventional silicon carbide semiconductor device is produced as described above, the misalignment of the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 is likely to occur when the JFET width w2 is increased. When misalignment occurs, the first p ⁺ -type base region 3 is in a floating state, and the first p ⁺ -type base region 3 can not relieve the electric field concentration at the bottom of the trench 18, and the avalanche resistance decreases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which the avalanche withstand capability does not decrease even if a misalignment occurs between p ⁺ -type regions in order to solve the above-mentioned problems of the prior art.

  In order to solve the problems described above and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A first conductivity type first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the first conductivity type semiconductor substrate. A first semiconductor region of a second conductivity type is selectively provided in the inside of the first semiconductor layer. A second semiconductor region of a second conductivity type is provided selectively in the inside of the first semiconductor layer and in contact with the first semiconductor region. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer to the semiconductor substrate side. A third semiconductor region of a first conductivity type, which has an impurity concentration higher than that of the semiconductor substrate, is selectively provided inside the second semiconductor layer. A trench is provided which penetrates the third semiconductor region and the second semiconductor layer to reach the first semiconductor layer, a bottom surface is in contact with the first semiconductor region, and a sidewall is in contact with the second semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. The first semiconductor region, the second semiconductor region, and the trench have a stripe shape, and an angle between the depth direction of at least one of the first semiconductor region and the second semiconductor region and the depth direction of the trench is , Greater than 0 ° and less than 90 °.

  In the semiconductor device according to the present invention, in the above-described invention, the first angle formed by the depth direction of the first semiconductor region and the depth direction of the trench is larger than 0 ° and smaller than 90 °. Do.

  In the semiconductor device according to the present invention, in the above-described invention, the first angle is an angle which makes the distance between the adjacent first semiconductor regions in the depth direction of the trench smaller than the width of the second semiconductor region. It is characterized by being.

In the semiconductor device according to the present invention, in the above-described invention, when the first angle is θ, the θ is a distance Z between the first semiconductor regions, a width x of the trenches, and a center between adjacent trenches. Of the second semiconductor region,
Z / sin θ- (y-x) / tan θ <w
It is characterized by satisfying.

  The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a second angle formed by the depth direction of the second semiconductor region and the depth direction of the trench is larger than 0 ° and smaller than 90 °. Do.

  Further, in the semiconductor device according to the present invention, in the above-mentioned invention, the second angle is an angle which makes the length of the second semiconductor region projected in the depth direction of the trench larger than the distance between the first semiconductor regions. It is characterized by being.

Further, in the semiconductor device according to the present invention, in the above-described invention, when the second angle is θ, the θ is a distance Z between the first semiconductor regions, a width x of the trenches, and a center between adjacent trenches. Of the second semiconductor region,
Z <w / sin θ + (y−x) / tan θ
It is characterized by satisfying.

  In the semiconductor device according to the present invention, in the above-described invention, a first angle formed by a depth direction of the first semiconductor region and a depth direction of the trench, a depth direction of the second semiconductor region, and a depth direction of the trench It is characterized in that the second angle formed by is larger than 0 ° and smaller than 90 °.

  Further, in the semiconductor device according to the present invention, in the above-described invention, the first angle and the second angle project the distance of the first semiconductor region in the depth direction of the trench in the depth direction of the trench The angle may be smaller than the length of the second semiconductor region.

In the semiconductor device according to the present invention, in the above-described invention, when the first angle is θ and the second angle is 90 ° -θ, the θ is a distance Z between the first semiconductor regions, and the trench With respect to the width x, the distance y between the centers of the adjacent trenches, and the width w of the second semiconductor region,
Z / sin θ− (y−x) / tan θ <w / cos θ + (y−x) tan θ
It is characterized by satisfying.

According to the invention described above, the trench and the first p ⁺ -type base region (the first semiconductor region of the second conductivity type) have a stripe shape, and the first p ⁺ -type base region intersects with the trench. Thereby, the distance between the adjacent first p ⁺ -type base regions in the depth direction of the trench can be narrowed, and the first p ⁺ -type base region and the second p ⁺ -type base region (second semiconductor type second semiconductor region) Even if misalignment occurs, the first p ⁺ -type base region can be in contact with the second p ⁺ -type base region.

Further, the angle formed between the depth direction of the depth direction and the 1p ⁺ -type base region of the trench, the distance of the 1p ⁺ -type base region is smaller than the width of the 2p ⁺ -type base region adjacent at depth direction of the trench To set. Accordingly, even if misalignment occurs in the first 1p ⁺ -type base region and the 2p ⁺ -type base region, it can as a first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always. Therefore, even if a wide JFET width, since the first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always without first 1p ⁺ -type base region in a floating state, the 1p ⁺ -type base region Can reduce the electric field concentration at the bottom of the trench, so the avalanche resistance does not decrease.

According to the semiconductor device of the present invention, even if misalignment occurs between the p ⁺ -type regions, the avalanche tolerance is not lowered.

FIG. 1 is a top view showing a structure of a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of the A-A ′ portion of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 7 is a top view for explaining the conditions under which the first p ⁺ -type base region and the second p ⁺ -type base region are in contact in the silicon carbide semiconductor device according to the first embodiment. In Embodiment 1, it is a graph which shows the relationship between the angle which a 1st p ^<+> type | mold base region and a trench make, and JFET width. 6 is a graph of FIG. 4 in the case of a cell pitch of 2.0 μm in the first embodiment. FIG. 17 is a top view showing the structure of the silicon carbide semiconductor device of A when the conditions are not satisfied in the first embodiment. FIG. 16 is a top view showing a structure of a silicon carbide semiconductor device of B when conditions are satisfied in the first embodiment. FIG. 7 is a cross-sectional view showing the state in the middle of the production of the silicon carbide semiconductor device according to the first embodiment (part 1). FIG. 16 is a cross-sectional view showing the state in the middle of the production of the silicon carbide semiconductor device according to the first embodiment (part 2). FIG. 16 is a cross-sectional view showing the state in the middle of the production of the silicon carbide semiconductor device according to the first embodiment (part 3). FIG. 16 is a cross-sectional view showing the state in the middle of the production of the silicon carbide semiconductor device according to the first embodiment (No. 4). FIG. 16 is a top view showing a structure of a silicon carbide semiconductor device according to a second embodiment. In Embodiment 2, it is a graph which shows the relationship between the angle which a 2nd p ^<+> type | mold base region and a trench make, and JFET width. FIG. 14 is a graph of FIG. 13 in the case of a cell pitch of 2.0 μm and an angle of 45 ° in the second embodiment. FIG. 21 is a top view showing the structure of the silicon carbide semiconductor device of A when the conditions are not satisfied in the second embodiment. FIG. 21 is a top view showing a structure of a silicon carbide semiconductor device of B in the case where the conditions are satisfied in the second embodiment. FIG. 16 is a top view showing a structure of a silicon carbide semiconductor device according to a third embodiment. FIG. 18 is a cross-sectional view of the A-A ′ portion of FIG. 17 showing the structure of the silicon carbide semiconductor device according to the third embodiment. FIG. 16 is a top view for explaining the conditions under which the first p ⁺ -type base region and the second p ⁺ -type base region are in contact in the silicon carbide semiconductor device according to the third embodiment. In Embodiment 3, it is a graph which shows the relationship between the angle which a 1st p ^<+> type | mold base region and a trench make, and JFET width. FIG. 24 is a cross-sectional view of a portion A-A ′ of FIG. 23 showing a structure of a conventional silicon carbide semiconductor device. FIG. 24 is a cross-sectional view of a B-B ′ portion of FIG. 23 showing a structure of a conventional silicon carbide semiconductor device. It is a top view which shows the structure of the conventional silicon carbide semiconductor device. FIG. 18 is another top view showing the structure of a conventional silicon carbide semiconductor device. It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device (the 1). It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device (the 2). It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device (the 3: alignment gap absence). It is sectional drawing which shows the state in the middle of manufacture of the conventional silicon carbide semiconductor device (the 3: alignment gap presence). FIG. 16 is a top view showing a state in the middle of manufacturing of the conventional silicon carbide semiconductor device in the case where there is misalignment.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and redundant description will be omitted.

Embodiment 1
The semiconductor device according to the present invention is configured using a semiconductor having a wider band gap than silicon (hereinafter, referred to as a wide band gap semiconductor). Here, the structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described as an example.

  FIG. 1 is a top view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view of the A-A ′ portion of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. The cross sectional view of the silicon carbide semiconductor device showing the trench structure and the like is omitted because it is the same as the cross sectional view (see FIGS. 21 and 22) of the conventional silicon carbide semiconductor device. Therefore, in the following description, reference numerals which are not shown in FIGS. 1 and 2 are described, but the configuration indicated by these reference numerals corresponds to the configuration of reference numerals given in FIG. 21 and FIG.

  The silicon carbide semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is on the front surface (surface on the p-type base layer 6 side) side of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide. It is a MOSFET provided with a MOS gate.

The silicon carbide substrate comprises an n ^-- type drift layer (first semiconductor layer of a first conductivity type) 2 and a p-type base layer (a first semiconductor layer of a first conductivity type) on an n ⁺ -type support substrate (semiconductor substrate of the first conductivity type) Each silicon carbide layer to be the second semiconductor layer 6 of the two conductivity type is epitaxially grown in order. The MOS gate is composed of p-type base layer 6, n ⁺ -type source region (third semiconductor region of the first conductivity type) 7, p ⁺ -type contact region 8, trench 18, gate insulating film 9 and gate electrode 10. Ru. Specifically, on the surface layer on the source side (the source electrode 13 side) of n ⁻ type drift layer 2, an n type region (first semiconductor type second semiconductor layer) 5 in contact with p type base layer 6 Is provided. The n-type region 5 is a so-called current spreading layer (CSL) which reduces carrier spreading resistance.

In the n-type region 5, a first p ⁺ -type base region (a first semiconductor region of a second conductivity type) 3 and a second p ⁺ -type base region (a second semiconductor region of a second conductivity type) 4 are selectively It is provided. As shown in FIG. 1, the trench 18, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 have a stripe shape. The first p ⁺ -type base region 3 partially covers the bottom of the trench 18 (see FIG. 21) and intersects with the trench 18. The first p ⁺ -type base region 3 is provided at a depth not reaching the n ⁺ -type silicon carbide substrate 1.

The second p ⁺ -type base region 4 is selectively provided between the adjacent trenches 18 (mesa portion) as in the conventional example. Second p ⁺ -type base region 4 is in contact with the sidewall of trench 18, and the lower surface (the surface in the direction of n ⁺ -type silicon carbide substrate 1) is in contact with first p ⁺ -type base region 3. By providing the first 1p ⁺ -type base region 3, it is possible to form a pn junction between the vicinity of the bottom surface of the trench 18, the first 1p ⁺ -type base region 3 and the n-type region 5. The first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 have a higher impurity concentration than the p-type base layer 6.

Here, that the first p ⁺ -type base region 3 intersects with the trench 18 means that the depth direction of the trench 18 (first direction in FIG. 1) and the depth direction of the first p ⁺ -type base region 3 (second in FIG. 1). The angle θ formed by the directions is larger than 0 ° and smaller than 90 °. As described above, by forming the first p ⁺ -type base region 3 obliquely to the trench 18, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 can be narrowed. . Therefore, even if misalignment occurs in the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4 may be in contact with the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4.

In the example of FIG. 1, the angle θ between the depth direction of the trench 18 and the depth direction of the first p ⁺ -type base region 3 is 45 °. Further, in FIG. 1, the cell pitch y is 2.0 μm, the trench width x is 0.8 μm, the width w1 of the second p ⁺ -type base region 4 is 1.0 μm, and the distance Z of the first p ⁺ -type base region 3 is 1.0 μm In the case of When the distance Z between the first p ⁺ -type base regions 3 is 1.0 μm, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is 0.2 μm. The calculation of the distance X will be described later. In FIG. 1, the distance X (0.2 μm) between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is smaller than the width w1 (1.0 μm) of the second p ⁺ -type base region 4. For this reason, as shown in FIGS. 1 and 2, even if misalignment occurs between the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4, the first p ⁺ -type base region 3 and the second p ⁺ -type base It can be in contact with the region 4.

In Figure 1, a case where the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4 is in contact, depending on the conditions, the first 1p ⁺ -type base region 3 a 2p ⁺ -type base region 4 Togase' There is also no case. Although not shown, in the case of FIG. 1, when the cell pitch y is 1.2 μm, the distance X between adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is 1.1 μm, and the second p ⁺ -type base It becomes larger than the width w1 of the area 4. In this case, if misalignment occurs, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 may not be in contact with each other.

Hereinafter, conditions for the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 to be in contact with each other will be described in detail. FIG. 3 is a top view for explaining the condition under which the first p ⁺ -type base region and the second p ⁺ -type base region are in contact in the silicon carbide semiconductor device according to the first embodiment. From FIG. 3, if the distance X between the first p ⁺ -type base region 3 in the depth direction of the trench 18 is equal to or more than the width w1 of the second p ⁺ -type base region 4, the first p ⁺ -type base region 3 and the second p ⁺ In some cases, the mold base region 4 does not contact (for example, see FIG. 6). Therefore, if the distance X between the first p ⁺ -type base region 3 in the depth direction of the trench 18 is smaller than the width w 1 of the second p ⁺ -type base region 4, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 I am in touch with you. That is, it is sufficient if X <w1.

Further, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is from the length Y1 of the first p ⁺ -type base region 3 projected in the depth direction of the trench 18 in the depth direction of the trench 18 The length Y2 of the side surface M of the projected first p ⁺ -type base region 3 is subtracted. That is, X = Y1-Y2. Assuming that the JFET width is Z, the length Y1 of the first p ⁺ -type base region 3 projected in the depth direction of the trench 18 is Y1 = Z / sin θ. The length Y2 of the side surface M of the first p ⁺ -type base region 3 projected in the depth direction of the trench 18 is (yx) / tan θ, where x is the width of the trench 18 and y is the cell pitch. As a result,
Z / sin θ− (y−x) / tan θ <w1 (1)
As a result, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 always come in contact with each other.

FIG. 4 is a graph showing the relationship between the angle formed by the first p ⁺ -type base region and the trench and the JFET width in the first embodiment. In FIG. 4, and 1.0 .mu.m width x of the trench 18, the width w1 of the 2p ⁺ -type base region 4 1.0 .mu.m, the distance X of the 2p ⁺ -type base region 4 to 1.0 .mu.m, 1 cell pitch y. The result made into 0 micrometer-5.0 micrometers is shown.

In FIG. 4, in the lower side of each curve (the side where the JFET width is small), the above equation (1) is satisfied, and the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are in contact It will be. Conventionally, θ = 90 °. In this case, not only the size of cell pitch y but JFET width Z is fixed at 1.0 μm, but in the first embodiment, 0 ° <θ <90. Since it is °, the JFET width Z can be expanded according to the size of the cell pitch y.

Here, FIG. 5 is a graph of FIG. 4 in the case of the cell pitch of 2.0 μm in the first embodiment. In FIG. 5, point A is a point not satisfying the above equation (1) (θ = 45 °, JFET width Z = 1.80 μm), and point B satisfies the above equation (1) The point is (θ = 45 °, JFET width Z = 1.40 μm). FIG. 6 is a top view showing the structure of the silicon carbide semiconductor device of A when the conditions are not satisfied in the first embodiment. As shown in FIG. 6, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is 1.34 μm, which is larger than 1.0 μm of the width w1 of the second p ⁺ -type base regions 4. Therefore, when the formation position of the second p ⁺ -type base region 4 is shifted, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 do not come in contact with each other. In the example of FIG. 6, in the three second p ⁺ -type base regions 4, the middle second p ⁺ -type base region 4 is not in contact with the first p ⁺ -type base region 3.

On the other hand, FIG. 7 is a top view showing the structure of the silicon carbide semiconductor device of B when the conditions are satisfied in the first embodiment. As shown in FIG. 7, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is 0.77 μm, which is smaller than 1.0 μm of the width w1 of the second p ⁺ -type base regions 4. Therefore, even if the formation position of the second p ⁺ -type base region 4 is shifted, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are always in contact with each other. In the example of FIG. 7, all three second p ⁺ -type base regions 4 are in contact with the first p ⁺ -type base region 3.

In the inside of the p-type base layer 6, an n ⁺ -type source region 7 and a p ⁺ -type contact region 8 are selectively provided so as to be in contact with each other. The depth of the p ⁺ -type contact region 8 may be, for example, the same as or deeper than that of the n ⁺ -type source region 7.

Trench 18 penetrates n ⁺ -type source region 7 and p-type base layer 6 from the front surface of the substrate to reach n-type region 5. Inside the trench 18, a gate insulating film 9 is provided along the sidewall of the trench 18, and a gate electrode 10 is provided inside the gate insulating film 9. The source side end of the gate electrode 10 may or may not protrude outward from the front surface of the substrate. The gate electrode 10 is electrically connected to a gate pad (not shown) at a portion not shown. The interlayer insulating film 11 is provided on the entire front surface of the base so as to cover the gate electrode 10 embedded in the trench 18.

Source electrode 13 is in contact with n ⁺ -type source region 7 and p ⁺ -type contact region 8 via a contact hole opened in interlayer insulating film 11 and is electrically insulated from gate electrode 10 by interlayer insulating film 11. There is. For example, a barrier metal 12 may be provided between the source electrode 13 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side. A source electrode pad 14 is provided on the source electrode 13. A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate (the back surface of the n ⁺ -type silicon carbide substrate 1 to be the n ⁺ -type drain region).

(Method of Manufacturing Semiconductor Device According to First Embodiment)
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 8 to 11 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. First, a n ⁺ -type silicon carbide substrate 1 made of an n ⁺ -type drain region. Next, the aforementioned n ⁻ -type drift layer 2 is epitaxially grown on the front surface of the n ⁺ -type silicon carbide substrate 1. The state up to here is described in FIG.

Next, the lower n-type region 5 a is epitaxially grown on the n ⁻ -type drift layer 2. The lower n-type region 5 a may be formed in the surface layer of the n ⁻ -type drift layer 2 by ion implantation of an n-type impurity. The lower n-type region 5 a is a part of the n-type region 5. Next, a stripe-like first p ⁺ -type base region 3 is formed by photolithography and ion implantation of p-type impurities. The first p ⁺ -type base region 3 is formed to cross the trench 18 to be formed later. The state up to here is described in FIG.

Next, the upper n-type region 5 b is epitaxially grown on the lower n-type region 5 a. The upper n-type region 5b is, n ^- -type region is epitaxially grown, by ion implantation of n-type impurity, n ^- may be formed on the surface layer of the mold region. The upper n-type region 5 b and the lower n-type region 5 a are combined to form an n-type region 5. Next, a stripe-like second p ⁺ -type base region 4 is formed by photolithography and ion implantation of p-type impurities. The state up to here is described in FIG.

Next, the p-type base layer 6 is epitaxially grown on the upper n-type region 5 b and the second p ⁺ -type base region 4. The state up to here is described in FIG. Next, the n ⁺ -type source region 7 is selectively formed in the surface layer of the p-type base layer 6 by photolithography and ion implantation of n-type impurities.

Next, the p ⁺ -type contact region 8 is selectively formed in the surface layer of the p-type base layer 6 so as to be in contact with the n ⁺ -type source region 7 by photolithography and ion implantation of p-type impurities. The formation order of the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 may be switched. After all ion implantation has been completed, activation annealing is performed.

Next, a stripe-shaped trench 18 is formed through the n ⁺ -type source region 7 and the p-type base layer 6 to reach the n-type region 5 by photolithography and etching. In addition, an oxide film is used as a mask at the time of trench formation. After the trench etching, isotropic etching may be performed to remove damage to the trench 18 or hydrogen annealing may be performed to round the corners of the bottom of the trench 18 and the opening of the trench 18. Only one of isotropic etching and hydrogen annealing may be performed. Alternatively, hydrogen annealing may be performed after isotropic etching.

  Next, gate insulating film 9 is formed along the front surface of the silicon carbide substrate and the inner wall of trench 18. Next, polysilicon is deposited and etched, for example, so as to be embedded in the trench 18, so that polysilicon serving as the gate electrode 10 is left inside the trench 18. At this time, etching back may be performed to leave polysilicon on the inner side of the front surface of the substrate, or the polysilicon may be projected outside of the front surface of the substrate by patterning and etching.

Next, interlayer insulating film 11 is formed on the entire front surface of the silicon carbide base so as to cover gate electrode 10. The interlayer insulating film 11 is formed of, for example, NSG (None-doped Silicate Glass: non-doped silicate glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Ru. Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned to form a contact hole, and the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 are exposed.

Next, a barrier metal 12 is formed to cover the interlayer insulating film 11 and patterned to expose the n ⁺ -type source region 7 and the p ⁺ -type contact region 8 again. Next, the source electrode 13 is formed in contact with the n ⁺ -type source region 7. The source electrode 13 may be formed to cover the barrier metal or may be left only in the contact hole.

Next, the source electrode pad 14 is formed to fill the contact hole. A portion of the metal layer deposited to form the source electrode pad 14 may be used as a gate pad. On the back surface of the n ⁺ -type silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the drain electrode using sputtering deposition or the like. The metal film may be stacked by combining a plurality of Ni films and Ti films. Thereafter, annealing such as rapid thermal annealing (RTA) is performed so that the metal film is silicided to form an ohmic contact. Thereafter, a thick film such as a laminated film in which, for example, a Ti film, an Ni film, and gold (Au) are sequentially laminated is formed by electron beam (EB: Electron Beam) evaporation or the like to form a drain electrode.

  In the above-described epitaxial growth and ion implantation, as n-type impurities (n-type dopants), for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. that become n-type with respect to silicon carbide Should be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl) or the like which becomes p-type with respect to silicon carbide may be used. . Thus, the MOSFETs shown in FIGS. 1 and 2 are completed.

As described above, according to the first embodiment, the trench and the first p ⁺ -type base region have a stripe shape, and the first p ⁺ -type base region is oblique to the trench. Thereby, the distance between the adjacent first p ⁺ -type base regions in the depth direction of the trench can be narrowed, and even if misalignment occurs between the first p ⁺ -type base regions and the second p ⁺ -type base regions, the first p ^{The +} type base region can be in contact with the second p ⁺ type base region.

Further, the angle formed between the depth direction of the depth direction and the 1p ⁺ -type base region of the trench, the distance of the 1p ⁺ -type base region is smaller than the width of the 2p ⁺ -type base region adjacent at depth direction of the trench To set. Accordingly, even if misalignment occurs in the first 1p ⁺ -type base region and the 2p ⁺ -type base region, it can as a first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always. Therefore, even if a wide JFET width, since the first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always without first 1p ⁺ -type base region in a floating state, the 1p ⁺ -type base region Can reduce the electric field concentration at the bottom of the trench, so the avalanche resistance does not decrease.

Second Embodiment
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 12 is a top view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the first p ⁺ -type base region 3 and the trench 18 are orthogonal to each other, and the second p ⁺ -type base region 4 and the trench 18 Is diagonally crossing.

Here, that the second p ⁺ -type base region 4 intersects with the trench 18 means that the depth direction of the trench 18 (first direction in FIG. 12) and the depth direction of the second p ⁺ -type base region 4 (second in FIG. 12). The angle θ with the direction is larger than 0 ° and smaller than 90 °. As described above, in the second embodiment, the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 can be obtained by forming the second p ⁺ -type base region 4 and the trench 18 obliquely. Even if the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are misaligned, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 can be in contact with each other. it can.

Hereinafter, conditions for the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 to be in contact with each other will be described in detail. Than 12, if the length W of the 2p ⁺ -type base region 4 which is projected in the depth direction of the trench 18, is below the 1p ⁺ -type base region 3 intervals Z, the first 1p ⁺ -type base region 3 The second p ⁺ -type base region 4 may not be in contact (for example, see FIG. 15). Therefore, the 2p ⁺ -type base region 4 of length W is, the distance Z is larger than the first 1p ⁺ -type base region 3 of the 1p ⁺ -type base region 3 a 2p ⁺ -type base obtained by projecting in the depth direction of the trench 18 It is in contact with area 4 without fail. That is, it is sufficient if Z <W.

Here, the length W of the 2p ⁺ -type base region 4 which is projected in the depth direction of the trench 18 is projected in the depth direction of the 2p ⁺ -type base region 4 of the width Y1 and the trench 18 which is projected in the depth direction of the trench 18 And the length Y2 of the side surface M of the second p ⁺ -type base region 4. That is, W = Y1 + Y2. Width Y1 of the 2p ⁺ -type base region 4 which is projected in the depth direction of the trench 18, when the width of the 2p ⁺ -type base region 4 and w1, a Y1 = w1 / sin [theta. The length Y2 of the side surface M of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 is (yx) / tan θ, where x is the width of the trench 18 and y is the cell pitch. As a result,
Z <w1 / sin θ + (y−x) / tan θ (2)
As a result, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 always come in contact with each other.

FIG. 13 is a graph showing the relationship between the angle formed by the second p ⁺ -type base region and the trench and the JFET width in the second embodiment. In Figure 13, 1.0 .mu.m width x of the trench 18, with the width w1 of the 2p ⁺ -type base region 4 1.0 .mu.m, the distance X of the 2p ⁺ -type base region 4 to 1.0 .mu.m, the cell pitch y 1 It shows the results of .0 μm to 5.0 μm.

In FIG. 13, in the lower side of each curve (the side where the JFET width is small), the above equation (2) is satisfied, and the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are in contact with each other. become. Conventionally, θ = 90 °, and in this case, the JFET width is fixed at 1.0 μm, not limited to the size of cell pitch y, but in the first embodiment, 0 ° <θ <90 °. Therefore, the JFET width Z can be expanded according to the size of the cell pitch y.

Here, FIG. 14 is a graph of FIG. 13 in the case of a cell pitch of 2.0 μm and an angle of 45 ° in the second embodiment. In FIG. 14, point A is a point not satisfying the above equation (2) (θ = 45 °, JFET width Z = 4.00 μm), and point B satisfies the above equation (2). The point is (θ = 45 °, JFET width Z = 2.00 μm). FIG. 15 is a top view showing the structure of the silicon carbide semiconductor device of A when the conditions are not satisfied in the second embodiment. As shown in FIG. 15, the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 is 2.61 μm, which is smaller than the JFET width 4.0 μm. Therefore, when the formation position of the second p ⁺ -type base region 4 is shifted, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 do not come in contact with each other. In the example of FIG. 15, in the three second p ⁺ -type base regions 4, the middle second p ⁺ -type base region 4 is not in contact with the first p ⁺ -type base region 3.

On the other hand, FIG. 16 is a top view showing the structure of the silicon carbide semiconductor device of B when the conditions are satisfied in the second embodiment. As shown in FIG. 16, the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 is 2.61 μm, which is larger than the JFET width 2.0 μm. Therefore, even if the formation position of the second p ⁺ -type base region 4 is shifted, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are always in contact with each other. In the example of FIG. 16, all of the three second p ⁺ -type base regions 4 are in contact with the second p ⁺ -type base region 4.

The method of manufacturing the semiconductor device according to the second embodiment is the same as that of the first embodiment except that the second p ⁺ -type base region 4 is formed to be oblique to the trench 18. I omit it.

As described above, according to the second embodiment, the trench and the second p ⁺ -type base region have a stripe shape, and the second p ⁺ -type base region is oblique to the trench. As a result, the length of the second p ⁺ -type base region projected in the depth direction of the trench can be increased, and even if there is misalignment between the first p ⁺ -type base region and the second p ⁺ -type base region, the first p ^{The +} type base region can be in contact with the second p ⁺ type base region.

Further, the angle formed between the depth direction of the depth direction and the 2p ⁺ -type base region of the trench, the length of the 2p ⁺ -type base region is greater than the distance of the 1p ⁺ -type base region obtained by projecting in the depth direction of the trench To set. Accordingly, even if misalignment occurs in the first 1p ⁺ -type base region and the 2p ⁺ -type base region, it can as a first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always. Therefore, even if a wide JFET width, since the first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always without first 1p ⁺ -type base region in a floating state, the 1p ⁺ -type base region Can reduce the electric field concentration at the bottom of the trench, so the avalanche resistance does not decrease.

Third Embodiment
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 17 is a top view showing the structure of the silicon carbide semiconductor device according to the third embodiment. 18 is a cross-sectional view taken along the line AA 'of FIG. 17 showing the structure of the silicon carbide semiconductor device according to the third embodiment. The difference between the silicon carbide semiconductor device according to the third embodiment and the silicon carbide semiconductor device according to the first embodiment is that the first p ⁺ -type base region 3 and the trench 18 cross each other, and the second p ⁺ -type base region 4 The trenches 18 are diagonally crossed.

As described above, the first p ⁺ -type base region 3 is configured to obliquely intersect with the trench 18 so that the adjacent first p ⁺ -type base region 3 in the depth direction of the trench 18 (the first direction in FIG. The distance X can be narrowed. Further, by forming the second p ⁺ -type base region 4 and the trench 18 obliquely, the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 can be increased. Therefore, even if misalignment occurs in the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4 may be in contact with the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4.

In the example of FIG. 17, the angle between the depth direction of the trench 18 and the depth direction of the first p ⁺ -type base region 3 (the second direction in FIG. 17) is θ, and the depth direction of the trench 18 and the second p ⁺ -type base region 4 It is an example in the case of 90 degree- (theta) of the angle which a depth direction (3rd direction of FIG. 17) makes. Thus, in the example of FIG. 17, the depth direction of the first p ⁺ -type base region 3 and the depth direction of the second p ⁺ -type base region 4 are orthogonal to each other. FIG. 17 is an example in the case of θ = 45 °.

Further, in FIG. 17, the cell pitch y is 2.0 μm, the trench width x is 0.8 μm, the width w1 of the second p ⁺ -type base region 4 is 1.0 μm, and the distance Z of the first p ⁺ -type base region 3 is 1.0 μm In the case of When the distance Z between the first p ⁺ -type base regions 3 is 1.0 μm, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is 1.01 μm. When the width w1 of the second p ⁺ -type base region 4 is 1.0 μm, the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 is 1.81 μm. In the example of FIG. 17, the distance W (1.01 μm) of the adjacent first p ⁺ -type base region 3 in the depth direction of the trench 18 projects the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 Less than (1.81 μm). Therefore, as shown in FIGS. 17 and 18, even if misalignment occurs between the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4, the first p ⁺ -type base region 3 and the second p ⁺ -type base It can be in contact with the region 4.

In Figure 17, shows the case where the first 1p ⁺ -type base region 3 and the 2p ⁺ -type base region 4 is in contact, depending on the conditions, the first 1p ⁺ -type base region 3 a 2p ⁺ -type base region 4 Togase' There is also no case.

Hereinafter, conditions for the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 to be in contact with each other will be described in detail. FIG. 19 is a top view illustrating the conditions under which the first p ⁺ -type base region and the second p ⁺ -type base region are in contact in the silicon carbide semiconductor device according to the third embodiment. As shown in FIG. 19, if the distance X between the first p ⁺ -type base regions 3 in the depth direction of the trench 18 is equal to or greater than the length W of the second p ⁺ -type base regions 4 projected in the depth direction of the trench 18, the first p ^In some cases, the ⁺ type base region 3 and the second p ⁺ type base region 4 are not in contact with each other. Therefore, if the distance X between the first p ⁺ -type base regions 3 in the depth direction of the trench 18 is smaller than the length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are always in contact with each other. That is, it is sufficient if X <W.

Further, the distance X between the adjacent first p ⁺ -type base regions 3 in the depth direction of the trench 18 is Z / sin θ− (y−x) / tan θ similarly to the first embodiment. The length W of the second p ⁺ -type base region 4 projected in the depth direction of the trench 18 is w1 / sin (90 ° −θ) + (y−x) / tan (90 °) in the same manner as in the first embodiment. −θ) = w1 / cos θ + (y−x) tan θ. Here, the JFET width is Z, the width of the second p ⁺ -type base region 4 is w1, the width of the trench 18 is x, and the cell pitch is y. As a result,
Z / sin θ− (y−x) / tan θ <w1 / cos θ + (y−x) tan θ (3)
As a result, the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 always come in contact with each other.

FIG. 20 is a graph showing the relationship between the angle formed by the first p ⁺ -type base region and the trench and the JFET width in the third embodiment. In Figure 20, the width x of the trench 18 1.0 .mu.m, the width w1 of the 2p ⁺ -type base region 4 1.0 .mu.m, the distance X of the 2p ⁺ -type base region 4 to 1.0 .mu.m, 1 cell pitch y. The result made into 0 micrometer-2.0 micrometers is shown.

In FIG. 20, in the lower side of each curve (the side where the JFET width is small), the above equation (3) is satisfied, and the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 always contact It will be. Conventionally, θ = 90 °. In this case, JFET width Z is fixed at 1.0 μm, not limited to the size of cell pitch y. However, in the third embodiment, 0 ° <θ <90. Since it is °, the JFET width Z can be expanded according to the size of the cell pitch y.

Further, in the above example, a depth direction and the 1p ⁺ -type angle in the depth direction of the base region 3 theta trench 18, the depth direction and the angle of the 2p ⁺ -type depth direction of the base region 4 of the trench 18 90 The case of ° -θ is shown. However, the respective angles need to be greater than 0 ° and smaller than 90 °, and the depth direction of the first p ⁺ -type base region 3 and the depth direction of the second p ⁺ -type base region 4 may not be orthogonal.

The manufacturing method of the semiconductor device according to the third embodiment is the same as the first embodiment except that the first p ⁺ -type base region 3 and the second p ⁺ -type base region 4 are formed to intersect with the trench 18. Since it is the same as the above, the description is omitted.

As described above, according to the third embodiment, the trench, the first p ⁺ -type base region and the second p ⁺ -type base region have a stripe shape, and the first p ⁺ -type base region and the second p ⁺ The mold base region is oblique to the trench. Thereby, the distance between the adjacent first p ⁺ -type base regions in the depth direction of the trench can be narrowed, and further, the length of the second p ⁺ -type base region projected in the depth direction of the trench can be increased. . Therefore, even if misalignment occurs in the first 1p ⁺ -type base region and the 2p ⁺ -type base region, it can as a first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always.

The angle between the depth direction of the trench and the depth direction of the first p ⁺ -type base region and the angle between the depth direction of the trench and the depth direction of the second p ⁺ -type base region are the first p ^{+ in} the depth direction of the trench. The distance between the mold base regions is set to be larger than the length of the second p ⁺ -type base regions projected in the depth direction of the trench. Accordingly, even if misalignment occurs in the first 1p ⁺ -type base region and the 2p ⁺ -type base region, it can as a first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always. Therefore, even if a wide JFET width, since the first 1p ⁺ -type base region and the 2p ⁺ -type base region is in contact always without first 1p ⁺ -type base region in a floating state, the 1p ⁺ -type base region Can reduce the electric field concentration at the bottom of the trench, so the avalanche resistance does not decrease.

  The present invention can be variously modified without departing from the spirit of the present invention. In each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, and the like are variously set according to the required specifications. In each of the above-described embodiments, although the MOSFET is described as an example, the present invention is not limited thereto. Various silicon carbides that conduct and block current by being gate-controlled based on a predetermined gate threshold voltage It can be widely applied to semiconductor devices. As a silicon carbide semiconductor device whose gate drive is controlled, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like can be mentioned. In each of the above-described embodiments, although the case of using silicon carbide as the wide band gap semiconductor is described as an example, the present invention is also applicable to a wide band gap semiconductor such as gallium nitride (GaN) other than silicon carbide. It is. In each embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. However, the present invention similarly applies the first conductivity type to p-type and the second conductivity type to n-type. It holds.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used for a power conversion device or a power supply device such as various industrial machines, and is particularly suitable for a silicon carbide semiconductor device having a trench gate structure. ing.

1 n ⁺ silicon carbide substrate 2 n ⁻ type drift layer 3 first p ⁺ type base region 4 second p ⁺ type base region 5 n type region 5 a lower n type region 5 b upper n type region 6 p type base layer 7 n ⁺ Source region 8 p ⁺ contact region 9 gate insulating film 10 gate electrode 11 interlayer insulating film 12 barrier metal 13 source electrode 14 source electrode pad 18 trench

Claims (10)

A semiconductor substrate of a first conductivity type;
A first semiconductor layer of a first conductivity type provided on the front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
A first semiconductor region of a second conductivity type selectively provided inside the first semiconductor layer;
A second semiconductor region of a second conductivity type selectively provided in the first semiconductor layer and in contact with the first semiconductor region;
A second semiconductor layer of a second conductivity type provided on the side opposite to the semiconductor substrate side of the first semiconductor layer;
A third semiconductor region of a first conductivity type selectively provided inside the second semiconductor layer, having a higher impurity concentration than the semiconductor substrate;
A trench penetrating through the third semiconductor region and the second semiconductor layer to reach the first semiconductor layer, a bottom surface being in contact with the first semiconductor region, and a sidewall being in contact with the second semiconductor region;
A gate electrode provided inside the trench via a gate insulating film;
Equipped with
The first semiconductor region, the second semiconductor region, and the trench have a stripe shape.
An angle formed by the depth direction of at least one of the first semiconductor region and the second semiconductor region and the depth direction of the trench is larger than 0 ° and smaller than 90 °.   The semiconductor device according to claim 1, wherein a first angle formed by the depth direction of the first semiconductor region and the depth direction of the trench is larger than 0 ° and smaller than 90 °.   3. The semiconductor device according to claim 2, wherein the first angle is an angle which makes the distance between the adjacent first semiconductor regions in the depth direction of the trench smaller than the width of the second semiconductor region. . Assuming that the first angle is θ, the θ is a distance Z between the first semiconductor regions, a width x of the trenches, a distance y between centers of the adjacent trenches, and a width w of the second semiconductor regions. ,
Z / sin θ- (y-x) / tan θ <w
The semiconductor device according to claim 3, wherein   The semiconductor device according to claim 1, wherein a second angle formed by the depth direction of the second semiconductor region and the depth direction of the trench is larger than 0 ° and smaller than 90 °.   6. The semiconductor device according to claim 5, wherein the second angle is an angle that makes the length of the second semiconductor region projected in the depth direction of the trench larger than the distance between the first semiconductor regions. . Assuming that the second angle is θ, the θ is a distance Z between the first semiconductor regions, a width x of the trenches, a distance y between centers of adjacent trenches, and a width w of the second semiconductor regions. ,
Z <w / sin θ + (y−x) / tan θ
The semiconductor device according to claim 6, wherein   The first angle formed by the depth direction of the first semiconductor region and the depth direction of the trench and the second angle formed by the depth direction of the second semiconductor region and the depth direction of the trench are greater than 0 ° and 90 ° The semiconductor device according to claim 1, which is smaller.   The first angle and the second angle are angles that make the distance between the first semiconductor regions in the depth direction of the trench smaller than the length of the second semiconductor region projected in the depth direction of the trench. The semiconductor device according to claim 8, characterized in that: Assuming that the first angle is θ and the second angle is 90 ° -θ, the θ is a distance Z between the first semiconductor regions, a width x of the trench, a distance y between centers of adjacent trenches, For the width w of the second semiconductor region,
Z / sin θ− (y−x) / tan θ <w / cos θ + (y−x) tan θ
The semiconductor device according to claim 9, wherein

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