JP2022018416A - Digital video signal generation circuit, system, method, and program - Google Patents

Abstract

To provide a digital video signal generation circuit, system, method, and program that eliminate the shift of reception timing of video signal data on a screen panel.SOLUTION: A digital video signal generation circuit according to one embodiment simultaneously receives multiple pieces of video signal data obtained by dividing one video signal in order to display on a plurality of screens, and outputs digital video signals corresponding to the multiple pieces of video signal data to different serial transmission paths at different timing. The timing to output the respective digital video signals to the respective serial transmission paths is adjusted by units of a transmission time required to transmit data of one symbol of the respective pieces of video signal data on the respective serial transmission paths.SELECTED DRAWING: Figure 1

Description

Embodiments relate to digital video signal generation circuits, systems, methods and programs.

Liquid crystal panels and organic EL panels are used as screen panels for flat-screen TVs, which are receivers for digital TVs. However, due to the increase in the number of pixels per screen due to the increase in size of screen panels, images on the screen panel are displayed. The amount of signal data transmitted is increasing.

Normally, the video signal data is transmitted to the image panel by the serial data transmission lane, but in order to transmit the increasing one-screen video signal data, it is composed of a multi-lane in which a plurality of lanes for serial data transmission are bundled. Flat cables and even multiple flat cables are used.

Japanese Patent No. 5290473 JP-A-2015-75495 Japanese Patent No. 4529443

However, if the cable length (hereinafter referred to as cable length) differs between different flat cables, the reception timing shifts (timing skew) between the video signal data on one screen on the screen panel, and the video is displayed normally. It may not be possible.

An object to be solved by the present invention is to provide a digital video signal generation circuit, a system, a method and a program for eliminating a deviation in the reception timing of video signal data in a screen panel.

The digital video signal generation circuit according to one embodiment simultaneously receives a plurality of video signal data divided so as to display one video signal on a plurality of screens, and each digital video signal corresponding to the plurality of video signal data. Is output to different serial transmission lines at different timings.

FIG. 1 is a block diagram showing a functional configuration example of the receiving device according to the first embodiment. FIG. 2 is a block diagram showing a functional configuration example of a lane group data signal output unit of the receiving device according to the same embodiment. FIG. 3 is a diagram showing an example of a screen display area of the screen panel according to the embodiment. FIG. 4 is a block diagram showing a functional configuration example of the lane data signal output unit of the receiving device according to the embodiment. FIG. 5 is a block diagram showing a configuration example of a shift register of the receiving device according to the embodiment. FIG. 6 is a block diagram showing a functional configuration example of the lane group data receiving unit of the receiving device according to the same embodiment. FIG. 7 is a block diagram showing a physical configuration example related to transmission of a digital video signal of the receiving device according to the embodiment. FIG. 8 is a block diagram showing a physical configuration example of a screen panel of the receiving device according to the embodiment. FIG. 9 is an example of transmitting and receiving a digital video signal in the receiving device according to the second embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

(First Embodiment)
In the present embodiment, for example, when the display screen of 8K video is divided into a plurality of parts and the data of each divided display screen is assigned to different cables and transmitted, the output timing of the digital video signal transmitted by each cable is transmitted. Is shown as an example of adjusting according to each cable length.

Normally, the image data is composed of data of 1 symbol = 8 bits for each pixel color (RGB). An example of adjusting the output timing (delay time) of the digital video signal by grouping these for each screen lane group (cable) for each symbol is shown.

FIG. 1 is a block diagram showing a functional configuration example of the receiving device according to the first embodiment.
The image data acquisition unit 1 is, for example, a receiver for digital television broadcasting, receives a broadcast signal of advanced broadband satellite digital broadcasting (4K / 8K broadcasting), and acquires a video signal (data related to video content). Further, the signal is not limited to a broadcast signal, and may be a video signal for digital television broadcasting acquired from a storage medium such as a DVD or a hard disk or the Internet.

The tuner unit 11 receives and processes a broadcast signal radio wave in a desired frequency band via an antenna (not shown), a coaxial cable by cable broadcasting, or the like.

The demodulation unit 12 extracts data related to the video signal from the digital data obtained by demodulating the broadcast signal radio wave.

The video signal processing unit 13 performs data processing such as decoding on the data related to the video signal extracted by the demodulation unit 12 by a specified method, and acquires the video signal.

The image data processing unit 2 performs data processing on the video signal output by the video signal processing unit 13 for the purpose of improving the image quality, dividing the image data, and the like.

The image processing unit 21 performs data processing on the video signal output by the video signal processing unit 13 for the purpose of improving the resolution, improving the frame rate, adjusting the image quality, etc., and displays the video on the screen panel unit 421. Output video signal data. These methods are general methods and details are omitted.

The image segmentation unit 22 separates and outputs the video signal data for each region (referred to as a screen panel region) on the screen panel unit 421 determined in advance. This makes it possible to transmit video signal data in parallel for each screen panel area, which also contributes to shortening the transmission delay. Each of the divided video signal data output by the image segmentation unit 22 is referred to as screen lane group data. The screen lane group data is transmitted on different transmission lines. FIG. 1 shows an example in which screen lane group data is transmitted from the image segmentation unit 22 through four transmission lines. The screen panel area will be described later.

The image data transmission unit 3 receives the screen lane group data output by the image division unit 22, and transmits the screen lane group data, that is, the divided video signal data to the screen display unit 4 via the serial transmission interface. .. Here, the lane is a transmission method using one serial transmission line (referred to as a serial transmission line), which is the smallest unit of a transmission line for serial data transmission, and is also referred to as a serial lane. A method of transmitting data using a plurality of serial lanes is called a multi-lane. Multi-lanes are used when there is more data transmission than serial lanes can handle. However, due to the recent increase in the size of the screen panel, the amount of data on one screen has further increased, and it has become impossible to handle even multi-lane data. In the present embodiment, a method of using a plurality of multi-lanes to deal with such a situation is adopted. Further, in the present embodiment, each multi-lane in the method using a plurality of multi-lanes is referred to as a screen lane group.

The lane group data signal output units 31-1, 31-2, 31-3, and 31-4 are parallel to the screen lane group data (divided video signal data) input from the image division unit 22, respectively. A digital video signal is generated by performing serial conversion or encoding, and the digital video signal is output to interfaces 5-1, 5-2, 5-3, and 5-4, respectively. The functions of the lane group data signal output units 31-1, 31-2, 31-3, and 31-4 are the same, and unless the functions are particularly distinguished, the lane group data signal output units 31 are meant to indicate the individual functions. It is called.

The image display unit 4 receives the digital video signal for each screen lane group, displays the video content on the screen unit 42, and makes it viewable by the user.

The lane group data receiving units 41-1, 41-2, 41-3, and 41-4 are digital video signals transmitted by the lane group data signal output units 31-1, 31-2, 31-3, and 31-4, respectively. Are received via the interface units 5-1, 5-2, 5-3, and 5-4, respectively. The functions of the lane group data receiving units 41-1, 41-2, 41-3, and 41-4 are the same, and when the functions are not particularly distinguished, they are referred to as lane group data receiving units 41 in the sense of indicating each. .. Each lane group data receiving unit 41 reproduces the screen lane group data from the digital video signal and outputs the screen lane group data to the screen unit 42.

The screen unit 42 is a monitor, and in particular, in the present embodiment, it is a large-sized monitor of a flat-screen television for a digital television such as a liquid crystal panel or an organic EL panel. The screen unit 42 receives video signal data from the lane group data receiving units 41-1, 41-2, 41-3, 41-4, causes a panel driver or the like to control the image panel based on the video signal data, and controls the video. Display the content and present the video content to the user.

The delay amount measuring unit 45 has a function of measuring the delay amount between screen lane group data. The measured delay amount is used for the set delay amount set in the lane group data signal output unit 31. The set delay amount is a delay amount added to the output timing for the digital video signal, and will be described later.

The communication unit 46 exchanges data between the image display unit 4 and the image data transmission unit 3 by using a communication method such as I2C.
The delay amount comparison unit 47 compares, for example, the delay amount between the screen lane group data calculated by the delay amount measurement unit 45 from the arrival timing of each screen lane group data, and controls the delay difference via the communication unit 46. Send to. The control unit 6 sets the received delay difference as the set delay amount for each lane group data signal output unit 31.

The interface units 5-1, 5-2, 5-3, and 5-4 are, for example, flat cables for serial data transmission, and are serial for transmitting a digital video signal from the image data transmission unit 3 to the image display unit 4. It is a bundle of transmission lines. The interface unit 5 includes a protocol for transmitting a digital video signal, and in the present embodiment, Vbyone (registered trademark), which is a standard for serial data transmission, is applied.

V-byone is a serial data transmission standard usually used when transmitting a digital video signal to a screen panel or the like, and includes a pair of differential lines. One pair of differential lines (serial transmission lines) corresponds to lanes, and a flat cable in which a plurality of (for example, 16 in this embodiment) serial transmission lines are bundled corresponds to a screen lane group (multi-lane). do. Since Vbyone is a general technique, details will be omitted. The functions of the interface units 5-1, 5-2, 5-3, and 5-4 are the same, and when the functions are not particularly distinguished, they are referred to as the interface unit 5 in the sense of indicating each.

In the V-byone standard, a clock can be generated on the receiving side from the data transmitted on each serial transmission line, so that each lane can have a clock. Further, according to the V-byone standard, assuming that the generated clock period is a UI, the timing shift of the clock period between each lane on the receiving side of the V-byone is suppressed to 5 UI. Specifically, in an 8K television, 1 UI is about 350 ps, and from now on, it must be suppressed within 5 UI ≈ 1.7 ns.

Even if the timing deviation of the clock cycle of each lane is suppressed to a small extent, the data reception timing deviation on the receiving side of V-byone may become a problem. Specifically, assuming that the relative permittivity is 1 equivalent to that of air and the transmission speed of an electric signal is 3 × 10 to the 8th power / s, the propagation distance for one clock is about 100 mm. The propagation distance is even shorter for printed circuit boards and flat cables with high relative permittivity, so if the pattern design on the printed circuit board or the cable length connecting the boards is different, data reception timing shift (timing skew) will occur between the cables. there is a possibility.

In this embodiment, as shown in FIG. 1, interface units 5-1, 5-2, 5-3, and 5-4 (corresponding to each flat cable) having different cable lengths are used. In this case, the lengths are the same within one screen lane group (inside the flat cable), but the lengths may differ for each screen lane group (between flat cables). Skew is likely to occur. In the present embodiment, the timing skew is eliminated by adjusting the clock (symbol clock) of the symbol data described later.

The control unit 6 sets the set delay amount for changing the output timing of the digital video signal output from each lane group data signal output unit 31 in each lane group data signal output unit 31. The set delay amount may be calculated by the user from the difference in the cable lengths of the interface units 5-1, 5-2, 5-3, and 5-4. For example, the set delay amount is set to 0 for the lane group data signal output unit 31 of the interface unit 5 having the longest cable length. For the other lane group data signal output unit 31, the cable length (transmission time) of the interface unit 5 to be connected and the set delay amount are added so that the transmission time of the longest interface unit 5 is the same. Determine the set delay amount. The determined set delay amount may be set in each lane group data signal output unit 31 from a user interface such as a personal computer keyboard (not shown) or a remote controller of a television via the control unit 6.

Further, the control unit 6 includes video signal data (referred to as input video signal data) input to each lane group data signal output unit 31 and video signal data (output video signal data) output from the lane group data reception unit 41. It may be determined by adjusting the set delay amount while inputting (referred to as) and the control unit 6 comparing the input video signal data and the output video signal data.
For example, the set delay amount at which the input video signal data and the output video signal data match may be set from the control unit 6 to each lane group data signal output unit 31.

Further, a method using learning by artificial intelligence or the like may be used. Specifically, each lane group data signal output unit 31 is operated by giving an appropriate intermediate value delay amount as a set delay amount. After comparing the input video signal data and the output video signal data of one of the group lanes and confirming that they worked correctly, adjust the set delay amount of the other group lanes to adjust the input video signal data and the output video. Compare with the signal data to confirm that it works correctly. By performing this for all group lanes, the set delay amount for all group lanes is determined and set in each lane group data signal output unit 31.

The control unit 6 and the image data transmission unit 3 or the image display unit 4 may exchange data by a communication method such as I2C.

FIG. 2 is a block diagram showing a functional configuration example of a lane group data signal output unit of the receiving device according to the same embodiment.
The lane group data dividing unit 311 divides the screen lane group data (divided video signal data) input from the image dividing unit 22 and outputs the digital video signal to a plurality of serial transmission lines. The data output by the lane group data dividing unit 311 is referred to as lane data. By dividing into lane data, it is possible to transmit screen lane group data even when the transmission speed is limited by one serial transmission line.

The lane data signal output units 312-1, 312-2, and 311-NL generate digital video signals for output to the serial transmission line, respectively. NL is the maximum number of lanes to which one screen lane group data can be distributed, and corresponds to the number of serial transmission lines in the flat cable. In this embodiment, the NL is 16. Since the functions of the lane data signal output units 312-1, 312-2, and 311-NL are the same, they are referred to as lane data signal output units 312 in the sense of indicating each, unless the functions are particularly distinguished.

Each lane data signal output unit 312 generates a digital video signal for the lane data input from the lane group data division unit 311 according to the protocol of the interface unit 5, and outputs the digital video signal to the interface unit 5.

FIG. 3 is a diagram showing an example of a screen display area of the screen panel according to the embodiment.
The screen panel areas 421-1, 421-2, 421-3, and 421-4 correspond to the screen lane group data, respectively. That is, the screen panel of the screen unit 42 (for example, the screen panel unit 421 described later) is divided into four screen panel areas 421-1, 421-2, 421-3, 421-4, and pixels in each screen panel area. Each piece of information is screen lane group data. The screen panel areas 421-1, 421-2, 421-3, and 421-4 are similar areas in the screen panel, and are referred to as screen panel areas 421 in the sense that they are individually indicated, unless otherwise specified.

Scan paths 4211-1, 4211-2, 4211-3, and 4211-4 schematically show the paths of scan lines in the screen panel areas 421-1, 421-2, 421-3, and 421-4, respectively. .. The scanning paths 4211-1, 4211-2, 4211-3, and 4211-4 are similar scanning line paths, and are referred to as scanning paths 4211 in the sense that they are individually indicated, unless otherwise specified.

The scanning path 4211 is composed of a solid line arrow and a dotted line arrow, and the solid line arrow indicates a scanning line. Dotted arrows indicate movement between scan lines. For example, in the screen panel of the screen unit 42, it is shown that scanning is performed from left to right in order from the solid line arrow (scanning line) at the top. Scanning is performed for each screen panel area 421-1, 421-2, 421-3, 421-4, respectively. Although only 10 scanning lines are shown in FIG. 3 for each screen panel area 421, there are actually 4000 lines and other lines corresponding to the corresponding pixels of the digital television.

The reason for dividing it as a screen panel area is shown in detail below. Due to the increase in size of digital televisions in recent years, the number of pixels per screen is increasing. Digital video signals of digital television are originally signals transmitted in one serial data transmission lane, but the video screen display cycle (hereinafter referred to as frame rate) does not change, so increasing the number of pixels means digital video. It means that the frequency of the signal increases. For example, if only the pixel portion of an 8K image is simply calculated, the frame rate is 120 Hz, the number of pixels is 7680 × 4320, and the resolution is 8 bits for each color of RGB. It must be transferred from the transmission unit 3 to the screen display unit 4. In reality, since a margin portion is provided for the synchronization signal and the screen, the frequency becomes higher, and it is physically impossible to transmit the digital video signal on one serial transmission line. In the present embodiment, the 8K screen is divided into four to handle data independently, and further, for example, a bundle of 16 serial transmission lanes is bundled as a screen lane group, and four screen lane groups (4). If a digital video signal is transmitted to each screen panel area divided into four using two flat cables), the clock frequency will drop to about 3 GHz even if the format margin is included, so data transfer is possible. become.

The data of each pixel in each screen panel area 421 is output to each lane group data signal output unit 31 in the order of the scanning path 4211. The data for each pixel includes symbol data of R, G and B. The symbol data is bit data allocated to each of R, G, and B of one pixel (pixel). Usually, in the case of a video image by 8K broadcasting, for example, the symbol data of R, G, and B are each composed of 8 bits of data.

Pixels 4212-1, 4212-2, 4212-3, 4212-4 show examples of pixels on the screen panel areas 421-1, 421-2, 421-3, 421-4, respectively. Pixels 4212-1, 4212-2, 4212-3, and 4212-4 are examples of similar pixels, and when not particularly distinguished, they are referred to as pixels 4212 in the sense that they indicate individuals.

As an example of pixels for each of the four screen panel areas 421, three pixels (P11, P12, P13), (P21, P22, P23), (P31, P32, P33), (P41, P42, P43) are shown. It is output from the screen dividing unit 22 in the order of the scanning path 4211 for each screen panel area 421. These pixel data are simultaneously input to the lane group data signal output unit 31. Specifically, the data of the pixels P11, P21, P31, and P41 for each screen panel area 421 are simultaneously input to each lane group data signal output unit 31, and the lane data signal output unit of each lane group data signal output unit 31. It is input to 312-1 at the same timing. For example, when the data of the pixels (P11, P12, P13) is input to the lane group data signal output unit 31-1, the pixels (P11, P12, P13) are the lane data signal output units 312-1, 312-2, respectively. It is input to 312-3. Here, an example of three pixels has been shown, but the data of NL pixels are input to the lane data signal output units 312-1 to 312-NL, respectively.
The data of these pixels P11, P21, P31, and P41 need to be output from the lane group data receiving unit 41 at the same timing and input to the screen unit 42 at the same timing.

FIG. 4 is a block diagram showing a functional configuration example of the lane data signal output unit of the receiving device according to the embodiment.
The symbol data output unit 3121 divides the lane data input from the lane group data division unit 311 into symbol data of R, G, and B and outputs the data. The symbol data output unit 3121 outputs symbol data at the timing of the input symbol clock. The symbol clock is a time interval for processing data of one pixel (one symbol data for each of R, G, and B).

The shift registers 3122-1, 3122-2, and 3122-NSR are, for example, one-stage shift registers in which NFF flip-flops are arranged in parallel. NFF is the number of flip-flops. Since the shift registers 3122-1, 3122-2, and 3122-NSR have the same functions, they are referred to as shift registers 3122 in the sense that they indicate individual functions when the functions are not particularly distinguished. NSR is the number of shift registers.
The shift register 3122 is a shift register that operates at the timing of the input symbol clock. Specifically, the shift register 3122 outputs the flip-flop data at the same time as the data of one pixel (one symbol data of each of R, G, and B) is input. The input 1 pixel (1 symbol data for each of R, G, and B) data is input to the flip-flop. That is, the shift register 3122-1, 3122-2, 3122-NSR outputs the data of 1 pixel (1 symbol data for each of R, G, and B) with a delay time in symbol clock units (maximum NSR symbol clock). Delay time) can be given.

FIG. 5 is a block diagram showing a configuration example of a shift register of the receiving device according to the embodiment.

At the timing of the symbol clock, one symbol data (8 bits) of each screen lane group is input to the shift register 3122 in parallel. The output of the flip-flop (FF) data and the input to the FF are performed simultaneously at the timing of the symbol clock.

Returning to FIG. 4, the selector unit 3123 determines from which shift register of the shift registers 3122-1, 3122-2, and 3122-NSR is to be output to the subsequent stage, and outputs the determined shift register to the subsequent stage. Output. The selector unit 3123 of the present embodiment is set with a set delay amount input for each lane group data signal output unit 31 from the control unit 6, and the selector unit 3123 is a shift corresponding to the set set delay amount. Select the register as the shift register to be output to the subsequent stage. In the present embodiment, the same set delay amount is set for all the lane data signal output units 312 in each lane group data signal output unit 31.

The parallel-serial conversion unit 3124 serializes the output (parallel data of R, G, B data bits for one pixel) from any of the shift registers 3122-1, 3122-2, and 3122-NSR determined by the selector unit 3123. Convert to data (also called serial lane data).

The 8B10B conversion unit 3125 performs 8B10B conversion on the serial lane data input from the parallel-serial conversion unit 3124, and outputs the converted serial lane data (referred to as converted serial lane data). The 8B10B conversion (also referred to as 8B10B modulation) is a general coding method, and a detailed description thereof will be omitted.

The interface unit 3126 generates a digital video signal by performing various data conversion, frame data generation, signal generation, etc. on the converted serial lane data input from the 8B10B conversion unit 3125 according to the protocol of the interface unit 5. , The generated digital video signal is output to the interface unit 5. In this embodiment, in order to apply V-byone to the interface unit 5, the interface unit 3126 generates a digital video signal according to the V-by-one rules and outputs it to the interface unit 5. The V-by-one clock required on the receiving side of the V-by-one is determined by the number of bits transmitted on the serial transmission line. The V-byone clock is simply a value 10 times or more the symbol clock.

Since the shift register 3122 is operated by the symbol clock as described above, the delay amount actually added to the output timing of the digital video signal is an integral multiple of the symbol clock with respect to the set delay amount.

In the present embodiment, the shift register 3122, the parallel-serial conversion unit, the 8B10B conversion unit, and the interface unit are described for each lane data signal output unit 312, but one for each lane group data signal output unit 31. A shift register 3122, a parallel-serial conversion unit, an 8B10B conversion unit, and an interface unit may be installed and shared by each lane data signal output unit 312.

FIG. 6 is a block diagram showing a functional configuration example of the lane group data receiving unit of the receiving device according to the same embodiment.
The lane data receiving units 411-1, 411-2, and 411-NL each receive digital video signals from the interface unit 5, perform various data conversions, and output lane data. The lane data receiving units 411-1, 411-2, and 411-NL receive digital video signals output from the lane data signal output units 312-1, 312-2, 312-3, and 312-4, respectively. NL indicates the number of lanes in each interface unit 5, and in this embodiment, NL = 16. The lane data receiving units 411-1, 411-2, and 411-NL have the same functions, and are referred to as lane data receiving units 411 in the sense that they are individual unless otherwise specified.

The lane data receiving unit 411 includes an interface unit 3126, an 8B10B conversion unit 3125, an interface unit (not shown) corresponding to the parallel-serial conversion unit 3124, a serial-parallel conversion unit, and an 8B10B decoding unit, respectively, of the lane data signal output unit 312. ..

The interface unit of the lane data reception unit 411 receives the digital video signal received from the interface unit 5 by a reception method corresponding to the protocol of the interface unit 3126 (in this embodiment, a reception method according to the V-by-one standard), and converts serial. The lane data is acquired and output to the 8B10B decoding unit. The 8B10B decoding unit outputs the input serial lane data according to the convention of 8B10B modulation. The serial-parallel conversion unit converts the serial lane data into parallel lane data and outputs it.

The lane group data output unit 412 reproduces the screen lane group data from the lane data output by each lane data reception unit 411 and outputs the screen lane group data to the screen unit 42 at a predetermined timing.

In the present embodiment, since the converted serial lane data received in the interface unit of each lane data receiving unit 411 is synchronized, the serial lane data output by each lane data receiving unit 411 is also synchronized. .. Further, the screen lane group data output from each lane group data receiving unit 41 is also synchronized between the screen lane group data. Specifically, P11, P21, P31, and P41 of FIG. 3 are output from each lane group data receiving unit 41 at the same time. The reason is that the selector unit 3123 of each lane group data output unit 31 changes the output timing of the digital video signal for each screen lane group data.

FIG. 7 is a block diagram showing a physical configuration example related to transmission of a digital video signal of the receiving device according to the embodiment.

The video signal generation board 33 includes, for example, the functions of the lane group data signal output unit 31 of the image data transmission unit 2 and the image data transmission unit 3, processes the received video signal, and outputs the digital video signal.

The panel display control board 43 includes the function of the lane group data receiving unit 41, and includes a pixel driving element that controls the pixels of the screen panel 421.

The flat cables 53-1, 53-2, 53-3, and 53-4 correspond to the interface units 5-1, 5-2, 5-3, and 5-4, respectively.

As televisions become larger and have higher definition, the difference in length of flat cables corresponding to each screen lane group tends to increase. In the present embodiment, the selector unit 3123 changes the output timing of the digital video signal output from the video signal generation board 33 in consideration of the set delay amount of the flat cable set for each screen lane group. By matching the timing of the digital video signal input to the panel display control board 43, the difference in the length of the flat cable is absorbed.

In this embodiment, an example of setting the delay amount in symbol clock units for each parallel data (state in which the bits of the symbol data are made parallel) is shown. The video signal has symbol data (for example, 8 bits) for one video location (pixel) on the screen. Since the video signals are processed in units of such as image quality improvement, they are treated as parallel data. For the processing of parallel data, a clock called a symbol clock, which is slower than the V-byone clock (for example, one-eighth of the V-byone clock) is used. In the present embodiment, the output of the pixel data is delayed by the shift register in units of the symbol clock time using this symbol clock, and the selector unit 3123 determines which stage of the shift register pixel data is used as the output data. Therefore, the amount of delay with respect to the output timing was determined.

To add the delay amount, it is also possible to use a shift register using a V-byone clock instead of the symbol clock. In this case, the flip-flop FF is connected serially instead of making the flip-flop FF parallel as in the shift register 3122. However, when the FF is connected serially, the shift register needs to have a higher operating speed than the parallel shift register 3122. That is, when trying to set the delay amount in the shift register for serial data, there is a weakness that the clock of the shift register is fast and the number of stages increases. Further, if there are many circuits that operate with a high-speed clock, power consumption and layout design in the IC become difficult, so it is desirable to make adjustments in symbol units such as the shift register 3122.

As in the present embodiment, the time skew of the digital video signal can be eliminated by adjusting the delay amount for each screen lane group in the symbol clock time unit by the selector unit 3123. Further, if the adjustment is made in units of the symbol clock time, there is also an effect that the accuracy of ± 5 UI with respect to the reference lane defined by Vbyone is secured between the screen lane groups.

FIG. 8 is a block diagram showing a physical configuration example of a screen panel of the receiving device according to the embodiment.

The screen unit 42 includes an image panel unit 421 and a panel driver 422, and is, for example, a liquid crystal panel or an organic EL panel.

The image panel unit 421 is a portion that provides the user with video as audiovisual information by controlling an RGB light source or the like for each pixel by the panel driver 422.

The panel driver 422 receives the screen lane group data from the lane group data output unit 412 and controls the display of the image panel unit 421 according to the screen lane group data. Specifically, the panel driver 422 executes display control for the area of the image panel unit 421 corresponding to the received screen lane group data.

The BEP310, T-CON410, and transmission line 510 are dotted because they are installed on the back side of the image panel unit 421, that is, on the side that cannot be viewed. The T-CON410 is installed in the lower center of the image panel portion 421, and the BEP310 is placed next to the T-CON410.

The BEP 310 is a post-stage processing circuit (Back End Processor) for the screen display unit 4, and includes the function of the image data transmission unit 3.

The T-CON 410 is a timing controller included in the lane group data receiving unit 41 and controlling the timing at which the lane group data output unit 412 outputs the screen lane group data to the panel driver 422.

The transmission line 510 is a transmission line for digital video signals connecting the BEP 310 and the T-CON 410, and includes all of the flat cables 53-1, 53-2, 53-3, and 53-4.

In the present embodiment, the screen lane group data output from each lane group data receiving unit 41 of the T-CON 410 is synchronized between the lane group data. The reason is that the output timing of the digital video signal is changed for each screen lane group data in the selector unit 3123 of each lane group data output unit 31 of the image data transmission unit 3. Therefore, there is no timing deviation (timing skew) between the screen lane group data output by each lane group data receiving unit 41, and there is no display problem.

As shown in FIG. 7, in a panel-type television such as a flat-screen television, each pixel element of the screen panel 421 is driven by a video signal generation board 33 (including BEP310) that generates a digital video signal and a received digital video signal ( It is divided into a panel display control board 43 (including T-CON410) to be controlled). If the reception timing of the digital video signal transmitted between the two circuit boards is different between the screen lane groups, the desired video cannot be displayed on the screen panel 421. If the number of pixels is a resolution of about 4K, transmission can be performed with a single flat cable at a clock rate of about 3 GHz with 16 lanes, so the fluctuation range of the timing skew does not become large.

On the other hand, in the case of a single large panel compatible with large high-definition televisions such as 8K televisions, the screen can be divided (vertical division or horizontal division) in order to efficiently apply signals to each element of the panel. It will be possible. When the screen is divided on an 8K television or the like, the video signal data of each divided screen is simultaneously transmitted from the BEP 310 using a plurality of flat cables.

However, if the cable length of the flat cable varies, a problem (timing skew) in which the reception timing of the digital video signal shifts occurs, and the problem becomes remarkable at the time of high-speed transmission such as 8K television.

The present embodiment shown above solves the problem of timing skew due to cable length variation that occurs in a large high-definition television. Further, according to the present embodiment, it is not necessary to match the cable length between different flat cables, the degree of freedom regarding the structural design of the television and the cable routing is increased, and the design that reduces the performance and the manufacturing cost becomes possible. In this embodiment, one symbol is described as 8 bits, but it goes without saying that it is easy to extend this to 10 bits and 12 bits.

(Second embodiment)
If the length of the flat cable of each screen lane group (for example, interface units 5-1, 5-2, 5-3, 5-4) is different, not only the transmission delay time but also the characteristics of the cable change. When the characteristics of the cable change, the state of waveform distortion of the digital video signal transmitted by the cable changes. The state of waveform distortion depends on the length of the flat cable. Since the waveform distortion occurs, the waveform of the digital video signal is blunted, which affects the reception timing of the digital video signal. That is, the difference in the cable length between the flat cables to which the screen lane group data is transmitted leads to the difference in the state of the waveform distortion, and also causes the difference in the transmission delay time of the transmitted digital video signal. In this embodiment, an example of solving this problem by changing the degree of pre-emphasis in the V-byone driver according to the set delay amount (cable length) for each screen lane group will be described.

FIG. 9 is an example of transmitting and receiving a digital video signal in the receiving device according to the second embodiment.

The lane group video signal output unit 331-1, 331-2, 331-3, 331-4 has the same function as the lane group data signal output unit 31 of FIG. 1 for each screen lane group. In this figure, unlike the lane group data signal output unit 31 of FIG. 1, only the function for one lane data in the lane group data signal output unit 31 is shown, but the function for all lane data is included. Screen lane group data for each image panel area is input from the image division unit 22 to the lane group video signal output unit 331-1, 331-2, 331-3, 331-4, respectively, and the digital video signal for each lane is input. Output. Since the lane group video signal output unit 331-1, 331-2, 331-3, 331-4 have the same function, the lane group video signal output unit 331 is meant to indicate an individual unless otherwise specified. It is called.

The delay units 3311-1, 3311-2, 3311-3, and 3311-4 control the output timing of the digital video signal of the input lane data, and output the data as parallel data. Since the delay units 3311-1, 3311-2, 3311-3, and 3311-4 have the same functions, they are referred to as delay units 3311 in the sense that they are individually indicated unless otherwise specified. Each delay unit 3311 includes the same functions as the shift register 3122 and the selector unit 3123 in FIG.

Vby1 driver3312-1, 3312-2, 3312-3, 3312-4 correct and output the waveform of the output of the digital video signal with respect to the input serial lane data as necessary. The operation of correcting the output waveform of a digital video signal is called pre-emphasis. Pre-emphasis is a general technique, and the specific method is omitted. Since Vby1 driver3312-1, 3312-2, 3312-3, and 3312-4 have similar functions, they are referred to as Vby1 driver3312 in the sense of indicating each unless otherwise specified.

The Vby1 driver 3312 is included in, for example, the interface unit 3126 in FIG. Although the parallel-serial conversion unit 3124 and the 8B10B conversion unit 3125 in FIG. 4 are not shown in FIG. 9, the same function is included in FIG. Therefore, the data input to the Vby1 driver 3312 is serial data output by the function corresponding to the 8B10B conversion unit 3125.

The flat cables 53-1, 53-2, 53-3, and 53-4 correspond to the interface units 5-1, 5-2, 5-3, and 5-4 in FIG. 1, respectively, and are Vby1 drivers3312-1 and 3312. -2, 3312-3, 3312-4 is a transmission line for transmitting a digital video signal output by the V-byone protocol, for example, a flat cable. In the figure, only one pair of differential lines (one serial transmission line) is shown for each of the flat cables 53-1, 53-2, 53-3, and 53-4, but each is not shown. It has a transmission line. In this embodiment, each of the flat cables 53-1, 53-2, 53-3, and 53-4 has 16 differential lines (multi-lanes). Since the flat cables 53-1, 53-2, 53-3, and 53-4 have the same functions, they are referred to as flat cables 53 in the sense that they are individually indicated unless otherwise specified.

The output signals 51-1, 51-2, 51-3, and 51-4 are examples of digital signal waveforms output by the lane group video signal output units 331-1, 331-2, 331-3, and 331-4, respectively. Shows. Since the output signals 51-1, 51-2, 51-3, and 51-4 are similar signals, they are referred to as output signals 51 in the sense that they are individual unless otherwise specified.

The input signals 52-1, 52-2, 52-3, and 52-4 are the digital video signals output by the lane group video signal output units 331-1, 331-2, 331-3, and 331-4, respectively. An example of the waveform immediately before reaching the panel display control board 43 via the flat cables 53-1, 53-2, 53-3, 53-4 is shown. Since the input signals 52-1, 52-2, 52-3, and 52-4 are similar signals, they are referred to as input signals 52 in the sense of indicating each unless otherwise specified.

The panel display control board 43 is the same as the description in FIG.

FIG. 9 shows an example in which the flat cables 53 have different cable lengths. A delay is added to the output timing of the digital video signal in each delay unit 3311 according to the cable length of each of the connected flat cables 53. Specifically, since the cable length increases in the order of the flat cables 53-1, 53-2, 53-3, 53-4, the delay portions 3311-1, 3311-2, 3311-3, 3311-4 are in this order. Therefore, the amount of delay added to the output timing of the digital video signal is increased. Here, the difference in length is negligible for each serial transmission line in each flat cable 53, and the set delay amount for the selector unit 3123 in the delay unit 3311 is the same value. The set delay amount determined for each lane group video signal output unit 331 is set in the selector unit 3123 of each delay unit 3311. The selector unit 3123 determines a shift register 3122 for outputting lane data based on a set set delay amount.

Next, since the degree of deterioration of the waveform of the digital video signal depends on the cable length of each flat cable 53 to which the digital video signal is transmitted, in the Vby1 driver 3312, the cable length of the flat cable 53 to which each Vby1 driver 3312 is connected. The waveform of the output signal 51 is corrected according to the above. Specifically, in Vby1 driver3312-1, 3312-2, 3312-3, 3312-4, the waveforms of the input signals 52-1, 52-2, 52-3, 52-4 are as shown in FIG. The output signals 51-1, 51-2, 51-3, and 51-4 are corrected in the same manner. In the example of FIG. 9, since the cable length becomes longer in the order of the flat cables 53-1, 53-2, 53-3, 53-4, the Vby1 driver3312-1, 3312-2, 3312-3, 3312-4 In order, increase the amount of waveform correction (increasing pre-emphasis).

For example, the control unit 6 may determine the correction amount of the waveform for each Vby1 driver 3312-1, 3312-2, 3312-3, 3312-4, and the control unit 6 may set each Vby1 driver 3312. The user may determine the correction amount of the waveform and set it in the control unit 6 from a user interface (not shown). Further, the control unit 6 may determine the correction amount of the waveform while comparing the input video signal data of each lane group data signal output unit 31 with the output video signal data, and set it in each Vby1 driver 3312. Further, the control unit 6 may determine the correction amount of the waveform by using a method using learning by artificial intelligence or the like, and set it in each Vby1 driver 3312.

As for the method of determining the set delay amount and the waveform correction amount, for example, each lane group data signal output unit 31 has a function of transmitting data so that the delay amount of each screen lane group can be understood, and is based on the data. The corresponding lane group data signal receiving unit 41 on the receiving side reports the data reception timing to the transmitting side, so that the control unit 6 on the transmitting side grasps the delay amount and the delay amount and / or waveform with respect to the screen lane group. The feature is that the set value of the correction amount can be changed. As the data that shows the delay amount of the screen lane group, cue data (also referred to as a synchronization code) transmitted by serial transmission can be used. By detecting the synchronization code and measuring the detection time difference for each screen lane group, the delay amount based on the detection time difference is set in the selector unit 3123 of each lane group data signal output unit 31 as the set delay amount.

By the above procedure, when the length of the flat cable which is the transmission line of each screen lane group is different, even if the state of waveform distortion due to the characteristics of the cable is different as well as the transmission delay time, it depends on each flat cable. It is possible to eliminate the deviation of the reception timing of the transmitted digital video signal on the panel display board 43 and to eliminate the deviation of the output timing of the screen lane group data output to the screen panel.

The digital video signal to be transmitted is affected by the inductance component and the capacitance component due to the length of the cable, and waveform distortion occurs. This distortion mainly appears as a bluntness at the rising edge of the waveform, but preventing this is a technique called pre-emphasis, which emphasizes the rising edge of the signal before transmission. However, doing this raises the high frequency component on the cable, which may increase the noise of the entire system, so it is common not to raise it unnecessarily. Therefore, it is not preferable to apply the same pre-emphasis to the full screen lane group. According to this embodiment, in order to carry out pre-emphasis according to the length of the cable (flat cable 53) transmitted for each screen lane group, the absolute amount of high frequency components can be reduced, and the entire system can be reduced. It has the effect of suppressing the increase in noise.

According to at least one embodiment described above, it is possible to provide a digital video signal generation circuit, a system, a method, and a program that eliminates a deviation in the reception timing of video signal data in a screen panel.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof. Furthermore, in each of the constituent elements of the claim, even if the constituent elements are divided and expressed, or a plurality of the constituent elements are expressed together, or even if they are expressed in combination, it is within the scope of the present invention. Further, a plurality of embodiments may be combined, and an example composed of these combinations is also within the scope of the invention.

Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment. In the block diagram, data and signals may be exchanged between blocks that are not connected, or even if they are connected but in a direction in which an arrow is not shown. Each function shown in the block diagram, and the processing shown in the flowchart and sequence chart are hardware (IC chip, etc.), software (program, etc.), digital signal processing arithmetic chip (Digital Signal Processor, DSP), or their hardware. It may be realized by a combination of hardware and software. Further, the apparatus of the present invention is applied even when the claim is expressed as a control logic, when it is expressed as a program including an instruction for executing a computer, and when it is expressed as a computer-readable recording medium in which the instruction is described. be. Further, the names and terms used are not limited, and other expressions are included in the present invention as long as they have substantially the same content and the same meaning.

1 ... image data acquisition unit, 2 ... image data processing unit, 3 ... image data transmission unit, 4 ... image display unit, 5 ... interface unit, 6 ... control unit, 11 ... tuner unit, 12 ... demodulation unit, 13 ... video Signal processing unit, 21 ... Image processing unit, 22 ... Image division unit, 31 ... Lane group data signal output unit, 33 ... Video signal generation board, 41 ... Lane group data receiving unit, 42 ... Screen unit, 43 ... Panel display control Board, 45 ... Delay amount measurement unit, 46 ... Communication unit, 47 ... Delay amount comparison unit, 51-1 to 51-4 ... Output signal, 52-1 to 52-4 ... Input signal, 53-1 to 53-4 ... Flat cable, L1 to L16 ... Screen panel area, 310 ... BEP, 311 ... Lane group data division unit, 312 ... Lane data signal output unit, 312-1 to 311-NL ... Lane data signal output unit, 331, 331- 1 to 331-4 ... Lane group video signal output unit, 410 ... T-CON, 411 ... Lane data reception unit 411-1 to 411-NL ... Lane data reception unit, 412 ... Lane group data output unit, 421 ... Image Panel unit, 421-1 to 421-4 ... Screen panel area, 422 ... Panel driver, 510 ... Transmission path, 3121: Symbol data output unit, 3122 ... Shift register, 3123 ... Selector unit, 3124 ... Parallel-serial conversion unit, 3125 ... 8B10B conversion unit, 3126 ... interface unit, 3311-1 to 3311-4 ... delay unit, 3312-1 to 3312-4 ... Vby1 driver, 4211-1 to 4211-4 ... scanning path, 4212-1 to 4212- 4 ... pixels.

Claims (9)

Digital that simultaneously receives multiple video signal data divided to display one video signal on multiple screens, and outputs each digital video signal corresponding to the multiple video signal data to different serial transmission lines at different timings. Video signal generation circuit. The timing for outputting each digital video signal to each serial transmission line is adjusted in units of transmission time required to transmit data for one symbol of each video signal data on each serial transmission line. Item 1. The digital video signal generation circuit according to Item 1. The timing for outputting each digital video signal to each serial transmission line is adjusted in units of transmission time required to transmit a bit in one symbol of each video signal data on each serial transmission line. The digital video signal generation circuit according to any one of items 1 and 2. The one according to any one of claims 1 to 3, wherein the output timing of each digital video signal to the serial transmission line is determined by the length of the serial transmission line through which each digital video signal is transmitted. Digital video signal generation circuit. With reference to the output timing of the first digital video signal to the first serial transmission line having the maximum length of each of the serial transmission lines, to the second serial transmission line excluding the first serial transmission line. A digital video signal generation circuit that delays the output timing of the second digital video signal.
The output timing of the second digital video signal is the difference between the first transmission time determined by the length of the first serial transmission line and the second transmission time determined by the length of the second serial transmission line. The digital video signal generation circuit according to any one of claims 1 to 4, wherein the delay amount is the amount of the delay. Each of the digital video signals is corrected according to the characteristics of waveform distortion depending on the length of each serial transmission line, and is output to each of the serial transmission lines according to any one of claims 1 to 5. The digital video signal generation circuit described in the section. Digital that simultaneously receives multiple video signal data divided to display one video signal on multiple screens, and outputs each digital video signal corresponding to the multiple video signal data to different serial transmission lines at different timings. Video signal generation circuit and
A screen display means for connecting the serial transmission line, receiving and processing each digital video signal, and acquiring the plurality of video signal data is provided.
The digital video signal generation circuit includes specific data in each digital video signal and transmits the data.
The screen display means includes a delay difference measuring means that receives the specific data from each digital video signal and measures the delay difference between the digital video signals from the specific data.
The digital video signal generation circuit is a system that determines a delay amount with respect to an output timing of each digital video signal based on a delay difference between the digital video signals received from the delay difference measuring means. A method of simultaneously receiving a plurality of video signal data divided so as to display one video signal on a plurality of screens, and outputting each digital video signal corresponding to the plurality of video signal data to a different serial transmission line at different timings. .. A program in which a computer receives multiple video signal data at the same time and outputs a digital video signal.
A procedure for simultaneously receiving a plurality of video signal data divided so as to display one video signal on a plurality of screens, and outputting each digital video signal corresponding to the plurality of video signal data to a different serial transmission line at different timings. A program for causing the computer to execute.

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