KR102582966B1 - Interface Board and Display Device using the same - Google Patents

Abstract

The present invention provides an interface board including an external receiver and an FPGA unit. The external receiver is connected to one channel of the external device and converts the transmission data signal of the first transmission system transmitted through one channel to the second transmission system, and extracts and outputs a clock signal and a data signal. The FPGA unit operates based on the clock signal output from the external receiver, is connected to the remaining channel of the external device, and converts the transmission data signal of the first transmission system transmitted through the remaining channel of the external device into a transmission data signal of the third transmission system. Convert and output.

Description

Interface board and display device using the same {Interface Board and Display Device using the same}

The present invention relates to an interface board and a display device using the same.

Thanks to the development of process technology and driving circuit technology, display devices are being implemented with large, high-resolution screens. UHD (Ultra High Definition) has 3840*2160 = 8.3 million pixels. The number of pixels in UHD is approximately 4 times greater than the number of pixels in FHD (Full High Definition) (1920*1080), which has 2.07 million pixels. Therefore, UHD can reproduce input images more precisely than FHD, producing clearer and smoother picture quality. Pixel refers to the smallest unit of dot that makes up a computer display or computer image. The number of pixels means PPI (Pixels Per Inch).

HD resolution is also expressed as “K” such as 2K, 4K, and 8K. Here, K stands for ‘Kilo’, or 1,000, in the digital cinema standard. For example, based on the number of horizontal pixels, 2K means 2,000 pixels and 4K means 4,000 pixels. 2K with a resolution of 2048*1080 is almost similar to FHD's resolution of 1920*1080, but 2K is mainly used in broadcasting and movies. 4K, which refers to a resolution of 4096*2160, is also called QFHD (Quad Full High Definition) because it is four times the resolution of FHD, or UD (Ultra Definition) and UHD (Ultra High Definition) because it is a completely different level of high definition than FHD.

In the pixel array of a display device with UHD resolution, the number of data lines is 3840*3 = 11,520, and the number of gate lines is 2160. 3 in 3840*3 is when 1 pixel contains 3 RGB subpixels. to drive data lines

If the data driver is selected as a source drive IC (Integrated Circuit) with 720 channels, approximately 16 are required. In the source drive IC, one channel is connected to one data line, and the data line is connected to one subpixel per row line of the pixel array.

In display devices, the amount of data transmission is increasing due to high resolution, expanded color depth, and high-speed operation in order to realize high-quality images. As the amount of data transmission increases, the clock frequency, data transfer rate, and bandwidth between devices increase.

A representative interface method for data transmission between devices in a display device is the LVDS (Low-Voltage Differential Signaling) interface. However, the LVDS interface cannot properly respond to the increase in data signal transmission. For this reason, in order to implement a display device with UHD resolution or higher, it is necessary to develop an interface board that can converge the increase in the amount of data signal transmission as well as the increase in clock frequency, data transfer rate, and bandwidth between devices.

The present invention to solve the problems of the above-described background technology is to provide an interface board that can converge the increase in clock frequency, data transfer rate, and bandwidth between devices while minimizing the device configuration, and a high-resolution display device using the same.

As a means of solving the above-described problem, the present invention provides an interface board including an external receiver and an FPGA unit. The external receiver is connected to one channel of the external device and converts the transmission data signal of the first transmission system transmitted through one channel to the second transmission system, and extracts and outputs a clock signal and a data signal. The FPGA unit operates based on the clock signal output from the external receiver, is connected to the remaining channel of the external device, and converts the transmission data signal of the first transmission system transmitted through the remaining channel of the external device into a transmission data signal of the third transmission system. Convert and output.

The FPGA unit includes a first internal receiver that receives the clock signal and data signal of the second transmission system output from the external receiver, converts it to the third transmission system, and transmits the converted clock signal and data signal to its internal device, and an external device. It may include a second internal receiver that receives the transmission data signal of the first transmission system transmitted through the remaining channel, converts it into a transmission data signal of the third transmission system, and outputs it.

The FPGA unit may include a data conversion unit that decodes the transmission data signal of the third transmission system, and a data alignment unit that sorts the transmission data signal of the third transmission system output from the data conversion unit and the data signal output from the first internal receiving unit. You can.

In another aspect, the present invention provides a display device including an image supply unit, an interface board, a plurality of timing control units, and a display panel. The video supply unit outputs a transmission data signal. The interface board is connected to one channel of the video supply unit and converts the transmission data signal of the first transmission system transmitted through one channel to the second transmission system, as well as an external receiver that extracts and outputs clock signals and data signals. , operates based on the clock signal output from the external receiver, is connected to the remaining channel of the video supply unit, and converts the transmission data signal of the first transmission system transmitted through the remaining channel of the video supply unit into a transmission data signal of the third transmission system. It includes an FPGA unit that outputs. A plurality of timing control units receive transmission data signals of the third transmission system output from the interface board. The display panel displays images based on transmission data signals output from multiple timing control units.

The FPGA unit includes a first internal receiver that receives the clock signal and data signal of the second transmission system output from the external receiver, converts it to the third transmission system, and transmits the converted clock signal and data signal to its internal device, and an image supply unit. A second internal receiver that receives the transmission data signal of the first transmission system transmitted through the remaining channel, converts it into a transmission data signal of the third transmission system, and outputs it, and a data conversion unit that decodes the transmission data signal of the third transmission system. It may include a unit and a data alignment unit that aligns the transmission data signal of the third transmission system output from the data conversion unit and the data signal output from the first internal receiving unit.

In another aspect, the present invention provides an interface board including a switch unit, an external receiver, and an FPGA unit. The switch unit is connected to one channel of the external device and outputs at least two copies of the transmission data signal of the first transmission system transmitted through one channel. The external receiver is connected to the first output terminal of the switch unit and receives the transmission data signal of the first transmission system copied from the first output terminal, converts the copied transmission data signal of the first transmission system to the second transmission system, and transmits a clock signal. Extract and output. The FPGA unit operates based on the clock signal output from the external receiver, is connected to the second output terminal of the switch unit and the remaining channel of the external device, receives the transmission data signal of the first transmission system copied from the second output terminal, and receives the remaining channel of the external device. The transmission data signal of the first transmission system is received from the channel, and all received transmission data signals of the first transmission system are converted into transmission data signals of the third transmission system and output.

The FPGA unit receives the clock signal of the second transmission system output from the external receiver, converts it to the third transmission system, and transmits the converted clock signal to its internal device, the second output terminal of the switch unit, and the external device. It may include a second internal receiver that converts all transmission data signals of the first transmission system received from the remaining channels into transmission data signals of the third transmission system and outputs them.

The FPGA unit may include a data conversion unit that decodes the transmission data signal of the third transmission system output from the second internal receiving unit, and a data alignment unit that sorts the transmission data signal of the third transmission system output from the data conversion unit.

In another aspect, the present invention provides a display device including an image supply unit, an interface board, a plurality of timing control units, and a display panel.

The video supply unit outputs a transmission data signal. The interface board is connected to one channel of the video supply unit and includes a switch unit that copies and outputs at least two transmission data signals of the first transmission system transmitted through one channel, and is connected to the first output terminal of the switch unit and provides a first output terminal. An external receiver that receives the transmission data signal of the first transmission system copied from the first transmission system, converts the copied transmission data signal of the first transmission system to the second transmission system, and extracts and outputs a clock signal, and It operates based on the first clock signal, is connected to the second output terminal of the switch unit and the remaining channel of the video supply unit, receives the transmission data signal of the first transmission system copied from the second output terminal, and transmits the first transmission from the remaining channel of the video supply unit. It includes an FPGA unit that receives transmission data signals of the system, converts all received transmission data signals of the first transmission system into transmission data signals of the third transmission system, and outputs them. A plurality of timing control units receive transmission data signals of the third transmission system output from the interface board. The display panel displays images based on transmission data signals output from multiple timing control units.

The FPGA unit includes a first internal receiver that receives the clock signal of the second transmission system output from the external receiver, converts it to the third transmission system, and transmits the converted clock signal to its internal device, the second output terminal of the switch unit, and the video supply unit. A second internal receiver that converts all transmission data signals of the first transmission system received from the remaining channels into transmission data signals of the third transmission system and outputs them, and a transmission data signal of the third transmission system output from the second internal receiver. It may include a data conversion unit that decodes and a data alignment unit that sorts the transmission data signals of the third transmission system output from the data conversion unit.

The present invention has the effect of providing an interface board that can converge the clock frequency, data transfer rate, and increase in bandwidth between devices, and a high-resolution display device using the same. In addition, the present invention has the effect of providing an interface board that can minimize the configuration of the device while enjoying the advantages optimized for the interfacing method.

1 is a block diagram for explaining the configuration of a general organic light emitting display device.
Figure 2 is a block diagram illustrating the main configuration of a high-resolution organic light emitting display device according to a first embodiment of the present invention.
Figure 3 is a block diagram schematically showing an interface board according to a first experimental example.
Figure 4 is a block diagram schematically showing an interface board according to a first experimental example.
Figure 5 is a block diagram schematically showing an interface board according to the first embodiment.
Figure 6 is a diagram for explaining the function of the data sorting unit.
Figure 7 is a diagram showing the data conversion system of the interface board.
Figure 8 is an example of pin allocation of the FPGA unit for connection to an external receiver.
Figure 9 is a block diagram schematically showing an interface board according to a second embodiment.
Figure 10 is a diagram for explaining the function of the data sorting unit.
11 is a diagram showing the data conversion system of the interface board.
Figure 12 is an example of pin allocation of the FPGA unit for connection to an external receiver.

Hereinafter, specific details for implementing the present invention will be described with reference to the attached drawings.

The channels described in the data communication-related description below are two signal lines through which the same signal is transmitted with opposite polarities, and are also called lanes or pairs. A signal line refers to a physical transmission path through which signals such as data and clocks are transmitted serially.

The display device of the present invention can be implemented as a display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED). In the following embodiments, the description will focus on an organic light emitting display device as an example of a display device, but the present invention is not limited thereto.

FIG. 1 is a block diagram for explaining the configuration of a general organic light emitting display device, and FIG. 2 is a block diagram for explaining the main configuration of a high-resolution organic light emitting display device according to a first embodiment of the present invention.

As shown in FIG. 1, a typical organic light emitting display device includes a timing control unit 120, a data driver 130, a gate driver 140, and a display panel 150.

The timing control unit 120 receives a data signal (DATA) as well as a data enable signal (DE) or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from an external device. The timing control unit 120 provides a gate timing control signal (GDC) for controlling the operation timing of the gate driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs.

The data driver 130 samples and latches the data signal (DATA) supplied from the timing control unit 120 in response to the data timing control signal (DDC) supplied from the timing control unit 120, converts it to a gamma reference voltage, and outputs it. . The data driver 130 outputs a data signal (DATA) through the data lines (DL1 to DLn). The data driver 130 may be formed in the form of an integrated circuit (IC).

The gate driver 140 outputs a gate signal (or scan signal) in response to the gate timing control signal (GDC) supplied from the timing control unit 120. The gate driver 140 outputs a gate signal (or scan signal) through the gate lines GL1 to GLm. The gate driver 140 is formed in the form of an integrated circuit (IC) or is formed in the non-display area of the display panel 150 using a gate in panel method (formed in a thin film form).

The display panel 150 displays images in response to the data signal (DATA) and gate signal supplied from the data driver 130 and the gate driver 140. The display panel 150 includes subpixels (SP) that operate to display images. The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel.

The general organic light emitting display device described above can be implemented at high resolution by increasing the resolution of the display panel 150 to UHD (Ultra High Definition) or higher. High-resolution organic light emitting display devices require an interface board to converge the increase in the amount of data transmission as well as the increase in clock frequency, data transfer rate, and bandwidth between devices.

As shown in FIG. 2, a high-resolution organic light emitting display device is similar to four 4K display panels 150 attached together. Although there may be differences depending on the configuration or driving method of the device, in order to drive the illustrated display panel 150, data signals input from the outside must be upscaled to high resolution. In order to supply a large amount of upscaled data signals to the display panel 150 through data drivers (the data drivers are omitted for convenience of explanation), approximately four timing control units 120a to 120d must be provided.

However, it is difficult for the four independent timing control units 120a to 120d to upscale and distribute data signals input from the outside to meet high resolution. In addition, since the timing control unit has a limited transmission amount of each transmission data signal, this point must also be taken into consideration.

For the above reason, an interface board 170 as shown is required to upscale the data signal (DATA) output from the image supply unit 110 to high resolution and distribute it to the plurality of timing control units 120a to 120d.

Meanwhile, when adopting the LVDS (Low-Voltage Differential Signaling) interface on a 120Hz display panel with FHD (Full High Definition) resolution and 10 bit color depth, 48 signal lines in 24 pairs are used. need. The LVDS interface transmits clock signals along with data signals. Therefore, in the LVDS interface, as the amount of transmission data increases, the clock frequency also increases, necessitating EMI (Electromagnetic interference) control.

According to the LVDS interface standard, a signal that changes around a voltage of 1.2V at ground (GND) must be transmitted. Due to the implementation of the miniaturized process of LSI (Large Scale Integration), the specifications of the signal voltage required for the LVDS interface have brought about significant limitations in LSI design. In this situation, interfaces such as DVI (Digital Video Interface), HDMI (High Definition Multimedia Interface), and DisplayPort were proposed and put into practical use.

DVI and HDMI have a skew adjustment function, and HDMI has a built-in content protection function, HDCP (High-bandwidth digital content protection), so it has many advantages in transmitting video signals between devices, but it requires a license fee and requires a device. Internal video signal transmission also has the disadvantage of excessive functionality and high power consumption.

DisplayPort was standardized by VESA (Video Electronics Standards Association) as a specification that can replace LVDS. Like HDMI, DisplayPort has built-in HDCP considering transmission between devices, so it has excessive functions and has problems with increased power consumption. The transmission speed is fixed, so loss occurs when transmitting signals at low frequencies, and there is a need for clock reproduction on the receiving side. there is.

The V-by-One interface was developed by THine Electronics. Due to the introduction of the equalizer function, the V-by-one interface improved signal transmission quality compared to the existing LVDS interface and realized high-speed data transmission of up to 3.75Gbps per pair. The V-by-one interface solved the skew adjustment problem caused by clock transmission of the LVDS interface by applying CDR (Clock Data Recovery). And because the V-by-one interface does not require clock transmission, which is necessary in LVDS, EMI noise due to clock transmission can be reduced. This V-by-one interface increases the amount of transmission data and can effectively respond to high-speed operation.

Since the V-by-One interface has the above advantages, in the following embodiment, the video supply unit 110 and the interface board 170 transmit and receive transmission data signals through V-by-One as an example, but the present invention is not limited to this.

The present applicant has conducted experiments based on FPGA (Field-Programmable Gate Array) to develop an interface board 170 suitable for high-resolution organic light emitting display devices. However, the interface board according to the experimental examples had the following problems.

FIG. 3 is a block diagram schematically showing the interface board according to the first experimental example, and FIG. 4 is a block diagram schematically showing the interface board according to the first experimental example.

As shown in FIG. 3, the interface board 170 according to the first experimental example includes an external receiving unit 30 (external Rx) and an FPGA unit 40 (FPGA). The external receiver 30 receives the transmission data signal of the V-by-One system (first transmission system) output from the video supply unit 110, converts it to the LVDS system (second transmission system), and outputs it. . The video supply unit 110 transmits a transmission data signal in a V-by-One system through a transmitter 115 (Tx) provided internally or externally.

The FPGA unit 40 functions to upscale and output the transmission data signal output from the external receiver 30. For example, the FPGA unit 40 transmits the input transmission data signal to suit the high resolution supported by the display panel, such as upscaling the original HD (1280 × 720) transmission data signal to a transmission data signal of 4K UHD (3840 It may play the role of converting into a data signal, but is not limited to this.

However, the interface board 170 according to the first experimental example must correspond to all channels (Channel[0] to Channel[N]) of the video supply unit 110 and channels of the external receiver 30. That is, the external receiving unit 30 must be configured with a device (e.g., IC) having the number of channels corresponding to all channels (Channel[0] to Channel[N]) of the transmitting unit 115. In addition, the input/output terminals (I/O) of the FPGA unit 40 must also be allocated to the number of channels corresponding to all channels (Channel[0] to Channel[N]) of the transmitter 115.

The interface board 170 according to the first experimental example enables accurate characterization (impedance matching, etc.) between the transmitting end and the receiving end by using the external receiving unit 30. However, the interface board 170 according to the first experimental example was found to cause a problem of increased manufacturing costs when implementing the device due to an increase in the number of channels of the external receiver 30 and the FPGA unit 40.

As shown in FIG. 4, the interface board 170 according to the second experimental example includes an FPGA unit 40 and an internal receiving unit 44. The internal receiving unit 44 is provided inside the FPGA unit 40. The internal receiver 44 is implemented to receive the transmission data signal of the V-by-One system output from the video supply unit 110 and convert it to the LVDS system.

The FPGA unit 40 functions to upscale and output the transmission data signal output from the internal receiver 30. For example, the FPGA unit 40 transmits the input transmission data signal to suit the high resolution supported by the display panel, such as upscaling the original HD (1280 × 720) transmission data signal to a transmission data signal of 4K UHD (3840 It may play the role of converting into a data signal, but is not limited to this.

However, the interface board 170 according to the second experimental example undergoes a characterization process (interfacing method characterization at the FPGA Factory) for the FPGA unit 40 to use the internal receiving unit 30 (e.g., communication port such as Ethernet MAC Blocks, etc.). ) is needed.

The interface board 170 according to the second experimental example can be implemented as a relatively simple board by using the internal receiver 30. However, even though the interface board 170 according to the second experimental example has gone through the characterization process of the FPGA unit 40 for use in the internal receiver 30, the frequency specification range supported by the interface board 170 is very limited, so the devices It was found that it was difficult to converge the clock frequency, data transfer rate, and increase in bandwidth between devices, resulting in poor mass production.

As shown above, the experimental examples need to be improved to have a configuration that can reduce manufacturing costs while securing mass production specifications capable of supporting high resolution when implementing an interface board using FPGA.

<First embodiment>

Figure 5 is a block diagram schematically showing the interface board according to the first embodiment, Figure 6 is a diagram for explaining the function of the data alignment unit, Figure 7 is a diagram showing the data conversion system of the interface board, and Figure 8 is a diagram showing the data conversion system of the interface board. This is an example of pin allocation for the FPGA unit for connection to an external receiver.

As shown in FIGS. 5 to 8, the interface board 170 according to the first embodiment includes an external receiving unit 30 (external Rx) and an FPGA unit 40 (FPGA). The external receiver 30 receives the transmission data signal of the V-by-One system output from the video supply unit 110, converts it to the LVDS system, and outputs it. The video supply unit 110 transmits a transmission data signal in a V-by-One system through a transmitter 115 (Tx) provided internally or externally.

The external receiver 30 receives a transmission data signal output from one channel of the video supply unit 110. For example, the external receiver 30 receives the transmission data signal of the V-by-One system output from the first channel (Channel[0]) of the video supply unit 110, converts it to the LVDS system, and generates a clock signal from this. ) and data signals (Data) are extracted.

In order to perform the above functions, the external receiver 30 includes a sample & hold function that samples the transmission data signal received from the outside, a PLL (phase lock loop) that generates its own clock signal, and a data serializer that serializes the transmission data signal. (Data Serializer), etc., but is not limited thereto.

The external receiver 30 has a PLL (phase lock loop) that generates a clock signal, and can change the frequency in various ways in response to signals input from the outside (user needs). Therefore, the external receiver 30 can provide the advantage of setting the frequency specification (Spec) range of the clock signal (Clock) broadly.

Meanwhile, the LVDS system uses two different low voltages, so two signal lines (e.g. D0+, D)-) form a pair. And the data signal transmitted through a pair of signal lines includes a clock signal (Clock) and a data signal (Data). Therefore, in Figure 5, it is shown that the clock signal (Clock) and the data signal (Data) are output separately to a pair of signal lines, but this is due to the configuration of the signals transmitted through the pair of signal lines and the separate It should be understood as expressed to show that it is used for its intended purpose.

The FPGA unit 40 functions to upscale and output the transmission data signal output from the video supply unit 110. For example, the FPGA unit 40 transmits the input transmission data signal to suit the high resolution supported by the display panel, such as upscaling the original HD (1280 × 720) transmission data signal to a transmission data signal of 4K UHD (3840 It may play the role of converting into a data signal, but is not limited to this. The FPGA unit 40 operates based on a clock signal (Clock) output from the external receiver 30. Therefore, the FPGA unit 40 may have the same operating characteristics as the external receiver 30.

The FPGA unit 40 includes a first internal receiver (41, LVDS Rx), a second internal receiver (42, PHY), a data conversion unit (43, interfacing L2), and a data alignment unit (45, Alignment FIFO). . Other control logic parts are omitted as they are unrelated to the interface.

The first internal receiving unit 41 is a data communication receiving unit provided inside the FPGA unit 40. The first internal receiver 41 converts the data signal (Data) and clock signal (Clock) of the LVDS system output from the external receiver 30 into the TTL (Transistor-Transistor Logic) system (third transmission system).

The first internal receiver 41 converts the data signal (Data) output from the external receiver 30 into a TTL system and transmits it to the data alignment unit 45. In addition to the data signal (Data), the remaining clock signal (Clock) is used as a reference clock signal (Reference Clock) that can be utilized inside the FPGA unit 40. The FPGA unit 40 can use the reference clock signal transmitted from the first internal receiver 41 as a clock signal required to drive the internal device (IP) or to restore the internal clock signal. .

The first internal receiver 41 receives a clock signal (Clock) and a data signal (Data) from the external receiver 30. For this reason, the FPGA unit 40 must allocate a total of 8 input/output terminals (I/O) as shown in FIG. 8 in order to use the first internal receiver 41 under the above conditions.

The second internal receiving unit 42 is a data communication receiving unit provided inside the FPGA unit 40. The second internal receiver 42 has channels corresponding to the number of remaining channels (Channel[1] to Channel[N]) of the video supply unit 110. The second internal receiver 42 parallelizes the transmission data signals of the V-by-One system output from the remaining channels of the video supply unit 110 and converts them to the TTL system. That is, the second internal receiver 42 serves to change the transmission data signal of the serial transmission system input from the outside into the transmission data signal of the parallel transmission system. The transmission data signal converted by the second internal receiver 42 is transmitted to the data conversion unit 43.

The data conversion unit 43 serves to decode the TTL system transmission data signal output from the second internal receiver 42 so that it can be used by a device (eg, timing control unit) connected to the rear of the FPGA unit 40. The data conversion unit 43 transmits the parallel converted and decoded transmission data signal of the TTL system to the data alignment unit 45.

The data alignment unit 45 serves to align the TTL system transmission data signal output from the data conversion unit 43 and the TTL system transmission data signal output from the first internal receiving unit 41. The transmission data signals of the TTL system output from the data conversion unit 43 are parallelized, but alignment is required to uniformly output them to devices connected at a later stage. The data alignment unit 45 aligns transmission data signals that are distorted during parallelization, as shown in FIG. 6.

The above interface board 170 transmits only the V-by-One system transmission data signal output from one channel (CH*1) of the video supply unit 110 to the LVDS system from the outside of the FPGA unit 40, as shown in FIG. As an example, the transmission data signal of the V-by-One system converted and output from the remaining channels (CH*m, m is an integer greater than 2) is converted to the TTL system inside the FPGA unit 40, but the present invention It is not limited to this.

The interface board 170 configured as in the first embodiment restores the clock signal (Clock) by connecting the external receiver 30 optimized for the interfacing method of at least one channel. And the restored clock signal (Clock) is used as a reference clock signal (Reference Clock) required to drive the internal device of the FPGA unit 40.

As such, the first embodiment can provide an interface board that can converge clock frequency, data transfer rate, increase in bandwidth, etc. between devices because the frequency specification (Spec) range is wide. In addition, the first embodiment connects the external receiver 30 to at least one channel of the image supply unit 110, so that the device configuration can be minimized while enjoying advantages optimized for the interfacing method. In addition, the first embodiment has the advantage of being able to use a data signal (Data) in addition to restoring and using the clock signal (Clock).

<Second Embodiment>

Figure 9 is a block diagram schematically showing the interface board according to the second embodiment, Figure 10 is a diagram for explaining the function of the data alignment unit, Figure 11 is a diagram showing the data conversion system of the interface board, and Figure 12 is a diagram showing the data conversion system of the interface board. This is an example of pin allocation for the FPGA unit for connection to an external receiver.

As shown in FIGS. 9 to 12, the interface board 170 according to the second embodiment includes a switch unit (50, cross-point switch), an external receiver (30, external Rx), and an FPGA unit (40, FPGA). Includes.

The switch unit 50 serves to receive a transmission data signal output from one channel of the video supply unit 110, duplicate it at least in two, and output it. For example, the switch unit 50 receives the transmission data signal of the V-by-One system (first transmission system) output from the first channel (Channel[0]) of the video supply unit 110 and converts it into two identical signals. Copy and print. The switch unit 50 copies the transmission data signal of the V-by-One system (first transmission system) output from the first channel (Channel[0]) and outputs one through its first output terminal to the external receiver ( 30), and the remaining one is output through its second output terminal and delivered to the second internal receiver 42 of the FPGA unit 40.

The external receiver 30 receives the transmission data signal of the V-by-One system (first transmission system) output from the first channel (Channel[0]) output from the switch unit 50 and transmits it to the LVDS system (second transmission system). It plays the role of converting to a transmission system and outputting it. The external receiver 30 extracts and outputs only a clock signal (Clock) from the transmission data signal of the V-by-One system (first transmission system) output from the first channel (Channel[0]) received. The video supply unit 110 transmits a transmission data signal in a V-by-One system through a transmitter 115 (Tx) provided internally or externally.

In order to perform the above functions, the external receiver 30 may include, but is not limited to, a sample & hold for sampling a clock signal received from the outside, a phase lock loop (PLL) for generating its own clock signal, etc.

The external receiver 30 has a PLL (phase lock loop) that generates a clock signal, and can change the frequency in various ways in response to signals input from the outside (user needs). Therefore, the external receiver 30 can provide the advantage of setting the frequency specification (Spec) range of the clock signal (Clock) broadly.

The FPGA unit 40 functions to upscale and output the transmission data signal output from the video supply unit 110. For example, the FPGA unit 40 transmits the input transmission data signal to suit the high resolution supported by the display panel, such as upscaling the original HD (1280 × 720) transmission data signal to a transmission data signal of 4K UHD (3840 It may play the role of converting into a data signal, but is not limited to this. The FPGA unit 40 operates based on a clock signal (Clock) output from the external receiver 30. Therefore, the FPGA unit 40 may have the same operating characteristics as the external receiver 30.

The FPGA unit 40 includes a first internal receiver (41, LVDS Rx), a second internal receiver (42, PHY), a data conversion unit (43, interfacing L2), and a data alignment unit (45, Alignment FIFO). . Other control logic parts are omitted as they are unrelated to the interface.

The first internal receiving unit 41 is a data communication receiving unit provided inside the FPGA unit 40. The first internal receiver 41 converts the clock signal (Clock) of the LVDS system output from the external receiver 30 into the Transistor-Transistor Logic (TTL) system (third transmission system).

The clock signal output from the first internal receiver 41 is used as a reference clock signal that can be used inside the FPGA unit 40. The FPGA unit 40 can use the reference clock signal transmitted from the first internal receiver 41 as a clock signal required to drive the internal device (IP) or to restore the internal clock signal. .

The first internal receiver 41 receives only a clock signal (Clock) from the external receiver 30. For this reason, in the FPGA unit 40, if only a total of 2 input/output terminals (I/O) are allocated as shown in FIG. 12, the first internal receiver 41 can be used under the above conditions. That is, the second embodiment can use a total of 6 input/output terminals (I/O) for different purposes compared to the first embodiment.

The second internal receiving unit 42 is a data communication receiving unit provided inside the FPGA unit 40. The second internal receiver 42 has channels corresponding to the number of all channels (Channel[0] to Channel[N]) of the video supply unit 110. The second internal receiver 42 parallelizes the transmission data signals of the V-by-One system output from all channels of the video supply unit 110 and converts them to the TTL system. That is, the second internal receiver 42 serves to change the transmission data signal of the serial transmission system input from the outside into the transmission data signal of the parallel transmission system. The transmission data signal converted by the second internal receiver 42 is transmitted to the data conversion unit 43.

Meanwhile, due to the use and function of the switch unit 50, the second internal receiver 42 uses the V-by-One system (first transmission system) output from the first channel (Channel[0]) of the video supply unit 110. ) of the transmission data signal as well as the transmission data signals of the remaining channels (Channel[1] to Channel[N]) can be received.

The data conversion unit 43 serves to decode the TTL system transmission data signal output from the second internal receiver 42 so that it can be used by a device (eg, timing control unit) connected to the rear of the FPGA unit 40. The data conversion unit 43 transmits the parallel converted and decoded transmission data signal of the TTL system to the data alignment unit 45.

The data alignment unit 45 sorts the TTL system transmission data signals output from the data conversion unit 43. The transmission data signals of the TTL system output from the data conversion unit 43 are parallelized, but alignment may be necessary to uniformly output them to devices connected at a later stage. The data alignment unit 45 aligns transmission data signals that are distorted during parallelization, as shown in FIG. 10. The data alignment unit 45 serves to align the TTL system transmission data signals output from the data conversion unit 43, but this may be omitted.

The above interface board 170 transmits only the V-by-One system transmission data signal output from one channel (CH*1) of the video supply unit 110 to the LVDS system from the outside of the FPGA unit 40, as shown in FIG. 11. As an example, the transmission data signal of the V-by-One system converted and output from the remaining channels (CH*m, m is an integer greater than 2) is converted to the TTL system inside the FPGA unit 40, but the present invention It is not limited to this.

The interface board 170 configured as in the second embodiment restores the clock signal (Clock) by connecting the external receiver 30 optimized for interfacing only at least one channel. And the restored clock signal (Clock) is used as a reference clock signal (Reference Clock) required to drive the internal device of the FPGA unit 40.

As such, the second embodiment can provide an interface board that can converge clock frequency, data transfer rate, increase in bandwidth, etc. between devices because the frequency specification (Spec) range is wide. In addition, the second embodiment connects the external receiver 30 to at least one channel of the image supply unit 110, so that the device configuration can be minimized while enjoying advantages optimized for the interfacing method. In addition, since the second embodiment receives only the restored clock signal (Clock) from the external receiver 30, it uses fewer input/output terminals (I/O) than the first embodiment, so the remaining input/output terminals (I/O) are used. It has the advantage of being usable for other purposes.

The present invention has the effect of providing an interface board capable of converging clock frequencies, data transfer rates, increases in bandwidth, etc. between devices, and a high-resolution display device using the same. In addition, the present invention has the effect of providing an interface board that can minimize the configuration of the device while enjoying the advantages optimized for the interfacing method.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

110: video supply unit 120: timing control unit
130: data driver 140: gate driver
150: display panel 170: interface board
30: External receiver 40: FPGA unit
41: first internal receiving unit 42: second internal receiving unit
43: data conversion unit 45: data sorting unit

Claims (10)

Converting a transmission data signal of a first transmission system connected through at least one channel of an external device and transmitted through the at least one channel into a transmission data signal of a second transmission system, and extracting a clock signal and a data signal an external receiver that outputs the clock signal and includes a clock signal generator for extracting the clock signal; and
It operates with the same characteristics as the external receiver based on the clock signal output from the external receiver, is connected to the remaining channel of the external device, and transmits the transmission data signal of the first transmission system transmitted through the remaining channel of the external device. 3 An interface board including an FPGA unit that converts and outputs transmission data signals of the transmission system. According to paragraph 1,
The FPGA unit is,
It receives the clock signal and data signal of the second transmission system output from the external receiver, converts it into a transmission data signal of the third transmission system, and converts the converted clock signal and data signal of the third transmission system into its internal device. A first internal receiving unit that transmits to,
An interface board comprising a second internal receiver that receives the transmission data signal of the first transmission system transmitted through the remaining channel of the external device, converts it into a transmission data signal of the third transmission system, and outputs the transmission data signal. According to paragraph 2,
The FPGA unit is,
a data conversion unit that decodes the transmission data signal of the third transmission system;
An interface board comprising a data alignment unit that aligns the transmission data signal of the third transmission system output from the data conversion unit and the data signal output from the first internal reception unit. a video supply unit that outputs a transmission data signal of a first transmission system;
Converts the transmission data signal of the first transmission system connected through at least one channel of the video supply unit and transmitted through the at least one channel into a transmission data signal of the second transmission system, and converts a clock signal and a data signal. an external receiver that extracts and outputs the clock signal and includes a clock signal generator for extracting the clock signal;
It operates with the same characteristics as the external receiver based on the clock signal output from the external receiver, is connected to the remaining channel of the video supply unit, and transmits the transmission data signal of the first transmission system transmitted through the remaining channel of the video supply unit. 3 An interface board including an FPGA unit that converts and outputs transmission data signals of the transmission system;
a plurality of timing control units that receive transmission data signals of the third transmission system output from the interface board; and
A display device comprising a display panel that displays an image based on transmission data signals output from each of the plurality of timing control units. According to paragraph 4,
The FPGA unit is,
It receives the clock signal and data signal of the second transmission system output from the external receiver, converts it into a transmission data signal of the third transmission system, and converts the converted clock signal and data signal of the third transmission system into its internal device. A first internal receiving unit that transmits to,
a second internal receiver that receives the transmission data signal of the first transmission system transmitted through the remaining channel of the video supply unit, converts it into a transmission data signal of the third transmission system, and outputs it;
a data conversion unit that decodes the transmission data signal of the third transmission system;
A display device comprising a data alignment unit that aligns the transmission data signal of the third transmission system output from the data conversion unit and the data signal output from the first internal reception unit. a switch unit connected through at least one channel of an external device and copying and outputting at least two transmission data signals of a first transmission system transmitted through the at least one channel;
It is connected to the first output terminal of the switch unit, receives the transmission data signal of the first transmission system copied from the first output terminal, and converts the copied transmission data signal of the first transmission system into a transmission data signal of the second transmission system. An external receiver that extracts and outputs a clock signal and includes a clock signal generator for extracting the clock signal; and
A first transmission system that operates with the same characteristics as the external receiver based on the clock signal output from the external receiver, is connected to the second output terminal of the switch unit and the remaining channel of the external device, and is copied from the second output terminal. An FPGA that receives transmission data signals, receives transmission data signals of the first transmission system from the remaining channels of the external device, and converts all received transmission data signals of the first transmission system into transmission data signals of the third transmission system and outputs them. Interface board containing parts. According to clause 6,
The FPGA unit is,
A first internal unit that receives the clock signal of the second transmission system output from the external receiver, converts it into a transmission data signal of the third transmission system, and transmits the converted clock signal of the third transmission system to its internal device. With a receiving unit,
An interface board including a second output terminal of the switch unit and a second internal receiver that converts all transmission data signals of the first transmission system received from the remaining channels of the external device into transmission data signals of the third transmission system and outputs them. In clause 7,
The FPGA unit is,
a data conversion unit that decodes the transmission data signal of the third transmission system output from the second internal reception unit;
An interface board including a data alignment unit that sorts transmission data signals of the third transmission system output from the data conversion unit. a video supply unit that outputs a transmission data signal of a first transmission system;
a switch unit connected through at least one channel of the video supply unit and copying and outputting at least two transmission data signals of the first transmission system transmitted through the at least one channel;
It is connected to the first output terminal of the switch unit, receives the transmission data signal of the first transmission system copied from the first output terminal, and converts the copied transmission data signal of the first transmission system into a transmission data signal of the second transmission system. In addition, an external receiver that extracts and outputs a clock signal and includes a clock signal generator for extracting the clock signal,
A first transmission system that operates with the same characteristics as the external receiver based on the clock signal output from the external receiver, is connected to the second output terminal of the switch unit and the remaining channel of the video supply unit, and is copied from the second output terminal. An FPGA that receives transmission data signals, receives transmission data signals of the first transmission system from the remaining channels of the video supply unit, and converts all received transmission data signals of the first transmission system into transmission data signals of the third transmission system and outputs them. an interface board containing a unit;
a plurality of timing control units that receive transmission data signals of the third transmission system output from the interface board; and
A display device comprising a display panel that displays an image based on transmission data signals output from each of the plurality of timing control units. According to clause 9,
The FPGA unit is,
A first internal device that receives the clock signal of the second transmission system output from the external receiver, converts it into a transmission data signal of the third transmission system, and transmits the converted clock signal of the third transmission system to its internal device. With a receiving unit,
a second internal receiver that converts all transmission data signals of the first transmission system received from the second output terminal of the switch unit and the remaining channels of the video supply unit into transmission data signals of a third transmission system and outputs them;
a data conversion unit that decodes the transmission data signal of the third transmission system output from the second internal reception unit;
A display device comprising a data sorting unit that sorts transmission data signals of the third transmission system output from the data conversion unit.

Images