JP7330928B2 - Digital video signal generation circuit and system - Google Patents

Description

Embodiments relate to digital video signal generation circuits, systems, methods, and programs.

Liquid crystal panels and organic EL panels are used as screen panels for flat-panel televisions, which are receivers for digital television. Signal data transmission is increasing.

Normally, video signal data is transmitted to the image panel via lanes for serial data transmission, but in order to transmit video signal data for an increasing number of screens, it is configured with multiple lanes for serial data transmission, in which multiple lanes for serial data transmission are bundled. Flat cables or even multiple flat cables are used.

Japanese Patent No. 5290473 JP 2015-75495 A Japanese Patent No. 4529443

However, if the cable lengths (hereafter referred to as cable lengths) are different between different flat cables, a difference in reception timing (timing skew) occurs between video signal data for one screen on the screen panel, resulting in normal video display. may not be possible.

A problem to be solved by the present invention is to provide a digital video signal generation circuit, system, method, and program that eliminate the reception timing deviation of video signal data on a screen panel.

A digital video signal generation circuit according to one embodiment simultaneously receives a plurality of video signal data divided to display one video signal on a plurality of screens, and receives each digital video signal corresponding to the plurality of video signal data. to different serial transmission lines at different timings, wherein the delay amount of the serial transmission line having the longest transmission line among the plurality of serial transmission lines and the transmission of the other serial transmission lines A set delay amount to be added to the delay amount of the other serial transmission line is determined so that the time becomes the same.

FIG. 1 is a block diagram showing a functional configuration example of a receiver according to the first embodiment. FIG. 2 is a block diagram showing a functional configuration example of a lane group data signal output section of the receiving device according to the embodiment. FIG. 3 is a diagram showing an example of a screen display area of a screen panel according to the embodiment. FIG. 4 is a block diagram showing a functional configuration example of a lane data signal output section of the receiving device according to the embodiment. FIG. 5 is a block diagram showing a configuration example of a shift register of the receiving device according to the embodiment. FIG. 6 is a block diagram showing a functional configuration example of a lane group data receiving section of the receiving device according to the embodiment. FIG. 7 is a block diagram showing a physical configuration example related to transmission of a digital video signal of the receiving device according to the embodiment. FIG. 8 is a block diagram showing a physical configuration example of a screen panel of the receiving device according to the embodiment. FIG. 9 is an example of transmission/reception of a digital video signal in the receiving device according to the second embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
In this embodiment, for example, when the display screen of 8K video is divided into a plurality of pieces and the data of each divided display screen is assigned to a different cable and transmitted, the output timing of the digital video signal transmitted by each cable is adjusted according to each cable length.

Normally, image data consists of data of 1 symbol=8 bits for each pixel color (RGB). An example of adjusting the output timing (delay time) of the digital video signal by grouping these for each screen lane group (cable) in units of symbols will be shown.

FIG. 1 is a block diagram showing a functional configuration example of a receiver according to the first embodiment.
The image data acquisition unit 1 is, for example, a receiver for digital television broadcasting, receives broadcast signals of advanced wideband satellite digital broadcasting (4K/8K broadcasting), and acquires video signals (data relating to video content). Also, the signal is not limited to a broadcast signal, and may be a video signal for digital television broadcasting obtained from a storage medium such as a DVD or a hard disk, or the Internet.

The tuner unit 11 receives and processes broadcast signal radio waves in a desired frequency band via an antenna (not shown) or a coaxial cable for cable broadcasting.

The demodulator 12 extracts data relating to the video signal from the digital data obtained by demodulating the broadcast signal radio wave.

The video signal processing unit 13 performs data processing such as decoding by a prescribed method on the data related to the video signal extracted by the demodulation unit 12, and acquires the video signal.

The image data processing unit 2 performs data processing on the video signal output from the video signal processing unit 13 for the purpose of improving the image quality, dividing the image data, and the like.

The image processing unit 21 performs data processing on the video signal output from the video signal processing unit 13 for the purpose of improving the resolution, improving the frame rate, adjusting the image quality, etc., and performs data processing for displaying the video on the screen panel unit 421 . Outputs video signal data. These methods are common methods, and the details are omitted.

The image dividing unit 22 divides the video signal data for each predetermined area on the screen panel unit 421 (referred to as a screen panel area) and outputs the data. As a result, the video signal data can be transmitted in parallel for each screen panel area, which contributes to shortening the transmission delay. Each piece of divided video signal data output by the image dividing section 22 is referred to as screen lane group data. The screen lane group data are transmitted through separate transmission paths. FIG. 1 shows an example in which each screen lane group data is transmitted from the image division unit 22 through four transmission paths. The screen panel area will be described later.

The image data transmission unit 3 receives the screen lane group data output from the image division unit 22, and transmits the screen lane group data, that is, the divided video signal data to the screen display unit 4 via an interface for serial transmission. . Here, a lane is a transmission method using one serial transmission line (called a serial transmission line), which is the minimum unit of a transmission line for serial data transmission, and is also called a serial lane. A method of transmitting data using a plurality of serial lanes is called multi-lane. Multi-lanes are used when there is more data transmission than the serial lanes can handle. However, due to the recent increase in size of the screen panel, the amount of data per screen has increased further, and a situation has arisen in which even multi-lanes cannot be used. In the present embodiment, a method that uses a plurality of multi-lanes to deal with such a situation is adopted. Further, in the present embodiment, each multilane in the method using a plurality of multilanes is referred to as a screen lane group.

The lane group data signal output units 31-1, 31-2, 31-3, and 31-4 convert the screen lane group data (divided video signal data) input from the image division unit 22 into parallel data. A digital video signal is generated by performing serial conversion, encoding, and the like, and the digital video signal is output to interfaces 5-1, 5-2, 5-3, and 5-4, respectively. Note that the functions of the lane group data signal output units 31-1, 31-2, 31-3, and 31-4 are the same. called.

The image display unit 4 receives the digital video signal for each screen lane group, displays the video content on the screen unit 42, and allows the user to view the video content.

Lane group data receivers 41-1, 41-2, 41-3, and 41-4 receive digital video signals transmitted by lane group data signal output units 31-1, 31-2, 31-3, and 31-4, respectively. are received via the interface units 5-1, 5-2, 5-3 and 5-4, respectively. Note that the lane group data receiving units 41-1, 41-2, 41-3, and 41-4 have the same functions, and will be referred to as the lane group data receiving unit 41 to indicate each of them unless the functions are distinguished. . Each lane group data receiving section 41 reproduces the screen lane group data from the digital video signal and outputs it to the screen section 42 .

The screen unit 42 is a monitor, and particularly in the present embodiment, it is a large-sized monitor of a flat-screen television for digital television such as a liquid crystal panel or an organic EL panel. The screen unit 42 receives video signal data from the lane group data receiving units 41-1, 41-2, 41-3, and 41-4, controls an image panel by a panel driver or the like based on the video signal data, and displays an image. Display content and present video content to the user.

The delay amount measuring unit 45 has a function of measuring a delay amount between screen lane group data. The measured delay amount is used as the set delay amount set in the lane group data signal output section 31 . The set delay amount is a delay amount added to the output timing of the digital video signal, and will be described later.

The communication unit 46 exchanges data between the image display unit 4 and the image data transmission unit 3 using a communication method such as I2C.
The delay amount comparison unit 47 compares the delay amount between each screen lane group data calculated from the arrival timing of each screen lane group data by the delay amount measurement unit 45, for example, and transmits the delay difference to the control unit 6 via the communication unit 46. Send to The control unit 6 sets the received delay difference as the set delay amount for each lane group data signal output unit 31 .

The interface units 5-1, 5-2, 5-3, and 5-4 are, for example, flat cables for serial data transmission, and are serial cables for transmitting digital video signals from the image data transmission unit 3 to the image display unit 4. A bundle of transmission lines. The interface unit 5 includes a protocol for transmitting digital video signals, and in this embodiment, Vbyone (registered trademark), which is a standard for serial data transmission, is applied.

Vbyone is a serial data transmission standard typically used for transmitting digital video signals to a screen panel or the like, and includes a pair of differential lines. A pair of differential lines (serial transmission lines) corresponds to a lane, and a flat cable bundled with a plurality of (for example, 16 in this embodiment) serial transmission lines corresponds to a screen lane group (multi-lane). do. Since Vbyone is a commonly used technique, details thereof will be omitted. The functions of the interface units 5-1, 5-2, 5-3, and 5-4 are the same, and when the functions are not distinguished, they are referred to as the interface unit 5 to indicate each.

According to the Vbyone standard, since a clock can be generated on the receiving side from data transmitted on each serial transmission line, each lane can have its own clock. Further, according to the Vbyone standard, if the generated clock cycle is UI, the timing deviation of the clock cycle between the lanes on the Vbyone receiving side is suppressed to 5 UI. Specifically, in 8K television, 1 UI is about 350 ps, and it must be suppressed within 5 UI≈1.7 ns.

Even if the timing deviation of the clock cycle of each lane is kept small, the data reception timing deviation on the receiving side of Vbyone may pose a problem. Specifically, assuming that the dielectric constant is 1, which is the same as that of air, and the speed at which an electric signal is transmitted is 3×10 8 /s, the propagation distance for one clock is about 100 mm. Since the propagation distance is even shorter for printed circuit boards and flat cables with high dielectric constants, if the pattern design on the printed circuit board or the length of the cable that connects the boards differs, a difference in data reception timing (timing skew) will occur between the cables. there is a possibility.

In this embodiment, as shown in FIG. 1, interface units 5-1, 5-2, 5-3, and 5-4 (corresponding to flat cables) having different cable lengths are used. In this case, the lengths are the same within one screen lane group (within the flat cable), but the length may be different for each screen lane group (between the flat cables). Skew is likely to occur. In this embodiment, the timing skew is eliminated by adjusting a symbol data clock (symbol clock), which will be described later.

The control unit 6 sets, to each lane group data signal output unit 31, a set delay amount for changing the output timing of the digital video signal output from each lane group data signal output unit 31. FIG. The set delay amount may be calculated by the user from the difference in cable length between the interfaces 5-1, 5-2, 5-3, and 5-4. For example, the set delay amount is set to 0 for the lane group data signal output section 31 of the interface section 5 having the longest cable length. For the other lane group data signal output units 31, the cable length (transmission time) of the connected interface unit 5 and the set delay amount are added so that the transmission time is the same as the longest transmission time of the interface unit 5. Determine the set delay amount. The determined set delay amount may be set in each lane group data signal output unit 31 via the control unit 6 from a user interface such as a personal computer keyboard or a television remote control (not shown), for example.

In addition, the control unit 6 is provided with video signal data input to each lane group data signal output unit 31 (referred to as input video signal data) and video signal data output from the lane group data receiving unit 41 (output video signal data). ), and the controller 6 compares the input video signal data and the output video signal data to adjust and determine the set delay amount.
For example, it is also possible to set a set delay amount that matches the input video signal data and the output video signal data from the control section 6 to each lane group data signal output section 31 .

Alternatively, a method using learning by artificial intelligence or the like may be used. Specifically, each lane group data signal output unit 31 is operated by giving an appropriate intermediate delay amount as a set delay amount. Compare the input video signal data and the output video signal data of one of the group lanes, and if it is confirmed that the movement is correct, adjust the set delay amount of the other group lanes to match the input video signal data and the output video. Compare with signal data to confirm correct movement. By performing this for all group lanes, the set delay amount for all group lanes is determined and set to each lane group data signal output section 31 .

The control unit 6 and the image data transmission unit 3 or the image display unit 4 may exchange data by a communication method such as I2C.

FIG. 2 is a block diagram showing a functional configuration example of a lane group data signal output section of the receiving device according to the embodiment.
The lane group data division unit 311 divides the screen lane group data (divided video signal data) input from the image division unit 22 and outputs the data as digital video signals to a plurality of serial transmission lines. The data output by the lane group data division unit 311 is called lane data. By dividing the data into lane data, it is possible to transmit the screen lane group data even when the transmission speed of a single serial transmission line is limited.

Lane data signal output units 312-1, 312-2, and 311-NL respectively generate digital video signals for output to serial transmission lines. NL is the maximum number of lanes to which one screen lane group data can be distributed, and corresponds to the number of serial transmission lines in the flat cable. In this embodiment, NL is 16. Since the lane data signal output units 312-1, 312-2, and 311-NL have the same functions, they are referred to as lane data signal output units 312 unless their functions are distinguished.

Each lane data signal output unit 312 generates a digital video signal from the lane data input from the lane group data division unit 311 according to the protocol of the interface unit 5 and outputs the digital video signal to the interface unit 5 .

FIG. 3 is a diagram showing an example of a screen display area of a screen panel according to the embodiment.
The screen panel areas 421-1, 421-2, 421-3 and 421-4 respectively correspond to screen lane group data. That is, a screen panel of the screen unit 42 (for example, a screen panel unit 421 to be described later) is divided into four screen panel areas 421-1, 421-2, 421-3, and 421-4, and pixels in each screen panel area are Let each information be screen lane group data. Note that the screen panel areas 421-1, 421-2, 421-3, and 421-4 are similar areas within the screen panel, and will be referred to as the screen panel area 421 in the sense that they are individually indicated unless otherwise distinguished.

Scanning paths 4211-1, 4211-2, 4211-3 and 4211-4 schematically show scanning line paths in the screen panel areas 421-1, 421-2, 421-3 and 421-4 respectively. . The scanning paths 4211-1, 4211-2, 4211-3, and 4211-4 are paths of similar scanning lines, and will be referred to as the scanning paths 4211 in the sense that they are individually indicated unless otherwise distinguished.

The scanning path 4211 is composed of solid line arrows and dotted line arrows, and the solid line arrows indicate scanning lines. Dotted arrows indicate movement between scanlines. For example, it indicates that the screen panel of the screen unit 42 is scanned from left to right in order from the uppermost solid line arrow (scanning line). Scanning is performed for each screen panel area 421-1, 421-2, 421-3, 421-4 respectively. Although only 10 scanning lines are shown in each screen panel area 421 in FIG. 3, there are actually 4000 lines corresponding to the corresponding pixels of the digital television.

The reason for dividing as the screen panel area is detailed below. Due to the recent enlargement of digital televisions, the number of pixels per screen is increasing. Although the digital video signal of a digital television is originally a signal that is transmitted through a single serial data transmission lane, the image screen display cycle (hereinafter referred to as the frame rate) does not change, so an increase in the number of pixels does not affect digital video. It means that the frequency of the signal increases. For example, if the frame rate is 120 Hz, the number of pixels is 7680 × 4320, and the resolution is 8 bits for each color of RGB, and the video signal data is converted to 8B10B, the image data is generated at a clock frequency of about 150 GHz. It must be transferred from the transmission unit 3 to the screen display unit 4 . In practice, since margins are provided for the synchronizing signal and the screen, the frequency becomes higher, and it becomes physically impossible to transmit the digital video signal over one serial transmission line. In this embodiment, the 8K screen is divided into four so that data can be handled independently, and further, for example, a bundle of 16 serial transmission lanes is bundled as a screen lane group to form four screen lane groups (4 If digital video signals are sent to each of the four divided screen panel areas using one flat cable), the clock frequency will drop to about 3 GHz even if the margins on the format are included, so data transfer is possible. become.

Data of each pixel of each screen panel area 421 is output to each lane group data signal output section 31 in order of the scanning path 4211 . The data for each pixel includes R, G and B symbol data. Symbol data is bit data assigned to each of R, G, and B of one pixel (picture element). Normally, in the case of a video image by 8K broadcasting, for example, symbol data of R, G, and B are each composed of 8-bit data.

Pixels 4212-1, 4212-2, 4212-3 and 4212-4 are examples of pixels on screen panel areas 421-1, 421-2, 421-3 and 421-4 respectively. Pixels 4212-1, 4212-2, 4212-3, and 4212-4 are examples of similar pixels, and will be referred to as pixels 4212 in the sense that they are individually indicated unless otherwise distinguished.

Three pixels (P11, P12, P13), (P21, P22, P23), (P31, P32, P33), (P41, P42, P43) are shown as examples of pixels for each of the four screen panel areas 421, respectively. , and is output from the screen dividing unit 22 in the order of the scanning path 4211 for each screen panel area 421 . These pixel data are input to the lane group data signal output section 31 at the same time. Specifically, the data of the pixels P11, P21, P31, and P41 for each screen panel area 421 are simultaneously input to each lane group data signal output section 31, and the lane data signal output section of each lane group data signal output section 31 312-1 at the same timing. For example, when the data of the pixels (P11, P12, P13) are input to the lane group data signal output section 31-1, the pixels (P11, P12, P13) are output to the lane data signal output sections 312-1, 312-2, respectively. , 312-3. Although an example of three pixels is shown here, data of NL pixels are input to lane data signal output units 312-1 to 312-NL, respectively.
The data of these pixels P11, P21, P31, and P41 must be output from the lane group data receiving section 41 at the same timing and input to the screen section 42 at the same timing.

FIG. 4 is a block diagram showing a functional configuration example of a lane data signal output section of the receiving device according to the embodiment.
The symbol data output unit 3121 divides the lane data input from the lane group data division unit 311 into R, G, and B symbol data and outputs the R, G, and B symbol data. The symbol data output section 3121 outputs symbol data at the timing of the input symbol clock. A symbol clock is a time interval for processing data of one pixel (one symbol data for each of R, G, and B).

Each of the shift registers 3122-1, 3122-2, and 3122-NSR is a one-stage shift register in which, for example, NFF flip-flops are arranged in parallel. NFF is the number of flip-flops. Since the shift registers 3122-1, 3122-2, and 3122-NSR have similar functions, they are referred to as the shift register 3122 to indicate each of them unless the functions are distinguished. NSR is the number of shift registers.
The shift register 3122 is a shift register that operates at the timing of the input symbol clock. Specifically, the shift register 3122 outputs flip-flop data at the same time that data of one pixel (one symbol data of each of R, G, and B) is input. Input data of one pixel (one symbol data of each of R, G, and B) is input to a flip-flop. That is, the shift registers 3122-1, 3122-2, and 3122-NSR cause the data output of one pixel (one symbol data for each of R, G, and B) to be output with a delay time in units of symbol clocks (up to NSR symbol clocks). delay time) can be given.

FIG. 5 is a block diagram showing a configuration example of a shift register of the receiving device according to the embodiment.

One symbol data (8 bits) of each screen lane group is input in parallel to the shift register 3122 at the timing of the symbol clock. Data output from the flip-flop (FF) and data input to the FF are performed simultaneously at the timing of the symbol clock.

Returning to FIG. 4, the selector unit 3123 determines which of the shift registers 3122-1, 3122-2, and 3122-NSR outputs the output from the shift register to the subsequent stage, and outputs the output of the determined shift register to the subsequent stage. Output. In the selector unit 3123 of the present embodiment, the set delay amount input from the control unit 6 to each lane group data signal output unit 31 is set. A register is selected as a shift register to be output to a subsequent stage. In this embodiment, all lane data signal output units 312 in each lane group data signal output unit 31 are set to the same set delay amount.

The parallel-serial conversion unit 3124 converts the output (parallel data of R, G, and B data bits for one pixel) from any of the shift registers 3122-1, 3122-2, and 3122-NSR determined by the selector unit 3123 into serial data. Convert to data (also called serial lane data).

The 8B10B converter 3125 performs 8B10B conversion on the serial lane data input from the parallel-serial converter 3124 and outputs the converted serial lane data (referred to as converted serial lane data). 8B10B conversion (also referred to as 8B10B modulation) is a general encoding scheme, and detailed description thereof will be omitted.

The interface unit 3126 converts various data, generates frame data, generates signals, etc. according to the protocol of the interface unit 5 for the converted serial lane data input from the 8B10B conversion unit 3125, and generates a digital video signal. , and outputs the generated digital video signal to the interface unit 5 . In this embodiment, since Vbyone is applied to the interface unit 5 , the interface unit 3126 generates a digital video signal according to the Vbyone protocol and outputs it to the interface unit 5 . The Vbyone clock required at the Vbyone receiver is determined by the number of bits transmitted on the serial transmission line. The Vbyone clock is simply ten times or more the symbol clock.

Since the shift register 3122 is operated by the symbol clock as described above, the delay amount actually added to the output timing of the digital video signal with respect to the set delay amount is an integral multiple of the symbol clock.

In the present embodiment, the shift register 3122, the parallel-serial conversion unit, the 8B10B conversion unit, and the interface unit are described for each lane data signal output unit 312, but one for each lane group data signal output unit 31. The shift register 3122, the parallel-serial conversion unit, the 8B10B conversion unit, and the interface unit may be installed and shared by each lane data signal output unit 312.

FIG. 6 is a block diagram showing a functional configuration example of a lane group data receiving section of the receiving device according to the embodiment.
The lane data receiving units 411-1, 411-2, and 411-NL receive digital video signals from the interface unit 5, convert various data, and output lane data. Lane data receivers 411-1, 411-2, 411-NL receive digital video signals output from lane data signal output units 312-1, 312-2, 312-3, 312-4, respectively. NL indicates the number of lanes in each interface unit 5, and NL=16 in this embodiment. Note that the lane data reception units 411-1, 411-2, and 411-NL have similar functions, and will be referred to as lane data reception units 411 in the sense that they are individually indicated unless otherwise distinguished.

The lane data reception unit 411 includes an interface unit (not shown), a serial-parallel conversion unit, and an 8B10B decoding unit corresponding to the interface unit 3126, 8B10B conversion unit 3125, and parallel-serial conversion unit 3124 of the lane data signal output unit 312, respectively. .

The interface unit of the lane data receiving unit 411 receives the digital video signal received from the interface unit 5 by a receiving method corresponding to the protocol of the interface unit 3126 (in this embodiment, a receiving method according to the Vbyone protocol), and converts it to serial data. Lane data is obtained and output to the 8B10B decoding unit. The 8B10B decoder outputs serial lane data from the input converted serial lane data according to the 8B10B modulation protocol. The serial-parallel converter converts serial lane data into parallel lane data and outputs the parallel lane data.

The lane group data output unit 412 reproduces screen lane group data from the lane data output by each lane data reception unit 411, and outputs the screen lane group data to the screen unit 42 at predetermined timing.

In this embodiment, since each converted serial lane data received by the interface section of each lane data receiving section 411 is synchronized, the serial lane data output by each lane data receiving section 411 are also synchronized. . Furthermore, the screen lane group data output from each lane group data receiving section 41 is also synchronized among the screen lane group data. Specifically, P11, P21, P31, and P41 in FIG. 3 are output from each lane group data receiver 41 at the same time. This is because the selector section 3123 of each lane group data output section 31 changes the output timing of the digital video signal for each screen lane group data.

FIG. 7 is a block diagram showing a physical configuration example related to transmission of a digital video signal of the receiving device according to the embodiment.

The video signal generation board 33 includes, for example, the functions of the lane group data signal output section 31 of the image data transmission section 2 and the image data transmission section 3, processes the received video signal, and outputs a digital video signal.

The panel display control board 43 includes the function of the lane group data receiving section 41 and includes pixel driving elements that control the pixels of the screen panel 421 .

Flat cables 53-1, 53-2, 53-3 and 53-4 correspond to interface sections 5-1, 5-2, 5-3 and 5-4, respectively.

As televisions become larger and have higher definition, the difference in the length of flat cables corresponding to each screen lane group tends to increase. In this embodiment, the selector unit 3123 changes the output timing of the digital video signal output from the video signal generation board 33 in consideration of the set delay amount of the flat cable set for each screen lane group. By matching the timing of the digital video signal input to the panel display control board 43, the difference in the length of the flat cable is absorbed.

In the present embodiment, an example is shown in which the delay amount is set in units of symbol clocks for each parallel data (a state in which the bits of symbol data are parallel). A video signal has symbol data (for example, 8 bits) for one video point (pixel) on the screen. The video signals are processed as parallel data because the processing such as image quality improvement is performed on a unit-by-unit basis. Parallel data processing uses a symbol clock, which is slower than the Vbyone clock (for example, 1/8 of the Vbyone clock). In this embodiment, the symbol clock is used to delay the output of pixel data by the shift register in units of symbol clock time, and the selector unit 3123 determines which stage of the shift register pixel data is to be used as output data. Thus, the amount of delay with respect to the output timing was determined.

It is also possible to use a shift register using the Vbyone clock instead of the symbol clock to add the delay amount. In this case, the FFs are serially connected instead of parallel flip-flops FFs as in the shift register 3122 . However, when the FFs are serially connected, the shift register must operate faster than the parallel shift register 3122 . That is, when trying to set a delay amount with a shift register for serial data, there is a drawback that the clock of the shift register is fast and the number of stages increases. Also, if there are many circuits that operate with a high-speed clock, power consumption and layout design within the IC become difficult.

As in the present embodiment, the time skew of the digital video signal can be eliminated by adjusting the delay amount for each screen lane group in units of symbol clock time using the selector unit 3123 . Further, if the adjustment is performed in units of symbol clock time, there is an effect of ensuring the accuracy of ±5 UI with respect to the "reference lane" defined by Vbyone between screen lane groups.

FIG. 8 is a block diagram showing a physical configuration example of a screen panel of the receiving device according to the embodiment.

The screen section 42 includes an image panel section 421 and a panel driver 422, and is, for example, a liquid crystal panel or an organic EL panel.

The image panel section 421 is a section that provides images to the user as audiovisual information by controlling the RGB light sources and the like for each pixel by the panel driver 422 .

The panel driver 422 receives the screen lane group data from the lane group data output unit 412 and controls the display of the image panel unit 421 according to the screen lane group data. Specifically, the panel driver 422 executes display control for the area of the image panel section 421 corresponding to the received screen lane group data.

The BEP 310, T-CON 410, and transmission line 510 are shown as dotted lines because they are installed behind the image panel unit 421, that is, on the unviewable side. The T-CON 410 is installed in the lower center of the image panel section 421, and the BEP 310 is placed next to the T-CON 410. FIG.

The BEP 310 is a post-processing circuit (Back End Processor) for the screen display section 4 and includes the functions of the image data transmission section 3 .

The T-CON 410 is included in the lane group data receiving section 41 and is a timing controller that controls the timing at which the lane group data output section 412 outputs screen lane group data to the panel driver 422 .

A transmission line 510 is a digital video signal transmission line that connects the BEP 310 and the T-CON 410, and includes all flat cables 53-1, 53-2, 53-3, and 53-4.

In this embodiment, the screen lane group data output from each lane group data receiving unit 41 of the T-CON 410 is synchronized between each lane group data. This is because the selector section 3123 of each lane group data output section 31 of the image data transmission section 3 changes the output timing of the digital video signal for each screen lane group data. Therefore, there is no timing shift (timing skew) between the screen lane group data output from each lane group data receiving section 41, and no display problem occurs.

As shown in FIG. 7, in a panel-type television such as a flat-screen television, each pixel element of the screen panel 421 is driven ( control) and the panel display control board 43 (including the T-CON 410). A desired image cannot be displayed on the screen panel 421 if there is a difference between the reception timings of the digital video signals transmitted between the two circuit boards between the screen lane groups. If the number of pixels has a resolution of about 4K, it can be transmitted over a single flat cable with a clock rate of about 3 GHz and 16 lanes, so the fluctuation range of the timing skew does not increase.

On the other hand, in the case of a single large panel compatible with large high-definition televisions such as 8K televisions, it is necessary to divide the screen (vertical division or horizontal division) in order to efficiently apply signals to each element of the panel. It becomes possible. When the screen is divided in an 8K television or the like, the video signal data of each divided screen is simultaneously transmitted from the BEP 310 using a plurality of flat cables.

However, if there is variation in the cable length of the flat cable, a problem (timing skew) occurs in which the reception timing of the digital video signal shifts, and this problem becomes significant during high-speed transmission such as 8K television.

The present embodiment described above solves the problem of timing skew caused by variations in cable length that occurs in large-sized high-definition televisions. In addition, according to this embodiment, it is not necessary to match the cable lengths of different flat cables, the degree of freedom regarding the structural design of the television and cable routing is increased, and the performance and manufacturing cost can be reduced. In this embodiment, one symbol is explained as 8 bits, but it goes without saying that this can easily be extended to 10 bits and 12 bits.

(Second embodiment)
If the length of the flat cable of each screen lane group (for example, the interface units 5-1, 5-2, 5-3, 5-4) differs, not only the transmission delay time but also the characteristics of the cable will change. When the characteristics of the cable change, the state of waveform distortion of the digital video signal transmitted by the cable changes. The state of waveform distortion depends on the length of the flat cable. The waveform distortion causes the waveform of the digital video signal to become dull, which affects the reception timing of the digital video signal. That is, a difference in cable length between flat cables through which each screen lane group data is transmitted leads to a difference in waveform distortion state, and causes a difference in the transmission delay time of the transmitted digital video signal. In this embodiment, an example will be described in which this problem is solved by changing the degree of pre-emphasis in the Vbyone driver according to the set delay amount (cable length) for each screen lane group.

FIG. 9 is an example of transmission/reception of a digital video signal in the receiving device according to the second embodiment.

The lane group video signal output units 331-1, 331-2, 331-3, and 331-4 have the same function as the lane group data signal output unit 31 in FIG. 1 for each screen lane group. Unlike the lane group data signal output section 31 in FIG. 1, this figure shows only the functions for one lane data in the lane group data signal output section 31, but includes the functions for all lane data. The lane group video signal output units 331-1, 331-2, 331-3, and 331-4 receive screen lane group data for each image panel area from the image dividing unit 22, respectively, and output digital video signals for each lane. Output. Note that since the lane group video signal output units 331-1, 331-2, 331-3, and 331-4 have the same function, the lane group video signal output units 331-1, 331-2, 331-3, and 331-4 refer to the individual lane group video signal output units unless otherwise specified. called.

The delay units 3311-1, 3311-2, 3311-3, and 3311-4 respectively control the output timing of the digital video signal of the input lane data and output them as parallel data. Since the delay units 3311-1, 3311-2, 3311-3, and 3311-4 have the same function, they are individually referred to as the delay unit 3311 unless otherwise specified. Each delay section 3311 includes functions similar to those of the shift register 3122 and selector section 3123 in FIG.

The Vby1 drivers 3312-1, 3312-2, 3312-3, and 3312-4 respectively correct the output waveform of the digital video signal for the input serial lane data, if necessary, and output it. The operation of correcting the output waveform of the digital video signal is called pre-emphasis. Pre-emphasis is a common technique, and a specific method is omitted. Since the Vby1 drivers 3312-1, 3312-2, 3312-3, and 3312-4 have similar functions, they will be referred to as Vby1 drivers 3312 in the sense that they are individually indicated unless otherwise distinguished.

The Vby1 driver 3312 is included in, for example, the interface section 3126 in FIG. Although FIG. 9 does not show the parallel-serial converter 3124 and 8B10B converter 3125 in FIG. 4, FIG. 9 also includes similar functions. Therefore, data input to the Vby1 driver 3312 is serial data output by a function corresponding to the 8B10B conversion section 3125 .

Flat cables 53-1, 53-2, 53-3 and 53-4 correspond to interface units 5-1, 5-2, 5-3 and 5-4 in FIG. -2, 3312-3, and 3312-4 are transmitted in accordance with the Vbyone protocol, and are, for example, flat cables. In the figure, only one pair of differential lines (one serial transmission line) is shown for each of the flat cables 53-1, 53-2, 53-3, and 53-4, but each has a plurality of serial transmission lines (not shown). It has a transmission line. In this embodiment, each of the flat cables 53-1, 53-2, 53-3 and 53-4 has 16 differential lines (multilane). Since the flat cables 53-1, 53-2, 53-3, and 53-4 have the same function, they are referred to as flat cables 53 unless otherwise specified.

Output signals 51-1, 51-2, 51-3, and 51-4 are examples of digital signal waveforms output by lane group video signal output units 331-1, 331-2, 331-3, and 331-4, respectively. showing. Since the output signals 51-1, 51-2, 51-3, and 51-4 are similar signals, they are referred to as the output signal 51 in the sense that they are individually indicated unless otherwise distinguished.

Input signals 52-1, 52-2, 52-3, and 52-4 are digital video signals output by lane group video signal output units 331-1, 331-2, 331-3, and 331-4, respectively. Examples of waveforms immediately before reaching the panel display control board 43 via the flat cables 53-1, 53-2, 53-3 and 53-4 are shown. Since the input signals 52-1, 52-2, 52-3, and 52-4 are similar signals, they will be referred to as input signals 52 in the sense that they are individually indicated unless otherwise distinguished.

The panel display control board 43 is the same as that described with reference to FIG.

FIG. 9 shows an example in which the flat cables 53 have different cable lengths. Each delay unit 3311 adds a delay to the output timing of the digital video signal according to the cable length of each flat cable 53 connected. Specifically, since the cable length increases in the order of the flat cables 53-1, 53-2, 53-3 and 53-4, the delay units 3311-1, 3311-2, 3311-3 and 3311-4 , the amount of delay added to the output timing of the digital video signal is increased. Here, it is assumed that each serial transmission line in each flat cable 53 has a negligible length difference, and the set delay amount for the selector section 3123 in the delay section 3311 is the same value. The set delay amount determined for each lane group video signal output unit 331 is set in the selector unit 3123 of each delay unit 3311 . The selector unit 3123 determines the shift register 3122 to output the lane data based on the set delay amount.

Next, since the degree of deterioration of the waveform of the digital video signal depends on the cable length of each flat cable 53 through which the digital video signal is transmitted, the cable length of the flat cable 53 to which each Vby1 driver 3312 is connected is The waveform of the output signal 51 is corrected in accordance with . Specifically, the Vby1 drivers 3312-1, 3312-2, 3312-3 and 3312-4 are such that the waveforms of the input signals 52-1, 52-2, 52-3 and 52-4 are as shown in FIG. The output signals 51-1, 51-2, 51-3 and 51-4 are corrected so as to be similar. In the example of FIG. 9, since the cable length increases in the order of flat cables 53-1, 53-2, 53-3 and 53-4, Vby1 drivers 3312-1, 3312-2, 3312-3 and 3312-4 In order, increase the waveform correction amount (increase pre-emphasis).

The waveform correction amount for each of the Vby1 drivers 3312 - 1 , 3312 - 2 , 3312 - 3 and 3312 - 4 may be determined by, for example, the control unit 6 and set to each Vby1 driver 3312 . The waveform correction amount may be determined by the user and set in the control unit 6 from a user interface (not shown). Alternatively, the control unit 6 may determine the waveform correction amount while comparing the input video signal data and the output video signal data of each lane group data signal output unit 31 and set it to each Vby1 driver 3312 . Alternatively, the control unit 6 may determine the correction amount of the waveform using a method using learning by artificial intelligence or the like, and set it to each Vby1 driver 3312 .

The method of determining the set delay amount and the waveform correction amount is as follows. Then, the corresponding lane group data signal receiving unit 41 on the receiving side reports the data reception timing to the transmitting side, so that the control unit 6 on the transmitting side grasps the delay amount and determines the delay amount and/or waveform for the screen lane group It is characterized in that the set value of the correction amount can be changed. As the data from which the amount of delay of the screen lane group can be known, cue data (also referred to as a synchronization code) transmitted by serial transmission can be used. By detecting the synchronization code and measuring the detection time difference for each screen lane group, the delay amount based on the detection time difference is set in the selector section 3123 of each lane group data signal output section 31 as the set delay amount.

With the above procedure, when the length of the flat cable that is the transmission line of each screen lane group is different, even if the state of waveform distortion due to the characteristics of the cable as well as the transmission delay time is different, each flat cable can be used. It is possible to eliminate the reception timing deviation in the panel display substrate 43 of the transmitted digital video signal and eliminate the output timing deviation of the screen lane group data to be output to the screen panel.

Waveform distortion occurs in the transmitted digital video signal under the influence of the inductance component and the capacitance component due to the length of the cable. This distortion mainly appears as a dull rise of the waveform, but this is prevented by a technique called pre-emphasis, which emphasizes the rise of the signal before transmission. However, doing this raises the high frequency components on the cable, which may increase the noise of the entire system, so it is common not to raise it unnecessarily. Therefore, it is not preferable to apply similar pre-emphasis to all screen lane groups. According to the present embodiment, since pre-emphasis is performed according to the length of the cable (flat cable 53) transmitted for each screen lane group, the absolute amount of high frequency components can be reduced. This has the effect of suppressing an increase in noise.

According to at least one embodiment described above, it is possible to provide a digital video signal generation circuit, system, method, and program that eliminate the reception timing deviation of video signal data on a screen panel.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof. Furthermore, in each constituent element of the claims, even if the constituent element is divided and expressed, a plurality of constituent elements are expressed together, or a combination of these is expressed, it is within the scope of the present invention. Moreover, a plurality of embodiments may be combined, and examples configured by such combinations are also within the scope of the invention.

Also, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual mode. In the block diagram, data and signals may be exchanged between unconnected blocks, or between connected blocks in directions not indicated by arrows. Each function shown in the block diagram and the process shown in the flow chart and sequence chart can be implemented by hardware (IC chip, etc.), software (program, etc.), arithmetic chip for digital signal processing (Digital Signal Processor, DSP), or these hardware. It may be realized by a combination of hardware and software. In addition, when the claims are expressed as control logic, when expressed as a program including instructions to be executed by a computer, and when expressed as a computer-readable recording medium in which the instructions are written, the apparatus of the present invention is applied. be. Also, the names and terms used are not limited, and other expressions are included in the present invention as long as they have substantially the same content and the same meaning.

DESCRIPTION OF SYMBOLS 1... Image data acquisition part 2... Image data processing part 3... Image data transmission part 4... Image display part 5... Interface part 6... Control part 11... Tuner part 12... Demodulation part 13... Video Signal processing unit 21 Image processing unit 22 Image division unit 31 Lane group data signal output unit 33 Video signal generation board 41 Lane group data reception unit 42 Screen unit 43 Panel display control Substrate 45 Delay amount measuring unit 46 Communication unit 47 Delay amount comparison unit 51-1 to 51-4 Output signal 52-1 to 52-4 Input signal 53-1 to 53-4 ... flat cable L1 to L16 ... screen panel area 310 ... BEP 311 ... lane group data division section 312 ... lane data signal output section 312-1 to 311-NL ... lane data signal output section 331, 331- 1 to 331-4... Lane group video signal output unit 410... T-CON 411... Lane data receiving unit 411-1 to 411-NL... Lane data receiving unit 412... Lane group data output unit 421... Image Panel unit 421-1 to 421-4 Screen panel area 422 Panel driver 510 Transmission path 3121 Symbol data output unit 3122 Shift register 3123 Selector 3124 Parallel-serial conversion unit 3125... 8B10B conversion unit, 3126... interface unit, 3311-1 to 3311-4... delay unit, 3312-1 to 3312-4... Vby1 driver, 4211-1 to 4211-4... scanning path, 4212-1 to 4212- 4... Pixel.

Claims (7)

Digital that simultaneously receives a plurality of video signal data divided to display one video signal on a plurality of screens, and outputs each digital video signal corresponding to the plurality of video signal data to different serial transmission lines at different timings A video signal generation circuit ,
Add to the delay amounts of the other serial transmission lines so that the delay amount of the serial transmission line having the longest transmission line among the plurality of serial transmission lines and the transmission time of the other serial transmission lines become the same. A digital video signal generation circuit that determines the amount of set delay. A timing for outputting each of the digital video signals to each of the serial transmission lines is adjusted in units of a transmission time required to transmit data for one symbol of each of the video signal data through each of the serial transmission lines. Item 2. The digital video signal generation circuit according to item 1. The timing of outputting each of the digital video signals to each of the serial transmission lines is adjusted in units of transmission time required to transmit bits within one symbol of each of the video signal data through each of the serial transmission lines. 3. The digital video signal generation circuit according to claim 1 or 2. 4. The method according to any one of claims 1 to 3, wherein the output timing of each digital video signal to the serial transmission line is determined by the length of the serial transmission line through which each digital video signal is transmitted. Digital video signal generation circuit. Based on the output timing of the first digital video signal to the first serial transmission line having the maximum length among the serial transmission lines, to the second serial transmission line excluding the first serial transmission line A digital video signal generating circuit that delays the output timing of the second digital video signal,
A difference between a first transmission time determined by the length of the first serial transmission line and a second transmission time determined by the length of the second serial transmission line is defined as an output timing of the second digital video signal. 5. The digital video signal generation circuit according to any one of claims 1 to 4, wherein the delay amount is set to . 6. The digital video signal is output to each serial transmission line after being corrected according to characteristics of waveform distortion depending on the length of each serial transmission line. The digital video signal generation circuit according to the item. Digital that simultaneously receives a plurality of video signal data divided to display one video signal on a plurality of screens, and outputs each digital video signal corresponding to the plurality of video signal data to different serial transmission lines at different timings a video signal generation circuit;
a screen display means connected to the serial transmission line, receiving and processing each of the digital video signals, and acquiring the plurality of video signal data;
The digital video signal generation circuit includes specific data in each digital video signal and transmits it,
The screen display means comprises delay difference measuring means for receiving the specific data from each digital video signal and measuring the delay difference between each digital video signal from the specific data,
The digital video signal generating circuit adjusts the delay amount of the serial transmission line having the longest transmission line among the plurality of serial transmission lines so that the transmission time of the other serial transmission lines is equal to the transmission time of the other serial transmission lines. A system that determines the set delay amount to be added to the delay amount of the serial transmission line .

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