JP2017011338A - Communication system, transmitter, communication method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust a delay generated among a plurality of transfer lanes, without an increased circuit scale of equipment of the serial data reception side.SOLUTION: A transmitter in a communication system includes: an insertion unit which inserts a control code between target codes which are transmitted through a first transmission lane and a second transmission lane; and a set unit which sets operation clock signals having a plurality of different phases into the second transmission lane. The receiver includes a calculation unit which calculates a delay time by subtracting an arrival time of a control code transmitted through the first transmission lane from an arrival time of a control code transmitted through the second transmission lane, for each operation clock signal of different phases. The transmitter further includes a transmission unit which performs serial transmission of the target code of the second transmission lane, using an operation clock signal having a smallest delay time among each delay time of the operation clock signals of different phases.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication device, a communication method, and a program.

  There is a technique called high-speed serial communication that converts target data into serial data and transfers the data at a high speed in bit units. In high-speed serial communication, there is a case where target data is serially transferred by a multi-lane method using a plurality of transfer lanes in order to further increase the communication speed.

  However, in the multi-lane method, serial data having a high frequency component exceeding 1 GHz is transferred by a plurality of lanes, and the transfer delay amount is different for each transfer lane. Therefore, the serial data cannot be normally received on the deserializer side.

  In order to solve this problem, a method of adjusting a delay amount by providing a buffer memory for adjusting a delay amount for each transfer lane on the deserializer side is already known.

  For example, in a serial data receiving device having a plurality of transfer lanes, a buffer memory is provided for each transfer lane of the receiving device, and the received serial data is written according to a timing signal reflecting delay information between the transfer lanes. A method of adjusting a delay amount between transfer lanes by reading a buffer memory is known (for example, Patent Document 1).

  However, the conventional technology has a problem that the circuit scale of the device on the serial data receiving side increases.

  For example, in the prior art, a buffer memory is provided in each transfer lane on the deserializer side in order to adjust the delay amount between the transfer lanes. In preparation for the case where the delay amount between transfer lanes becomes large, a buffer memory having a sufficient capacity is provided on the deserializer side, so that the circuit scale on the deserializer side becomes large.

  Furthermore, when the delay amount exceeds the system assumption, or when a communication error occurs at a timing corresponding to the delay time before and after the target data, a memory RW overrun error and a memory RW underrun error occur. There is.

  Therefore, an object of the present invention is to adjust a delay generated between a plurality of transfer lanes without increasing the circuit scale of a device that receives serial data.

  In the embodiment, the communication system includes a transmission device that serially transmits a target code using a plurality of transfer lanes, and a reception device that receives the target code. The transmission device includes a first transmission lane and a first transmission lane. An insertion unit that inserts a control code between target codes transmitted in two transmission lanes, and a setting unit that sets operation clock signals having a plurality of different phases in the second transmission lane. Is a delay obtained by subtracting the arrival time of the control code transmitted from the first transmission lane from the arrival time of the control code transmitted from the second transmission lane for each of the operation clock signals having a plurality of different phases. The transmitter further includes an operation clock signal having a smallest delay time among the delay times of the operation clock signals having the plurality of different phases. Communication system having a transmitting unit for transmitting serial target code of the second transmission lanes are disclosed using.

  The delay occurring between a plurality of transfer lanes can be adjusted without increasing the circuit scale of the device receiving the serial data.

It is a figure which shows the structural example of a write data transfer system. It is a figure explaining the connection of a writing optical system. It is a figure explaining the data output procedure of a serializer. It is a figure for demonstrating an RD rule. It is a figure which shows the timing chart of a serializer output. It is a figure which shows an example of a conversion table. It is a figure which shows the example of a serializer-deserializer connection. It is a figure which shows the 1st example of the delay control between multilanes. It is a figure which shows the 2nd example of the delay control between multilanes. It is a figure which shows the 3rd example of the delay control between multilanes.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has substantially the same function structure, the duplicate description is abbreviate | omitted by attaching | subjecting the same code | symbol.

[First Embodiment]
FIG. 1 is a diagram illustrating a configuration example of a write data transfer system 1. The write data transfer system 1 includes a CTL (Controller) 10, a page memory 20, an image development unit 30, a CPU 40, an external memory 50, a VCSEL (Vertical Cavity Surface Emitting LASER) (Bk (Black)) 60a, VCSEL (Ma (Magenta)) 60b, VCSEL (Cy (Cyan)) 60c, VCSEL (Ye (Yellow)) 60d, plotter controller 100, PC 200, plotter controller 300, plotter controller 400, Have In the following description, the VCSEL 60a, the VCSEL 60b, the VCSEL 60c, and the VCSEL 60d are denoted as VCSEL 60 when they are not distinguished.

  The plotter control unit 100 corrects the image data transmitted from a PC (Personal Computer) 200 by area gradation correction, edge correction, skew correction, and the like, and the corrected image data is controlled by the plotter control unit 300 and the plotter control. High-speed serial transfer to the unit 400.

  The plotter control unit 100 includes a video input unit 101, a parameter control unit 102, a noise removal unit 103, a line memory 104, an image processing unit 105, a pixel count unit 106, a line memory group 107, and a skew correction unit. 108, an 8B / 10B converter 109, a SER (Serializer) function unit 110, and an LVDS (Low voltage differential signaling) driver 111.

  Upon receiving a print instruction from the user, the PC 200 transmits an image file such as GIF or JPEG to the CTL 10 using a printer driver. The CTL 10 converts the received image file into image data such as bitmap data and transfers it to the image development unit 30.

  The image development unit 30 transfers image data to the plotter control unit 100 by communicating with the video input unit 101. Specifically, after the MFSYNC signal is output from the video input unit 101, the image development unit 30 transfers the image data to the plotter control unit 100 line by line each time the MLSYNC signal is output. Note that the MFSYNC signal is a pulse-type synchronization signal indicating the top of the page. The MLSYNC signal is a pulse-type synchronization signal indicating the end of the line.

  In addition, the image development unit 30 transfers image data for one line to the video input unit 101 for each color (black, magenta, cyan, and yellow) in accordance with the timing at which the MLSYNC signal is output from the video input unit 101. . Note that the image development unit 30 may transfer image data of colors other than black, magenta, cyan, and yellow to the video input unit 101.

  When the CPU 40 refers to the external memory 50 and detects completion of preparation for image formation, the CPU 40 generates a start trigger signal and transmits the start trigger signal to the parameter control unit 302 and the parameter control unit 402.

  The video input unit 301 and the video input unit 401 generate a start trigger based on the received start trigger signal. The video input unit 301 generates black and magenta FSYNC_N signals and LSYNC_N signals from the generated start trigger, and transmits them to the noise removal unit 103. Further, the video input unit 401 generates cyan and yellow FSYNC_N signals and LSYNC_N signals from the generated start trigger, and transmits them to the noise removing unit 103.

  The noise removing unit 103 removes noise such as electrostatic pulses included in the FSYNC_N signal and the LSYNC_N signal received from the video input unit 301 and the video input unit 401.

  For example, in an image forming apparatus equipped with this writing data system, it is necessary to operate a photosensitive drum and a polygon motor (not shown) at high speed when supporting ultrahigh-speed printing exceeding 100 PPM. For this purpose, a high-output drive motor, a large-diameter photosensitive drum, and the like are required, and the size of each drive unit increases, so the distance between the units inevitably increases.

  Accordingly, the VCSEL for exposing each photosensitive drum is also arranged at a distant position, and it is necessary to dispose the plotter control unit 300 and the plotter control unit 400 for controlling the VCSEL at distant positions. In addition, the plotter control unit 300 and the plotter control unit 100 connected to the plotter control unit 400 are inevitably arranged at positions away from each other, and the distance between the plotter control unit 300 and the plotter control unit 400 and the plotter control unit 100 is several. May be a meter away.

  For this reason, the FSYNC_N signal and the LSYNC_N signal are transmitted from the plotter control unit 300 and the plotter control unit 400 to the plotter control unit 100 through a signal line of several meters, and there is a high possibility of being affected by noise therebetween.

  Therefore, a noise removal circuit is required for the reception unit of the FSYNC_N signal and the LSYNC_N signal.

  Further, the image development unit 30 and the plotter control unit 100 are not particularly limited in physical arrangement, and can be arranged in the vicinity. For this reason, a noise removal circuit is not essential for the reception unit of the MFSYNC signal and the MLSYNC signal.

  The noise removing unit 103 transfers the received FSYNC_N signal to the video input unit 101 as an FSYNC signal.

  Further, the noise removing unit 103 generates one LCLR signal for every four LSYNC_N signals starting from the FSYNC signal, and transmits the generated LCLR (Line Clear) signal to the video input unit 101. Specifically, the noise removing unit 103 generates an LCLR signal and transmits it to the video input unit 101 while providing a predetermined time difference for each color. For example, the noise removal unit 103 generates an LCLR signal related to black, an LCLR signal related to magenta, an LCLR signal related to cyan, and an LCLR signal related to yellow, and transmits each LCLR signal to the video input unit 101 in the order of generation. To do.

  The video input unit 101 generates an MFSYNC signal and an MLSYNC signal for each color (black, magenta, cyan, yellow) using the received LCLR signal as a starting point, and transmits the MFSYNC signal and the MLSYNC signal to the image development unit 30. Thus, the video input unit 101 sequentially receives image data for one line for each color from the image development unit 30 in accordance with the timing at which the MFSYNC signal and the MLSYNC signal are transmitted. The video input unit 101 operates in synchronization with the same clock as the image development unit 30.

  The video input unit 101 writes the image data for one line received from the image development unit 30 to the line memory 104. The video input unit 101 reads the image data for four lines with the LCLR signal interposed therebetween after the image data for four lines is written to the line memory 104. Note that the video input unit 101 can set the timing of write processing and read processing between LCLR signals. For example, the video input unit 101 can set the timing of the write process and the read process so that the first half of the LCLR signal is written twice to the line memory 104 and the second half is read from the line memory 104 twice. it can. Further, the video input unit 101 writes the timing of the write process and the read process so that the line memory 104 is written four times after the first LCLR signal and the line memory 104 is read four times after the second LCLR signal. It can also be set.

  Subsequently, the video input unit 101 performs area gradation correction on the pixel data. The area gradation correction is correction that performs pseudo gradation expression using a plurality of pixels on the output side corresponding to the coordinates of one pixel on the input side. The video input unit 101 transmits the pixel data after area gradation correction to the image processing unit 105. Note that the image processing unit 105 to be described later may perform area gradation correction.

  The area gradation correction is performed in the case of a system in which the light emitting device can output only a binary expression such as LEDA. It is not necessary to implement in the case of a light emitting device capable of multi-value expression using PWM such as LD. A VCSEL is a device in which 20 to 40 LDs are arranged at high density, and a sufficiently high-definition image (1200 × 2400 dpi) can be obtained even if each LD performs binary representation. Furthermore, it is also possible to obtain an ultra-high definition (2400 × 4800 dpi) image by PWM control of each LD. Therefore, when using VCSEL, whether to perform area gradation is switched depending on whether binary representation is used in the VCSEL system.

  The image processing unit 105 performs image data processing such as edge correction (1), trimming correction (2), and internal pattern superimposition (3) on the received set of pixels.

  Edge correction (1) is a correction for detecting an edge from image data and smoothing it. An edge may occur in the image data after area gradation correction. The image processing unit 105 can perform edge correction after area gradation correction, thereby smoothing edges generated in image data when area gradation correction is performed.

  Trimming correction (2) is correction for deleting unnecessary portions of image data. For example, the image processing unit 105 performs trimming correction in the main scanning direction and the sub-scanning direction, and matches the trimming boundary with the printable range on the sheet.

  The internal pattern superimposition (3) is correction for superimposing pattern images such as a test pattern, a forgery prevention pattern, and an adjustment pattern on image data. Examples of the adjustment pattern include a density adjustment pattern, a color misregistration correction pattern, and a blade deflection avoidance pattern. The image processing unit 105 generates each pattern in accordance with the resolution of the VCSEL 60, and generates image data optimized for the VCSEL 60 by superimposing the pattern on the image data.

  Note that the image processing unit 105 may perform correction using a line memory (not shown) when the image data is subjected to jaggy correction.

  The image processing unit 105 writes the image processed image data to the skew correction line memory group 107. When the Mbit recording can be performed at one address of the skew correction line memory, the image processing unit 105 may write image data for M pixels at one address. Thereby, the image data after the image processing can be recorded with a minimum memory.

  The pixel count unit 106 counts the number of pixels included in the image data after the image data processing. For example, the CPU 40 may calculate a charge amount charged to the user according to the number of pixels counted by the pixel count unit 106. In addition to the number of pixels of the image data, the pixel count unit 106 may count the number of pixels of the pattern image such as the test pattern, the anti-counterfeiting pattern, and the adjustment pattern. Thereby, the toner consumption amount can be accurately grasped.

  Further, the plotter control unit 100 processes the four lines of image data written to the line memory 104 of the video input unit 101 simultaneously with a multi-data path until four lines are written to the line memory group 107 of the skew correction unit.

  By using the multi-data path, the image processing unit 105 can refer to two-dimensional data at several pixels at a time in the main scanning direction and the sub-scanning direction, so that processing such as edge processing and jaggy correction can be performed. Accuracy is improved. In addition, by using a multi-data path, the transfer rate of image data is improved, and the printing process speed is improved. In addition, high-resolution image data and image data on which a high-resolution pattern is superimposed can be transferred without delaying the transfer time. In addition, the video input unit 101 performs image processing such as area gradation correction on image data copied in the main scanning direction and the sub-scanning direction, and transfers high-resolution image data through a multi-data path. Good.

  The skew correction unit 108 performs skew correction by switching the line memory that reads the image data recorded in the line memory group 107 for skew correction according to the position of the image data. The skew correction unit 108 reads the line memory group 107 at a cycle of 1 / N of the cycle written to the line memory group 107 by the image processing unit 105. Thereby, the resolution in the sub-scanning direction of the image data after skew correction is increased N times, and the image data can be increased in resolution.

  The 8B / 10B conversion unit 109 converts the 8-bit code string (image data) received from the skew correction unit 108 into a 10-bit code string based on the conversion table. The 8B / 10B conversion unit 109 arranges the converted 10-bit code string in the encoded block.

  The SER function unit 110 converts the 10-bit parallel data (image data) arranged in the encoding block into serial data that is sequentially output by dividing it into 10 times bit by bit. The SER function unit 110 serially transmits black and magenta image data among black, magenta, cyan, and yellow image data to the plotter control unit 300, and serially transmits cyan and yellow image data to the plotter control unit 400. . The serializer procedure will be described later.

  The plotter control unit 300 includes a video input unit 301, a parameter control unit 302, a DES function unit 303, a driver 304a, a driver 304b, and an LVDS driver 305. The plotter control unit 400 includes a video input unit 401, a parameter control unit 402, a DES function unit 403, a driver 404a, a driver 404b, and an LVDS driver 405.

  The DES function unit 303 receives black and magenta 10-bit code strings via the LVDS driver 305. The DES function unit 303 inversely converts the 10-bit code string of black and magenta into an 8-bit code string, outputs the black code string to the driver 304a, and outputs the magenta code string to the driver 304b. The driver 304a turns on the VCSEL 60a based on the output black code string. The driver 304b turns on the VCSEL 60b based on the output magenta serial data.

  The DES function unit 403 receives a 10-bit code string of cyan and yellow via the LVDS driver 405. The DES function unit 403 converts the cyan and yellow 10-bit code string back to 8 bits, outputs the cyan code string to the driver 304c, and outputs the yellow code string to the driver 304d. The driver 304c turns on the VCSEL 60c based on the output cyan code string. The driver 304b turns on the VCSEL 60d based on the output yellow code string.

  In the first embodiment, the example in which the image data for two colors is serially transmitted to the two plotter control units has been described, but the present invention is not limited to this. For example, the image data of each color (black, magenta, cyan, yellow) may be serially transmitted separately to the four plotter control units.

  The optical system to be used may be a multi-LD (Laser Diode), LEDA (LED Array), or the like in addition to the VCSEL.

  FIG. 2 is a diagram for explaining the connection of the writing optical system. FIG. 2 shows an example in which the chip related to the plotter control unit 100 is used for a plurality of optical systems such as LEDA (b) and LD optical system (c) in addition to the VCSEL optical system (a).

  The plotter control unit 100 performs LD control. In order to realize high-quality image data generation using an LD, PWM control of light emission data is indispensable. The PWM control is a technique that realizes gradation control and main scanning position correction control by time-dividing the light-on / off data signal for each pixel and finely controlling the light emission / light-off time of each pixel.

  In order to form high-quality image data, highly accurate PWM control in which one pixel is divided into 32 or 64 is desired. In an MFP that realizes a printing speed of about 50 to 60 PPM, the lighting cycle of one pixel is about 60 MHz. In order to divide this into 32, a frequency of 60 × 64 = 3840 MHz is required.

  In a normal one-phase PLL, a source oscillation of 33.3 MHz is used, and it is multiplied by 30 to obtain an operation frequency of 1 GHz. In order to generate a frequency equivalent to 4 GHz, a source oscillation exceeding 100 MHz and a circuit capable of realizing a multiplication by 100 or more are required, which leads to a significant system cost increase.

  Therefore, by using a multi-phase PLL, it is possible to efficiently generate an LD on / off signal corresponding to 4 GHz.

  In the multi-phase PLL, a source oscillation of 33.3 MHz is used and multiplied by 30 to generate four 1 GHz PLLs that are 90 °, 180 °, and 270 ° out of phase. The LD lighting / extinguishing signal generates four signal groups synchronized with the four PLLs.

  At the final stage of outputting the LD on / off signal, the LD on / off signal corresponding to the resolution (for example, 1/64) of the PWM control is generated by superimposing the four signal groups.

  1/64 of the lighting cycle 60 MHz is a lighting time of 260.4 ns. Since a lighting signal of 1 ns can be generated using each PLL, a lighting signal of 260 ns is generated using 0 ° and 180 °. At this time, the 180 ° lighting signal is delayed by 0.5 ns with respect to 0 °. Therefore, when these two lighting signals are superimposed, a lighting signal having a width of 260.5 ns can be generated. In this manner, a system using a multi-phase PLL can perform highly accurate PWM control exceeding the frequency of the PLL. As described above, the plotter control unit 100 has a multi-phase PLL in order to perform LD control.

  In the VCSEL optical system (a), the plotter control unit 100 includes a SER function unit 110. The plotter control unit 100 converts an 8-bit code related to image data into a 10-bit code. The SER function unit 110 converts 10-bit parallel data into 10-bit serial data. The SER function unit 110 serially transmits 10-bit serial data to the plotter control unit 300 after delay control is performed on the 10-bit serial data using a multi-phase PLL. The DES function unit 303 converts 10-bit serial data into 8-bit parallel data and outputs the converted data to the VCSEL 60. Note that delay control using a multi-phase PLL will be described later.

  In LEDA (b), the plotter control unit 100 converts the arrangement of the image data according to the LED arrangement of the LEDA 70. The plotter control unit 100 may perform array conversion using a line memory when the array conversion is one line or more.

  In the LD optical system (c), the plotter control unit 100 includes an LD 80. The plotter control unit 100 generates a high-frequency clock using a multi-phase PLL, and performs serializer data delay control.

  As described above, when the plotter control unit 100 is used for a plurality of writing optical systems in general, the multi-phase PLL used in the LD optical system is also used in the VCSEL optical system, so that the multi-phase PLL is effectively used. Can do.

  FIG. 3 is a diagram for explaining the data output procedure of the serializer. FIG. 3A shows an 8-bit encoded block. The lowest level is LSB (Least Significant Bit) and the top level is MSB (Most Significant Bit). The 8B / 10B conversion unit 109 acquires the received 8 bits of image data in order from the upper bits, and stores them sequentially from the LSB of the encoded block. For example, when an 8-bit bit string ABCDEFGH (A is the most significant bit and H is the least significant bit) is stored in an 8-bit encoded block, the encoded block includes A, B in order from the LSB as shown in (a). , C, D, E, F, G, H bits are stored. Subsequently, the 8B / 10B conversion unit 109 converts the 8-bit bit string into a 10-bit bit string based on the conversion table, acquires the 10-bit bit string in order from the upper bits, and stores the 10-bit bit string in order from the LSB of the encoded block. . FIG. 3B shows a coding block in which a 10-bit bit string is stored in order from the LSB. For example, when a 10-bit bit string abcdeifghj (a is the most significant bit and j is the least significant bit) is stored in a 10-bit encoded block, the encoded block has a, b in order from the LSB as shown in (b). , C, d, e, i, f, g, h, j bits are stored.

  FIG. 3C shows a transmission order of bits transmitted by the LVDS driver 111. The SER function unit 110 converts the parallel data stored in the 10-bit coding block into serial data, and sets the 10-bit serial data in the normal order in the LVDS driver 111 as shown in FIG. Serially transmitted to the unit 300 and the plotter control unit 400. The normal order indicates the order from the upper bit to the lower bit of the bit string related to the transferred image data. That is, the bits b, c, d, e, i, f, g, h, j are transmitted in order from a stored in the LSB of (b).

  FIG. 4 is a diagram for explaining the RD rule. FIG. 4 shows the RD rule, and the upper side of FIG. 4 shows the selection of the polarity data of RD + and RD−. In FIG. 4, when it is High, it indicates that it is RD +, and when it is Low, it indicates that it is RD-. The lower side of FIG. 4 shows an array of 10-bit serial data to be transferred. Each square is 10-bit serial data. “COM” in the square indicates a COM symbol code. The COM symbol code is a code used for recognizing that it is outside the image data when negated. Hereinafter, the symbol code “COM” is referred to as a COM code. “Dm.n (m, n is an integer)” in the square indicates the code of the image data. That is, m and n indicate data code group numbers. A 10-bit code having a positive polarity and a negative polarity is associated with each 8-bit code. The numerical value in parentheses in the square indicates the number of “1” bits included in the 10-bit serial data. For example, “COM (6)” indicates that the COM code includes six “1” bits.

  The 10-bit code has two polarities, RD + and RD-. Based on the RD rule, the 8B / 10B conversion unit 109 converts the 8-bit code into a 10-bit code having a polarity of RD + or RD−. The “RD rule” is a rule for selecting the polarity of RD + and RD− when converting an 8-bit code to a 10-bit code. According to the RD rule, when the number of “1” bits of the current 10-bit code to be transmitted is five, the next 10-bit code is data having the same polarity as the current 10-bit code. On the other hand, when the number of “1” bits of the current 10-bit code is other than 5, the next 10-bit code is data having a polarity different from that of the current 10-bit code.

  For example, in FIG. 4, since the number of bits of “1” is 6 in the third serial data from the left side, the SER function unit 110 inverts the polarity of the next fourth code from RD− to RD +. Subsequently, since the number of bits of “1” is 4 in the fourth serial data, the SER function unit 110 inverts the polarity of the next fifth code from RD + to RD−. Subsequently, since the number of bits of “1” is 5 in the fifth serial data, the SER function unit 110 maintains the polarity of the next sixth code at RD−.

  FIG. 5 is a diagram illustrating a timing chart of the serializer output. The horizontal axis in FIG. 5 indicates time.

  The clock indicates an operation clock of the SER function unit 110. SkewLgate indicates the position of the tip and end of an 8-bit code string (image data) input to the SER function unit 110. SkewData indicates an 8-bit code string (image data) input to the SER function unit 110. SerLgate indicates the position of the leading end of the symbol code string “STP” and the end of the symbol code string “END”. The symbol code “STP” is a code used when detecting the start point of the image data. The symbol code “END” is a code used when detecting the end point of the image data. Hereinafter, the symbol code “STP” is referred to as an STP code, and the symbol code “END” is referred to as an END code.

  SerData indicates a COM code, an STP code, an END code, and image data converted into 10 bits.

  The skew correction unit 108 detects the position of the front end and the end of the image data by detecting the edge of SkewLgate, and acquires an 8-bit code string. The skew correction unit 108 transmits the acquired 8-bit code string to the 8B / 10B conversion unit 109. The 8B / 10B conversion unit 109 adds a plurality of STP codes before the 8-bit code string and adds a plurality of END codes after the 8-bit code string. Subsequently, the 8B / 10B conversion unit 109 detects a SerLgate edge to detect a position outside the image data, and generates SerData by adding a plurality of COM codes to the position outside the image data. Thus, the distance between the image data is increased by adding a plurality of COM codes outside the image data.

  FIG. 6 is a diagram illustrating an example of the conversion table. The 8B / 10B conversion unit 109 converts an 8-bit symbol code into a 10-bit symbol code based on the conversion table of FIG. “Symbol Name” indicates the type of symbol code. Twelve types of symbol codes are prepared, and a symbol code is assigned to each of one type of COM code, five types of STP codes (STP1 to 5), and five types of END codes (END1 to 5). “Data Byte Name” indicates the name of the symbol code. “Data Byte Value (hex)” represents an 8-bit symbol code in hexadecimal. “8B code” indicates an 8-bit symbol code. The “10B code” is a 10-bit symbol code of polarity RD + and polarity RD− corresponding to an 8-bit symbol code.

  In order to make it easy to detect a boundary between image data, for example, a code in which five or more bits of 0 or 1 are continuous is assigned to the COM code. The COM code is used as a marker when calculating the delay amount between the transfer lanes.

  Further, for example, a code other than 5 having 1 bit number is assigned to the COM code so that RD + and RD− are alternately generated. Since the COM code is continuously generated, whether or not the operation of the plotter control unit 100 is normal can be confirmed by using a code in which RD + and RD− are alternately generated. For example, K28.5 or K28.1 is assigned to the COM code. Further, K28.2, K28.3, and K28.4 may be assigned to the COM code.

  FIG. 7 is a diagram illustrating an example of serializer-deserializer connection. The skew correction unit 108 divides the image data of 4 lines (4 bits × 4) into 8-bit code using 4-bit image data per pixel, and sequentially transmits the 8-bit code to the 8B10B conversion unit 109. . For example, the skew correction unit 108 transmits SkewLgate0 to 7 and SkewData0 to 7 (8-bit code) to each channel from CH0 to CH7. The 8B10B conversion unit 109 acquires SkewData0 to 7 (8-bit code) by detecting the edges of SkewLgate0 to 7 in each channel from CH0 to CH7. Note that the 8B10B conversion unit 109 may apply reset signals to the channels CH0 to CH7 and cancel the reset of only the channels to be used.

  Subsequently, the 8B10B conversion unit 109 converts the 8-bit code into a 10-bit code and outputs it to the SER function unit 110.

  The SER function unit 110 acquires each bit in order from the LSB of the encoded block, and sets the acquired bit in the LVDS driver 111. Subsequently, the LVDS driver 111 outputs a differential signal related to serial data to the LVDS driver 305 as a normal output (RXP) and an inverted output (RXM).

  The LVDS driver 305 receives a differential signal related to serial data as a normal rotation input (TXP) and an inverting input (RXM). The LVDS driver 305 outputs the serial data to the DES function unit 303 as a 10-bit code. The DES function unit 303 acquires a 10-bit code for each channel and converts it into an 8-bit code. The DES function unit 303 detects a plurality of COM codes in which 0 or 1 bits are continuous five times or more in each channel. The DES function unit 303 calculates a delay time between channels based on the COM code detected in each channel.

  FIG. 8 is a diagram illustrating a first example of delay control between multilanes. The horizontal axis in FIG. 8 indicates time (t). “Clk_ref” indicates a waveform of the source oscillation. “Clk_v0” indicates a transmission clock waveform when the phase is 0 °. “Clk_v1” indicates a transmission clock waveform when the phase is 90 °. “Clk_v2” indicates a transmission clock waveform when the phase is 180 °. “Clk_v3” indicates a transmission clock waveform when the phase is 270 °. “Clk_w $ c” indicates a clock waveform for controlling each channel that has received 8-bit data. “Clk_w $ c” is used when 8-bit data is acquired in the 8B / 10B conversion. “8B” indicates an 8-bit code string. “10B” indicates a code string converted from an 8-bit code to a 10-bit code. “RD” indicates polarity. For example, “RD +” corresponds to a bit string obtained by bit-inverting “RD−”. “RXP0” indicates a bit string transmitted from the LVDS driver 111 via the first transfer lane of CH1. “RXP1” indicates a bit string transmitted from the LVDS driver 111 via the second transfer lane of CH2. “TXP0” indicates a bit string received from the LVDS driver 305 via the first transfer lane of CH1. “TXP1” indicates a bit string received from the LVDS driver 305 via the second transfer lane of CH2.

  (Adjustment) The following “RXP0”, “RXP1”, “TXP0”, and “TXP1” indicate bit strings of the first transfer lane (CH1) and the second transfer lane (CH2) after delay time adjustment.

  A case where 16-bit image data is divided into 8-bit bit strings and serial transfer is performed using two transfer lanes will be described with reference to FIG. The 8B / 10B conversion unit 109 inserts a plurality of COM codes into the bit string. The 8B / 10B conversion unit 109 extracts the divided 8-bit bit string (COM code) by detecting the edge of the waveform of “clk_w $ c”. The 8B / 10B conversion unit 109 converts the 8-bit bit string (8B) into a 10-bit bit string (10B) based on the conversion table.

  The DES function unit 303 detects 5T (“00000” or “11111”) in the COM code, and calculates a delay time between the first transfer lane and the second transfer lane. As a result of calculating the delay time, it is assumed that CH1 is delayed by “1.3 clk_v (clk_v is a transmission clock)”, and CH0 is delayed by “0.25clk_v”.

  Specifically, the LVDS driver 111 divides “clk_v0” by 10 to generate a clock clk_w0 having a wavelength 10 times the transmission clock. The DES function unit 303 calculates the delay amount in units of clk_w0 by “ROUND ((1.3clk_v−0.25clk_v) /10.0)”. Since the delay amount in units of clk_w0 is “0”, the LVDS driver 111 does not have to perform delay control in units of clk_w0.

  Subsequently, the DES function unit 303 calculates a delay amount in units of clk_v by “ROUND ((1.3clk_v−0.25clk_v) /1.0)”. Since the delay amount in units of clk_v is “1”, the LVDS driver 111 delays the transmission clock of CH0 by 1 clk_v using the shift register.

  Note that a shift register having a capacity capable of a maximum delay of 9 clk_v is used. Since the amount of delay can be adjusted using clk_w0 for 10 clk_v or more, the shift register only needs to have a capacity of a maximum of 9 clk_v.

  Subsequently, the DES function unit 303 calculates a delay amount in units less than clk_v. The delay amount when the phases of CH0 and CH1 are the same (the phase of CH0 is 0 °) is “0.3clk_v”. The DES function unit 303 calculates a delay amount “0.3clk_v−0.25clk_v = 0.05clk_v” when CH0 has a phase difference of 90 ° (corresponding to clk_v1). Further, the DES function unit 303 calculates a delay amount “0.3 clk_v−0.5 clk_v = −0.15 clk_v” when CH0 is set to a phase difference of 180 ° (corresponding to clk_v2). Further, the DES function unit 303 calculates the delay amount “0.3 clk_v−0.75 clk_v = −0.45 clk_v” when CH0 is set to a phase difference of 270 ° (corresponding to clk_v1). Since clk_v1 having a phase difference of 90 ° for CH0 has the smallest delay amount, the LVDS driver 111 serially transmits a 10-bit bit string using the transmission clock clk_v1.

  Thereby, a delay amount of 1.25 clk_v is given to a 10-bit bit string serially transmitted from CH0. The delay amount correction residual is 0.05 clk_v.

  Thus, the correction residual of the delay amount on the serializer side is less than 1/8 clk_v, and correction can be performed with higher accuracy than when the delay amount is corrected in clk_v units. In addition, since the delay amount is corrected on the serializer side, it is not necessary to correct the delay amount on the deserializer side, and the delay occurring between multiple transfer lanes can be adjusted without increasing the circuit scale on the deserializer side can do.

  Note that the delay amount in clk_w0 unit, the delay amount in clk_v0 unit, and the delay amount in units less than clk_v can be obtained in the same order regardless of the order. The amount may be calculated.

  In addition, when serially transferring the same color image data using a plurality of transfer lanes, the LVDS driver 111 corrects the delay amount. However, when one transfer lane is allocated to one color image data, the delay is considered. There is no need to correct the delay amount.

[Second Embodiment]
FIG. 9 is a diagram illustrating a second example of delay control between multilanes. The case where 16-bit image data is divided into 8-bit bit strings and serial transfer is performed using two transfer lanes will be described with reference to FIG. The 8B / 10B conversion unit 109 inserts a plurality of COM codes into the bit string. The 8B / 10B conversion unit 109 extracts the divided 8-bit bit string (COM code) by detecting the edge of the waveform of “clk_w $ c”. The 8B / 10B conversion unit 109 converts the 8-bit bit string (8B) into a 10-bit bit string (10B) based on the conversion table.

  The DES function unit 303 detects 5T (“00000” or “11111”) in the COM code, and calculates a delay time between the first transfer lane and the second transfer lane. As a result of calculating the delay time, it is assumed that CH1 is delayed by “1.3 clk_v (clk_v is a transmission clock)”, and CH0 is delayed by “0.25clk_v”.

  Specifically, the DES function unit 303 divides “clk_v0” by 10 to generate a clock clk_w0 having a wavelength 10 times the transmission clock. The DES function unit 303 calculates the delay amount in units of clk_w0 by “ROUND ((1.3clk_v−0.25clk_v) /10.0)”. Since the delay amount in units of clk_w0 is “0”, the LVDS driver 111 does not have to perform delay control in units of clk_w0.

  Subsequently, the DES function unit 303 calculates a delay amount in units of clk_v by “ROUND ((1.3clk_v−0.25clk_v) /1.0)”. Since the delay amount in clk_v units is “1”, the LVDS driver 111 delays the transmission clock of CH0 by 1 clk_v.

  Subsequently, the DES function unit 303 calculates a delay amount “1.3clk_v−0.25clk−1.0” less than clk_v. The delay amount less than clk_v is “0.15clk_v”. The DES function unit 303 stores the 10-bit bit string received from the LVDS driver 111 in the buffer memory. The DES function unit 303 uses two buffer memories (total of 2 clk_v) having a capacity of 1 clk_v. In order to correct an error in delay control, the DES function unit 303 may use a buffer memory having a capacity of 10 clk_v.

  The DES function unit 303 corrects the delay amount less than clk_v by storing the extra bits in the buffer memory and delaying the reading of the 10-bit bit string of CH0 by “0.15clk_v”.

  In this way, by correcting the delay amount in units of transmission clocks on the serializer side, the DES function unit 303 only needs to have a buffer memory for two cycles of the transmission clock, which increases the circuit scale on the deserializer side. Can be suppressed.

[Third Embodiment]
FIG. 10 is a diagram illustrating a third example of delay control between multilanes. A case where 16-bit image data is divided into 8-bit bit strings and serially transferred using two transfer lanes will be described with reference to FIG. The 8B / 10B conversion unit 109 inserts a plurality of COM codes into the bit string. The 8B / 10B conversion unit 109 extracts the divided 8-bit bit string (COM code) by detecting the edge of the waveform of “clk_w $ c”. The 8B / 10B conversion unit 109 converts the 8-bit bit string (8B) into a 10-bit bit string (10B) based on the conversion table.

  The DES function unit 303 detects 5T (“00000” or “11111”) in the COM code, and calculates a delay time between the first transfer lane and the second transfer lane. As a result of calculating the delay time, it is assumed that CH1 is delayed by “11.4 clk_v (clk_v is a transmission clock)”, and CH0 is delayed by “0.25clk_v”.

  Specifically, the DES function unit 303 divides “clk_v0” by 10 to generate a clock clk_w0 having a wavelength 10 times the transmission clock. The DES function unit 303 calculates the delay amount in units of clk_w0 by “ROUND ((11.4clk_v−0.25clk_v) /10.0)”. Since the delay amount in units of clk_w0 is “1clk_w0 (the same delay amount as 10clk_v)”, the LVDS driver 111 delays the transmission clock by “1clk_w0” using clk_w0.

  Subsequently, the DES function unit 303 calculates a delay amount “11.4clk_v−0.25clk−10.0” less than clk_v. The delay amount less than clk_v is “1.15clk_v”. The DES function unit 303 stores the 10-bit bit string received from the LVDS driver 111 in the buffer memory. The DES function unit 303 uses two buffer memories (total of 20 clk_v) having a capacity of 10 clk_v. In order to correct an error in delay control, the DES function unit 303 may use a buffer memory having a capacity of 100 clk_v.

  The DES function unit 303 corrects the delay amount less than clk_v by storing the extra bits in the buffer memory, thereby delaying the reading of the bit string of CH010 bits by “1.15 clk_v”.

  In this way, by correcting the delay amount in units of 10 transmission clocks on the serializer side, the DES function unit 303 only needs to have a buffer memory for 20 transmission clock cycles. Increase in scale can be suppressed.

  In the second and third embodiments, a multi-phase PLL is not required for delay control of the plotter control unit. Therefore, a plotter control unit dedicated to VCSEL writing having a single-phase PLL may be used.

  Although the VCSEL write control system has been described above by way of the embodiment, the present invention is not limited to the above embodiment, and various modifications and improvements can be made within the scope of the present invention. For example, a VCSEL is used for the exposure unit, but the present invention is not limited to this. As long as it is a line head, an LED head, an organic EL head, an LD array head, or the like may be used.

  The high-speed serial transfer described above is not limited to use for transferring image data. The high-speed serial transfer described above may also be applied when transferring data other than image data.

  Next, an embodiment of a storage medium storing a program and data for performing the above-described processing will be described. Specific examples of the storage medium include a CD-ROM, a magneto-optical disk, a DVD ROM, an FD, a flash memory, a memory card, a memory stick, and various other ROMs and RAMs. By causing the computer to execute the program stored in these storage media, the processing in this embodiment can be realized. In addition, the functions for the above-described communication control method and the function for realizing the functions of the serial communication device can be stored in a storage medium or distributed via a network for easy distribution. can do.

  In the present embodiment, the plotter control unit 100 is an example of a transmission device. The plotter control unit 300 and the plotter control unit 400 are an example of a receiving device. The 8B / 10B conversion unit 109 is an example of an insertion unit. The LVDS driver 111 is an example of a setting unit. The LVDS driver 111 is an example of a transmission unit. The DES function unit 303 and the DES function unit 403 are examples of a calculation unit. Further, the DES function unit 303 and the DES function unit 403 may have a function of an adjustment unit. The COM code is an example of a control signal.

1 VCSEL write control system 10 CTL
20 page memory 30 image development unit 40 CPU
50 External memory 60a VCSEL (Bk)
60b VCSEL (Ma)
60c VCSEL (Cy)
60d VCSEL (Ye)
100, 300, 400 Plotter control unit 101 Video input unit 102 Parameter control unit 103 Noise removal unit 104 Line memory 105 Image processing unit 106 Pixel counting unit 107 Line memory group 108 Skew correction unit 109 8B / 10B conversion unit 110 SER function unit 200 PC
111,305,405 LVDS drivers 301,401 Video input units 302,402 Parameter control units 303,403 DES function units 304a, 304b, 404a, 404b drivers

JP 2014-216981 A

Claims (10)

A communication system including a transmission device that serially transmits a target code using a plurality of transfer lanes, and a reception device that receives the target code,
The transmitter is
An insertion unit for inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
A setting unit configured to set operation clock signals having different phases in the second transmission lane,
The receiving device is:
A delay time obtained by subtracting the arrival time of the control code transmitted from the first transmission lane from the arrival time of the control code transmitted from the second transmission lane for each of the operation clock signals having a plurality of different phases. A calculation unit for calculating,
The transmission device further includes:
A communication system comprising: a transmission unit that serially transmits a target code of the second transmission lane using an operation clock signal having a smallest delay time among delay times for the operation clock signals having a plurality of different phases.   The communication system according to claim 1, wherein the transmission unit delays the timing of serial transmission of the target code of the second transmission lane in units of the period of the operation clock signal so that the delay time is minimized.   2. The transmission unit according to claim 1, wherein the transmission unit delays the timing at which the target code of the second transmission lane is serially transmitted in a cycle unit that is an integer multiple of twice or more of the operation clock signal so that the delay time is minimized. The communication system described.   4. The operation unit according to claim 1, wherein the setting unit sets, in the second transmission lane, four-phase operation clock signals having a phase difference of 90 ° related to the operation clock signals having different phases. The communication system according to item. A communication system including a transmission device that serially transmits a target code using a plurality of transfer lanes, and a reception device that receives the serially transferred target code,
The transmitter is
An insertion unit for inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
A setting unit that sets an operation clock signal having the same phase as that of the first transmission lane to the second transmission lane,
The receiving device is:
A calculation unit that calculates a delay time obtained by subtracting the arrival time of the control code transmitted from the first transmission lane from the arrival time of the control code transmitted from the second transmission lane;
The transmission device further includes:
A transmission unit that serially transmits the target code after delaying the timing of serial transmission of the target code of the second transmission lane by the period of the operation clock signal so that the delay time is minimized. And
The receiving device further includes:
A communication system having an adjustment unit for adjusting the buffering time of the serially transmitted target code so as to minimize the delay time. A communication system including a transmission device that serially transmits a target code using a plurality of transfer lanes, and a reception device that receives the serially transferred target code,
The transmitter is
An insertion unit for inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
A setting unit that sets an operation clock signal having the same phase as that of the first transmission lane to the second transmission lane,
The receiving device is:
A calculation unit that calculates a delay time obtained by subtracting the arrival time of the control code transmitted from the first transmission lane from the arrival time of the control code transmitted from the second transmission lane;
The transmission device further includes:
The timing for serially transmitting the target code of the second transmission lane is delayed by a unit of an integer multiple of the operation clock signal so that the delay time is minimized, and then the target code is serially transmitted. And a transmission unit to
The receiving device further includes:
A communication system having an adjustment unit for adjusting the buffering time of the serially transmitted target code so as to minimize the delay time. A transmitter that serially transmits a target code to a receiver using a plurality of transfer lanes,
An insertion unit for inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
A setting unit configured to set operation clock signals having different phases to the second transmission lane;
The control code transmitted from the first transmission lane is calculated from the arrival time of the control code transmitted from the second transmission lane, calculated by the receiving device, for each of the operation clock signals having a plurality of different phases. And a transmitter that serially transmits the target code of the second transmission lane using an operation clock signal having the smallest delay time out of the delay time obtained by subtracting the arrival time. A communication method for serially transmitting a target code to a receiving device using a plurality of transfer lanes,
Inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
Setting operation clock signals of a plurality of different phases in the second transmission lane;
The control code transmitted from the first transmission lane is calculated from the arrival time of the control code transmitted from the second transmission lane, calculated by the receiving device, for each of the operation clock signals having a plurality of different phases. And serially transmitting the target code of the second transmission lane using an operation clock signal having the smallest delay time out of the delay time obtained by subtracting the arrival time. Inserting a control code between target codes transmitted in the first transmission lane and the second transmission lane;
Setting operation clock signals of a plurality of different phases in the second transmission lane;
A delay time obtained by subtracting the arrival time of the control code transmitted from the first transmission lane from the arrival time of the control code transmitted from the second transmission lane for each of the operation clock signals having a plurality of different phases. A calculating step;
And serially transmitting the target code of the second transmission lane using the operation clock signal having the smallest delay time among the delay times for the operation clock signals having a plurality of different phases.   A program for causing a computer to execute the communication method according to claim 8 or 9.

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