JP2021507383A5 - - Google Patents
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- JP2021507383A5 JP2021507383A5 JP2020532976A JP2020532976A JP2021507383A5 JP 2021507383 A5 JP2021507383 A5 JP 2021507383A5 JP 2020532976 A JP2020532976 A JP 2020532976A JP 2020532976 A JP2020532976 A JP 2020532976A JP 2021507383 A5 JP2021507383 A5 JP 2021507383A5
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- 210000004027 cell Anatomy 0.000 claims 35
- 210000000352 storage cell Anatomy 0.000 claims 16
- 238000000034 method Methods 0.000 claims 12
- 230000010354 integration Effects 0.000 claims 1
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762610119P | 2017-12-22 | 2017-12-22 | |
| US62/610,119 | 2017-12-22 | ||
| US15/984,255 | 2018-05-18 | ||
| US15/984,255 US11436143B2 (en) | 2017-12-22 | 2018-05-18 | Unified memory organization for neural network processors |
| PCT/US2018/067301 WO2019126758A1 (en) | 2017-12-22 | 2018-12-21 | A unified memory organization for neural network processors |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021507383A JP2021507383A (ja) | 2021-02-22 |
| JP2021507383A5 true JP2021507383A5 (enExample) | 2022-01-11 |
| JP7266602B2 JP7266602B2 (ja) | 2023-04-28 |
Family
ID=66949585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020532976A Active JP7266602B2 (ja) | 2017-12-22 | 2018-12-21 | ニューラルネットワークプロセッサに対する統合メモリ構造 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11436143B2 (enExample) |
| EP (1) | EP3729279B1 (enExample) |
| JP (1) | JP7266602B2 (enExample) |
| CN (1) | CN111630502B (enExample) |
| WO (1) | WO2019126758A1 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11783167B1 (en) | 2018-04-20 | 2023-10-10 | Perceive Corporation | Data transfer for non-dot product computations on neural network inference circuit |
| US11568227B1 (en) | 2018-04-20 | 2023-01-31 | Perceive Corporation | Neural network inference circuit read controller with multiple operational modes |
| US12093696B1 (en) | 2018-04-20 | 2024-09-17 | Perceive Corporation | Bus for transporting output values of a neural network layer to cores specified by configuration data |
| US10977338B1 (en) | 2018-04-20 | 2021-04-13 | Perceive Corporation | Reduced-area circuit for dot product computation |
| US11341397B1 (en) | 2018-04-20 | 2022-05-24 | Perceive Corporation | Computation of neural network node |
| US11586910B1 (en) * | 2018-04-20 | 2023-02-21 | Perceive Corporation | Write cache for neural network inference circuit |
| US11481612B1 (en) | 2018-04-20 | 2022-10-25 | Perceive Corporation | Storage of input values across multiple cores of neural network inference circuit |
| US11461623B2 (en) * | 2018-10-18 | 2022-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for defect-tolerant memory-based artificial neural network |
| US11995533B1 (en) | 2018-12-05 | 2024-05-28 | Perceive Corporation | Executing replicated neural network layers on inference circuit |
| FR3089649A1 (fr) * | 2018-12-06 | 2020-06-12 | Stmicroelectronics (Rousset) Sas | Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones |
| FR3094104A1 (fr) | 2019-03-20 | 2020-09-25 | Stmicroelectronics (Rousset) Sas | Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones compte tenu de sa topologie |
| US11941533B1 (en) | 2019-05-21 | 2024-03-26 | Perceive Corporation | Compiler for performing zero-channel removal |
| CN113204478B (zh) * | 2021-04-06 | 2022-05-03 | 北京百度网讯科技有限公司 | 测试单元的运行方法、装置、设备和存储介质 |
| US12159214B1 (en) | 2021-04-23 | 2024-12-03 | Perceive Corporation | Buffering of neural network inputs and outputs |
| KR102509472B1 (ko) * | 2022-06-07 | 2023-03-14 | 리벨리온 주식회사 | 뉴럴 프로세싱 장치 및 그의 공유 페이지 테이블 사용 방법 |
| KR20230168574A (ko) | 2022-06-07 | 2023-12-14 | 리벨리온 주식회사 | 뉴럴 프로세싱 장치의 공유 페이지 테이블 사용 방법 및 피지컬 페이지 할당 방법 |
| KR102774907B1 (ko) * | 2022-12-14 | 2025-03-04 | 리벨리온 주식회사 | 뉴럴 프로세서 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02292684A (ja) * | 1989-05-06 | 1990-12-04 | Takayama:Kk | 画像認識システム |
| US5956703A (en) * | 1995-07-28 | 1999-09-21 | Delco Electronics Corporation | Configurable neural network integrated circuit |
| JP2001290699A (ja) | 2000-04-10 | 2001-10-19 | Matsushita Electric Ind Co Ltd | デュアルポートｒａｍアクセス装置 |
| US7073044B2 (en) * | 2001-03-30 | 2006-07-04 | Intel Corporation | Method and apparatus for sharing TLB entries |
| GB2417111B (en) | 2002-04-22 | 2006-08-16 | Micron Technology Inc | Providing a register file memory with local addressing in a SIMD parallel processor |
| GB2417105B (en) | 2004-08-13 | 2008-04-09 | Clearspeed Technology Plc | Processor memory system |
| GB0623276D0 (en) * | 2006-11-22 | 2007-01-03 | Transitive Ltd | Memory consistency protection in a multiprocessor computing system |
| US8271763B2 (en) | 2009-09-25 | 2012-09-18 | Nvidia Corporation | Unified addressing and instructions for accessing parallel memory spaces |
| US8990506B2 (en) * | 2009-12-16 | 2015-03-24 | Intel Corporation | Replacing cache lines in a cache memory based at least in part on cache coherency state information |
| US8868848B2 (en) * | 2009-12-21 | 2014-10-21 | Intel Corporation | Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform |
| US8982140B2 (en) * | 2010-09-24 | 2015-03-17 | Nvidia Corporation | Hierarchical memory addressing |
| US9274960B2 (en) * | 2012-03-20 | 2016-03-01 | Stefanos Kaxiras | System and method for simplifying cache coherence using multiple write policies |
| US9009419B2 (en) * | 2012-07-31 | 2015-04-14 | Advanced Micro Devices, Inc. | Shared memory space in a unified memory model |
| CN104756078B (zh) * | 2012-08-20 | 2018-07-13 | 唐纳德·凯文·卡梅伦 | 处理资源分配的装置和方法 |
| US9563425B2 (en) * | 2012-11-28 | 2017-02-07 | Intel Corporation | Instruction and logic to provide pushing buffer copy and store functionality |
| US9733995B2 (en) * | 2014-12-17 | 2017-08-15 | Intel Corporation | Scalable synchronization mechanism for distributed memory |
| EP3035204B1 (en) | 2014-12-19 | 2018-08-15 | Intel Corporation | Storage device and method for performing convolution operations |
| US10324861B2 (en) * | 2015-02-05 | 2019-06-18 | Eta Scale Ab | Systems and methods for coherence in clustered cache hierarchies |
| US9940287B2 (en) * | 2015-03-27 | 2018-04-10 | Intel Corporation | Pooled memory address translation |
| US10664751B2 (en) | 2016-12-01 | 2020-05-26 | Via Alliance Semiconductor Co., Ltd. | Processor with memory array operable as either cache memory or neural network unit memory |
| GB2543520B (en) * | 2015-10-20 | 2019-06-19 | Advanced Risc Mach Ltd | Memory access instructions |
| US20170060736A1 (en) * | 2015-12-09 | 2017-03-02 | Mediatek Inc. | Dynamic Memory Sharing |
-
2018
- 2018-05-18 US US15/984,255 patent/US11436143B2/en active Active
- 2018-12-21 JP JP2020532976A patent/JP7266602B2/ja active Active
- 2018-12-21 CN CN201880074349.6A patent/CN111630502B/zh active Active
- 2018-12-21 WO PCT/US2018/067301 patent/WO2019126758A1/en not_active Ceased
- 2018-12-21 EP EP18890583.0A patent/EP3729279B1/en active Active
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