JP7266602B2 - ニューラルネットワークプロセッサに対する統合メモリ構造 - Google Patents

ニューラルネットワークプロセッサに対する統合メモリ構造 Download PDF

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JP7266602B2
JP7266602B2 JP2020532976A JP2020532976A JP7266602B2 JP 7266602 B2 JP7266602 B2 JP 7266602B2 JP 2020532976 A JP2020532976 A JP 2020532976A JP 2020532976 A JP2020532976 A JP 2020532976A JP 7266602 B2 JP7266602 B2 JP 7266602B2
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ハン，リャン
ジャン，シャオウェイ
チェン，ジャン
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アリババ グループ ホウルディング リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Neurology (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP2020532976A 2017-12-22 2018-12-21 ニューラルネットワークプロセッサに対する統合メモリ構造 Active JP7266602B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762610119P 2017-12-22 2017-12-22
US62/610,119 2017-12-22
US15/984,255 2018-05-18
US15/984,255 US11436143B2 (en) 2017-12-22 2018-05-18 Unified memory organization for neural network processors
PCT/US2018/067301 WO2019126758A1 (en) 2017-12-22 2018-12-21 A unified memory organization for neural network processors

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JP2021507383A JP2021507383A (ja) 2021-02-22
JP2021507383A5 JP2021507383A5 (enExample) 2022-01-11
JP7266602B2 true JP7266602B2 (ja) 2023-04-28

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US (1) US11436143B2 (enExample)
EP (1) EP3729279B1 (enExample)
JP (1) JP7266602B2 (enExample)
CN (1) CN111630502B (enExample)
WO (1) WO2019126758A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11586910B1 (en) * 2018-04-20 2023-02-21 Perceive Corporation Write cache for neural network inference circuit
US11481612B1 (en) 2018-04-20 2022-10-25 Perceive Corporation Storage of input values across multiple cores of neural network inference circuit
US12093696B1 (en) 2018-04-20 2024-09-17 Perceive Corporation Bus for transporting output values of a neural network layer to cores specified by configuration data
US11783167B1 (en) 2018-04-20 2023-10-10 Perceive Corporation Data transfer for non-dot product computations on neural network inference circuit
US10740434B1 (en) 2018-04-20 2020-08-11 Perceive Corporation Reduced dot product computation circuit
US11568227B1 (en) 2018-04-20 2023-01-31 Perceive Corporation Neural network inference circuit read controller with multiple operational modes
US11295200B1 (en) 2018-04-20 2022-04-05 Perceive Corporation Time-multiplexed dot products for neural network inference circuit
US11461623B2 (en) * 2018-10-18 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for defect-tolerant memory-based artificial neural network
US11995533B1 (en) 2018-12-05 2024-05-28 Perceive Corporation Executing replicated neural network layers on inference circuit
FR3089649A1 (fr) * 2018-12-06 2020-06-12 Stmicroelectronics (Rousset) Sas Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones
FR3094104A1 (fr) 2019-03-20 2020-09-25 Stmicroelectronics (Rousset) Sas Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones compte tenu de sa topologie
US11615322B1 (en) 2019-05-21 2023-03-28 Perceive Corporation Compiler for implementing memory shutdown for neural network implementation configuration
CN113204478B (zh) * 2021-04-06 2022-05-03 北京百度网讯科技有限公司 测试单元的运行方法、装置、设备和存储介质
US12159214B1 (en) 2021-04-23 2024-12-03 Perceive Corporation Buffering of neural network inputs and outputs
KR20230168574A (ko) 2022-06-07 2023-12-14 리벨리온 주식회사 뉴럴 프로세싱 장치의 공유 페이지 테이블 사용 방법 및 피지컬 페이지 할당 방법
KR102509472B1 (ko) * 2022-06-07 2023-03-14 리벨리온 주식회사 뉴럴 프로세싱 장치 및 그의 공유 페이지 테이블 사용 방법
KR102774907B1 (ko) * 2022-12-14 2025-03-04 리벨리온 주식회사 뉴럴 프로세서

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001290699A (ja) 2000-04-10 2001-10-19 Matsushita Electric Ind Co Ltd デュアルポートｒａｍアクセス装置
JP6250780B1 (ja) 2016-12-01 2017-12-20 ヴィア アライアンス セミコンダクター カンパニー リミテッド キャッシュメモリ又はニューラルネットワークユニットメモリとして動作可能なメモリアレイを有するプロセッサ

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02292684A (ja) * 1989-05-06 1990-12-04 Takayama:Kk 画像認識システム
US5956703A (en) * 1995-07-28 1999-09-21 Delco Electronics Corporation Configurable neural network integrated circuit
US7073044B2 (en) * 2001-03-30 2006-07-04 Intel Corporation Method and apparatus for sharing TLB entries
GB2419005B (en) 2002-04-22 2006-06-07 Micron Technology Inc Providing a register file memory with local addressing in a SIMD parallel processor
GB2417105B (en) 2004-08-13 2008-04-09 Clearspeed Technology Plc Processor memory system
GB0623276D0 (en) * 2006-11-22 2007-01-03 Transitive Ltd Memory consistency protection in a multiprocessor computing system
US8271763B2 (en) 2009-09-25 2012-09-18 Nvidia Corporation Unified addressing and instructions for accessing parallel memory spaces
US8990506B2 (en) * 2009-12-16 2015-03-24 Intel Corporation Replacing cache lines in a cache memory based at least in part on cache coherency state information
US8868848B2 (en) * 2009-12-21 2014-10-21 Intel Corporation Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform
US8982140B2 (en) * 2010-09-24 2015-03-17 Nvidia Corporation Hierarchical memory addressing
US9274960B2 (en) * 2012-03-20 2016-03-01 Stefanos Kaxiras System and method for simplifying cache coherence using multiple write policies
US9009419B2 (en) * 2012-07-31 2015-04-14 Advanced Micro Devices, Inc. Shared memory space in a unified memory model
WO2014031540A1 (en) * 2012-08-20 2014-02-27 Cameron Donald Kevin Processing resource allocation
US9563425B2 (en) * 2012-11-28 2017-02-07 Intel Corporation Instruction and logic to provide pushing buffer copy and store functionality
US9733995B2 (en) * 2014-12-17 2017-08-15 Intel Corporation Scalable synchronization mechanism for distributed memory
EP3035204B1 (en) 2014-12-19 2018-08-15 Intel Corporation Storage device and method for performing convolution operations
US10324861B2 (en) * 2015-02-05 2019-06-18 Eta Scale Ab Systems and methods for coherence in clustered cache hierarchies
US9940287B2 (en) * 2015-03-27 2018-04-10 Intel Corporation Pooled memory address translation
GB2543520B (en) * 2015-10-20 2019-06-19 Advanced Risc Mach Ltd Memory access instructions
US20170060736A1 (en) * 2015-12-09 2017-03-02 Mediatek Inc. Dynamic Memory Sharing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001290699A (ja) 2000-04-10 2001-10-19 Matsushita Electric Ind Co Ltd デュアルポートｒａｍアクセス装置
JP6250780B1 (ja) 2016-12-01 2017-12-20 ヴィア アライアンス セミコンダクター カンパニー リミテッド キャッシュメモリ又はニューラルネットワークユニットメモリとして動作可能なメモリアレイを有するプロセッサ

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EP3729279A1 (en) 2020-10-28
US20190196970A1 (en) 2019-06-27
EP3729279A4 (en) 2021-03-03
WO2019126758A1 (en) 2019-06-27
CN111630502A (zh) 2020-09-04
EP3729279B1 (en) 2025-05-21
CN111630502B (zh) 2024-04-16
US11436143B2 (en) 2022-09-06
JP2021507383A (ja) 2021-02-22

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