JP2021192432A5 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP2021192432A5 JP2021192432A5 JP2021128401A JP2021128401A JP2021192432A5 JP 2021192432 A5 JP2021192432 A5 JP 2021192432A5 JP 2021128401 A JP2021128401 A JP 2021128401A JP 2021128401 A JP2021128401 A JP 2021128401A JP 2021192432 A5 JP2021192432 A5 JP 2021192432A5
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- 239000004065 semiconductor Substances 0.000 title claims 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 2
- 229910052719 titanium Inorganic materials 0.000 claims 2
- 239000010936 titanium Substances 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
Claims (5)
前記第1のトランジスタは、ソースまたはドレインの一方が前記発光素子の画素電極と電気的に接続され、ソースまたはドレインの他方が電流供給線と電気的に接続され、In the first transistor, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element, and the other of the source and the drain is electrically connected to the current supply line.
前記第2のトランジスタは、ソースまたはドレインの一方が信号線と電気的に接続され、ソースまたはドレインの他方が前記第1のトランジスタのゲート電極と電気的に接続され、In the second transistor, one of the source and the drain is electrically connected to the signal line, and the other of the source and the drain is electrically connected to the gate electrode of the first transistor.
前記第3のトランジスタは、ソースまたはドレインの一方が配線と電気的に接続され、ソースまたはドレインの他方が前記画素電極と電気的に接続され、In the third transistor, one of the source and the drain is electrically connected to the wiring, and the other of the source and the drain is electrically connected to the pixel electrode.
前記電流供給線としての機能を有する第1の導電層は、前記信号線としての機能を有する第2の導電層と同層に配置され、The first conductive layer having a function as the current supply line is arranged in the same layer as the second conductive layer having a function as the signal line.
前記第1の導電層及び前記第2の導電層は、前記配線としての機能を有する第3の導電層よりも上層に配置され、The first conductive layer and the second conductive layer are arranged above the third conductive layer having a function as the wiring.
前記第3の導電層は、前記第1のトランジスタのゲート電極よりも上層に配置され、The third conductive layer is arranged above the gate electrode of the first transistor.
前記第3の導電層は、前記第2のトランジスタのソースまたはドレインの一方と電気的に接続された第4の導電層と、前記第2のトランジスタのソースまたはドレインの他方と電気的に接続された第5の導電層と、前記第1のトランジスタのソースまたはドレインの一方と電気的に接続され、かつ、前記第3のトランジスタのソースまたはドレインの他方と電気的に接続された第6の導電層と、同層に配置され、The third conductive layer is electrically connected to a fourth conductive layer electrically connected to one of the source or drain of the second transistor and to the other of the source or drain of the second transistor. The fifth conductive layer is electrically connected to one of the source or drain of the first transistor, and is electrically connected to the other of the source or drain of the third transistor. Placed in the same layer as the layer,
前記第3の導電層は、前記第1の導電層及び前記第2の導電層と同じ方向に延伸している領域を有し、The third conductive layer has a region extending in the same direction as the first conductive layer and the second conductive layer.
前記第1の導電層は、前記第3の導電層と重なりを有し、The first conductive layer has an overlap with the third conductive layer and has an overlap.
前記第1の導電層は、前記第1のトランジスタのゲート電極と重なりを有し、The first conductive layer has an overlap with the gate electrode of the first transistor and has an overlap.
前記第1の導電層は、前記第3のトランジスタのゲート電極と重なりを有し、The first conductive layer has an overlap with the gate electrode of the third transistor and has an overlap.
前記第6の導電層は、前記第1の導電層及び前記第2の導電層と同層に配置された第7の導電層を介して、前記画素電極と電気的に接続される半導体装置。The sixth conductive layer is a semiconductor device electrically connected to the pixel electrode via a seventh conductive layer arranged in the same layer as the first conductive layer and the second conductive layer.
前記第1のトランジスタは、ソースまたはドレインの一方が前記発光素子の画素電極と電気的に接続され、ソースまたはドレインの他方が電流供給線と電気的に接続され、In the first transistor, one of the source and the drain is electrically connected to the pixel electrode of the light emitting element, and the other of the source and the drain is electrically connected to the current supply line.
前記第2のトランジスタは、ソースまたはドレインの一方が信号線と電気的に接続され、ソースまたはドレインの他方が前記第1のトランジスタのゲート電極と電気的に接続され、In the second transistor, one of the source and the drain is electrically connected to the signal line, and the other of the source and the drain is electrically connected to the gate electrode of the first transistor.
前記第3のトランジスタは、ソースまたはドレインの一方が配線と電気的に接続され、ソースまたはドレインの他方が前記画素電極と電気的に接続され、In the third transistor, one of the source and the drain is electrically connected to the wiring, and the other of the source and the drain is electrically connected to the pixel electrode.
前記第2のトランジスタのゲート電極と前記第3のトランジスタのゲート電極とは、互いに異なる走査線と電気的に接続され、The gate electrode of the second transistor and the gate electrode of the third transistor are electrically connected to different scanning lines.
前記電流供給線としての機能を有する第1の導電層は、前記信号線としての機能を有する第2の導電層と同層に配置され、The first conductive layer having a function as the current supply line is arranged in the same layer as the second conductive layer having a function as the signal line.
前記第1の導電層及び前記第2の導電層は、前記配線としての機能を有する第3の導電層よりも上層に配置され、The first conductive layer and the second conductive layer are arranged above the third conductive layer having a function as the wiring.
前記第3の導電層は、前記第1のトランジスタのゲート電極よりも上層に配置され、The third conductive layer is arranged above the gate electrode of the first transistor.
前記第3の導電層は、前記第2のトランジスタのソースまたはドレインの一方と電気的に接続された第4の導電層と、前記第2のトランジスタのソースまたはドレインの他方と電気的に接続された第5の導電層と、前記第1のトランジスタのソースまたはドレインの一方と電気的に接続され、かつ、前記第3のトランジスタのソースまたはドレインの他方と電気的に接続された第6の導電層と、同層に配置され、The third conductive layer is electrically connected to a fourth conductive layer electrically connected to one of the source or drain of the second transistor and to the other of the source or drain of the second transistor. The fifth conductive layer is electrically connected to one of the source or drain of the first transistor, and is electrically connected to the other of the source or drain of the third transistor. Placed in the same layer as the layer,
前記第3の導電層は、前記第1の導電層及び前記第2の導電層と同じ方向に延伸している領域を有し、The third conductive layer has a region extending in the same direction as the first conductive layer and the second conductive layer.
前記第1の導電層は、前記第3の導電層と重なりを有し、The first conductive layer has an overlap with the third conductive layer and has an overlap.
前記第1の導電層は、前記第1のトランジスタのゲート電極と重なりを有し、The first conductive layer has an overlap with the gate electrode of the first transistor and has an overlap.
前記第1の導電層は、前記第3のトランジスタのゲート電極と重なりを有し、The first conductive layer has an overlap with the gate electrode of the third transistor and has an overlap.
前記第6の導電層は、前記第1の導電層及び前記第2の導電層と同層に配置された第7の導電層を介して、前記画素電極と電気的に接続される半導体装置。The sixth conductive layer is a semiconductor device electrically connected to the pixel electrode via a seventh conductive layer arranged in the same layer as the first conductive layer and the second conductive layer.
前記第1の導電層乃至前記第7の導電層は、チタンまたは窒化チタンを含む第1の膜と、前記第1の膜上のアルミニウムを含む第2の膜と、前記第2の膜上のチタンまたは窒化チタンを含む第3の膜と、をそれぞれ有する半導体装置。The first conductive layer to the seventh conductive layer is on a first film containing titanium or titanium nitride, a second film containing aluminum on the first film, and on the second film. A semiconductor device having a third film containing titanium or titanium nitride, respectively.
平面視において、前記第6の導電層の面積は、前記第4の導電層の面積よりも大きい半導体装置。A semiconductor device in which the area of the sixth conductive layer is larger than the area of the fourth conductive layer in a plan view.
平面視において、前記第6の導電層の面積は、前記第5の導電層の面積よりも大きい半導体装置。A semiconductor device in which the area of the sixth conductive layer is larger than the area of the fifth conductive layer in a plan view.
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JP2022047778A JP7082252B1 (en) | 2015-12-28 | 2022-03-24 | Semiconductor device |
JP2022065607A JP7079387B1 (en) | 2015-12-28 | 2022-04-12 | Semiconductor device |
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JP2015256583 | 2015-12-28 | ||
JP2015256583 | 2015-12-28 | ||
JP2016218998 | 2016-11-09 | ||
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JP2021192432A JP2021192432A (en) | 2021-12-16 |
JP2021192432A5 true JP2021192432A5 (en) | 2022-03-22 |
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JP2021128401A Active JP7058791B2 (en) | 2015-12-28 | 2021-08-04 | Semiconductor device |
JP2022047778A Active JP7082252B1 (en) | 2015-12-28 | 2022-03-24 | Semiconductor device |
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JP2022082726A Active JP7105394B1 (en) | 2015-12-28 | 2022-05-20 | semiconductor equipment |
JP2022110972A Active JP7140937B1 (en) | 2015-12-28 | 2022-07-11 | semiconductor equipment |
JP2022142945A Active JP7173717B1 (en) | 2015-12-28 | 2022-09-08 | semiconductor equipment |
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JP2022203857A Active JP7228746B1 (en) | 2015-12-28 | 2022-12-21 | semiconductor equipment |
JP2023019800A Active JP7298040B2 (en) | 2015-12-28 | 2023-02-13 | light emitting device |
JP2023097652A Active JP7402373B2 (en) | 2015-12-28 | 2023-06-14 | light emitting device |
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KR102401432B1 (en) | 2014-02-24 | 2022-05-26 | 엘지디스플레이 주식회사 | Display device |
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