JP2021180333A - Semiconductor device - Google Patents

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JP2021180333A
JP2021180333A JP2021128134A JP2021128134A JP2021180333A JP 2021180333 A JP2021180333 A JP 2021180333A JP 2021128134 A JP2021128134 A JP 2021128134A JP 2021128134 A JP2021128134 A JP 2021128134A JP 2021180333 A JP2021180333 A JP 2021180333A
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conductive layer
main surface
hole
film
semiconductor device
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昭彦 野村
Akihiko Nomura
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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Abstract

To provide a reliable semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate having one main surface and another main surface opposite to the one main surface; a first conductive layer provided on the other main surface side; a second conductive layer provided on the semiconductor substrate in a through hole that penetrates the semiconductor substrate from the one main surface to the other main surface in a thickness direction and exposes the first conductive layer; a third conductive layer in the through hole provided on the first conductive layer; and a fourth conductive layer formed between the second conductive layer and the third conductive layer at an end of the through hole.SELECTED DRAWING: Figure 5

Description

本発明は、半導体装置に関し、特に、シリコン貫通電極（ＴＳＶ：Through Silicon Via）を備える半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a through silicon via (TSV).

シリコン基板等の半導体基板を貫通する貫通孔を介して電極を設ける構造を備える半導体装置やその製造方法が種々提案されている。 Various semiconductor devices having a structure in which electrodes are provided through through holes penetrating a semiconductor substrate such as a silicon substrate and methods for manufacturing the same have been proposed.

特開２００５−２９４３２０号公報Japanese Unexamined Patent Publication No. 2005-294320 特開２０１０−１１４２０１号公報Japanese Unexamined Patent Publication No. 2010-114201 特開２００８−５３４３０号公報Japanese Unexamined Patent Publication No. 2008-53430

本発明者がＴＳＶを備える半導体装置およびその製造方法を鋭意研究した結果、シリコン基板に設けられた貫通孔に形成したメッキ用のシード層にピンホール等の欠陥が生じ、その欠陥からシリコン基板の表面に設けた電極層に侵食が生じてしまい、それが原因となって、半導体装置の信頼性が低くなってしまうことがあることを見出した。 As a result of diligent research by the present inventor on a semiconductor device equipped with a TSV and a method for manufacturing the same, defects such as pinholes occur in the seed layer for plating formed in the through holes provided in the silicon substrate, and the defects cause defects in the silicon substrate. It has been found that the electrode layer provided on the surface is eroded, which may reduce the reliability of the semiconductor device.

本発明の主な目的は、基板に設けられた貫通電極を備える半導体装置であって、信頼性の高い半導体装置を提供することにある。 A main object of the present invention is to provide a semiconductor device provided with a through electrode provided on a substrate, and to provide a highly reliable semiconductor device.

本発明の第１の態様に係る半導体装置は、一主面と前記一主面とは反対側の他の主面とを有する半導体基板と、前記他の主面側に設けられた第１の導電層と、前記一主面から前記他の主面まで前記半導体基板を厚さ方向に貫通して前記第１の導電層を露出する貫通孔内であって前記半導体基板上に設けられた第２の導電層と、前記貫通孔内であって前記第１の導電層上に設けられた第３の導電層と、前記貫通孔の端部であって前記第２の導電層と前記第３の導電層の間に形成された第４の導電層と、を備える。 The semiconductor device according to the first aspect of the present invention includes a semiconductor substrate having one main surface and another main surface opposite to the one main surface, and a first surface provided on the other main surface side. A first provided on the semiconductor substrate in a through hole that penetrates the semiconductor substrate from the one main surface to the other main surface in the thickness direction and exposes the first conductive layer. The second conductive layer, the third conductive layer in the through hole provided on the first conductive layer, the second conductive layer at the end of the through hole, and the third conductive layer. A fourth conductive layer formed between the conductive layers of the above.

本発明の第２の態様に係る半導体装置は、一主面と前記一主面とは反対側の他の主面とを有する半導体基板と、前記他の主面側に設けられた第１の導電層と、前記第１の導電層上に設けられた第２の導電層と、前記一主面から前記他の主面まで前記半導体基板を厚さ方向に貫通して前記第１の導電層を露出する貫通孔内であって前記半導体基板上に設けられた第３の導電層と、前記貫通孔内であって前記第１の導電層上に設けられた第４の導電層と、前記第３の導電層と前記第４の導電層の間に前記第３の導電層及び前記第４の導電層の一方と一体に形成され、前記第３の導電層及び前記第４の導電層のいずれよりも厚さが小さい第５の導電層と、を備える。 The semiconductor device according to the second aspect of the present invention includes a semiconductor substrate having one main surface and another main surface opposite to the one main surface, and a first surface provided on the other main surface side. The conductive layer, the second conductive layer provided on the first conductive layer, and the first conductive layer penetrating the semiconductor substrate from the one main surface to the other main surface in the thickness direction. A third conductive layer provided on the semiconductor substrate in the through hole that exposes the surface, a fourth conductive layer provided on the first conductive layer in the through hole, and the above. Between the third conductive layer and the fourth conductive layer, the third conductive layer and one of the fourth conductive layers are integrally formed, and the third conductive layer and the fourth conductive layer are formed. A fifth conductive layer having a thickness smaller than any of the above is provided.

本発明によれば、信頼性の高い半導体装置が提供される。 According to the present invention, a highly reliable semiconductor device is provided.

図１−１は、本発明の好ましい第１の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 1-1 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred first embodiment of the present invention. 図１−２は、本発明の好ましい第１の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 1-2 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred first embodiment of the present invention. 図１−３は、本発明の好ましい第１の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 1-3 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred first embodiment of the present invention. 図１−４は、本発明の好ましい第１の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 1-4 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred first embodiment of the present invention. 図１−５は、本発明の好ましい第１の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 1-5 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred first embodiment of the present invention. 図２は、図１−３（Ｆ）のＡ部の部分拡大概略縦断面図である。FIG. 2 is a partially enlarged schematic vertical sectional view of a part A of FIG. 1-3 (F). 図３は、図１−３（Ｇ）のＢ部の部分拡大概略縦断面図である。FIG. 3 is a partially enlarged schematic vertical sectional view of a portion B of FIG. 1-3 (G). 図４は、図３のＣ部の部分拡大概略縦断面図である。FIG. 4 is a partially enlarged schematic vertical sectional view of a portion C in FIG. 図５は、図１−４（Ｈ）のＤ部の部分拡大概略縦断面図である。FIG. 5 is a partially enlarged schematic vertical sectional view of a portion D in FIG. 1-4 (H). 図６−１は、本発明の好ましい第２の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 6-1 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred second embodiment of the present invention. 図６−２は、本発明の好ましい第２の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 6-2 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred second embodiment of the present invention. 図６−３は、本発明の好ましい第２の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 6-3 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred second embodiment of the present invention. 図６−４は、本発明の好ましい第２の実施の形態の半導体装置の製造方法を説明するための概略縦断面図である。FIG. 6-4 is a schematic vertical sectional view for explaining a method for manufacturing a semiconductor device according to a preferred second embodiment of the present invention. 図７は、図６−１（Ｃ）のＥ部の部分拡大概略縦断面図である。FIG. 7 is a partially enlarged schematic vertical sectional view of a portion E of FIG. 6-1 (C). 図８は、図６−２（Ｄ）のＦ部の部分拡大概略縦断面図である。FIG. 8 is a partially enlarged schematic vertical sectional view of the F portion of FIG. 6-2 (D). 図９は、図６−２（Ｅ）のＧ部の部分拡大概略縦断面図である。FIG. 9 is a partially enlarged schematic vertical sectional view of a portion G in FIG. 6-2 (E). 図１０は、図６−３（Ｆ）のＨ部の部分拡大概略縦断面図である。FIG. 10 is a partially enlarged schematic vertical sectional view of the H portion of FIG. 6-3 (F). 図１１は、図６−３（Ｇ）のＩ部の部分拡大概略縦断面図である。FIG. 11 is a partially enlarged schematic vertical sectional view of a part I of FIG. 6-3 (G). 図１２は、比較のための半導体装置の製造方法を説明するための概略縦断面図である。FIG. 12 is a schematic vertical sectional view for explaining a method of manufacturing a semiconductor device for comparison. 図１３は、図１２のＪ部の部分拡大概略縦断面図である。FIG. 13 is a partially enlarged schematic vertical sectional view of a portion J in FIG. 図１４は、比較のための半導体装置の製造方法を説明するための概略縦断面図である。FIG. 14 is a schematic vertical sectional view for explaining a method of manufacturing a semiconductor device for comparison. 図１５は、図１４のＫ部の部分拡大概略縦断面図である。FIG. 15 is a partially enlarged schematic vertical sectional view of the K portion of FIG.

以下、本発明の好ましい実施の形態について図面を参照しながら説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

（第１の実施の形態）
図１−５（Ｊ）を参照すれば、本発明の好ましい第１の実施の形態の半導体装置１は、半導体シリコン基板１０と、酸化シリコン膜１２と、ＴｉＮ膜１４と、Ａｌ膜１６と、貫通孔２０と、ＣＶＤ酸化膜２２と、シードメタル層２４と、Ｃｕめっき層２６と、Ｃｕめっき層３０と、ソルダーレジスト３２とを備えている。 (First Embodiment)
Referring to FIG. 1-5 (J), the semiconductor device 1 of the preferred first embodiment of the present invention includes a semiconductor silicon substrate 10, a silicon oxide film 12, a TiN film 14, and an Al film 16. It includes a through hole 20, a CVD oxide film 22, a seed metal layer 24, a Cu plating layer 26, a Cu plating layer 30, and a solder resist 32.

酸化シリコン膜１２は、シリコン基板１０の主面１１上に設けられている。ＴｉＮ膜１４は、酸化シリコン膜１２上に設けられている。Ａｌ膜１６は、ＴｉＮ膜１４上に設けられている。貫通孔２０は、シリコン基板１０の主面１１とは反対側の主面１３から主面１１までシリコン基板１０を貫通し、さらに酸化シリコン膜１２およびＴｉＮ膜１４を貫通し、底部にＡｌ膜１６を露出して設けられている。ＣＶＤ酸化膜２２は、貫通孔２０の側面２１およびシリコン基板１０の主面１３上に設けられている。シードメタル層２４は、貫通孔２０内のＣＶＤ酸化膜２２上および主面１３上のＣＶＤ酸化膜２２上ならびに貫通孔２０の底部に露出するＡｌ膜１６上に設けられている。Ｃｕめっき層２６は、貫通孔２０内のシードメタル層２４上および主面１３上のシードメタル層２４上ならびに貫通孔２０の底部に設けられたシードメタル層２４上に設けられている。Ｃｕめっき層３０は、貫通孔２０内のＣｕめっき層２６上および主面１３上のＣｕめっき層２６上ならびに貫通孔２０の底部に設けられたＣｕめっき層２６上に設けられている。ソルダーレジスト３２は、シリコン基板１０の主面１３上のＣＶＤ酸化膜２２上、主面１３上のＣｕめっき層３０上および貫通孔２０内のＣｕめっき層３０の開孔３１内に設けられている。なお、ＭＯＳトランジスタ等の半導体素子等の回路素子（図示せず）は、シリコン基板１０の主面１１に形成され、酸化シリコン膜１２によって覆われている。Ａｌ膜１６は、半導体装置１を接続するデバイスパッド等として用いられる。 The silicon oxide film 12 is provided on the main surface 11 of the silicon substrate 10. The TiN film 14 is provided on the silicon oxide film 12. The Al film 16 is provided on the TiN film 14. The through hole 20 penetrates the silicon substrate 10 from the main surface 13 on the opposite side of the main surface 11 of the silicon substrate 10 to the main surface 11, further penetrates the silicon oxide film 12 and the TiN film 14, and the Al film 16 at the bottom. Is exposed and provided. The CVD oxide film 22 is provided on the side surface 21 of the through hole 20 and the main surface 13 of the silicon substrate 10. The seed metal layer 24 is provided on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the Al film 16 exposed at the bottom of the through hole 20. The Cu plating layer 26 is provided on the seed metal layer 24 in the through hole 20, the seed metal layer 24 on the main surface 13, and the seed metal layer 24 provided at the bottom of the through hole 20. The Cu plating layer 30 is provided on the Cu plating layer 26 in the through hole 20, the Cu plating layer 26 on the main surface 13, and the Cu plating layer 26 provided at the bottom of the through hole 20. The solder resist 32 is provided on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the openings 31 of the Cu plating layer 30 in the through holes 20. .. A circuit element (not shown) such as a semiconductor element such as a MOS transistor is formed on the main surface 11 of the silicon substrate 10 and is covered with the silicon oxide film 12. The Al film 16 is used as a device pad or the like for connecting the semiconductor device 1.

次に、図１−１〜１−５、図２〜５を参照して本発明の好ましい第１の実施の形態の半導体装置１の製造方法を説明する。 Next, a method for manufacturing the semiconductor device 1 according to the first preferred embodiment of the present invention will be described with reference to FIGS. 1-1 to 1-5 and FIGS. 2 to 5.

ＭＯＳトランジスタ等の半導体素子等の回路素子（図示せず）を、シリコン基板１０の主面１１に形成する。 A circuit element (not shown) such as a semiconductor element such as a MOS transistor is formed on the main surface 11 of the silicon substrate 10.

図１―１（Ａ）を参照すれば、次に、シリコン基板１０の主面１１上に酸化シリコン膜１２を形成し、酸化シリコン膜１２上にＴｉＮ膜１４を形成し、ＴｉＮ膜１４上にＡｌ膜１６を形成する。なお、ＴｉＮ膜１４はＡｌのマイグレーションを防止するために設けている。 Referring to FIG. 1-1 (A), next, a silicon oxide film 12 is formed on the main surface 11 of the silicon substrate 10, a TiN film 14 is formed on the silicon oxide film 12, and the TiN film 14 is formed on the TiN film 14. The Al film 16 is formed. The TiN film 14 is provided to prevent Al migration.

図１―１（Ｂ）を参照すれば、次に、シリコン基板１０の主面１１とは反対側の主面１３上にレジスト１８を形成し、レジスト１８に選択的に開孔１９を形成する。その後、レジスト１８をマスクとしてシリコン基板１０をエッチングして、シリコン基板１０の主面１３から主面１１までシリコン基板１０を貫通する貫通孔２０を形成する。 Referring to FIG. 1-1 (B), next, a resist 18 is formed on the main surface 13 opposite to the main surface 11 of the silicon substrate 10, and a hole 19 is selectively formed in the resist 18. .. After that, the silicon substrate 10 is etched using the resist 18 as a mask to form a through hole 20 penetrating the silicon substrate 10 from the main surface 13 to the main surface 11 of the silicon substrate 10.

図１―１（Ｃ）を参照すれば、次に、さらに酸化シリコン膜１２およびＴｉＮ膜１４をエッチングして、貫通孔２０の底部にＡｌ膜１６を露出させる。 Referring to FIG. 1-1 (C), the silicon oxide film 12 and the TiN film 14 are further etched to expose the Al film 16 to the bottom of the through hole 20.

図１―２（Ｄ）を参照すれば、次に、貫通孔２０の側面２１、底部およびシリコン基板１０の主面１３上に、ＣＶＤ酸化膜２２を形成する。 Referring to FIG. 1-2 (D), next, a CVD oxide film 22 is formed on the side surface 21, the bottom of the through hole 20, and the main surface 13 of the silicon substrate 10.

図１―２（Ｅ）を参照すれば、次に、ＣＶＤ酸化膜２２をエッチバックして、貫通孔２０の底部にＡｌ膜１６を露出させる。 Referring to FIG. 1-2 (E), the CVD oxide film 22 is then etched back to expose the Al film 16 to the bottom of the through hole 20.

図１―３（Ｆ）を参照すれば、次に、スパッタ法により、貫通孔２０内のＣＶＤ酸化膜２２上および主面１３上のＣＶＤ酸化膜２２上ならびに貫通孔２０の底部に露出するＡｌ膜１６上に、シードメタル層２４を形成する。シードメタル層２４は、最初にＴｉをスパッタし、その後、Ｃｕをスパッタして形成する。 Referring to FIG. 1-3 (F), next, Al exposed on the CVD oxide film 22 in the through hole 20 and on the CVD oxide film 22 on the main surface 13 and at the bottom of the through hole 20 by the sputtering method. The seed metal layer 24 is formed on the film 16. The seed metal layer 24 is formed by first sputtering Ti and then spattering Cu.

図１―３（Ｇ）を参照すれば、次に、全面Ｃｕめっきにより、貫通孔２０内のシードメタル層２４上および主面１３上のシードメタル層２４上ならびに貫通孔２０の底部に設けられたシードメタル層２４上に、Ｃｕめっき層２６を形成する。Ｃｕめっき層２６は無電解めっきまたはシードメタル層２４を利用した電解めっきで行う。 Referring to FIG. 1-3 (G), next, the entire surface is Cu-plated to be provided on the seed metal layer 24 in the through hole 20, on the seed metal layer 24 on the main surface 13, and on the bottom of the through hole 20. A Cu plating layer 26 is formed on the seed metal layer 24. The Cu plating layer 26 is performed by electroless plating or electrolytic plating using the seed metal layer 24.

図１―４（Ｈ）を参照すれば、次に、ドライフィルム２８を形成し、ドライフィルム２８に選択的に開孔２９を形成する。開孔２９は、貫通孔２０を露出し、貫通孔２０周辺のＣｕめっき層２６を露出するように形成する。 Referring to FIG. 1-4 (H), the dry film 28 is then formed and the dry film 28 is selectively formed with openings 29. The opening 29 is formed so as to expose the through hole 20 and expose the Cu plating layer 26 around the through hole 20.

図１―４（Ｉ）を参照すれば、次に、ドライフィルム２８をマスクとして、貫通孔２０内のＣｕめっき層２６上、主面１３上であってドライフィルム２８の開孔２９内のＣｕめっき層２６上ならびに貫通孔２０の底部に設けられたＣｕめっき層２６上に、Ｃｕめっき層３０を形成する。Ｃｕめっき層３０はシードメタル層２４およびＣｕめっき層２６を利用した電解めっきで行う。 Referring to FIG. 1-4 (I), next, using the dry film 28 as a mask, Cu on the Cu plating layer 26 in the through hole 20 and on the main surface 13 and in the opening 29 of the dry film 28. The Cu plating layer 30 is formed on the plating layer 26 and on the Cu plating layer 26 provided at the bottom of the through hole 20. The Cu plating layer 30 is electroplated using the seed metal layer 24 and the Cu plating layer 26.

図１―５（Ｊ）を参照すれば、次に、ドライフィルム２８を除去し、その後、Ｃｕめっき層３０に覆われていないＣｕめっき層２６およびシードメタル層２４を除去する。その後、ソルダーレジスト３２を、シリコン基板１０の主面１３上のＣＶＤ酸化膜２２上、主面１３上のＣｕめっき層３０上および貫通孔２０内のＣｕめっき層３０の開孔３１内に形成する。 Referring to FIG. 1-5 (J), the dry film 28 is then removed, followed by the Cu plating layer 26 and the seed metal layer 24 which are not covered by the Cu plating layer 30. After that, the solder resist 32 is formed on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the openings 31 of the Cu plating layer 30 in the through holes 20. ..

スパッタにより貫通孔２０内にシードメタル層２４を均一に形成するのは困難であり、貫通孔２０の底部の角部では、図２に示すように、未スパッタ部分２４１が発生する場合がある。本実施の形態では、全面Ｃｕめっきにより、シードメタル層２４上に、Ｃｕめっき層２６を形成しているので、図３に示すように、全面Ｃｕめっきにより、未スパッタ部分２４１に蓋をすることができる。Ｃｕめっきは等方成長なので、図４に示すように、未スパッタ部分２４１は、全面Ｃｕめっきにより埋め込まれる。従って、図５に示すように、ドライフィルム２８の現像液３４（炭酸ナトリウム混合液）が未スパッタ部分２４１を介してＡｌ膜１６に侵入して、Ａｌ膜１６を侵食するのを防止できる。なお、埋め込むためのＣｕめっき層２６の膜厚は１．０〜１．５μｍが好ましい。 It is difficult to uniformly form the seed metal layer 24 in the through hole 20 by sputtering, and an unspattered portion 241 may be generated at the corner of the bottom of the through hole 20, as shown in FIG. In the present embodiment, the Cu plating layer 26 is formed on the seed metal layer 24 by the entire surface Cu plating. Therefore, as shown in FIG. 3, the unsputtered portion 241 is covered by the entire surface Cu plating. Can be done. Since Cu plating is isotropic growth, as shown in FIG. 4, the unsputtered portion 241 is embedded by Cu plating on the entire surface. Therefore, as shown in FIG. 5, it is possible to prevent the developer 34 (sodium carbonate mixed solution) of the dry film 28 from invading the Al film 16 via the unspattered portion 241 and eroding the Al film 16. The film thickness of the Cu plating layer 26 for embedding is preferably 1.0 to 1.5 μm.

これに対して、図１２に示すように、全面Ｃｕめっきにより、シードメタル層２４上にＣｕめっき層２６を形成せずに、シードメタル層２４上にドライフィルム２８を形成し、ドライフィルム２８に選択的に開孔２９を形成すると、図１３に示すように、ドライフィルム２８の現像液３４が未スパッタ部分２４１を介してＡｌ膜１６に侵入して、Ａｌ膜１６を侵食し、Ａｌ空洞部１６１を形成してしまう。そして、その後、図１４に示すように、ドライフィルム２８をマスクにしてシードメタル層２４上にＣｕめっき層３０を形成し、その後ソルダーレジスト３２を形成する。その後の工程の半田ボール形成時のリフロ熱や半導体装置１の実装時の実装リフロ熱、外部応力、熱ストレス等が加わると、図１５に示すように、Ａｌ空洞部１６１を起点としてＣＶＤ酸化膜２２にクラック２２１が生じ、その結果、リーク不良の可能性が高くなり、信頼性を低下させてしまう。 On the other hand, as shown in FIG. 12, the dry film 28 is formed on the seed metal layer 24 without forming the Cu plating layer 26 on the seed metal layer 24 by the entire surface Cu plating, and the dry film 28 is formed. When the openings 29 are selectively formed, as shown in FIG. 13, the developer 34 of the dry film 28 invades the Al film 16 via the unplated portion 241 and erodes the Al film 16 to form the Al cavity portion. It forms 161. Then, as shown in FIG. 14, a Cu plating layer 30 is formed on the seed metal layer 24 using the dry film 28 as a mask, and then a solder resist 32 is formed. When the reflow heat at the time of forming the solder ball in the subsequent process, the mounting reflow heat at the time of mounting the semiconductor device 1, the external stress, the thermal stress, etc. are applied, as shown in FIG. 15, the CVD oxide film starts from the Al cavity portion 161. A crack 221 is formed in the 22, and as a result, the possibility of a leak defect is high and the reliability is lowered.

（第２の実施の形態）
図６−４（Ｉ）を参照すれば、本発明の好ましい第２の実施の形態の半導体装置２は、半導体シリコン基板１０と、酸化シリコン膜１２と、ＴｉＮ膜１４と、Ａｌ膜１６と、貫通孔２０と、ＣＶＤ酸化膜２２と、シードメタル層２４と、Ｃｕめっき層３０と、ソルダーレジスト３２とを備えている。 (Second embodiment)
Referring to FIG. 6-4 (I), the semiconductor device 2 of the preferred second embodiment of the present invention includes a semiconductor silicon substrate 10, a silicon oxide film 12, a TiN film 14, and an Al film 16. It includes a through hole 20, a CVD oxide film 22, a seed metal layer 24, a Cu plating layer 30, and a solder resist 32.

第１の実施の形態では、全面Ｃｕめっきにより、シードメタル層２４上に、Ｃｕめっき層２６を形成して、シードメタル層２４の未スパッタ部分２４１に蓋をすることにより、その後のドライフィルム２８の現像液３４（炭酸ナトリウム混合液）が未スパッタ部分２４１を介してＡｌ膜１６に侵入して、Ａｌ膜１６を侵食するのを防止したのに対して、本実施の形態では、シードメタル層２４上に、全面ＣｕめっきによりＣｕめっき層２６を形成しない。第１の実施の形態では、酸化シリコン膜１２およびＴｉＮ膜１４をエッチングして、貫通孔２０の底部にＡｌ膜１６を露出させた（図１―１（Ｃ）参照）が、本実施の形態では、酸化シリコン膜１２のみを除去し、ＴｉＮ膜１４は除去しない。従って、貫通孔２０は、シリコン基板１０の主面１１とは反対側の主面１３から主面１１までシリコン基板１０を貫通し、さらに酸化シリコン膜１２を貫通し、底部にＴｉＮ膜１４を露出して設けられている。ＣＶＤ酸化膜２２は、貫通孔２０の側面２１およびシリコン基板１０の主面１３上に設けられている。シードメタル層２４は、貫通孔２０内のＣＶＤ酸化膜２２上および主面１３上のＣＶＤ酸化膜２２上ならびに貫通孔２０の底部に露出するＴｉＮ膜１４上に設けられている。Ｃｕめっき層３０は、貫通孔２０内のシードメタル層２４上および主面１３上のシードメタル層２４上ならびに貫通孔２０の底部に設けられたシードメタル層２４上に設けられている。ソルダーレジスト３２は、シリコン基板１０の主面１３上のＣＶＤ酸化膜２２上、主面１３上のＣｕめっき層３０上および貫通孔２０内のＣｕめっき層３０の開孔３１内に設けられている。なお、酸化シリコン膜１２は、シリコン基板１０の主面１１上に設けられ、ＴｉＮ膜１４は、酸化シリコン膜１２上に設けられ、Ａｌ膜１６は、ＴｉＮ膜１４上に設けられている。ＭＯＳトランジスタ等の半導体素子等の回路素子（図示せず）は、シリコン基板１０の主面１１に形成され、酸化シリコン膜１２によって覆われている。 In the first embodiment, the Cu plating layer 26 is formed on the seed metal layer 24 by the entire surface Cu plating, and the unspattered portion 241 of the seed metal layer 24 is covered with the subsequent dry film 28. In this embodiment, the seed metal layer is prevented from invading the Al film 16 through the unplated portion 241 of the developing solution 34 (sodium carbonate mixed solution) and eroding the Al film 16. The Cu plating layer 26 is not formed on the 24 by Cu plating on the entire surface. In the first embodiment, the silicon oxide film 12 and the TiN film 14 are etched to expose the Al film 16 at the bottom of the through hole 20 (see FIG. 1-1 (C)). Then, only the silicon oxide film 12 is removed, and the TiN film 14 is not removed. Therefore, the through hole 20 penetrates the silicon substrate 10 from the main surface 13 on the opposite side of the main surface 11 of the silicon substrate 10 to the main surface 11, further penetrates the silicon oxide film 12, and exposes the TiN film 14 at the bottom. It is provided. The CVD oxide film 22 is provided on the side surface 21 of the through hole 20 and the main surface 13 of the silicon substrate 10. The seed metal layer 24 is provided on the CVD oxide film 22 in the through hole 20, on the CVD oxide film 22 on the main surface 13, and on the TiN film 14 exposed at the bottom of the through hole 20. The Cu plating layer 30 is provided on the seed metal layer 24 in the through hole 20, the seed metal layer 24 on the main surface 13, and the seed metal layer 24 provided at the bottom of the through hole 20. The solder resist 32 is provided on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the openings 31 of the Cu plating layer 30 in the through holes 20. .. The silicon oxide film 12 is provided on the main surface 11 of the silicon substrate 10, the TiN film 14 is provided on the silicon oxide film 12, and the Al film 16 is provided on the TiN film 14. A circuit element (not shown) such as a semiconductor element such as a MOS transistor is formed on a main surface 11 of a silicon substrate 10 and is covered with a silicon oxide film 12.

次に、図６−１〜６−４、図７〜１１を参照して本発明の好ましい第２の実施の形態の半導体装置２の製造方法を説明する。 Next, a method for manufacturing the semiconductor device 2 according to a second preferred embodiment of the present invention will be described with reference to FIGS. 6-1 to 6-4 and FIGS. 7 to 11.

ＭＯＳトランジスタ等の半導体素子等の回路素子（図示せず）を、シリコン基板１０の主面１１に形成する。 A circuit element (not shown) such as a semiconductor element such as a MOS transistor is formed on the main surface 11 of the silicon substrate 10.

図６―１（Ａ）を参照すれば、次に、シリコン基板１０の主面１１上に酸化シリコン膜１２を形成し、酸化シリコン膜１２上にＴｉＮ膜１４を形成し、ＴｉＮ膜１４上にＡｌ膜１６を形成する。なお、ＴｉＮ膜１４はＡｌのマイグレーションを防止するために設けている。 Referring to FIG. 6-1 (A), next, a silicon oxide film 12 is formed on the main surface 11 of the silicon substrate 10, a TiN film 14 is formed on the silicon oxide film 12, and the TiN film 14 is formed on the TiN film 14. The Al film 16 is formed. The TiN film 14 is provided to prevent Al migration.

図６―１（Ｂ）を参照すれば、次に、シリコン基板１０の主面１１とは反対側の主面１３上にレジスト１８を形成し、レジスト１８に選択的に開孔１９を形成する。その後、レジスト１８をマスクとしてシリコン基板１０をエッチングして、シリコン基板１０の主面１３から主面１１までシリコン基板１０を貫通する貫通孔２０を形成する。 Referring to FIG. 6-1 (B), next, a resist 18 is formed on the main surface 13 opposite to the main surface 11 of the silicon substrate 10, and a hole 19 is selectively formed in the resist 18. .. After that, the silicon substrate 10 is etched using the resist 18 as a mask to form a through hole 20 penetrating the silicon substrate 10 from the main surface 13 to the main surface 11 of the silicon substrate 10.

図６―１（Ｃ）、図７を参照すれば、次に、さらに酸化シリコン膜１２をエッチングして、貫通孔２０の底部にＴｉＮ膜１４を露出させる。 Referring to FIGS. 6-1 (C) and 7, the silicon oxide film 12 is further etched to expose the TiN film 14 to the bottom of the through hole 20.

図６―２（Ｄ）、図８を参照すれば、次に、貫通孔２０の側面２１、底部およびシリコン基板１０の主面１３上に、ＣＶＤ酸化膜２２を形成する。 Referring to FIGS. 6-2 (D) and 8, next, a CVD oxide film 22 is formed on the side surface 21, the bottom of the through hole 20, and the main surface 13 of the silicon substrate 10.

図６―２（Ｅ）、図９を参照すれば、次に、ＣＶＤ酸化膜２２をエッチバックして、貫通孔２０の底部にＴｉＮ膜１４を露出させる。 Referring to FIGS. 6-2 (E) and 9, the CVD oxide film 22 is then etched back to expose the TiN film 14 to the bottom of the through hole 20.

図６―３（Ｆ）、図１０を参照すれば、次に、スパッタ法により、貫通孔２０内のＣＶＤ酸化膜２２上および主面１３上のＣＶＤ酸化膜２２上ならびに貫通孔２０の底部に露出するＴｉＮ膜１４上に、シードメタル層２４を形成する。シードメタル層２４は、最初にＴｉをスパッタし、その後、Ｃｕをスパッタして形成する。 Referring to FIGS. 6-3 (F) and 10, next, by a sputtering method, the CVD oxide film 22 in the through hole 20 and the CVD oxide film 22 on the main surface 13 and the bottom of the through hole 20 are formed. A seed metal layer 24 is formed on the exposed TiN film 14. The seed metal layer 24 is formed by first sputtering Ti and then spattering Cu.

図６―３（Ｇ）を参照すれば、次に、ドライフィルム２８を形成し、ドライフィルム２８に選択的に開孔２９を形成する。開孔２９は、貫通孔２０を露出し、貫通孔２０周辺のシードメタル層２４を露出するように形成する。 Referring to FIG. 6-3 (G), the dry film 28 is then formed and the dry film 28 is selectively formed with openings 29. The opening 29 is formed so as to expose the through hole 20 and expose the seed metal layer 24 around the through hole 20.

図６―４（Ｈ）を参照すれば、次に、ドライフィルム２８をマスクとして、貫通孔２０内のシードメタル層２４上、主面１３上であってドライフィルム２８の開孔２９内のシードメタル層２４上ならびに貫通孔２０の底部に設けられたシードメタル層２４上に、Ｃｕめっき層３０を形成する。Ｃｕめっき層３０はシードメタル層２４を利用した電解めっきで行う。 Referring to FIG. 6-4 (H), next, using the dry film 28 as a mask, the seed on the seed metal layer 24 in the through hole 20 and on the main surface 13 and in the opening 29 of the dry film 28. The Cu plating layer 30 is formed on the metal layer 24 and on the seed metal layer 24 provided at the bottom of the through hole 20. The Cu plating layer 30 is electroplated using the seed metal layer 24.

図６―５（Ｉ）を参照すれば、次に、ドライフィルム２８を除去し、その後、Ｃｕめっき層３０に覆われていないシードメタル層２４を除去する。その後、ソルダーレジスト３２を、シリコン基板１０の主面１３上のＣＶＤ酸化膜２２上、主面１３上のＣｕめっき層３０上および貫通孔２０内のＣｕめっき層３０の開孔３１内に形成する。 Referring to FIG. 6-5 (I), the dry film 28 is then removed, followed by the seed metal layer 24 which is not covered by the Cu plating layer 30. After that, the solder resist 32 is formed on the CVD oxide film 22 on the main surface 13 of the silicon substrate 10, on the Cu plating layer 30 on the main surface 13, and in the openings 31 of the Cu plating layer 30 in the through holes 20. ..

スパッタにより貫通孔２０内にシードメタル層２４を均一に形成するのは困難であり、貫通孔２０の底部の角部では、図１１に示すように、未スパッタ部分２４２が発生する場合がある。本実施の形態では、ＴｉＮ膜１４を除去せずに残しているので、未スパッタ部分２４２が発生したとしても、ＴｉＮ膜１４がバリアとなり、ドライフィルム２８の現像液３４（炭酸ナトリウム混合液）が未スパッタ部分２４２を介してＡｌ膜１６に侵入して、Ａｌ膜１６を侵食するのを防止できる。 It is difficult to uniformly form the seed metal layer 24 in the through hole 20 by sputtering, and an unspattered portion 242 may be generated at the corner of the bottom of the through hole 20, as shown in FIG. In the present embodiment, since the TiN film 14 is left without being removed, even if the unspattered portion 242 is generated, the TiN film 14 serves as a barrier and the developer 34 (sodium carbonate mixed solution) of the dry film 28 becomes. It is possible to prevent the Al film 16 from being eroded by invading the Al film 16 through the unspattered portion 242.

なお、本実施の形態のように、ＴｉＮ膜１４を除去せずに残す場合であっても、酸化シリコン膜１２をエッチングするが、貫通孔２０の底部にＴｉＮ膜１４を残す際の面内のエッチング特性のばらつきにより、ＴｉＮ膜１４が一部除去されてしまい、ドライフィルム２８の現像液３４により、未スパッタ部分２４２とＴｉＮ膜１４が一部除去されてしまった部分からＡｌ膜１６が侵食される可能性もあるので、第１の実施の形態のように、全面Ｃｕめっきにより、シードメタル層２４上に、Ｃｕめっき層２６を形成することがより好ましい。 Even when the TiN film 14 is left without being removed as in the present embodiment, the silicon oxide film 12 is etched, but the TiN film 14 is left in the bottom of the through hole 20 in the plane. Due to the variation in etching characteristics, the TiN film 14 was partially removed, and the developer 34 of the dry film 28 eroded the Al film 16 from the unspattered portion 242 and the portion where the TiN film 14 was partially removed. Therefore, it is more preferable to form the Cu plating layer 26 on the seed metal layer 24 by the entire surface Cu plating as in the first embodiment.

以上、本発明の種々の典型的な実施の形態を説明してきたが、本発明はそれらの実施の形態に限定されない。従って、本発明の範囲は、次の特許請求の範囲によってのみ限定されるものである。 Although various typical embodiments of the present invention have been described above, the present invention is not limited to those embodiments. Therefore, the scope of the present invention is limited only by the following claims.

１０ 半導体シリコン基板
１２ 酸化シリコン膜
１４ ＴｉＮ膜
１６ Ａｌ膜
２０ 貫通孔
２２ ＣＶＤ酸化膜
２４ シードメタル層
２６ Ｃｕめっき層
２８ ドライフィルム
３０ Ｃｕめっき層
３２ ソルダーレジスト 10 Semiconductor silicon substrate 12 Silicon oxide film 14 TiN film 16 Al film 20 Through hole 22 CVD oxide film 24 Seed metal layer 26 Cu plating layer 28 Dry film 30 Cu plating layer 32 Solder resist

Claims (4)

一主面と前記一主面とは反対側の他の主面とを有する半導体基板と、
前記他の主面側に設けられた第１の導電層と、
前記一主面から前記他の主面まで前記半導体基板を厚さ方向に貫通して前記第１の導電層を露出する貫通孔内であって前記半導体基板上に設けられた第２の導電層と、
前記貫通孔内であって前記第１の導電層上に設けられた第３の導電層と、
前記貫通孔の端部であって前記第２の導電層と前記第３の導電層の間に形成された第４の導電層と、
を備える半導体装置。 A semiconductor substrate having one main surface and another main surface opposite to the one main surface,
The first conductive layer provided on the other main surface side and
A second conductive layer provided on the semiconductor substrate in a through hole that penetrates the semiconductor substrate from the one main surface to the other main surface and exposes the first conductive layer. When,
A third conductive layer in the through hole provided on the first conductive layer,
A fourth conductive layer formed between the second conductive layer and the third conductive layer at the end of the through hole.
A semiconductor device equipped with. 前記第２の導電層は前記貫通孔の側部に形成され、
前記第３の導電層は前記第２の導電層と同じ材料を含み前記貫通孔の底部に形成される
請求項１記載の半導体装置。 The second conductive layer is formed on the side of the through hole, and the second conductive layer is formed on the side portion of the through hole.
The semiconductor device according to claim 1, wherein the third conductive layer contains the same material as the second conductive layer and is formed at the bottom of the through hole. 一主面と前記一主面とは反対側の他の主面とを有する半導体基板と、
前記他の主面側に設けられた第１の導電層と、
前記第１の導電層上に設けられた第２の導電層と、
前記一主面から前記他の主面まで前記半導体基板を厚さ方向に貫通して前記第１の導電層を露出する貫通孔内であって前記半導体基板上に設けられた第３の導電層と、
前記貫通孔内であって前記第１の導電層上に設けられた第４の導電層と、
前記第３の導電層と前記第４の導電層の間に前記第３の導電層及び前記第４の導電層の一方と一体に形成され、前記第３の導電層及び前記第４の導電層のいずれよりも厚さが小さい第５の導電層と、
を備える半導体装置。 A semiconductor substrate having one main surface and another main surface opposite to the one main surface,
The first conductive layer provided on the other main surface side and
The second conductive layer provided on the first conductive layer and
A third conductive layer provided on the semiconductor substrate in a through hole that penetrates the semiconductor substrate from the one main surface to the other main surface in the thickness direction and exposes the first conductive layer. When,
A fourth conductive layer in the through hole provided on the first conductive layer,
Between the third conductive layer and the fourth conductive layer, the third conductive layer and one of the fourth conductive layers are integrally formed, and the third conductive layer and the fourth conductive layer are formed integrally. A fifth conductive layer, which is thinner than any of the above,
A semiconductor device equipped with. 前記第５の導電層は前記貫通孔の端部に形成され、
前記貫通孔内であって前記第３の導電層、前記第４の導電層及び前記第５の導電層上に設けられた第６の導電層をさらに備えた
請求項３記載の半導体装置。 The fifth conductive layer is formed at the end of the through hole and is formed.
The semiconductor device according to claim 3, further comprising a third conductive layer, a fourth conductive layer, and a sixth conductive layer provided on the fifth conductive layer in the through hole.
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Citations (5)

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JPH06349952A (en) * 1993-06-14 1994-12-22 Oki Electric Ind Co Ltd Wiring forming method
JP2000183160A (en) * 1998-12-11 2000-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP2001085434A (en) * 1999-09-14 2001-03-30 Hitachi Ltd Method for plating semiconductor substrate
WO2011111308A1 (en) * 2010-03-09 2011-09-15 パナソニック株式会社 Process for production of semiconductor device, and semiconductor device
JP2020198440A (en) * 2018-11-29 2020-12-10 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349952A (en) * 1993-06-14 1994-12-22 Oki Electric Ind Co Ltd Wiring forming method
JP2000183160A (en) * 1998-12-11 2000-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JP2001085434A (en) * 1999-09-14 2001-03-30 Hitachi Ltd Method for plating semiconductor substrate
WO2011111308A1 (en) * 2010-03-09 2011-09-15 パナソニック株式会社 Process for production of semiconductor device, and semiconductor device
JP2020198440A (en) * 2018-11-29 2020-12-10 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device

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