JP2021169659A - Electrolytic treatment method and electrolytic treatment apparatus - Google Patents

Abstract

To provide an efficient predetermined electrolytic treatment with respect to a semiconductor substrate by using treated ions in a treatment liquid.SOLUTION: An electrolytic treatment method comprises: a first step (S1) of forming, on a semiconductor substrate, an insulating structure in which an insulating layer and a conductive layer are sequentially laminated from the semiconductor substrate side in a single layer or multiple layers, and capacitively coupling the semiconductor substrate and the conductive layer; a second step (S2) of supplying a treatment solution to the insulating structure and arranging an electrode so as to be electrically connected to the treatment solution; a third step (S3) of connecting the semiconductor substrate and the electrode via a power source, using the semiconductor substrate as a cathode, and applying a voltage with the electrode used as an anode to reduce treated ions in the treatment solution on the insulating structure to form a film; and a fourth step (S4) of connecting the semiconductor substrate and the electrode without the power source, and discharging electric charges electrified to a capacitance of the insulating structure.SELECTED DRAWING: Figure 2

Description

The present invention relates to an electrolytic treatment method for performing a predetermined treatment on a semiconductor substrate using ions to be treated contained in a treatment liquid, and an electrolytic treatment apparatus for performing the electrolytic treatment method.

The electrolytic process (electrolytic treatment) is a technique used for various treatments such as plating treatment and etching treatment.

The plating process described above is conventionally performed by, for example, the plating apparatus described in Patent Document 1. Specifically, a current is passed between the anode immersed in the plating solution in the plating tank and the object to be processed (semiconductor substrate), and the metal ions in the plating solution are moved to the object to be processed by this current, and the metal is further subjected to. The plating treatment is performed by precipitating ions as a plating metal on the side to be treated.

However, when the plating process described in Patent Document 1 is performed, the efficiency of the plating process is poor because a current flows between the anode and the object to be processed even when sufficient metal ions are not accumulated on the surface to be processed. .. Further, since the plating treatment is performed in a state where sufficient metal ions are not accumulated in this way, the plating metal is unevenly deposited on the object to be treated, and the plating treatment is not uniformly performed.

Therefore, for example, the plating treatment described in Patent Document 2 has been proposed. In this plating process, a direct electrode and a counter electrode (object to be processed) are arranged so as to be electrically connected to the plating solution, and an indirect electrode that forms an electric field is arranged in the plating solution, and then the indirect electrode is used. A voltage is applied to move the ions to be treated in the plating solution to the counter electrode side, and further, the direct electrode and the indirect electrode are connected to reduce the ions to be treated that have moved to the counter electrode side.

Japanese Unexamined Patent Publication No. 2012-1320558 JP-A-2018-3133

"Development of Cu plating equipment for damascene wiring on high resistance substrates" by Yasushi Kanda et al. 222 (2009-1)

However, as a result of diligent studies by the present inventor, it was found that there is room for improvement in the plating rate in the plating treatment described in Patent Document 2. That is, since it is necessary to repeatedly move and reduce the ions to be treated, it takes time to form a film with a desired film thickness. In particular, for example, when wiring is formed in a hole or trench (fine wiring groove) having a high aspect ratio on a semiconductor substrate, a metal for wiring formation such as copper is embedded by performing a plating process. Since the film formation proceeds evenly on the semiconductor substrate in proportion, the film formation on the fine wiring groove is disadvantageous and takes time.

Further, Non-Patent Document 1 describes a method of forming wiring (film formation method) in a fine wiring groove. This method is a so-called damascene process, in which a barrier film and a seed film are formed in a fine wiring groove, and then Cu is formed by electrolytic plating using the seed as a feeding part.

However, in recent years, the feeding path (feeding portion) of the semiconductor substrate has been thinned by the barrier film and the seed film, and in the method described in Non-Patent Document 1, the resistance between the feeding point (periphery) and the center is increased. It becomes expensive and the uniformity of the plating process becomes an issue.

Further, since the film formation proceeds evenly on the semiconductor substrate in proportion to the electric flux density of the plating solution, the film formation in the fine wiring groove is disadvantageous. Then, it is difficult to embed Cu in the uneven fine wiring groove without an additive.

Further, when the seed film is made into a thin film, the seed film is dissolved at the time of plating. On the other hand, when the seed film is made thick, it overhangs the upper part of the fine wiring groove and voids are generated. Then, it is difficult to embed Cu in the fine wiring groove.

Therefore, there is room for improvement in speeding up the plating process, that is, improving efficiency.

The present invention has been made in view of this point, and an object of the present invention is to efficiently perform a predetermined electrolytic treatment on a semiconductor substrate by using ions to be treated in a treatment liquid.

In order to achieve the above object, the present invention is an electrolytic treatment method in which a semiconductor substrate is subjected to a predetermined treatment using ions to be treated contained in a treatment liquid, and is insulated from the semiconductor substrate side on the semiconductor substrate. The first step of forming an insulating structure in which layers and conductive layers are laminated in order into a single layer or a plurality of layers and capacitively coupling the semiconductor substrate and the conductive layer, and supplying the treatment liquid on the insulating structure. In addition, the second step of arranging the electrodes so as to be electrically connected to the treatment liquid, the semiconductor substrate and the electrodes are connected via a power source, and a voltage is applied to the treatment liquid. The third step of reducing the ions to be treated in the treatment liquid to the surface of the insulating structure or oxidizing the surface of the insulating structure, and connecting the semiconductor substrate and the electrode without using the power source. It is characterized by having a fourth step of discharging the electric charge charged in the capacitance of the insulating structure.

According to the present invention, since the semiconductor substrate and the conductive layer of the insulating structure are capacitively bonded, in the third step, for example, when the treatment liquid is a plating solution, the amount of electric charge charged in the capacitance of the insulating structure. It is possible to form a film by reducing the ions to be treated according to the above. Therefore, as compared with the conventional treatments described in Patent Document 2 and Non-Patent Document 1, for example, the amount of reduction of the wiring groove of the ion to be treated can be increased, and the film formation rate can be improved. Then, by repeatedly reducing the ions to be treated in the third step (charging step) and discharging the electric charge in the fourth step (discharging step), a film having a desired film thickness can be efficiently formed on the insulating structure. Can be well formed.

Further, when the insulating structure is oxidized in the third step, the amount of oxidation of the wiring groove of the insulating structure can be increased as in the case of reducing the ions to be treated described above. Therefore, for example, when the treatment liquid is used as a cleaning liquid and the surface of the wiring groove of the insulating structure is oxidized to clean the surface, the cleaning can be efficiently performed.

In the electrolytic treatment method, the voltage applied to the treatment liquid in the third step is larger than the ionization voltage for generating the ions to be treated, and the voltage applied to the treatment liquid in the fourth step. Is preferably smaller than the ionization voltage.

In the electrolytic treatment method, in the first step, the conductive layer is partially formed on the insulating layer, and in the third step, the surface of the partially formed conductive layer is covered with the cover. The treated ions may be reduced or the surface of the insulating structure may be oxidized.

In the electrolytic treatment method, in the third step, a voltage is applied to the treatment liquid using the semiconductor substrate as a cathode and the electrode as an anode to make the ions to be treated in the treatment liquid the insulating structure. It may be reduced to the surface of the film to form a film.

In the electrolysis treatment method, fine grooves are formed on the surface of the semiconductor substrate, and the conductive layer may be formed on the bottom surface of the fine grooves in the first step.

From another point of view, the present invention is an electrolytic treatment apparatus that performs a predetermined treatment on a semiconductor substrate using ions to be treated contained in a treatment liquid, and on the semiconductor substrate, an insulating layer and conductivity are provided from the semiconductor substrate side. An insulating structure in which layers are laminated in order is formed as a single layer or a plurality of layers, the semiconductor substrate and the conductive layer are capacitively coupled, and the treatment liquid is supplied onto the insulating structure, and the electrolysis is performed. The processing apparatus connects an electrode arranged so as to be electrically connected to the processing liquid, a power source connected to the semiconductor substrate and the electrode, and the semiconductor substrate and the electrode via the power source. It has a switch and a control unit for switching between connecting the semiconductor substrate and the electrodes without using the power supply, and the control unit connects the semiconductor substrate and the electrodes to the power supply. To reduce the ions to be treated in the treatment liquid to the surface of the insulating structure or to oxidize the surface of the insulating structure by connecting the conductors to the surface of the insulating structure and applying a voltage to the treatment liquid, and the semiconductor substrate. It is characterized in that the switch is controlled so as to execute a step of connecting the electrodes to the electrodes without going through the power source and discharging the charge charged in the capacitance of the insulating structure.

In the electrolytic processing apparatus, the resistance value of the charging resistance provided in the connection between the semiconductor substrate and the electrode via the power supply is the discharge resistance provided in the connection between the semiconductor substrate and the electrode via the power supply. It is preferably smaller than the resistance value.

In the electrolytic treatment apparatus, the conductive layer may be partially formed on the insulating layer.

In the electrolytic treatment apparatus, fine grooves may be formed on the surface of the semiconductor substrate, and the conductive layer may be formed on the bottom surface of the fine grooves.

In the electrolytic treatment apparatus, the insulating structure is formed into a plurality of layers, and the multilayered insulating structure includes a first conductive layer, a first insulating layer, a second conductive layer, and a second conductive layer from the treatment liquid side. The second insulating layer may be laminated in order, and the first conductive layer and the second conductive layer may be connected by a capacitance bond or a via.

According to the present invention, a predetermined electrolytic treatment on a semiconductor substrate can be efficiently performed by using the ions to be treated in the treatment liquid. That is, for example, when the treatment liquid is a plating liquid, the reduction amount of the wiring groove of the ion to be treated can be increased and the film formation rate can be improved, and as a result, a film having a desired film thickness can be efficiently formed. Can be done. Further, for example, when the treatment liquid is used as a cleaning liquid, the amount of oxidation on the surface of the insulating structure can be increased, and the surface can be efficiently cleaned.

It is explanatory drawing which shows the outline of the structure of the plating processing apparatus which concerns on this embodiment. It is a flowchart which shows the main process of the plating process of this embodiment. It is explanatory drawing which shows the charging process of step S3 of this embodiment. It is explanatory drawing which shows the charging process of step S3 of this embodiment. It is explanatory drawing which shows the discharge process of step S4 of this embodiment. It is explanatory drawing which shows the state of forming the wiring in a micropore and a microgroove in this embodiment. It is explanatory drawing which shows the outline of the structure of the plating processing apparatus which concerns on other embodiment. It is explanatory drawing which shows the charging process of step S3 of another embodiment. It is explanatory drawing which shows the charging process of step S3 of another embodiment. It is explanatory drawing which shows the discharge process of step S4 of another embodiment. It is explanatory drawing which shows the appearance that the copper plating was formed in another embodiment. It is explanatory drawing which shows the outline of the structure of the plating processing apparatus which concerns on other embodiment. It is explanatory drawing which shows the outline of the structure of the cleaning processing apparatus which concerns on other embodiment. It is explanatory drawing which shows the charging process in the cleaning process of another embodiment. It is explanatory drawing which shows the electric discharge process in the cleaning process of another embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, so that duplicate description will be omitted. Further, in the drawings used in the following description, the dimensions of each component do not necessarily correspond to the actual dimensions in order to give priority to the ease of understanding the technology. In this embodiment, a case where a plating treatment, for example, a copper plating treatment is performed as the electrolytic treatment according to the present invention will be described.

<Plating equipment>
First, a plating processing apparatus as an electrolytic processing apparatus according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an outline of the configuration of the plating processing apparatus 1 according to the present embodiment.

An insulating structure F is formed on the semiconductor substrate W processed by the plating processing apparatus 1. The insulating structure F has a structure in which the insulating layer Fa and the conductive layer Fb are laminated in order from the semiconductor substrate W side. The insulating layer Fa is composed of an insulating material such as SiO ₂ (silicon oxide) and SiCOH (silicon oxide containing carbon and hydrogen). The conductive layer Fb is composed of a barrier layer for suppressing the diffusion of copper and a seed layer for passing an electric current during the plating process, which are laminated in order from the semiconductor substrate W side. The barrier layer is composed of, for example, Ta (tantalum), TaN (tantalum nitride), Ti (titanium), and TiN (titanium nitride). The seed layer is composed of, for example, Cu (copper). The conductive layer Fb is formed on the entire surface of the insulating layer Fa. The semiconductor substrate W and the conductive layer Fb are capacitively coupled.

An electrode 10 is provided above the semiconductor substrate W so as to face the insulating structure F. Further, a plating solution M as a treatment liquid is filled between the insulating structure F and the electrode 10, and the insulating structure F and the electrode 10 are electrically connected to the plating liquid M. As the plating solution M, for example, a solution in which copper sulfate is dissolved is used. That is, the plating solution M contains copper ions as ions to be treated.

The means for supplying the plating solution M is not particularly limited, and for example, a nozzle (not shown) is used. After arranging the semiconductor substrate W, the electrode 10 may be arranged, and the plating solution M may be further supplied from the nozzle to fill the mixture. Alternatively, after arranging the semiconductor substrate W, the plating solution M may be supplied from the nozzle onto the insulating structure F, and the electrodes 10 may be further arranged.

The first wiring 20 is connected to the electrode 10, and the second wiring 21 is connected to the semiconductor substrate W. A switch 22 is provided in the first wiring 20, and a charging wiring 23 and a discharging wiring 24 are connected to the second wiring 21. The switch 22 switches between the connection between the first wiring 20 and the charging wiring 23 and the connection between the first wiring 20 and the discharge wiring 24. That is, the first wiring 20 and the second wiring 21 are connected via the charging wiring 23 or the discharging wiring 24 by switching the switch 22. The switching of the switch 22 is controlled by the control unit 40 described later.

The charging wiring 23 is provided with a DC power supply 30 and a charging resistor 31. For example, the DC power supply 30 is provided on the second wiring 21 side, and the charging resistor 31 is provided on the first wiring 20 side. The electrode 10 is connected to the positive electrode side of the DC power supply 30. The semiconductor substrate W is connected to the negative electrode side of the DC power supply 30.

The discharge wiring 24 is provided with a discharge resistor 32. The resistance value of the discharge resistor 32 is larger than the resistance value of the charge resistor 31.

The plating processing apparatus 1 described above is provided with a control unit 40. The control unit 40 is, for example, a computer equipped with a CPU, a memory, or the like, and has a program storage unit (not shown). The program storage unit stores a program that controls the processing of the semiconductor substrate W in the plating processing apparatus 1. The program may be recorded on a computer-readable storage medium and may be installed on the control unit 40 from the storage medium.

<Plating method>
Next, the plating process using the plating process device 1 configured as described above will be described. FIG. 2 is a flowchart showing the main steps (steps) of the plating process of the present embodiment.

(Step S1)
First, as shown in FIG. 1, the insulating structure F is formed on the semiconductor substrate W. The insulating structure F has a structure in which the insulating layer Fa and the conductive layer Fb are laminated in order from the semiconductor substrate W side. The method for forming the insulating layer Fa and the conductive layer Fb is not particularly limited, and for example, sputtering is used. Then, the semiconductor substrate W and the conductive layer Fb are capacitively coupled.

(Step S2)
Next, in the plating processing apparatus 1, the electrode 10 is arranged above the semiconductor substrate W as shown in FIG. 1, and the plating solution M is filled between the insulating structure F and the electrode 10. As described above, the arrangement of the electrodes 10 and the filling (supply) of the plating solution M are performed by any method. For example, after arranging the electrode 10, the plating solution M may be supplied from the nozzle to fill the electrode 10. Alternatively, for example, the electrode 10 may be arranged after the plating solution M is supplied onto the insulating structure F from the nozzle. Then, the electrode 10 and the insulating structure F are electrically connected to the plating solution M, respectively.

(Step S3)
Next, as shown in FIGS. 3A and 3B, the first wiring 20, the charging wiring 23, and the second wiring 21 are connected by the switch 22 to connect with the semiconductor substrate W (insulating structure F). The electrode 10 is connected via the DC power supply 30. Then, a DC voltage is applied with the electrode 10 as the anode and the insulating structure F as the cathode to form an electric field (electrostatic field). Then, a positive charge is accumulated on the electrode 10, and anions A, which are negatively charged particles in the plating solution M, are collected on the electrode 10. On the other hand, a negative charge is accumulated in the insulating structure F, and copper ions C, which are positively charged particles in the plating solution M, move to the insulating structure F. In FIG. 3, the dotted arrow indicates the flow of electric current.

At this time, the charging voltage applied to the plating solution M is larger than the ionization voltage for generating copper ions C. Then, as shown in FIGS. 4A and 4B, anions A are accumulated on the electrode 10, and an oxidation reaction occurs at the electrode 10. On the other hand, the copper ion C accumulated in the insulating structure F obtains an electric charge, and the copper ion C is reduced. Then, the copper plating 50 is deposited on the surface of the insulating structure F.

In the following description, the state in which electric charge is accumulated in the electrode 10 and the copper plating 50 is formed in step S3 may be referred to as “charging”.

(Step S4)
Next, as shown in FIGS. 5A and 5B, the first wiring 20, the discharge wiring 24, and the second wiring 21 are connected by the switch 22, and are connected to the semiconductor substrate W (insulation structure F). The electrode 10 is connected to the electrode 10 without going through the DC power supply 30. Then, the electric charge charged in the capacitance of the insulating structure F is discharged. In FIG. 5, the dotted arrow indicates the flow of electric current.

Here, as described above, the resistance value of the discharge resistor 32 is larger than the resistance value of the charge resistor 31. Then, since the voltage is largely digested by the discharge resistance 32 at the time of discharge, the discharge voltage applied to the plating solution M becomes smaller than the ionization voltage for generating the copper ion C. Therefore, in step S4, hydrogen, which has a lower ionization tendency than copper, is oxidized, so that the reduced copper atom is not oxidized.

In the following description, the state in which the electric charge charged in the capacitance of the insulating structure F is discharged in step S4 may be referred to as “discharge”.

(Step S5)
Next, the charging step in step S3 and the discharging step in step S4 are repeated in this order. By repeating charging and discharging in this way, the copper plating 50 is formed with a desired film thickness.

According to the above embodiment, since the semiconductor substrate W and the conductive layer Fb are capacitively coupled, in step S3, the copper plating 50 can be reduced according to the amount of electric charge charged in the capacitance of the insulating structure F. can. Therefore, for example, the amount of reduction in the wiring groove of the copper plating 50 can be increased and the growth rate of plating can be improved as compared with the conventional treatment described in Patent Document 2. Then, in step S5, the charging of step S3 (reduction of copper ions C) and the discharge of step S4 (discharge of electric charge) are repeated to form the copper plating 50 having a desired film thickness on the insulating structure F. It can be formed efficiently.

<Application example of this embodiment>
Next, an application example of the plating processing apparatus 1 and the plating processing method of the above-described embodiment will be described. The above embodiment can also be applied to the case where the wiring is embedded in the micropores (holes) or microgrooves (trench) formed on the surface of the semiconductor substrate W. FIG. 6 is an explanatory view showing how wiring is formed in the micropores 100 and the microgrooves 200.

In the application example of this embodiment, first, the fine holes 100 are plated to form wiring, and then the fine grooves 200 are plated to form wiring. Therefore, after forming the insulating structure F in the micropores 100 and the microgrooves 200 in step S1, steps S2 to S5 are performed to form wiring in the micropores 100, and then steps S2 to S5 are performed in the microgrooves 200. Form the wiring.

(Common process)
First, in step S1, as shown in FIG. 6A, the insulating structure F is formed inside the micropores 100, and the insulating structure F is formed on the bottom surface of the microgrooves 200. The method of forming the insulating structure F is not particularly limited as in step S1 of the above embodiment.

(Wiring forming step to microhole 100)
When forming the wiring in the micropores 100, in step S2, the plating solution M is filled inside the micropores 100, and the electrode 10 is arranged above the insulating structure F of the micropores 100. Note that this step S2 is the same as step S2 of the above embodiment.

Next, the charging step of step S3 is performed to deposit the copper plating 50 on the surface of the insulating structure F. Note that this step S3 is the same as step S3 of the above embodiment.

Next, the discharge step of step S4 is performed to discharge the electric charge charged in the capacitance of the insulating structure F. Note that this step S4 is the same as step S4 of the above embodiment.

Then, in step S5, the charging step in step S3 and the discharging step in step S4 are repeated in this order, and as shown in FIG. 6B, the copper plating 50 is formed in the micropores 100 from the bottom to the top. (Bottom-up), and the embedded wiring 110 is formed.

(Wiring forming process to the fine groove 200)
When forming the wiring in the fine groove 200, in step S2, the plating solution M is filled inside the fine groove 200, and the electrode 10 is arranged above the insulating structure F of the fine groove 200. Note that this step S2 is the same as step S2 of the above embodiment.

Next, the charging step of step S3 is performed to deposit the copper plating 50 on the surface of the insulating structure F. Note that this step S3 is the same as step S3 of the above embodiment.

Next, the discharge step of step S4 is performed to discharge the electric charge charged in the capacitance of the insulating structure F. Note that this step S4 is the same as step S4 of the above embodiment.

Then, in step S5, the charging step in step S3 and the discharging step in step S4 are repeated in this order, and as shown in FIG. 6C, the copper plating 50 is formed in the fine groove 200 from the bottom to the top. (Bottom-up), the embedded wiring 210 is formed.

In this embodiment as well, the same effects as those in the above embodiment can be enjoyed. That is, the embedded wirings 110 and 210 can be efficiently formed in the fine holes 100 and the fine grooves 200, respectively. Moreover, it is possible to reduce the load on the conductive layer Fb, that is, the load on the barrier layer and the seed layer.

Further, when the barrier layer and the seed layer are used as the feeding path of the semiconductor substrate as in the conventional method described in Non-Patent Document 1, the barrier layer and the seed layer are being thinned, so that the feeding point The resistance between the (periphery) and the center becomes high, and making the plating process uniform becomes an issue. In this respect, in the present embodiment, the semiconductor substrate W is the feeding path, and the semiconductor substrate W is uniformly fed, so that the uniformity of the plating process is improved.

Further, when the conventional methods described in Patent Document 2 and Non-Patent Document 1 are used, the film formation proceeds evenly on the semiconductor substrate in proportion to the electric flux density of the plating solution, so that the film formation in the fine wiring groove is performed. Is disadvantageous. In this respect, in the present embodiment, the degree of capacitance coupling in the fine holes 100 and the fine grooves 200 in which the insulating structure F is thin is higher than the surface of the insulating structure F. This is because the capacitance (capacitive coupling) is calculated by the following formula (1) and is determined by the thickness d of the insulating layer Fa between the conductive layer Fb and the semiconductor substrate W. As a result, the bottom of the micropores 100 and the microgrooves 200 is preferentially fed, and the copper plating 50 is efficiently formed (bottomed up) from the bottom to the top.
C = ε ・ S / d ・ ・ ・ (1)
However, C: capacitance, ε: dielectric constant, S: area, d: thickness

Further, when the conventional methods described in Patent Document 2 and Non-Patent Document 1 are used, when the seed layer is made into a thin film, the seed layer is dissolved at the time of plating. On the other hand, when the seed layer is made thick, it overhangs the upper part of the wiring groove and voids are generated. In this respect, in the present embodiment, since the insulating structure F is formed only on the bottom surface of the fine groove 200, it is possible to suppress the dissolution of the seed layer and the generation of voids described above.

<Other embodiments>
Next, another embodiment of the insulating structure F formed on the semiconductor substrate W will be described. FIG. 7 is an explanatory diagram showing an outline of the configuration of the plating processing apparatus 1 according to another embodiment.

The insulating structure F has a structure in which the insulating layer Fa and the conductive layer Fb are laminated in order from the semiconductor substrate W side. The insulating layer Fa is a barrier layer for suppressing the diffusion of copper, and the insulating layer Fa is made of an insulating material. The conductive layer Fb is a seed layer for passing an electric current during the plating process, and is composed of, for example, copper. The conductive layer Fb is partially formed on the insulating layer Fa. The semiconductor substrate W and the conductive layer Fb are capacitively coupled.

In the present embodiment, the barrier layer is the insulating layer Fa, but it may be the conductive layer Fb as in the above embodiment.

Then, in the present embodiment, first, in step S1, the insulating structure F is formed on the semiconductor substrate W. The method of forming the insulating structure F is not particularly limited as in step S1 of the above embodiment. However, when the conductive layer Fb is partially formed on the insulating layer Fa, a mask is provided on the insulating layer Fa and sputtering is performed at a desired portion to form the conductive layer Fb.

Next, in step S2, the electrode 10 is arranged above the semiconductor substrate W, and the plating solution M is filled between the insulating structure F and the electrode 10. Note that this step S2 is the same as step S2 of the above embodiment.

Next, in the charging step of step S3, as shown in FIGS. 8A and 8B, the first wiring 20, the charging wiring 23, and the second wiring 21 are connected by the switch 22, and the semiconductor substrate W is connected. (Insulation structure F) and the electrode 10 are connected via a DC power supply 30. Then, a DC voltage is applied with the electrode 10 as the anode and the insulating structure F as the cathode to form an electric field (electrostatic field). Then, a positive charge is accumulated on the electrode 10, and anions A, which are negatively charged particles in the plating solution M, are collected on the electrode 10. On the other hand, a negative charge is accumulated in the insulating structure F, and copper ions C, which are positively charged particles in the plating solution M, move to the insulating structure F. At this time, the copper ions C are accumulated only on the surface of the insulating structure F.

In step S3, the charging voltage applied to the plating solution M is larger than the ionization voltage for producing copper ions C. Then, as shown in FIGS. 9A and 9B, anions A are accumulated on the electrode 10, and an oxidation reaction occurs at the electrode 10. On the other hand, the copper ion C accumulated in the insulating structure F obtains an electric charge, and the copper ion C is reduced. Then, the copper plating 50 is deposited on the surface of the insulating structure F. At this time, the copper plating 50 is formed only on the surface of the conductive layer Fb, not on the other insulating layer Fa.

Next, in the discharge step of step S4, the first wiring 20, the discharge wiring 24, and the second wiring 21 are connected by the switch 22 as shown in FIGS. 10A and 10B, and the semiconductor substrate W is connected. (Insulation structure F) and the electrode 10 are connected without a DC power supply 30. Then, the electric charge charged in the capacitance of the insulating structure F is discharged.

Next, in step S5, the charging step in step S3 and the discharging step in step S4 are repeated in this order. Then, the copper plating 50 grows from the insulating structure F in the vertical direction and the horizontal direction, and the copper plating 50 is formed with a desired film thickness as shown in FIG.

In this embodiment as well, the same effects as those in the above embodiment can be enjoyed. That is, the amount of reduction in the wiring groove of the copper plating 50 in one charging step of step S3 can be increased, and the growth rate of plating can be improved. As a result, the copper plating 50 having a desired film thickness can be efficiently formed on the insulating structure F.

Further, the insulating structure F of the present embodiment, that is, the configuration in which the conductive layer Fb is partially formed on the insulating layer Fa, is also applied to the insulating structure F formed on the bottom surface of the fine groove 200 shown in FIG. can do. Then, the embedded wiring 210 can be formed in the fine groove 200.

<Other embodiments>
Next, another embodiment of the insulating structure F formed on the semiconductor substrate W will be described. FIG. 12 is an explanatory diagram showing an outline of the configuration of the plating processing apparatus 1 according to another embodiment.

In the above embodiment, the insulating structure F is formed in a single layer on the semiconductor substrate W, but in the present embodiment, the insulating structure F is formed in a plurality of layers. That is, the first insulating structure F1 and the second insulating structure F2 are laminated on the semiconductor substrate W in order from the semiconductor substrate W side. The first insulating structure F1 has a configuration in which the first insulating layer F1a and the first conductive layer F1b are laminated in order from the semiconductor substrate W side, and the second insulating structure F2 has a second insulation. The layer F2a and the second conductive layer F2b are laminated in order from the semiconductor substrate W side. The first conductive layer F1b and the second conductive layer F2b are capacitively coupled or connected by vias.

In such a case, since the total capacity of the insulating structures F1 and F2 can be increased, the reduction amount of the copper plating 50 can be further increased in step S3, and the growth rate of plating can be further improved. .. As a result, the copper plating 50 having a desired film thickness can be formed more efficiently on the insulating structure F.

<Other embodiments>
In the above embodiments, the case where the plating treatment is performed as the electrolytic treatment has been described, but the electrolytic treatment is not limited to this. For example, as an electrolytic treatment, a cleaning treatment may be performed. In such a case, a cleaning treatment device is used as the electrolytic treatment device. FIG. 13 is an explanatory diagram showing an outline of the configuration of the cleaning processing apparatus 300 according to another embodiment.

The cleaning processing device 300 has the positive and negative electrodes of the DC power supply 30 of the plating processing device 1 shown in FIG. 1 reversed. That is, in the cleaning processing apparatus 300, the semiconductor substrate W is connected to the positive electrode side of the DC power supply 310, and the electrode 10 is connected to the negative electrode side. Further, a cleaning liquid L as a treatment liquid is filled between the insulating structure F and the electrode 10, and the insulating structure F and the electrode 10 are electrically connected to the cleaning liquid L. The other configurations of the cleaning processing apparatus 300 are the same as the configurations of the plating processing apparatus 1.

Then, in the present embodiment, after the insulating structure F is formed on the semiconductor substrate W, the electrode 10 is arranged above the semiconductor substrate W, and the cleaning liquid L is filled between the insulating structure F and the electrode 10.

Next, in the charging step, as shown in FIGS. 14A and 14B, the first wiring 20, the charging wiring 23, and the second wiring 21 are connected by the switch 22, and the semiconductor substrate W (insulation structure) is connected. The body F) and the electrode 10 are connected via a DC power supply 30. Then, a DC voltage is applied with the electrode 10 as the cathode and the insulating structure F as the anode to form an electric field (electrostatic field). Then, a negative charge is accumulated on the electrode 10, and cations D, which are positively charged particles in the cleaning liquid L, are collected on the electrode 10. On the other hand, a positive charge is accumulated in the insulating structure F, and anions E as ions to be treated, which are negatively charged particles in the cleaning liquid L, move to the insulating structure F.

At this time, the charging voltage applied to the cleaning liquid L is larger than the ionization voltage for generating the cation D. Then, the cation D is accumulated on the electrode 10, and a reduction reaction occurs at the electrode 10. On the other hand, anions E are accumulated in the insulating structure F, and an oxidation reaction occurs in the insulating structure F. Then, the surface of the insulating structure F is cleaned.

Next, in the discharge step, as shown in FIGS. 15A and 15B, the first wiring 20, the discharge wiring 24, and the second wiring 21 are connected by the switch 22, and the semiconductor substrate W (insulation structure) is connected. The body F) and the electrode 10 are connected without going through the DC power supply 30. Then, the electric charge charged in the capacitance of the insulating structure F is discharged.

Next, the charging step and the discharging step are repeated in this order. Then, the surface of the insulating structure F is cleaned.

In this embodiment as well, the same effects as those in the above embodiment can be enjoyed. That is, the amount of oxidation of the insulating structure F in one charging step can be increased, and the surface of the insulating structure F can be efficiently cleaned. Then, this embodiment can be applied as a cleaning technique for the fine groove 200.

Although preferred embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modifications or modifications within the scope of the ideas described in the claims, which naturally belong to the technical scope of the present invention. It is understood as a thing.

1 Plating processing device 10 Electrode 20 1st wiring 21 2nd wiring 22 Switch 23 Charging wiring 24 Discharging wiring 30 DC power supply 31 Charging resistance 32 Discharging resistance 40 Control unit 50 Copper plating 100 Micropores 110 Embedded wiring 200 Microgroove 210 Embedded Wiring 300 Cleaning processing device 310 DC power supply A Anion C Copper ion D Cationic E Anion F (F1, F2) Insulation structure Fa (F1a, F2a) Insulation layer Fb (F1b, F2b) Conductive layer L Cleaning liquid M Plating liquid W semiconductor substrate

Claims (10)

An electrolytic treatment method in which a semiconductor substrate is subjected to a predetermined treatment using ions to be treated contained in a treatment liquid.
The first step of forming an insulating structure in which an insulating layer and a conductive layer are sequentially laminated on the semiconductor substrate from the semiconductor substrate side into a single layer or a plurality of layers, and capacitively coupling the semiconductor substrate and the conductive layer. ,
A second step of supplying the treatment liquid on the insulating structure and arranging the electrodes so as to be electrically connected to the treatment liquid.
The semiconductor substrate and the electrode are connected via a power source, and a voltage is applied to the treatment liquid to reduce the ions to be treated in the treatment liquid to the surface of the insulation structure or to reduce the surface of the insulation structure to the surface of the insulation structure. The third step of oxidation and
An electrolytic treatment method comprising a fourth step of connecting the semiconductor substrate and the electrodes without going through the power source and discharging the electric charge charged in the capacitance of the insulating structure. The voltage applied to the processing liquid in the third step is larger than the ionization voltage for generating the ions to be processed.
The electrolytic treatment method according to claim 1, wherein the voltage applied to the treatment liquid in the fourth step is smaller than the ionization voltage. In the first step, the conductive layer is partially formed on the insulating layer.
The third step according to claim 1 or 2, wherein the ion to be treated is reduced to the surface of the partially formed conductive layer or the surface of the insulating structure is oxidized. Electrolytic treatment method. In the third step, a voltage is applied to the treatment liquid using the semiconductor substrate as a cathode and the electrode as an anode to reduce the ions to be treated in the treatment liquid to the surface of the insulating structure. The electrolytic treatment method according to any one of claims 1 to 3, wherein a film is formed. Fine grooves are formed on the surface of the semiconductor substrate.
The electrolytic treatment method according to any one of claims 1 to 4, wherein in the first step, the conductive layer is formed on the bottom surface of the fine groove. An electrolytic treatment apparatus that performs a predetermined treatment on a semiconductor substrate using ions to be treated contained in a treatment liquid.
On the semiconductor substrate, an insulating structure in which an insulating layer and a conductive layer are sequentially laminated from the semiconductor substrate side is formed as a single layer or a plurality of layers.
The semiconductor substrate and the conductive layer are capacitively coupled to each other.
The treatment liquid is supplied onto the insulating structure.
The electrolytic treatment device is
An electrode arranged to be electrically connected to the treatment liquid and
The semiconductor substrate, the power supply connected to the electrodes, and
A switch that switches between connecting the semiconductor substrate and the electrode via the power supply and connecting the semiconductor substrate and the electrode without the power supply.
Has a control unit,
The control unit
The semiconductor substrate and the electrode are connected via the power source, and a voltage is applied to the treatment liquid to reduce the ions to be treated in the treatment liquid to the surface of the insulation structure or the surface of the insulation structure. And the process of oxidizing
It is characterized in that the switch is controlled so as to execute a step of connecting the semiconductor substrate and the electrode without going through the power source and discharging the electric charge charged in the capacitance of the insulating structure. , Electrolytic processing equipment. The resistance value of the charging resistance provided in the connection between the semiconductor substrate and the electrode via the power supply is smaller than the resistance value of the discharge resistance provided in the connection between the semiconductor substrate and the electrode via the power supply. 6. The electrolytic treatment apparatus according to claim 6. The electrolytic treatment apparatus according to claim 6 or 7, wherein the conductive layer is partially formed on the insulating layer. Fine grooves are formed on the surface of the semiconductor substrate.
The electrolytic treatment apparatus according to any one of claims 6 to 8, wherein the conductive layer is formed on the bottom surface of the fine groove. The insulating structure is formed in multiple layers.
The multi-layered insulating structure has a structure in which a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer are laminated in this order from the treatment liquid side.
The electrolytic treatment apparatus according to any one of claims 6 to 9, wherein the first conductive layer and the second conductive layer are connected by a capacitive coupling or via.

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