JP2004149926A - Method of forming embedded wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To uniform the surface height of an embedded wiring by suppressing erosion occurring in an area with dense embedded wiring and dishing occurring in an area of wide wiring width of the embedded wiring. <P>SOLUTION: A recessed groove 41 for wiring of small width and a recessed groove 42 for wiring of large width are formed in an insulating film 31, a barrier layer 32 and a copper film 33 are deposited on the insulating film 31, and the copper film 33 is subjected to reflow. Chemical-mechanical polishing is performed on the copper film 33 while feeding polishing slurry containing copper ions on a polishing pad. Negative voltage is applied to the copper film 33 to deposit a copper-plated layer 43 on the surface of the copper film 33 while continuing the chemical-mechanical polishing of the copper film 33. The surface height of the copper film 33 deposited on the recessed groove 41 for wiring of small width and the recessed groove 42 for wiring of large width is set to be substantially equal to the surface height of a projecting portion 31a of the insulating film 31. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a method for forming a buried interconnect in a semiconductor device manufacturing process.

  2. Description of the Related Art In recent years, as a method of forming an embedded wiring (including a plug) on a semiconductor substrate, a method of forming a concave portion including a wiring concave groove or a plug concave portion in an insulating film such as an oxide film formed on a semiconductor substrate is known. Then, a conductive film made of copper or the like is deposited over the entire surface of the insulating film including the concave portion, and then the conductive film (the conductive film excluding the inside of the concave portion) deposited on the insulating film is subjected to chemical mechanical polishing. A method of forming a buried wiring in a concave portion by removing the wiring has been proposed.

  Hereinafter, a conventional method for forming a buried interconnect will be described with reference to FIGS.

  FIG. 14 shows a schematic configuration of a conventional chemical mechanical polishing apparatus. As shown in FIG. 14, a polishing pad 102 is provided on a rotating platen 101, and a polishing pad 102 is provided above the polishing pad 102. A polishing slurry supply pipe 104 for supplying a polishing slurry 103 is provided on the polishing pad 102. Above the polishing pad 102, a substrate holding head 106 that holds the substrate to be polished 105 and presses the held substrate to be polished 105 against the polishing pad 102 is provided to be vertically movable.

  In a conventional chemical mechanical polishing apparatus, a substrate to be polished 105 is pressed against a polishing pad 102 by a substrate holding head 106 while a polishing slurry 103 is supplied onto a polishing pad 102 which rotates with the rotation of a platen 101. Then, the metal film such as copper deposited on the surface of the substrate 105 to be polished is subjected to chemical mechanical polishing and becomes flat.

  FIG. 15 schematically shows components of a polishing slurry 103 for polishing a metal film such as copper. The polishing slurry 103 is formed by polishing water 110 with abrasive grains 111 such as alumina or silica and oxidizing hydrogen peroxide or the like. Agent 112 is contained. The polishing slurry 103 is used to planarize the metal film by oxidizing the metal film with the oxidizing agent 112 and polishing and removing the oxidized metal film by the abrasive grains 111.

  Hereinafter, a method of forming a buried wiring of copper using the above-described chemical mechanical polishing apparatus and polishing slurry will be described with reference to FIGS.

  First, as shown in FIG. 16A, a narrow wiring concave groove 121 for forming a narrow embedded wiring such as a signal line in an insulating film 120 formed on a semiconductor substrate (not shown), and After forming a wide wiring concave groove 122 for forming a wide embedded wiring such as a voltage power supply line, an inspection electrode or an external connection electrode, a barrier made of, for example, TiN is formed on the entire surface of the insulating film 120. A layer 123 is deposited, and then a copper film 124 is deposited over the barrier layer 123 over the entire surface. In FIG. 16A, the groove pattern dense region indicates a region where the narrow buried wiring and thus the narrow wiring concave groove 121 are dense, and the pattern region having a large groove width is a voltage power supply line. 2 shows a region where a wide buried wiring such as an inspection electrode or an external electrode and a wide wiring concave groove 122 are formed.

  Next, the copper film 124 is subjected to a heat treatment and is reflowed, so that the copper film 124 is formed at the bottom of the narrow wiring concave groove 121 and the wide wiring concave groove 122 as shown in FIG. Fill securely to the corners.

  Next, when the copper film 124 is subjected to chemical mechanical polishing using the polishing slurry 103, as shown in FIG. 16C, a normal buried wiring 125 made of the copper film 124 and a wide buried wiring 126 are formed. Is formed.

  However, when the chemical mechanical polishing is performed as described above, as shown in FIG. 16C, in a pattern region having a large groove width, the film thickness at the central portion of the wide buried wiring 125 decreases, that is, so-called dishing. Occurs, and so-called erosion, in which the height of the narrow embedded wiring 125 is reduced from a predetermined value, occurs in the groove pattern dense area.

  As described above, when erosion or dishing occurs, the height of the embedded wiring is reduced and the wiring resistance is increased, so that there is a problem that the reliability of the embedded wiring is reduced.

  Also, if there is a surface step in the embedded wiring, a problem occurs in pattern formation due to the problem of the depth of focus of lithography.

  In view of the above, the present invention suppresses erosion that occurs in a region where the embedded wiring is dense, and dishing that occurs in a region where the wiring width of the embedded wiring is wide, and makes the surface height of the embedded wiring uniform, thereby An object of the present invention is to improve the reliability of embedded wiring and to secure a margin for the depth of focus of lithography.

  In order to achieve the above object, a method for forming a buried wiring according to the present invention comprises the steps of: (a) forming a concave groove in an insulating film formed on a semiconductor substrate; and forming a barrier layer on the insulating film. After the formation, a step (b) of forming a metal film on the barrier layer so as to fill the concave groove, and performing chemical mechanical polishing and electrolytic plating on the metal film in parallel, Forming a buried interconnect in the groove (c).

  According to the method for forming an embedded wiring of the present invention, in the step (c) of forming the embedded wiring in the concave groove, the chemical mechanical polishing and the electrolytic plating are performed on the metal film in parallel, so that the surface of the metal film has a chemical mechanical property. Although the thickness of the metal film is reduced due to polishing, a plating layer is formed on the surface of the metal film. In this case, the plating layer is quickly polished in the convex portion of the metal film, while the plating layer is hard to be polished in the concave portion of the metal film, so that the buried wiring is dense or the wiring width of the buried wiring is small. A plating layer is selectively formed in a region where the metal film is likely to be concave because of being wide. Therefore, erosion that occurs in a region where the buried wiring is dense and dishing that occurs in a region where the wiring width of the buried wiring is large are suppressed.

  In the method of forming an embedded wiring according to the present invention, in the step (c), the metal film on the convex portion of the insulating film is removed by the chemical mechanical polishing, and the metal film formed in the concave groove is formed. It is preferable that a plating layer composed of ions of the same metal as the metal constituting the metal film grows on the surface of the metal film.

  In the method for forming a buried interconnect according to the present invention, in the step (c), the thickness of the metal film on the convex portion of the insulating film is within a range of 80 to 10% of an initial film thickness by the chemical mechanical polishing. It is preferable that the electrolytic plating be started when the above conditions are satisfied.

  In the method for forming a buried interconnect according to the present invention, the step (c) is performed when the thickness of the metal film on the convex portion of the insulating film is 80% or more of an initial film thickness by the chemical mechanical polishing. It is preferable to start the electrolytic plating.

  In the method of forming an embedded wiring according to the present invention, in the step (b), it is preferable that after depositing the metal film on the barrier layer, a heat treatment is performed on the metal film.

  In the method for forming an embedded wiring according to the present invention, it is preferable that the metal film is a copper film.

  According to the method for forming an embedded wiring according to the present invention, the thickness of the metal film is reduced because the surface of the metal film is chemically and mechanically polished, but since the plating layer is formed on the surface of the metal film, the embedded wiring is densely packed. The erosion that occurs in the region where the wiring is formed and the dishing that occurs in the region where the wiring width of the buried wiring is large are suppressed, and the surface height of the buried wiring is made uniform, so that the variation in wiring resistance is reduced. Reliability is improved. Further, a margin of the depth of focus in lithography can be secured.

  In the method for forming an embedded wiring according to the present invention, when the electrolytic plating is started when the thickness of the metal film is 80% to 10% of the initial film thickness, the efficiency of chemical mechanical polishing is improved, and the throughput is improved. Can be done.

  In the method of forming an embedded wiring according to the present invention, when the electroplating is started when the thickness of the metal film becomes 100% to 80% of the initial film thickness, the chemical mechanical polishing and the electroplating proceed almost simultaneously. Therefore, erosion that occurs in a region where the embedded wirings are densely formed and dishing that occurs in a region where the wiring width of the embedded wiring is wide can be reliably suppressed, and the surface height of the embedded wiring can be reliably made uniform.

(1st Embodiment)
FIG. 1 schematically shows components of a polishing slurry 10 according to the first embodiment of the present invention. The polishing slurry 10 according to the first embodiment includes water 11 containing abrasive grains 12 such as alumina or silica, An oxidizing agent 13 such as hydrogen peroxide and ions 14 of the same kind of metal as the metal constituting the film to be polished are contained. When the film to be polished is a copper film, the metal ions 14 include copper ions (Cu ²⁺ ).

As a method of causing the polishing slurry 10 to contain copper ions, copper sulfate (CuSO ₄ ) is mixed into the polishing slurry 10 and the mixed copper sulfate is ionized to generate Cu ²⁺ and SO ₄ ^2- .

(Second embodiment)
FIG. 2 shows a schematic configuration of a substrate polishing apparatus according to a second embodiment of the present invention, and FIG. 3 is an enlarged view of a dashed line in FIG.

  As shown in FIG. 2, a polishing pad 21 is provided on a rotating platen 20. Above the polishing pad 21, the polishing slurry 10 according to the first embodiment is placed on the polishing pad 21. Is provided. Above the polishing pad 21, a substrate holding head 25 that holds the substrate 24 to be polished and presses the film to be polished of the substrate 24 to be polished against the polishing pad 21 is provided so as to be vertically movable.

  As a feature of the second embodiment, a DC voltage source 26 and an ammeter 27 are connected in series between the polishing slurry supply pipe 23 and the substrate holding head 25, and the DC voltage source 26, the polishing slurry supply pipe 23, A closed circuit is formed between the polishing slurry 10, the copper film 33, the substrate holding head 25, and the ammeter 27.

  As shown in FIG. 3, the substrate 24 to be polished includes a silicon wafer 30, an insulating film 31 sequentially deposited on the silicon wafer 30, a barrier layer 32 made of a TiN layer, and a copper film 33. . In this case, since the side surface of the silicon wafer 30 is rounded, the copper film 33 is formed so as to extend almost to the center in the thickness direction of the silicon wafer 30.

  The substrate holding head 25 is made of a conductive material, and an insulator 35 is attached to a portion of the substrate holding head 25 facing the polishing pad 21.

  As a result, the copper film 33 is electrically connected to the substrate holding head 25 at the peripheral portion (head conductive portion), and the substrate holding head 25 and the polishing pad 21, and further, the polishing slurry 10 on the polishing pad 21 are electrically connected. Electrically insulated.

(Method of polishing first substrate)
Hereinafter, a first substrate polishing method performed by using the substrate polishing apparatus according to the second embodiment will be described with reference to FIGS.

  First, as shown in FIG. 4A, an insulating film 31 formed on a silicon wafer 30 (not shown in FIGS. 4A to 4D) has a signal line or the like on it. A narrow wiring concave groove 41 for forming a narrow embedded wiring, and a wide wiring concave groove 42 for forming a wide embedded wiring such as a voltage power supply line, an inspection electrode or an external connection electrode. Is formed, a barrier layer 32 made of, for example, TiN is deposited on the entire surface of the insulating film 31, and then a copper film 33 is deposited on the entire surface of the barrier layer 32. The meanings of the dense groove pattern region and the pattern region having a large groove width are the same as those of the conventional substrate polishing method shown in FIG.

  Next, the copper film 33 is subjected to a heat treatment and reflowed, so that the copper film 33 is formed at the bottom of the narrow wiring concave groove 41 and the wide wiring concave groove 42 as shown in FIG. Fill up to the corners.

  Next, while rotating the platen 20 and rotating the polishing pad 21, the polishing slurry 10 according to the first embodiment is supplied onto the polishing pad 21 from the polishing slurry supply pipe 23 while the substrate holding head 25 is moved. Then, the copper film 33 is subjected to chemical mechanical polishing.

  Then, at the stage where the chemical mechanical polishing of the copper film 33 has progressed to a certain extent, a positive voltage is applied from the DC voltage source 26 to the polishing slurry supply pipe 23 while the chemical mechanical polishing of the copper film 33 is continued. A negative voltage is applied to the holding head 25.

In this way, the positive ions (Cu ²⁺ ) of copper contained in the polishing slurry 10 are attracted to the copper film 33 to which the negative voltage is applied via the substrate holding head 25 and from the copper film 33. The electrons are obtained and adhere to the surface of the copper film 33 as copper atoms. That is, as shown in FIG. 4C, the thickness of the copper film 33 is reduced by chemical mechanical polishing. However, since the surface of the copper film 33 is subjected to electrolytic plating of copper, the surface of the copper film 33 is Is formed. In this case, a plating layer 43 having substantially the same thickness grows on the surface of the copper film 33, but the plating layer 43 adhering to the copper film 33 on the projection 31a of the insulating film 31 is quickly removed by chemical mechanical polishing. Therefore, the surface height of the copper film 33 deposited in the narrow wiring concave groove 41 is substantially equal to the surface height of the projection 31 a of the insulating film 31. Further, the surface height of the copper film 33 deposited in the wide wiring concave groove 42 is slightly lower than the surface height of the convex portion 31a of the insulating film 31, but compared to a case where copper electrolytic plating is not performed. Since the height is higher, that is, the surface height of the protrusion 31 a of the insulating film 31 is approached, the step on the surface of the copper film 33 is reduced.

  Thereafter, when chemical mechanical polishing of the copper film 33, application of a positive voltage to the polishing slurry supply pipe 23, and application of a negative voltage to the substrate holding head 25 are continued, the copper film 33 is deposited in the wide concave groove 42 for wiring. Since the surface height of the copper film 33 is lower than the surface height of the projection 31a of the insulating film 31, a plating layer 43 grows on the surface of the copper film 33 deposited in the wide wiring concave groove 42, The step is gradually reduced.

  Next, when the barrier layer 32 is removed by polishing and the insulating film 31 is exposed, chemical mechanical polishing of the copper film 33, application of a positive voltage to the polishing slurry supply pipe 23, and application of a negative voltage to the substrate holding head 25 are performed. The application of the voltage is terminated. In this way, as shown in FIG. 4D, the narrow embedded wiring 45 deposited in the narrow wiring concave groove 41 and the wide embedded wiring 46 deposited in the wide wiring concave groove 42. And the height of the convex portion 31a of the insulating film 31 becomes substantially equal. However, the surface height of the central portion of the wide embedded wiring 46 is slightly lower than the surface height of the convex portion 31 a of the insulating film 31.

  As described above, according to the first substrate polishing method, the chemical mechanical polishing and the copper electrolytic plating are performed on the copper film 33 in parallel, so that the embedded wiring 45 having a narrow width in the groove pattern dense region is formed. The surface height of the wide embedded wiring 46 and the surface height of the insulating film 31 can be made substantially equal.

  The timing at which a positive voltage is applied from the DC voltage source 26 to the polishing slurry supply pipe 23 and a negative voltage is applied to the substrate holding head 25 to start electrolytic plating is based on the timing on the convex portion 31 a of the insulating film 31. It is preferable that the thickness of the copper film 33 falls within the range of 80 to 10% of the initial film thickness. The reason is as follows. That is, when electrolytic plating is started in a state where the thickness of the copper film 33 exceeds 80% of the initial film thickness, the plating layer 43 and the copper film 33 are chemically and mechanically polished while the plating layer 43 is deposited. This is because the polishing rate is substantially reduced, and if electrolytic plating is started in a state where the thickness of the copper film 33 is less than 10% of the initial film thickness, there is almost no effect of suppressing dishing and erosion.

  As described above, when the thickness of the copper film 33 falls within the range of 80 to 10% of the initial film thickness, a positive voltage is applied to the polishing slurry supply pipe 23 and a negative voltage is applied to the substrate holding head 25. When the voltage is applied, only the chemical mechanical polishing is performed until the thickness of the copper film 33 is reduced to a certain degree by the chemical mechanical polishing, so that the efficiency of the chemical mechanical polishing is improved. Can be suppressed.

  Instead of connecting the DC voltage source 26 between the polishing slurry supply pipe 23 and the substrate holding head 25, a positive voltage is applied to the polishing slurry supply pipe 23 from one DC voltage source, and the substrate holding head 25 May be applied with a negative voltage from another DC voltage source. By doing so, the application of a positive voltage to the polishing slurry supply pipe 23 and the application of a negative voltage to the substrate holding head 25 can be controlled independently. Further, between the polishing slurry supply pipe 23 and the substrate holding head 25, in addition to the DC voltage source 26, an AC voltage source may be connected in series.

(Method of polishing second substrate)
Hereinafter, a second substrate polishing method performed by using the substrate polishing apparatus according to the second embodiment will be described with reference to FIGS. 5 (a) to 5 (c) and FIG.

  First, a barrier layer 32 and a copper film 33 are sequentially deposited on an insulating film 31 in which a concave groove for wiring is formed, and then the copper film 33 is reflowed to form a narrow width, similarly to the first substrate polishing method. The wiring concave groove 41 and the wide wiring concave groove 42 are filled.

  Next, chemical mechanical polishing is performed on the copper film 33 while supplying the polishing slurry 10 according to the first embodiment onto the polishing pad 21 from the polishing slurry supply pipe 23. Thereafter, when the thickness of the copper film 33 decreases to a certain extent, a positive constant voltage is applied from the DC voltage source 26 to the polishing slurry supply pipe 23 and a negative constant voltage is applied to the substrate holding head 25. While measuring the value of the current flowing between the polishing slurry supply pipe 23 and the substrate holding head 25 with the ammeter 27, while calculating the resistance value between the polishing slurry supply pipe 23 and the substrate holding head 25, Copper electrolytic plating of the copper film 33 is performed.

  In this case, a large current flows when the electroplating is actively performed, so that the current value is large and the plating resistance is small, but only a small current flows when the electroplating is not performed. In addition, the plating resistance increases.

  FIGS. 5A to 5C and FIGS. 6A to 6C show a state in which the copper film 33 is formed on the silicon wafer 30 when the chemical mechanical polishing is performed while the electrolytic plating is performed. 5A to 5C show a cross-sectional structure, and FIGS. 6A to 6C show a planar structure. I have. FIG. 7 shows the relationship between the polishing time and the resistance value when chemical mechanical polishing is performed while performing electrolytic plating on the copper film 33.

  As shown in FIGS. 5A and 6A, in the initial stage of chemical mechanical polishing, a large current flows because the thickness of the copper film 33 is sufficiently large and the barrier layer 32 is not exposed. Therefore, the resistance value is small as shown by A in the graph of FIG.

  Thereafter, as shown in FIG. 5B and FIG. 6B, chemical mechanical polishing progresses, the thickness of the copper film 33 decreases, and when the barrier layer 32 starts to be exposed, the barrier 32 is removed. Since the constituent TiN has a higher specific resistance than Cu, the current value decreases, so that the resistance value continues to increase as shown by B in the graph of FIG.

  Thereafter, as shown in FIG. 5C and FIG. 6C, when the chemical mechanical polishing further progresses and the insulating film 31 is largely exposed, almost no current flows. Thus, the resistance value becomes almost infinite and the increase in the resistance value is saturated. In this state, the chemical mechanical polishing and the electrolytic plating are completed.

  In this way, by calculating the value of the current flowing between the polishing slurry supply pipe 23 and the substrate holding head 25 and thus the resistance value, the end point of the chemical mechanical polishing can be detected.

  In the second substrate polishing method, a current value flowing between the polishing slurry supply pipe 23 and the substrate holding head 25 and a resistance value are calculated while simultaneously performing electrolytic plating and chemical mechanical polishing. Alternatively, the end point of the chemical mechanical polishing can be detected by calculating the current value and thus the resistance value while performing only the chemical mechanical polishing without performing the electrolytic plating.

(Third substrate polishing method)
Hereinafter, a third substrate polishing method performed by using the substrate polishing apparatus according to the second embodiment will be described with reference to FIGS.

  First, as shown in FIG. 8A, an insulating film 31 formed on a silicon wafer 30 (not shown in FIGS. 8A to 8D) has a thin wiring After the concave groove 41 and the wide wiring concave groove 42 are formed, a barrier layer 32 made of, for example, TiN is deposited on the entire surface of the insulating film 31, and then copper is formed on the entire surface of the barrier layer 32. A film 33 is deposited. Next, a heat treatment is performed on the copper film 33 and the copper film 33 is reflowed, thereby filling the copper film 33 to the bottom corners of the narrow wiring concave groove 41 and the wide wiring concave groove 42. The meanings of the dense groove pattern region and the pattern region having a large groove width are the same as those of the conventional substrate polishing method shown in FIG.

  Next, the polishing slurry 10 according to the first embodiment is supplied from the polishing slurry supply pipe 23 onto the rotating polishing pad 21 to perform the chemical mechanical polishing on the copper film 33 and the DC voltage source 26. Then, a positive voltage is applied to the polishing slurry supply pipe 23 and a negative voltage is applied to the substrate holding head 25 to perform copper electrolytic plating on the copper film 33.

  In this case, as shown in FIG. 8B, since copper electrolytic plating is performed from the beginning of the chemical mechanical polishing, the copper plating layer 43 grows largely on the surface of the copper film 33, so that the width is wide. Dishing generated in the copper film 33 and the plating layer 43 deposited in the wiring concave groove 42 is smaller than that in the first substrate polishing method.

  Therefore, the surface height of the copper film 33 and the plating layer 43 deposited in the wide wiring concave groove 42 is slightly lower than the surface height of the projection 31 a of the insulating film 31, but the projection 31 a of the insulating film 31 , And the step on the surface is greatly reduced. Further, the copper film 33 and the plating layer 43 deposited in the narrow wiring concave groove 41 have the same height as the copper film 33 on the projection 31 a of the insulating film 31.

  Thereafter, when the chemical mechanical polishing and the electrolytic plating are continued, as shown in FIG. 8C, the surface heights of the copper film 33 and the plating layer 33 deposited in the wide wiring concave groove 42 become the same as that of the insulating film 31. This is equivalent to the surface height of the projection 31a.

  Further, when the chemical mechanical polishing and the electrolytic plating are continued, and the chemical mechanical polishing and the electrolytic plating are completed when the insulating film 31 is exposed, as shown in FIG. The width of the narrow buried wiring 45 and the width of the wide buried wiring 46 deposited in the wide wiring concave groove 42 are equal to the height of the projection 31 a of the insulating film 31.

  As described above, according to the third substrate polishing method, the chemical mechanical polishing and the electrolytic plating are performed in parallel on the copper film 33 from the beginning. The surface height of the wide embedded wiring 46 and the surface height of the insulating film 31 can be reliably made equal.

  Note that the timing of performing the electrolytic plating of copper on the copper film may be at the same time as the start of the chemical mechanical polishing. However, the thickness of the copper film 33 on the convex portion 31a of the insulating film 31 is 80% of the initial thickness. % May be performed. By doing so, the surface height of the wide embedded wiring 46 and the surface height of the insulating film 31 can be reliably made equal.

  In the first to third substrate polishing methods, the polishing slurry 10 contains copper ions, which are positive metal ions, but instead, the polishing slurry 10 contains negative metal ions. , A negative voltage is applied to the polishing slurry supply pipe 23, while a positive voltage is applied to the substrate holding head 25.

(Third embodiment)
FIG. 9 shows a schematic configuration of a substrate polishing apparatus according to a third embodiment of the present invention. As shown in FIG. 9, a polishing pad 21 is provided on a rotating platen 20. A polishing slurry supply pipe 23 for supplying the polishing slurry 10 according to the first embodiment to the upper surface of the polishing pad 21 is provided above the polishing pad 21. Above the polishing pad 21, a substrate holding head 25 that holds the substrate 24 to be polished and presses the held substrate 24 against the polishing pad 21 is provided to be vertically movable.

  As a feature of the third embodiment, between the polishing slurry supply pipe 23 and the polishing pad 21, a material such as titanium or the like is contacted so as to contact the polishing slurry 10 supplied onto the polishing pad 21 from the polishing slurry supply pipe 23. A rod-shaped conductor 51 made of a conductive material is provided, and the tip of the conductor 51 is formed in a spherical shape so as to increase the contact area with the polishing slurry 10.

  A DC voltage source 26 and an ammeter 27 are connected in series between the conductor 51 and the substrate holding head 25. The DC voltage source 26, the conductor 51, the polishing slurry 10, the copper film 33, the substrate A closed circuit is formed between the holding head 25 and the ammeter 27.

  According to the substrate polishing apparatus according to the third embodiment, a positive voltage is applied from the DC voltage source 26 to the conductor 51 and a negative voltage is applied to the substrate holding head 25 while performing chemical mechanical polishing on the copper film 33. The copper plating can be applied to the copper film 33 by applying the voltage. Further, the magnitude of the current flowing between the conductor 51 and the substrate holding head 25 can be detected by the ammeter 27.

  Therefore, the first to third substrate polishing methods can be reliably performed by using the substrate polishing apparatus according to the third embodiment.

(Fourth embodiment)
FIG. 10 shows a schematic configuration of a substrate polishing apparatus according to a fourth embodiment of the present invention. As shown in FIG. 10, a polishing pad 21 is provided on a rotating platen 20. A polishing slurry supply pipe 23 for supplying the polishing slurry 10 according to the first embodiment to the upper surface of the polishing pad 21 is provided above the polishing pad 21. Above the polishing pad 21, a substrate holding head 25 that holds the substrate 24 to be polished and presses the held substrate 24 against the polishing pad 21 is provided to be vertically movable.

  A feature of the fourth embodiment is that a roller 52a made of a conductive material that rotates while being in contact with the peripheral edge of the rotating polishing pad 21 and a roller holder 52b made of a conductive material that rotatably holds the roller 52a Are provided. Thereby, the roller 52 a of the roller member 52 can come into contact with the polishing slurry 10 supplied on the polishing pad 21.

  A DC voltage source 26 and an ammeter 27 are connected in series between the roller holding body 51b of the roller member 52 and the substrate holding head 25, and the DC voltage source 26, the roller member 52, the polishing slurry 10, A closed circuit is formed between the copper film 33, the substrate holding head 25, and the ammeter 27.

  According to the substrate polishing apparatus according to the fourth embodiment, a positive voltage is applied from the DC voltage source 26 to the roller member 52 and a negative voltage is applied to the substrate holding head 25 while performing chemical mechanical polishing on the copper film 33. By applying the voltage, copper electrolytic plating can be performed on the copper film 33. Further, the magnitude of the current flowing between the roller member 52 and the substrate holding head 25 can be detected by the ammeter 27.

  Therefore, the first to third substrate polishing methods can be reliably performed using the substrate polishing apparatus according to the fourth embodiment.

(Fifth embodiment)
FIG. 11 shows a schematic configuration of a substrate polishing apparatus according to a fifth embodiment of the present invention. As shown in FIG. 11, a polishing pad 21 is provided on a rotating platen 20. A polishing slurry supply pipe 23 for supplying the polishing slurry 10 according to the first embodiment to the upper surface of the polishing pad 21 is provided above the polishing pad 21. Above the polishing pad 21, a substrate holding head 25 that holds the substrate 24 to be polished and presses the held substrate 24 against the polishing pad 21 is provided to be vertically movable.

  As a feature of the fifth embodiment, a conductive film 54 is provided on the surface of the substrate holding head 25 via an insulating film 53, and the conductive film 54 is supplied on the polishing pad 21. It can be in contact with the polishing slurry 10.

  A DC voltage source 26 and an ammeter 27 are connected in series between the conductive film 54 and the substrate holding head 25. The DC voltage source 26, the conductive film 54, the polishing slurry 10, the copper film 33 A closed circuit is formed between the substrate holding head 25 and the ammeter 27.

  According to the substrate polishing apparatus according to the fifth embodiment, a positive voltage is applied to the conductive film 54 from the DC voltage source 26 and a negative voltage is applied to the substrate holding head 25 while performing chemical mechanical polishing on the copper film 33. To apply copper electrolytic plating to the copper film 33. Further, the magnitude of the current flowing between the conductive film 54 and the substrate holding head 25 can be detected by the ammeter 27.

  Therefore, the first to third substrate polishing methods can be reliably executed by using the substrate polishing apparatus according to the fifth embodiment.

(Sixth embodiment)
FIG. 12 shows a schematic configuration of a substrate polishing apparatus according to the sixth embodiment of the present invention, and FIG. 13 schematically shows a structure of a polishing pad 21 in the substrate polishing apparatus according to the sixth embodiment. .

  As shown in FIG. 12, a conductive polishing pad 21 is provided on a rotating platen 20, and an upper surface of the polishing pad 21 is provided above the polishing pad 21 according to the first embodiment. A polishing slurry supply pipe 23 for supplying the polishing slurry 10 is provided. Above the polishing pad 21, a substrate holding head 25 that holds the substrate 24 to be polished and presses the held substrate 24 against the polishing pad 21 is provided to be vertically movable.

  As a feature of the sixth embodiment, as shown in FIG. 13, the conductive polishing pad 21 includes a sheet 55 made of a carbon polymer, and conductive particles 56 scattered inside the sheet 55. It is composed of

  A DC voltage source 26 and an ammeter 27 are connected in series between the conductive polishing pad 21 and the substrate holding head 25. The DC voltage source 26, the polishing pad 21, the polishing slurry 10, the copper film A closed circuit is formed between 33, the substrate holding head 25 and the ammeter 27.

  According to the substrate polishing apparatus according to the sixth embodiment, a positive voltage is applied from the DC voltage source 26 to the polishing pad 21 and a negative voltage is applied to the substrate holding head 25 while performing chemical mechanical polishing on the copper film 33. By applying the voltage, copper electrolytic plating can be performed on the copper film 33. Further, the magnitude of the current flowing between the polishing pad 21 and the substrate holding head 25 can be detected by the ammeter 27.

  Therefore, the first to third substrate polishing methods can be reliably performed using the substrate polishing apparatus according to the sixth embodiment.

FIG. 1 is a schematic diagram illustrating a polishing slurry according to a first embodiment of the present invention. FIG. 6 is a schematic sectional view of a substrate polishing apparatus according to a second embodiment of the present invention. FIG. 5 is an enlarged cross-sectional view of a part surrounded by a dashed line in FIG. 2, showing a main part of a substrate polishing apparatus according to a second embodiment of the present invention. (A)-(d) is sectional drawing which shows each process of the 1st board | substrate polishing method performed using the board | substrate polishing apparatus which concerns on each embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the 2nd board | substrate polishing method performed using the board | substrate polishing apparatus which concerns on each embodiment of this invention. (A)-(c) is a perspective view which shows each process of the 2nd board | substrate polishing method performed using the board | substrate polishing apparatus which concerns on each embodiment of this invention. FIG. 6 is a diagram showing a relationship between a polishing time and a resistance value in a second substrate polishing method performed by using the substrate polishing apparatus according to each embodiment of the present invention. (A)-(d) is sectional drawing which shows each process of the 3rd board | substrate polishing method performed using the board | substrate polishing apparatus which concerns on each embodiment of this invention. FIG. 7 is a schematic sectional view of a substrate polishing apparatus according to a third embodiment of the present invention. FIG. 9 is a schematic sectional view of a substrate polishing apparatus according to a fourth embodiment of the present invention. FIG. 11 is a schematic sectional view of a substrate polishing apparatus according to a fifth embodiment of the present invention. FIG. 13 is a schematic sectional view of a substrate polishing apparatus according to a sixth embodiment of the present invention. It is a mimetic diagram showing the structure of the polish pad in the polish device of the substrate concerning a 6th embodiment of the present invention. FIG. 3 is a schematic sectional view of a conventional substrate polishing apparatus. It is a schematic diagram which shows the conventional polishing slurry. (A)-(c) is sectional drawing which shows each process of the conventional polishing method of the board | substrate.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 10 Polishing slurry 11 Water 12 Abrasives 13 Oxidant 14 Metal ion 20 Surface plate 21 Polishing pad 23 Polishing slurry supply tube 24 Substrate to be polished 25 Substrate holding head 26 DC voltage source 27 Ammeter 30 Silicon wafer 31 Insulating film 31a Convex part Reference Signs List 32 barrier layer 33 copper film 35 insulator 41 narrow wiring concave groove 42 wide wiring concave groove 43 plating layer 45 narrow embedded wiring 46 wide embedded wiring 51 conductor 52 roller member 52a roller 52b roller holder 53 Insulating film 54 Conductive film 55 Sheet-like body 56 Conductive particles

Claims (6)

(A) forming a concave groove in an insulating film formed on a semiconductor substrate;
(B) forming a metal layer on the barrier layer so as to fill the concave groove after forming a barrier layer on the insulating film;
Forming a buried wiring in the concave groove by performing chemical mechanical polishing and electrolytic plating on the metal film in parallel, and (c) forming a buried wiring.   In the step (c), the metal film on the convex portion of the insulating film is removed by the chemical mechanical polishing, and the surface of the metal film formed in the concave groove has a metal constituting the metal film. 2. The method according to claim 1, wherein a plating layer made of ions of the same kind of metal as above is grown.   In the step (c), the electrolytic plating is started when the thickness of the metal film on the convex portion of the insulating film is within the range of 80 to 10% of the initial film thickness by the chemical mechanical polishing. The method for forming a buried wiring according to claim 1, wherein:   In the step (c), the electrolytic plating is started when the thickness of the metal film on the convex portion of the insulating film is 80% or more of an initial film thickness by the chemical mechanical polishing. Item 3. The method for forming an embedded wiring according to Item 1 or 2.   5. The embedded wiring according to claim 1, wherein in the step (b), after depositing the metal film on the barrier layer, a heat treatment is performed on the metal film. 6. Formation method.   The method according to claim 1, wherein the metal film is a copper film.

Images