JP2021160170A - Printing device - Google Patents

Abstract

To provide a printing device that can appropriately adjust driving voltages in accordance with degrees of voltage drop, so as to prevent density unevenness from occurring in a printed image.SOLUTION: A printing device 1 comprises: a plurality of power-supply circuits 21-25 having different driving voltages preset therein, a head 11 having a plurality of nozzles 11a, and a controller 51 that adjusts the driving voltages of the plurality of power supply circuits 21-25. Any of the plurality of power-supply circuits 21-25 is associated with each of the plurality of nozzles 11a. For each of the plurality of power-supply circuits 21-25, the controller 51 boosts adjustment voltages for adjusting the driving voltages of the power-supply circuits more as the number of discharge nozzles, nozzles that are associated with the power-supply circuits and should eject liquid increases.SELECTED DRAWING: Figure 7

Description

The present invention relates to a printing apparatus that ejects a liquid such as ink from a nozzle and prints it on a recording medium such as paper.

A plurality of flow paths communicating with a plurality of nozzles, a plurality of drive elements provided corresponding to the plurality of flow paths to apply discharge energy to the liquid in the plurality of flow paths, and a drive voltage for the plurality of drive elements. A printing device including a plurality of power supply circuits for applying a voltage is known. The drive voltages of the plurality of power supply circuits are different from each other. In this printing apparatus, a plurality of nozzles are divided into a plurality of groups in advance based on the ejection characteristics of each nozzle, and an optimum power supply circuit is assigned to each group (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2017-177572

However, in each power supply circuit of the printing apparatus, when the number of nozzles to discharge the liquid is large among the plurality of nozzles included in the assigned nozzle group, the number of nozzles to discharge the liquid is small as compared with the case where the number of nozzles to discharge the liquid is small. Since the load fluctuation becomes large, a voltage lower than the drive voltage is output. For this reason, there is a problem that the discharge amount of the liquid discharged from each nozzle is smaller than the discharge amount that should be originally discharged, and density unevenness is likely to occur in the printed image.

An object of the present invention is to provide a printing apparatus capable of appropriately adjusting a drive voltage according to the magnitude of a voltage drop and less likely to cause density unevenness in a printed image.

According to the aspect of the present invention, there is a plurality of power supply circuits in which different drive voltages are preset and a head having a plurality of nozzles, and each of the plurality of nozzles has one of the plurality of power supply circuits. A head associated with the head and a controller for adjusting the drive voltage of the plurality of power supply circuits are provided, and the controller is associated with the power supply circuit and discharges liquid for each of the plurality of power supply circuits. As the number of discharge nozzles, which are power nozzles, increases, a printing device that increases the adjustment voltage for adjusting the drive voltage of the power supply circuit is provided.

According to the aspect of the present invention, for each of the plurality of power supply circuits, the controller increases the adjustment voltage of the power supply circuit as the number of discharge nozzles increases. Therefore, the drive voltage of each power supply circuit can be appropriately adjusted according to the magnitude of the voltage drop, and it is possible to suppress the occurrence of density unevenness in the printed image.

It is a top view which shows an example of the main part structure of the printing apparatus of this embodiment. It is a bottom view which shows an example of the head of this embodiment. It is a block diagram which shows an example of the structure of the 2nd board provided in the head of this embodiment, and the flexible circuit board connected to the 2nd board. It is a figure which shows an example of the circuit structure which a driver IC has. It is a circuit diagram which shows an example of the structure of the waveform generation circuit provided in the head of this embodiment. It is a figure which shows the outline of the printing flow of this embodiment. It is a table which shows an example of the adjustment voltage of each power supply circuit at a certain discharge timing. It is a table corresponding to FIG. 7 in the modification 1. It is a table corresponding to FIG. 7 in the modification 2. In the table corresponding to FIG. 7 in the modified example 3, (a) shows the earlier discharge timing of the two consecutive discharge timings, and (b) shows the later discharge timing of the two consecutive discharge timings. It is a table which shows an example of the adjustment voltage at the time of adjusting the drive voltage before the printing process in the printing apparatus of modification 4.

Hereinafter, the printing apparatus according to the embodiment of the present invention will be described with reference to FIGS. 1 to 7.

In FIG. 1, the upstream side in the transport direction of the sheet P is defined as the front side of the printing device 1, and the downstream side in the transport direction is defined as the rear side of the printing device 1. Further, a direction parallel to the surface to which the sheet P is conveyed (a surface parallel to the paper surface of FIG. 1) and orthogonal to the conveying direction is defined as a sheet width direction. The left side of the figure is the left side of the printing device 1, and the right side of the figure is the right side of the printing device 1. Further, the direction orthogonal to the transport surface of the sheet P (the direction orthogonal to the paper surface of FIG. 1) is defined as the vertical direction of the printing apparatus 1. In FIG. 1, the front side of the paper surface is the upper side, and the back side of the paper surface is the lower side. In the following, the front, back, left, right, top and bottom will be described as appropriate.

As shown in FIG. 1, the printing apparatus 1 includes a housing 2, a platen 3, four line heads 4, two transport rollers 5A and 5B, and a control device 7.

The platen 3 is placed flat in the housing 2. A sheet P is placed on the upper surface of the platen 3. The four line heads 4 are arranged side by side in the front-rear direction above the platen 3. The two transfer rollers 5A and 5B are arranged on the front side and the rear side of the platen 3, respectively. The two transfer rollers 5A and 5B are each driven by a motor (not shown) to transfer the seat P on the platen 3 to the rear. In the present embodiment, the configuration includes four line heads 4, but the number of line heads 4 is not limited to four.

As shown in FIG. 3, the control device 7 includes a first substrate 71. In addition to the FPGA (Field Programmable Gate Array) 711, the first substrate 71 includes a ROM (Read Only Memory) (not shown), a RAM (Random Access Memory) (not shown), an EEPROM (Electrically Erasable Programmable Read-Only Memory) 712, and the like. To be equipped. The control device 7 can communicate with an external device 9 such as a personal computer. The control device 7 controls the operations of the line heads 4 and the transfer rollers 5A and 5B according to a program stored in the ROM according to an instruction from an operation unit (not shown) included in the external device 9 or the printing device 1. A CPU (Central Processing Unit) or an MPU (Microprocessor Unit) may be used instead of the FPGA 711.

For example, the control device 7 controls the motors that drive the transfer rollers 5A and 5B, and causes the transfer rollers 5A and 5B to transfer the sheet P in the transfer direction. Further, the control device 7 controls each line head 4 to eject ink toward the sheet P. As a result, the image is printed on the sheet P. The sheet P may be a roll-shaped sheet including a supply roll including the upstream end in the transport direction and a recovery roll including the downstream end in the transport direction. In this case, the supply roll may be attached to the transfer roller 5A on the upstream side in the transfer direction, and the recovery roll may be attached to the transfer roller 5B on the downstream side in the transfer direction. Alternatively, the sheet P may be a roll-shaped sheet containing only the supply roll including the upstream end in the transport direction. In this case, the supply roll may be attached to the transport roller 5A on the upstream side in the transport direction.

Four head holding portions 8 are attached to the housing 2 corresponding to the four line heads 4. The four head holding portions 8 are arranged side by side in front of and behind the platen 3 and at positions between the transport rollers 5A and 5B. One line head 4 is held by each head holding portion 8.

The four line heads 4 eject four colors of ink, cyan (C), magenta (M), yellow (Y), and black (K), respectively. A corresponding one-color ink is supplied to each line head 4 from an ink tank (not shown).

As shown in FIG. 2, each line head 4 of the present embodiment includes nine heads 11. The nine heads 11 are arranged in two rows in a staggered manner along the seat width direction. Since one color of ink is supplied to one line head 4, the nine heads 11 included in the one line head 4 eject the one color of ink. In the present embodiment, the line head 4 includes nine heads 11, but the number of heads 11 is not limited to nine.

1680 nozzles 11a are opened on the bottom surface of each head 11 of the present embodiment, and the 1680 nozzles 11a form a plurality of nozzle rows arranged in the seat width direction. That is, the head 11 has a plurality of nozzles 11a. Each nozzle row is formed by a plurality of nozzles 11a arranged in the transport direction. In the present embodiment, each head 11 is provided with 1680 nozzles 11a, but the number of nozzles 11a is not limited to 1680.

Further, each head 11 is provided with the same number of drive elements 111 (described later) as the nozzles 11a, a second substrate 50, and a flexible circuit board 60. Since the printing apparatus 1 of the present embodiment includes four line heads 4, and each line head 4 includes nine heads 11, the printing apparatus 1 includes 36 heads 11. Therefore, the number of the second substrate 50 is 36, and the number of the flexible circuit boards 60 connected to the second substrate 50 is also 36. As shown in FIG. 3, the first substrate 71 of the control device 7 is connected to 36 second substrates 50. Note that FIG. 3 shows only one second substrate 50 and one flexible circuit board 60 for convenience.

The second substrate 50 includes an FPGA 51 as a controller, a non-volatile memory 52 such as EEPROM, a D / A converter 20, power supply circuits 21 to 26, and the like. In the present embodiment, the second substrate 50 includes six power supply circuits 21 to 26, but the number of power supply circuits is not limited to six. Further, the flexible circuit board 60 includes a non-volatile memory 62 such as EEPROM, a driver IC 27, and the like.

The FPGA 51 outputs a digital setting signal for setting the drive voltage of the power supply circuits 21 to 26 to the D / A converter 20 under the control of the FPGA 711 provided on the first substrate 71.

The D / A converter 20 converts the digital setting signal output by the FPGA 51 into an analog setting signal and outputs it to the power supply circuits 21 to 26.

The power supply circuits 21 to 26 can be, for example, a DC / DC converter composed of a plurality of electronic components such as FETs, inductors, resistors, and electrolytic capacitors. Each power supply circuit 21 to 26 outputs the drive voltage specified by the set signal to the driver IC 27. That is, the FPGA 51 adjusts the drive voltage of each power supply circuit 21 to 26. In the present embodiment, different drive voltages are preset in the power supply circuits 21 to 26.

The driver IC 27 is connected to the power supply circuit 21 via the wiring VDD1, is connected to the power supply circuit 22 via the wiring VDD2, is connected to the power supply circuit 23 via the wiring VDD3, and is connected to the power supply circuit 24 via the wiring VDD4. It is connected to the power supply circuit 25 via the wiring VDD5, and is connected to the power supply circuit 26 via the wiring H VDD. The power supply circuit 26 is connected to a drive element 111, which will be described later, via a wiring VCOM. In the wiring H VDD and the wiring VCOM, the wiring drawn from the power supply circuit 26 is branched into two wirings in the middle of the route.

The power supply circuits 21 to 26 are a waveform generation circuit 30 (1) to a waveform generation circuit 30 (n) (n is a natural number of 2 or more) formed inside the driver IC 27, and in the present embodiment, the drive included in the head 11 is provided. It is connected to the number of elements 111, that is, equal to 1680).

The waveform generation circuits 30 (1) to 30 (n) are provided corresponding to the n drive elements 111 included in each head 11. That is, the waveform generation circuits 30 (1) to 30 (n) are provided corresponding to the n nozzles 11a provided in each head 11. The driver IC 27 is connected to n signal lines 34 (1) to 34 (n). The driver IC 27 is connected to n drive elements 111 via n signal lines 34 (1) to 34 (n). Each signal line 34 is connected to an individual electrode of the driving element 111.

Further, the driver IC 27 includes n selectors 90 (1) to 90 (n) provided corresponding to the n drive elements 111. Each selector 90 is a hardware component composed of a plurality of FETs and the like formed inside the driver IC 27.

The power supply circuit 26 can be used as the VCOM power supply voltage of the drive element 111 or as the H VDD (high side back gate voltage) of the MPa transistors 31 to 315 described later.

The non-volatile memory 62 stores a nozzle ID or the like that identifies each nozzle 11a. Further, the non-volatile memory 52 stores, for example, the correspondence between the n nozzles 11a and the five power supply circuits 21 to 25. That is, any of the plurality of power supply circuits 21 to 25 is associated with each of the plurality of nozzles 11a. Note that these correspondences may be stored in the non-volatile memory 62 provided on the flexible circuit board 60 instead of the non-volatile memory 52.

Further, the driver IC 27 is connected to the FPGA 51 via n control lines 33 (1) to 33 (n) and a control line 40. The control lines 33 (1) to 33 (n) are control lines provided corresponding to the above-mentioned n waveform generation circuits 30 (1) to 30 (n). A signal for controlling the FET provided in each waveform generation circuit 30 is propagated to each control line 33. According to this signal, the waveform generation circuit 30 generates a drive signal for driving the drive element 111, and outputs the generated drive signal to the drive element 111 via the signal line 34.

Further, control signals for controlling n selectors 90 (1) to 90 (n) included in the driver IC 27 are transmitted to the control line 40. The FPGA 51 selects a power supply circuit for generating a drive signal to be output to each signal line 34 by controlling n selectors 90 (1) to 90 (n).

Next, an example of the circuit configuration included in the driver IC 27 will be described with reference to FIG. As shown in FIG. 4, the driver IC 27 is provided corresponding to n waveform generation circuits 30 (1) to 30 (n) and waveform generation circuits 30 (1) to 30 (n), respectively. The selector 90 (1) to 90 (n) is provided.

The driver IC 27 has n circuit configurations, which is the same as the number of nozzles. Since the n circuit configurations have the same configuration, the circuit configurations provided between the control line 33 (1) and the signal line 34 (1) will be described below. In the driver IC 27, a selector 90 (1) and a waveform generation circuit 30 (1) are formed between the control line 33 (1) and the signal line 34 (1).

The control line 33 (1) from the FPGA 51 is connected to the selector 90 (1). The control line 33 (1) is branched in the middle of the path connecting the FPGA 51 and the selector 90 (1), and the control line SB (1) branched from the control line 33 (1) is connected to the waveform generation circuit 30 (1). It is connected.

The selector 90 (1) and the waveform generation circuit 30 (1) are connected by five control lines S1 (1), S2 (1), S3 (1), S4 (1), and S5 (1). There is. The selector 90 (1) is selected from the five control lines S1 (1), S2 (1), S3 (1), S4 (1), and S5 (1) according to the instruction from the FPGA 51. One control line is connected to the control line 33 (1).

In the waveform generation circuit 30 (1), five wirings connected to the above-mentioned wirings VDD1 to VDD5, a wiring connected to the wiring H VDD, and a wiring connected to the wiring GND are connected.

Next, an example of the configuration of the waveform generation circuits 30 (1) to 30 (n) included in the head 11 of the present embodiment will be described with reference to FIG. Since the waveform generation circuits 30 (1) to 30 (n) have the same configuration, the waveform generation circuit 30 (1) will be described below. The waveform generation circuit 30 (1) includes five ProLiant (P-type Metal Oxide Semiconductor) transistors 31 to 315 (only two are shown in FIG. 5) and one NMOS (N-type Metal Oxide Semiconductor) transistor 32. , Resistance 35 and the like. The waveform generation circuit 30 (1) is connected to the individual electrodes of the drive element 111 via the signal line 34 (1).

The drive element 111 of the present embodiment has, for one pressure chamber, between the first active portion sandwiched between the individual electrode and the first constant potential electrode, and between the individual electrode and the second constant potential electrode. It is a piezoelectric element including a second active portion sandwiched between the two. Therefore, the drive element 111 includes a capacitor 111b and a capacitor 111b'.

Wiring VDD1 to VDD5 are connected to the five source terminals 311a to 315a of the five MPa transistors 31 to 315, respectively. The source terminal 32a of the NMOS transistor 32 is connected to the ground. That is, the epitaxial transistor 311 is connected to the power supply circuit 21 via the wiring VDD1. The epitaxial transistor 312 is connected to the power supply circuit 22 via the wiring VDD2. The epitaxial transistor 313 is connected to the power supply circuit 23 via the wiring VDD3. The epitaxial transistor 314 is connected to the power supply circuit 24 via the wiring VDD4. The epitaxial transistor 315 is connected to the power supply circuit 25 via the wiring VDD5.

A control line S1 (1) is connected to the gate terminal 311c of the epitaxial transistor 311. A control line S2 (1) is connected to the gate terminal 312c of the epitaxial transistor 312. A control line S3 (1) is connected to the gate terminal 313c of the epitaxial transistor 313. A control line S4 (1) is connected to the gate terminal 314c of the epitaxial transistor 314. A control line S5 (1) is connected to the gate terminal 315c of the epitaxial transistor 315. Further, a control line SB (1) is connected to the gate terminal 32c of the NMOS transistor 32.

Further, the drain terminals 311b to 315b of the five MIMO transistors 31 to 315 are connected to one end of the resistor 35. Further, the drain terminal 32b of the NMOS transistor 32 is connected to one end of the resistor 35. The other end of the resistor 35 is connected to the individual electrodes of the drive element 111 (the other end of the capacitor 111b'and one end of the capacitor 111b). The first constant potential electrode of the drive element 111 (one end of the capacitor 111b') is connected to the VCOM, and the second constant potential electrode of the drive element 111 (the other end of the capacitor 111b) is connected to the ground.

When the FPGA 51 outputs a low level (“L”) signal to the control line 33 (1), any one of the epitaxial transistors 31 to 315 connected to the signal line selected by the selector 90 (1) described above. One polyclonal transistor is turned on. The capacitor 111b is charged by the voltage supplied from any one of the power supply circuits 21 to 25, and the capacitor 111b'is discharged. On the other hand, when the FPGA 51 outputs a high level (“H”) signal to the control line 33 (1), the NMOS transistor 32 is turned on and the voltage output from any one of the power supply circuits 21 to 25. Charges the capacitor 111b'and discharges the capacitor 111b. By alternately charging and discharging the capacitors 111b and 111b', the driving element 111 is deformed and ink is discharged from the ejection port 11a of the nozzle.

That is, a drive signal for driving the drive element 111 is output to the signal line 34 (1). The power supply circuit that generates a drive signal by selecting one control line to be connected from the five control lines S1 (1) to S5 (1) by the selector 90 (1) is included in the power supply circuits 21 to 25. You can choose from.

Next, the flow of printing using the printing apparatus 1 of the present embodiment will be described with reference to FIG. In the present embodiment, first, print data is generated by the external device 9 (step S1). Then, the generated print data is transmitted from the external device 9 to the printing device 1 (step S2). When the printing device 1 receives the print data transmitted from the external device 9 (step S3), the printing device 1 analyzes the received print data (step S4), and executes a printing process based on the analyzed result (step S5). Then, when the printing process is completed, a series of printing flows is completed.

In the printing apparatus 1 of the present embodiment, any of the five power supply circuits 21 to 25 is assigned in advance to each nozzle 11a according to the ejection characteristics of the nozzle 11a. In this embodiment, five power supply circuits 21 to 25 are provided for 1680 nozzles 11a. Therefore, as shown in FIG. 7, a plurality of nozzles 11a are pre-assigned to each of the five power supply circuits 21 to 25. In FIG. 7, VDD1 to VDD5 mean power supply circuits 21 to 25, respectively. That is, 160 nozzles 11a are assigned to the power supply circuit 21, 320 nozzles 11a are assigned to the power supply circuit 22, and 720 nozzles 11a are assigned to the power supply circuit 23. The power supply circuit 24 is assigned 320 nozzles 11a, and the power supply circuit 25 is assigned 160 nozzles 11a. Then, these correspondences are stored in, for example, the non-volatile memory 52 of the second substrate 50. Further, the number of nozzles 11a assigned to the power supply circuits 21 to 25 described above is only an example, and can be appropriately changed according to the discharge characteristics of each nozzle 11a.

Then, in the printing apparatus 1 of the present embodiment, the drive voltages of the five power supply circuits 21 to 25 are also preset as shown in FIG. That is, the drive voltage of the power supply circuit 21 is 23.8 V, the drive voltage of the power supply circuit 22 is 23.5 V, the drive voltage of the power supply circuit 23 is 23.6 V, the drive voltage of the power supply circuit 24 is 23.7 V, and the drive voltage of the power supply circuit 25. The drive voltage is set to 23.8V. The above-mentioned drive voltage value is only an example, and the drive voltage value of each power supply circuit can be changed as appropriate.

Here, the inventor of the present invention includes a case where one drop of ink is ejected from one nozzle using one power supply circuit in which the drive voltage is set to 31 V, and one nozzle thereof. We actually measured how the drive voltage of the power supply circuit changes when 560 drops of ink are ejected from 560 nozzles at the same time. As a result, when one drop of ink was ejected from one nozzle, the voltage drop of the drive voltage was 0 V, whereas when 560 drops of ink were ejected from 560 nozzles at the same time, the drive voltage was reduced. The voltage drop of was about 1V. Here, it is known that the voltage drop (y) of the drive voltage is proportional to the product (x) of the magnitude of the drive voltage and the number of discharge nozzles. From this, the values (17360 (= 31 × 560), 1) and (31 (= 31 × 1), 0) obtained by actual measurement are substituted into the linear equation y = ax + b as (x, y), respectively. By doing so, the coefficients a and b were calculated. As a result, the value of the coefficient a was 5.771 × 10 ^-5 , and the value of the coefficient b was -1.789 × 10 ^-3 . That is, the voltage drop could be expressed by the following equation (1).
5.771 x ^10-5 x (drive voltage x number of discharge nozzles) -1.789 x 10 ^-3 (1)

Therefore, in the present embodiment, at each discharge timing, the voltage drop is calculated by substituting the drive voltage and the number of discharge nozzles set in the power supply circuit for each of the power supply circuits 21 to 25 into the above equation. Then, in order to compensate for the voltage drop, a voltage of almost the same amount as the voltage drop is set as the adjustment voltage. For example, in FIG. 7, the power supply circuit 21 has a drive voltage set to 23.8 V, and 160 nozzles 11a are assigned to it. Then, when it is necessary to discharge from 100 nozzles 11a at a certain discharge timing, the voltage drop of the power supply circuit 21 is about 0.1 V (5.771 × ^10-5 × (23.8) from the above equation (1). × 100) -1.789 × 10 ^-3 ). Therefore, the adjustment voltage for compensating for the voltage drop of the power supply circuit 21 is set to 0.1V. That is, at this discharge timing, the drive voltage of the power supply circuit 21 is adjusted to 23.8V + 0.1V = 23.9V. By the same calculation, the adjustment voltages of the power supply circuits 22 to 25 are 0.1V, 0.5V, 0.3V, and 0.0V, respectively, so that the drive voltages of the power supply circuits 22 to 25 are 23.6V, respectively. It is adjusted to 24.1V, 24.0V, and 23.8V. That is, in the FPGA 51, as the number of discharge nozzles 11a, which are nozzles for discharging liquid, increases, the adjustment voltage for adjusting the drive voltage of each power supply circuit 21 to 25 increases.

As described above, the voltage drop (y) in the power supply circuit is proportional to the product (x) of the magnitude of the drive voltage and the number of discharge nozzles. Therefore, when the number of discharge nozzles is the same, the voltage drop of the drive voltage is , Proportional to the magnitude of the drive voltage. Therefore, for example, when the number of discharge nozzles of the power supply circuit 21 and the power supply circuit 22 is the same at a certain discharge timing, the voltage drop of the power supply circuit 21 having a high drive voltage is larger than that of the power supply circuit 22 having a low drive voltage. Therefore, according to the present embodiment, the adjustment voltage of the power supply circuit 21 becomes larger than the adjustment voltage of the power supply circuit 22 at this discharge timing.

According to the present embodiment, at each discharge timing, the drive voltage of each of the power supply circuits 21 to 25 is adjusted by the adjustment voltage based on the product of the number of discharge nozzles and the drive voltage. Therefore, the drive voltage can be appropriately adjusted according to the magnitude of the voltage drop, and it is possible to suppress the occurrence of density unevenness in the printed image.

Next, a modified example of the above embodiment will be described. In the above embodiment, the drive voltage of the power supply circuits 21 to 25 is adjusted at each discharge timing, but the timing for adjusting the drive voltage is not limited to this.

For example, as shown in FIG. 8, the drive voltage of the power supply circuits 21 to 25 may be adjusted only at the timing of ejecting ink from all 1680 nozzles 11a (modification example 1). In this case, in the power supply circuit 21, the value of the number of ejection nozzles × the drive voltage is 2380. By substituting this value into the above equation (1), the voltage drop of the power supply circuit 21 is calculated to be about 0.2V. Therefore, the drive voltage of the power supply circuit 21 is adjusted to 23.8V + 0.2V = 24.0V. Similarly, the voltage drops of the power supply circuits 22 to 25 are calculated to be about 0.4V, about 1.0V, about 0.4V, and about 0.2V, respectively, so that the drive voltages of the power supply circuits 22 to 25 are respectively calculated. It is adjusted to 23.9V, 24.6V, 24.1V, and 24.0V. That is, the FPGA 51 adjusts the drive voltage by applying an adjustment voltage to each of the power supply circuits 21 to 25 at the ejection timing for ejecting ink from all of the plurality of nozzles 11a.

Since the voltage drop in each power supply circuit is proportional to the product of the number of discharge nozzles and the drive voltage, the voltage drop increases as the number of discharge nozzles increases. Therefore, at the ejection timing in which ink is ejected from all the nozzles assigned to each power supply circuit, the voltage drop in each power supply circuit becomes the largest. In the first modification, the FPGA 51 adjusts the drive voltage by applying an adjustment voltage to each of the power supply circuits 21 to 25 only at the timing of ejecting ink from all 1680 nozzles 11a. Therefore, the drive voltage can be appropriately adjusted at the timing when the voltage drop of each power supply circuit becomes the largest, and it is possible to suppress the occurrence of density unevenness in the printed image.

Alternatively, at each discharge timing, the drive voltage may be adjusted only for the power supply circuit in which the value of the voltage drop calculated by the above equation (1) is equal to or higher than a predetermined value (modification example 2). For example, at the discharge timing as shown in FIG. 9, the voltage drops of the power supply circuits 21 to 25 are calculated to be about 0.1V, about 0.4V, about 1.0V, about 0.1V, and about 0.0V, respectively. Will be done. Therefore, for example, the drive voltage is adjusted only for the power supply circuit 22 and the power supply circuit 23 whose voltage drop value is 0.4 V (an example of the first threshold value) or more, and the voltage drop value is less than 0.4. The drive voltage may be used as it is for a certain power supply circuit 21, power supply circuit 24, and power supply circuit 25. In this case, the drive voltages of the power supply circuit 22 and the power supply circuit 23 are adjusted to 23.9 V and 24.6 V, respectively, and the drive voltages of the power supply circuit 21, the power supply circuit 24, and the power supply circuit 25 are 23.8 V and 23. It is maintained at 7V and 23.8V. That is, the FPGA 51 adjusts the drive voltage of each of the power supply circuits 21 to 25 by applying an adjustment voltage at the discharge timing at which the value of the voltage drop becomes equal to or higher than the first threshold value.

According to the second modification, the drive voltage of each power supply circuit is adjusted at the discharge timing when the voltage drop becomes remarkable. That is, the drive voltage is surely adjusted at the timing when the number of discharge nozzles is equal to or more than a predetermined number and the density unevenness due to the voltage drop is likely to occur. Therefore, it is possible to efficiently suppress the occurrence of density unevenness in the printed image.

Alternatively, the drive voltage may be adjusted only for the power supply circuit in which the absolute value of the difference between the voltage drops at the two consecutive discharge timings is equal to or greater than a predetermined value (modification example 3). For example, at the discharge timing shown in FIG. 10A, the voltage drops of the power supply circuits 21 to 25 are about 0.1V, about 0.4V, about 1.0V, about 0.1V, and about 0.0V, respectively. It is calculated. On the other hand, at the discharge timing of FIG. 10B which is continuous after the discharge timing of FIG. 10A, the voltage drops of the power supply circuits 21 to 25 are about 0.2V, about 0.0V, and about 0.1V, respectively. It is calculated to be about 0.4V and about 0.1V. Therefore, the difference between the voltage drop of the power supply circuits 21 to 25 at the discharge timing of FIG. 10A and the discharge timing of FIG. 10B is + 0.1V, −0.4V, −0.9V, and + 0.3V, respectively. , + 0.1V. Therefore, at the discharge timing of FIG. 10B, for example, the drive voltage of the power supply circuit 22, the power supply circuit 23, and the power supply circuit 24 in which the absolute value of the difference in voltage drop is 0.2 V (an example of the second threshold value) or more. It is not necessary to adjust the drive voltage of the power supply circuit 21 and the power supply circuit 25 in which the absolute value of the difference in voltage drop is less than 0.2 V. That is, in the FPGA 51, for each of the power supply circuits 21 to 25, the first voltage drop at the discharge timing shown in FIG. 10 (a) and the discharge timing of FIG. 10 (a) are followed by the continuous voltage drop in FIG. 10 (b). When the second voltage drop at the discharge timing is calculated and the absolute value of the difference between the first voltage drop and the second voltage drop is equal to or greater than the second threshold value, the discharge timing in FIG. 10B shows. The drive voltage is adjusted by applying an adjustment voltage corresponding to the second voltage drop.

According to the third modification, the drive voltage is adjusted at the discharge timing at which the voltage drop changes significantly, that is, at the discharge timing at which the number of discharge nozzles greatly changes. Therefore, the drive voltage can be appropriately adjusted at the timing when the density unevenness is likely to occur in the printed image, and the density unevenness in the printed image can be reliably and efficiently suppressed.

In the above-described embodiment and modification, the drive voltage of each power supply circuit is adjusted during the printing process (step S5 in FIG. 6), but the present invention is not limited to this. In addition to the adjustment of the drive voltage performed during printing, the drive voltage may be adjusted before the printing process is executed (modification example 4). Specifically, the drive voltage is adjusted based on the usage period (days) of each power supply circuit stored in the non-volatile memory 52 or 62 and the cumulative number of discharge nozzles (total discharge number) in the usage period. .. For example, at a time prior to executing the printing process, the product of the total number of ejections and used number of days, of less than 5000000 × 10 ^6, of less than 5000000 × 10 ⁶ or more ^{10000000 × 10 6, 10000000 × 10} 6 or more 20000000 × If it is less than 10 ^6, respectively in the case of 20000000 × 10 ⁶ or more, the adjustment voltage 0V, 0.1 V, 0.2V, previously determined to 0.3V. As shown in FIG. 11, when used for 1825 days, the total number of discharges of the power supply circuits 21 to 25 is 2610 × 10 ⁶ , 4320 × 10 ⁶ , 6480 × 10 ⁶ , 3240 × 10 ⁶ , 1080 × 10, respectively. ^{Assuming that it was 6} , the products of the total number of discharges and the number of days of use are 4763250 × 10 ⁶ , 7884000 × 10 ⁶ , 11826000 × 10 ⁶ , 5913000 × 10 ⁶ , and 1971000 × 10 ⁶ , respectively. Therefore, for the power supply circuit 21 and the power supply circuit 25 the product of the total number of ejections and use of days is less than 5000000 × 10 ^6, the adjustment voltage and 0V. The power supply circuit 22 and the power supply circuit 24 the product is 10000000 × 10 than ⁶ 5000000 × 10 ⁶ or more total discharge number and use the number of days, the regulated voltage and 0.1 V. Then, the product of the total number of ejections and using the number of days for the power supply circuit 23 is less than 10000000 × 10 ⁶ or more 20000000 × 10 ^6, the adjustment voltage and 0.2V.

Generally, as the usage period becomes longer, the capacity of the electrolytic capacitor included in each power supply circuit decreases, so that the load fluctuation becomes larger. In the fourth modification, the drive voltage of each power supply circuit is increased as the usage period becomes longer, so that the drive voltage can be appropriately set according to the usage period of each power supply circuit before the printing process is executed.

In the above-described embodiment and the above-described modification, the printing apparatus 1 prints on the sheet P by a so-called line head method in which ink is ejected from a line head 4 which is fixed to the printing apparatus 1 and is long in the sheet width direction. However, the printing device 1 may print on the sheet P by a so-called serial head method in which the head 11 is moved in the sheet width direction by a carriage.

In the above-described embodiment and modification, the line head 4 is fixed to the printing apparatus 1 and the sheet P is conveyed, but the sheet P may be relatively moved with respect to the line head 4, for example, fixed. The line head 4 may be configured to move with respect to the printed sheet P.

1 Printing device 4 Line head 5A, 5B Conveyor roller 7 Control device 11 Head 11a Nozzle 21-26 Power supply circuit 27 Driver IC
50 2nd board 51 FPGA
52 Non-volatile memory 60 Flexible circuit board 62 Non-volatile memory 71 First board 711 FPGA
712 EEPROM

Claims (8)

Multiple power supply circuits with different drive voltages preset
A head having a plurality of nozzles, each of which is associated with any of the plurality of power supply circuits.
A controller for adjusting the drive voltage of the plurality of power supply circuits is provided.
The controller adjusts each of the plurality of power supply circuits for adjusting the drive voltage of the power supply circuit as the number of discharge nozzles associated with the power supply circuit and which are nozzles for discharging liquid increases. A printing device that increases the voltage. The plurality of power supply circuits include a first power supply circuit and a second power supply circuit having a drive voltage higher than that of the first power supply circuit.
At a certain discharge timing, when the number of the discharge nozzles is the same in the first power supply circuit and the second power supply circuit, the controller uses the adjustment voltage of the second power supply circuit as the first power supply. The printing apparatus according to claim 1, wherein the voltage is made larger than the adjusted voltage of the circuit. According to claim 1 or 2, the controller adjusts the drive voltage by applying the adjustment voltage to each of the plurality of power supply circuits at the discharge timing for discharging the liquid from all of the plurality of nozzles. The printing device described. The printing apparatus according to claim 1 or 2, wherein the controller adjusts the drive voltage by applying the adjustment voltage at the discharge timing at which the voltage drop becomes equal to or higher than the first threshold value for each of the plurality of power supply circuits. .. The controller is used for each of the plurality of power supply circuits.
The first voltage drop at the first discharge timing and the second voltage drop at the second discharge timing following the first discharge timing are calculated.
A claim for adjusting the drive voltage by applying the adjustment voltage at the second discharge timing when the absolute value of the difference between the first voltage drop and the second voltage drop is equal to or greater than the second threshold value. Item 2. The printing apparatus according to item 1 or 2. For each of the plurality of power supply circuits, a memory for storing the usage period and the total number of discharges, which is the cumulative number of the discharge nozzles in the usage period, is further provided.
The controller further adjusts the drive voltage for each of the plurality of power supply circuits according to the product of the total number of discharges stored in the memory and the usage period. The printing apparatus according to paragraph 1. The printing apparatus according to claim 4 or 5, wherein the adjusted voltage is equal to the voltage drop. The printing apparatus according to claim 7, wherein the voltage drop is calculated based on the product of the number of ejection nozzles and the value of the driving voltage.

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