JP2020104389A - Method, arithmetic device, head device, and head unit - Google Patents

Abstract

To provide a method and the like for restricting an increase of circuits for applying voltage to a nozzle.SOLUTION: In a method according to the present invention, a voltage value X(k) of the k-th rank is read through a first interface, from a first storage part which stores the first rank to the n-th rank assigned to a first head, and a plurality of voltage values assigned to each rank, and a voltage value Y(k) of the k-th rank is read through a second interface, from a second storage part which stores the first rank to the n-th rank assigned to a second head, and a plurality of voltage values assigned to each rank, in order to determine a magnitude of the approximation between the read voltage value X(k) and the read voltage value Y(k). Further, in the method, if the approximation is determined to be close, an average voltage value Axy(k) of the voltage value X(k) and the voltage value Y(k) is computed, in order to update the voltage value X(k) stored in the first storage part to the computed average voltage value Axy(k), and to update the voltage value Y(k) stored in the second storage part to the computed average voltage value Axy(k).SELECTED DRAWING: Figure 2

Description

The present technology relates to a method of setting a voltage applied to a nozzle that ejects a liquid, a computing device, a head device, and a head unit.

Conventionally, an inkjet recording apparatus including a plurality of heads having two nozzle rows has been proposed. The inkjet recording device includes a voltage conversion unit corresponding to each nozzle row, adjusts the voltage by the voltage conversion unit, and applies the adjusted voltage to each nozzle row (see, for example, Patent Document 1).

JP, 2009-83296, A

The inkjet recording apparatus has a voltage conversion unit for each of the plurality of nozzle rows. That is, as the number of nozzle rows of the head included in the inkjet recording apparatus increases, the number of voltage conversion units also increases.

The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a method, a computing device, a head device, and a head unit that can suppress an increase in a circuit that applies a voltage to a nozzle.

A method according to the present disclosure includes a first rank to an nth rank (n is a natural number of 2 or more) assigned to each of the plurality of first drive elements of the first head, and a plurality of voltage values assigned to each rank. From the first storage unit for storing the voltage value X(k) of the k-th rank (k is a natural number satisfying 1≦k≦n) through the first interface, and each of the plurality of second drive elements of the second head is read. From the second storage unit that stores the first rank to the nth rank assigned to each and a plurality of voltage values assigned to each rank, through the second interface, the voltage value Y(k) of the kth rank. The strength of the read-out and read-out voltage value X(k) and the read-out voltage value Y(k) is judged, and when the closeness is judged to be strong, it is judged as the voltage value X(k). , An average voltage value Axy(k) with the voltage value Y(k) is calculated, and the voltage value X(k) stored in the first storage unit is updated to the calculated average voltage value Axy(k). , And updates the voltage value Y(k) stored in the second storage unit to the calculated average voltage value Axy(k).

The arithmetic unit according to the present disclosure includes a first rank to an nth rank (n is a natural number of 2 or more) assigned to each of the plurality of first drive elements of the first head, and a plurality of voltage values assigned to each rank. From the first storage unit that stores, and through the first interface, the voltage value X(k) of the k-th rank (k is a natural number satisfying 1≦k≦n) is read and a plurality of second drive of the second head is performed. From the second storage unit that stores the first rank to the nth rank assigned to each element and the plurality of voltage values assigned to each rank, the voltage value Y( k) is read, the strength of the closeness between the read voltage value X(k) and the read voltage value Y(k) is determined, and when the closeness is determined to be strong, the voltage value X(k k) and the voltage value Y(k), an average voltage value Axy(k) is calculated, and the voltage value X(k) stored in the first storage unit is calculated through the first interface. The voltage value Axy(k) is updated, and the voltage value Y(k) stored in the second storage unit is updated to the average voltage value Axy(k) calculated through the second interface.

The head device according to the present disclosure is different from the first head in which a voltage is applied to a plurality of first drive elements arranged corresponding to a plurality of nozzles from a plurality of power supplies that output voltages of different sizes. A second head to which a voltage is applied to a plurality of second driving elements arranged corresponding to a plurality of nozzles from a plurality of power sources that output a voltage of a high voltage, and a plurality of first driving elements of the first head, respectively. First to n-th ranks (n is a natural number of 2 or more) assigned to each of the plurality of voltage values, and a plurality of voltage values assigned to each rank, and a plurality of second heads of the second head. The first rank to the nth rank assigned to each drive element, and the second storage unit that stores a plurality of voltage values assigned to each rank, and the kth rank stored in the first storage unit The voltage value X(k) of (k is a natural number) is the same as the voltage value Y(k) of the k-th rank stored in the second storage unit and the same as the voltage value X(k).

A head unit according to the present disclosure includes the head device described above and a plurality of power supplies, and the number of the plurality of power supplies is less than 2n.

In the method, the arithmetic device, the head device, and the head unit according to the present disclosure, the kth rank voltage value X(k) stored in the first storage unit and the kth rank stored in the second storage unit. If the voltage values Y(k) of 1 are approximate, the voltage values X(k) and Y(k) are updated with the average voltage value of the voltage values X(k) and Y(k). Since the voltage values X(k) and Y(k) have the same value, it is possible to reduce the number of circuits by applying a voltage to the nozzle in common.

FIG. 3 is a schematic plan view showing a printing device. FIG. 3 is a block diagram showing a power supply board, a first circuit board, a second circuit board, and the like. It is a figure which shows an example of the circuit structure with which a driver IC is equipped. It is a figure which shows an example of the circuit structure with which a driver IC is equipped. It is a circuit diagram which shows an example of a structure of a waveform generation circuit. It is a conceptual diagram which shows an example of the 1st table memorize|stored in the 1st memory|storage part and the 2nd table memorize|stored in the 2nd memory|storage part before execution of the voltage setting method. 6 is a flowchart illustrating a voltage setting method. 6 is a flowchart illustrating a voltage setting method. It is a conceptual diagram which shows an example of a synthetic|combination table. It is a conceptual diagram which shows an example of the 1st table memorize|stored in the 1st memory|storage part after execution of the voltage setting method, and the 2nd table memorize|stored in the 2nd memory|storage part. It is a conceptual diagram which shows the other example of the 1st table memorize|stored in the 1st memory|storage part and the 2nd table memorize|stored in the 2nd memory|storage part before execution of the voltage setting method. It is a conceptual diagram which shows the other example of a synthetic|combination table. It is a conceptual diagram which shows the other example of the 1st table memorize|stored in the 1st memory|storage part after execution of the voltage setting method, and the 2nd table memorize|stored in the 2nd memory|storage part. FIG. 14 is a block diagram showing a power supply board, a first circuit board, a second circuit board, and the like designed based on the first table and the second table shown in FIG. 13.

The present invention will be described below with reference to the drawings showing a printing apparatus according to an embodiment. FIG. 1 is a schematic plan view showing a printing apparatus. The printing device includes a first head 1, a second head 2, a carriage 3, and a control device 4. The carriage 3 is movable along the first direction. For example, the first direction is the left-right direction. The first head 1 and the second head 2 are arranged in a staggered manner on the carriage 3. A plurality of nozzles 11 that eject liquid, that is, ink, are formed on the lower surfaces of the first head 1 and the second head 2. A recording medium 5 such as paper or film passes below the first head 1 and the second head 2. The recording medium 5 moves along a second direction perpendicular to the first direction. For example, the second direction is the front-back direction.

Ink is ejected from the nozzles 11 toward the recording medium 5 to form an image on the recording medium 5. The carriage 3 moves to the left, for example, and stops when it reaches the left end of the recording medium 5. After the carriage 3 stops, the recording medium 5 moves forward by a predetermined distance and stops. After the recording medium 5 stops, the carriage 3 moves to the right, and stops when it moves to the right end of the recording medium 5. Ink is ejected when the carriage 3 moves in the left-right direction. An image is formed at a desired position on the recording medium 5 by repeatedly moving the carriage 3 in the left-right direction, ejecting ink when the carriage 3 is moved, and moving the recording medium 5 forward. It The control device 4 includes a power supply board 6 described later. The first head 1 includes a first circuit board 1a described below, and the second head 2 includes a second circuit board 2a described below.

The control device 4 can mutually communicate with an external device 9 such as a personal computer. The control device 4 controls the operations of the first head 1, the second head 2, and the carriage 3 according to an instruction from an operation unit (not shown) included in the external device 9 or the printing device. When a user's printing instruction is input via the external device 9 or an operation unit included in the printing device, the control device 4 transmits a printing instruction signal, raster data of an image to be printed, and the like to the power supply board 6.

FIG. 2 is a block diagram showing the power supply board 6, the first circuit board 1a, the second circuit board 2a, and the like. The power supply board 6 includes a controller 7, a memory 8 for temporarily storing raster data, a D/A converter 20, a power supply circuit 21, a power supply circuit 22, a power supply circuit 23, a power supply circuit 24, a power supply circuit 25, a power supply circuit 26, and a power supply. The circuit 27 and the like are provided. The controller 7 includes, for example, an FPGA (Field Programmable Gate Array), a CPU (Central Processing Unit), or an MPU (Microprocessor Unit).

The first circuit board 1a includes a driver IC 1b, a first storage unit 1c such as an EEPROM, and the like. The first storage unit 1c stores a first table 1d described later. The first storage unit 1c is connected to the controller 7 via the first interface 1e. The second circuit board 2a includes a driver IC 2b, a second storage unit 2c such as an EEPROM, a second interface 2e, and the like. The second storage unit 2c stores a second table 2d described later. The second storage unit 2c is connected to the controller 7 via the second interface 2e.

The controller 7 outputs a setting signal for setting the output voltage of the power supply circuit 21 to the power supply circuit 27 to the D/A converter 20. The D/A converter 20 converts the digital setting signal output from the controller 7 into an analog setting signal and outputs the analog setting signal to the power supply circuits 21 to 27.

The power supply circuit 21 to the power supply circuit 27 can be, for example, a DC/DC converter including a plurality of electronic components such as an FET, an inductor, a resistor, and an electrolytic capacitor. Examples of the DC/DC converter include a switching regulator. Each of the power supply circuits 21 to 27 outputs the output voltage designated by the setting signal to the driver IC 1b or the driver IC 2b.

The power supply circuit 21 is connected to the driver IC 1b and the driver IC 2b via the wiring VDD1. The power supply circuit 22 is connected to the driver IC 1b and the driver IC 2b via the wiring VDD2. The power supply circuit 23 is connected to the driver IC 1b via the wiring VDD3. The power supply circuit 24 is connected to the driver IC 2b via the wiring VDD4. The power supply circuit 25 is connected to the driver IC 1b and the driver IC 2b via the wiring VDD5. The power supply circuit 26 is connected to the driver IC 1b and the driver IC 2b via the wiring VDD6. The power supply circuit 27 is connected to the driver IC 1b and the driver IC 2b via the wiring HVDD. The power supply circuit 27 is connected to the drive element 111 described later via the wiring VCOM. The wiring HVDD and the wiring VCOM are obtained by branching the wiring drawn from the power supply circuit 27 into two wirings in the middle of the route.

The power supply circuit 21 to the power supply circuit 27 are the waveform generation circuit 30(1) to the waveform generation circuit 30(z) (z is a natural number of 2 or more, and is, for example, the first number) formed inside the driver IC 1b and the driver IC 2b, respectively. The number of drive elements (nozzles 11) included in the head 1 is equal to the number of drive elements (nozzles 11) included in the second head 2). Details of the driver IC 1b and the driver IC 2b will be described later (see FIGS. 3 to 5).

The power supply circuits 21 to 26 are power supply circuits normally used. The power supply circuit 27 is a power supply circuit of special specifications. The power supply circuit 27 can be used together as a VCOM power supply voltage of the drive element 111, or can be used as HVDD (high side bag gate voltage) of the PMOS transistors 311 to 315 described later.

The driver ICs 1b and 2b are connected to the controller 7 via z control lines 33(1) to 33(z) in parallel. In order to avoid complication of the drawing, the n control lines 33(1) to 33(z) are represented by a single line in FIG. Further, the driver ICs 1b and 2b are respectively connected to z driving elements 111 via n signal lines 34(1) to 34(z). Each signal line 34 is connected to an individual electrode of the driving element. The driver ICs 1b and 2b are connected to the wiring GND which is a ground line. Control signals for controlling z later-described selectors 90(1) to (z) included in the driver ICs 1b and 2b are transmitted to the control lines 33(1) to (z). The controller 7 selects the power supply circuit for generating the drive signal to be output to each signal line 34 by controlling the z selectors 90(1) to 90(z).

In the above embodiment, the plurality of control lines 33(1) to 33(z) are provided between the controller 7 and the driver ICs 1b and 2b, but the present invention is not limited to this. For example, some serial signal lines are provided between the controller 7 and the driver ICs 1b and 2b, and the controller 7 converts the signals sent via the control lines 33(1) to (z) into serial signals. The serial signal may be output to the driver ICs 1b and 2b via the serial signal line described above. In this case, the driver ICs 1b and 2b may convert the serial signals into parallel signals, take out the signals sent out on the control lines 33(1) to (z), and input them to z selectors or waveform generation circuits. .. As a result, the number of wires between the controller 7 and the driver ICs 1b and 2b can be reduced, or the number of pins required for the IC can be reduced.

The control lines 33(1) to (z) are control lines provided corresponding to the above-mentioned z waveform generation circuits 30(1) to (z). A signal for controlling the FET included in each waveform generation circuit 30 is propagated to each control line 33. In accordance with this signal, the waveform generation circuit 30 of the driver IC 1b, 2b generates a drive signal for driving the drive element 111, and outputs the generated drive signal to the drive element 111 via the signal line 34.

FIG. 3 is a diagram showing an example of a circuit configuration of the driver IC 1b. The driver IC 1b includes z waveform generation circuits 30(1) to (z) and z selectors 90(1) to (z) provided corresponding to the waveform generation circuits 30(1) to (z). ) Is provided. The number of selectors 90(1) to (z) is the same as the number of drive elements 111, that is, the number of selectors 90(1) to (z) is z and the number of drive elements 111 is z. .. Each selector 90 is a hardware constituent element including a plurality of transistors and the like formed inside the driver IC 1b.

Since the driver IC 1b includes z control lines 33 and signal lines 34, the number of which is the same as the number of nozzles, the number of nozzles between the control line 33(1) and the signal line 34(1) will be representatively shown below. The circuit configuration provided in the above will be described. In the driver IC 1b, the selector 90(1) and the waveform generation circuit 30(1) are formed between the control line 33(1) and the signal line 34(1).

The control line 33(1) from the controller 7 is connected to the selector 90(1). The control line 33(1) branches in the middle of the path connecting the controller 7 and the selector 90(1), and the control line SB(1) branched in the middle from the control line 33(1) is the waveform generation circuit 30( It is connected to 1).

The selector 90(1) and the waveform generation circuit 30(1) are connected via five control lines S1(1), S2(1), S3(1), S4(1), and S5(1). ing. The selector 90(1) selects one of the five control lines S1(1), S2(1), S3(1), S4(1), and S5(1) according to the instruction from the controller 7. One control line is connected to the control line 33(1).

Further, the waveform generation circuit 30(1) is connected to the five wirings connected to the wirings VDD1 to 5, 5, and 6 described above, the wiring connected to the wiring HVDD, and the wiring connected to the wiring GND. Has been done.

FIG. 4 is a diagram showing an example of a circuit configuration included in the driver IC 2b. The driver IC 2b includes z waveform generation circuits 30(1) to (z) and z selectors 90(1) to (z) provided corresponding to the waveform generation circuits 30(1) to (z). ) Is provided. The z selectors 90(1) to 90(z) are provided corresponding to the z drive elements 111. Each selector 90 is a hardware constituent element including a plurality of transistors and the like formed inside the driver IC 2b.

Since the driver IC 2b includes z control lines 33 and 34 signal lines, the number of which is the same as the number of nozzles, the number of nozzles between the control line 33(1) and the signal line 34(1) will be representatively shown below. The circuit configuration provided in the above will be described. In the driver IC 2b, the selector 90(1) and the waveform generation circuit 30(1) are formed between the control line 33(1) and the signal line 34(1).

The control line 33(1) from the controller 7 is connected to the selector 90(1). The control line 33(1) branches in the middle of the path connecting the controller 7 and the selector 90(1), and the control line SB(1) branched in the middle from the control line 33(1) is the waveform generation circuit 30( It is connected to 1).

The selector 90(1) and the waveform generation circuit 30(1) are connected via five control lines S1(1), S2(1), S3(1), S4(1), and S5(1). ing. The selector 90(1) selects one of the five control lines S1(1), S2(1), S4(1), and S5(1) according to an instruction from the controller 7, Connect to control line 33(1).

Further, the waveform generation circuit 30(1) is connected to the five wirings connected to the wirings VDD1, 2, 4 to 6 described above, the wiring connected to the wiring HVDD, and the wiring connected to the wiring GND. Has been done.

FIG. 5 is a circuit diagram showing an example of the configuration of the waveform generation circuit 30(1). Since the waveform generation circuits 30(1) to 30(z) have the same configuration, the waveform generation circuit 30(1) will be described with reference to FIG. The waveform generation circuit 30(1) includes six PMOS (P-type Metal Oxide Semiconductor) transistors 311 to 316 (only two shown in FIG. 5), one NMOS (N-type Metal Oxide Semiconductor) transistor 32, and a resistor. 35 and the like. The waveform generation circuit 30(1) is connected to the individual electrode of the drive element 111 via the signal line 34(1).

The drive element 111 of the present embodiment is a piezoelectric element as disclosed in FIG. 5 of JP-A-2015-24531 (Japanese Patent Application No. 2013-154357). The driving element 111 includes a first active portion sandwiched between an individual electrode and a first constant potential electrode, and a second active portion sandwiched between an individual electrode and a second constant potential electrode. Is. Therefore, the drive element 111 includes the capacitor 111b and the capacitor 111b'.

Five source terminals 311a to 315a of five PMOS transistors 311 to 315 are connected to the signal line 34(1). The source terminal 32a of the NMOS transistor 32 is connected to the ground. Note that, in FIG. 5, the PMOS transistors 312 to 315 are not shown.

A control line S1(1) is connected to the gate terminal 311c of the PMOS transistor 311. The control line S2(1) is connected to the gate terminal 312c of the PMOS transistor 312. The control line S3(1) is connected to the gate terminal 313c of the PMOS transistor 313. The control line S4(1) is connected to the gate terminal 314c of the PMOS transistor 314. The control line S5(1) is connected to the gate terminal 315c of the PMOS transistor 315. The control line SB(1) is connected to the gate terminal 32c of the NMOS transistor 32.

In the driver IC 1b of the first circuit board 1a, the PMOS transistor 311 is connected to the power supply circuit 21 via the wiring VDD1. The PMOS transistor 312 is connected to the power supply circuit 22 via the wiring VDD2. The PMOS transistor 313 is connected to the power supply circuit 23 via the wiring VDD3. The PMOS transistor 314 is connected to the power supply circuit 25 via the wiring VDD5. The PMOS transistor 315 is connected to the power supply circuit 26 via the wiring VDD6. The driver IC 1b of the first circuit board 1a is not connected to the power supply circuit 24.

In the driver IC 2b of the second circuit board 2a, the PMOS transistor 311 is connected to the power supply circuit 21 via the wiring VDD1. The PMOS transistor 312 is connected to the power supply circuit 22 via the wiring VDD2. The PMOS transistor 313 is connected to the power supply circuit 24 via the wiring VDD4. The PMOS transistor 314 is connected to the power supply circuit 25 via the wiring VDD5. The PMOS transistor 315 is connected to the power supply circuit 26 via the wiring VDD6. The driver IC 2b of the second circuit board 2a is not connected to the power supply circuit 23.

The drain terminals 311b to 315b of the five PMOS transistors 311 to 315 are connected to one end of the resistor 35. The drain terminal 32b of the NMOS transistor 32 is connected to one end of the resistor 35. The other end of the resistor 35 is connected to the individual electrodes of the drive element 111 (the other end of the capacitor 111b′ and the one end of the capacitor 111b). The first constant potential electrode (one end of the capacitor 111b') of the drive element 111 is connected to VCOM, and the second constant potential electrode (the other end of the capacitor 111b) of the drive element 111 is connected to the ground.

The portion of the piezoelectric body of the drive element 111 sandwiched between the first constant potential electrode and the individual electrode is polarized in the direction from the first constant potential electrode to the individual electrode. However, if a voltage higher than that of the first constant potential electrode is applied to the individual electrode, the polarization may be deviated. Therefore, in the present embodiment, the output voltage of the power supply that applies the first constant potential electrode voltage is set to be lower than the output voltage of the power supply that applies the VDD voltage to the individual electrodes.

When the controller 7 outputs a low level (“L”) signal to the control line 33(1), one of the PMOS transistors 311 to 315 connected to the signal line selected by the selector 90(1) described above. The two PMOS transistors are turned on. Here, the control line 33(1) to which the low level signal is input corresponds to, for example, S1(1) in FIG. The capacitor 111b is charged and the capacitor 111b' is discharged by the voltage supplied from any one of the power supply circuits 21 to 26. On the other hand, when the controller 7 outputs a high level (“H”) signal to the control line 33(1), the NMOS transistor 32 is turned on, and the capacitor 111b is turned on by the voltage output from the power supply circuit 27 connected to the wiring VCOM. ′ Is charged and the capacitor 111b is discharged. Here, the control line 33(1) to which the high level signal is input corresponds to SB(1) in FIG. By alternately charging and discharging the capacitors 111b and 111b', the drive element 111 is deformed and ink is ejected from the ejection port 11a of the nozzle.

That is, the drive signal for driving the drive element 111 is output to the signal line 34(1). The selector 90(1) selects one of the five control lines S1(1) to S5(1) as the control line to be connected, and thus the power supply circuit for generating the drive signal is six power supply circuits. It can be selected from 21 to 26.

As shown in FIG. 2, the five power supply circuits 21, 22, 25 to 27 are shared by the two driver ICs 1b and 2b. The total number of power supply circuits can be reduced as compared with the case where six power supply circuits are provided for each driver IC 1b and 2b.

Hereinafter, a method of determining the number of power supply circuits that output different voltages to the first head 1 and the second head 2, that is, a voltage setting method will be described. By executing this voltage setting method when designing the power supply board, the number of power supply circuits can be reduced.

FIG. 6 is a conceptual diagram showing an example of the first table 1d stored in the first storage unit 1c and the second table 2d stored in the second storage unit 2c before the execution of the voltage setting method.

As shown in FIG. 6, “rank”, “voltage value”, and “channel (ch)” are stored in the first table 1d. The voltage value is set corresponding to each rank. Further, the rank is represented by, for example, 6 levels of 1 to 6. The voltage value indicates the value of the output voltage of the power supply circuit. The unit of voltage value is volt. For example, before the voltage setting method is executed, the voltage value of the first rank is 21, the voltage value of the second rank is 22, the voltage value of the third rank is 23, the voltage value of the fourth rank is 24, and the voltage value of the fifth rank is 24. The voltage value is 25, and the voltage value of the sixth rank is 26. Hereinafter, the voltage value in the first table 1d will be expressed as X(n) (n is a natural number), and the voltage values of the first rank to the sixth rank will be expressed as X(1) to X(6), respectively.

The “channel” is an identifier for identifying each nozzle, and in this embodiment, is a number 1 to z for identifying each nozzle. Any of the first to sixth ranks is set corresponding to each of the numbers 1 to z.

As shown in FIG. 6, the “rank”, “voltage value”, and “channel (ch)” are stored in the second table 2d similarly to the first table 1d. The voltage value is set corresponding to each rank. For example, the rank is represented by 6 levels from 1 to 6. The voltage value indicates the value of the output voltage of the power supply circuit. The unit of voltage value is volt. For example, before executing the voltage setting method, the voltage value of the first rank is 21.5, the voltage value of the second rank is 22.5, the voltage value of the third rank is 23.5, and the voltage value of the fourth rank is The voltage value of the second rank is 24.5, the voltage value of the fifth rank is 25.5, and the voltage value of the sixth rank is 26.5. Hereinafter, the voltage values in the second table 2d will be expressed as Y(n), and the voltage values of the first rank to the sixth rank will be expressed as Y(1) to Y(6), respectively.

The rank is a channel, in other words, an index corresponding to the ejection performance of the nozzle 11. For example, the rank is determined according to the discharge amount of the nozzle 11 when a predetermined voltage is applied, and the discharge amount of the nozzle 11 of rank 1>the discharge amount of the nozzle 11 of rank 2>the nozzle 11 of rank 3 The relationship of discharge amount>discharge amount of nozzle 11 of rank 4>discharge amount of nozzle 11 of rank 5 is established.

The “channel” is an identifier for identifying each nozzle, and in this embodiment, is a number 1 to z for identifying each nozzle. Any of the first to fifth ranks is set corresponding to each of the identification numbers 1 to z. The sixth rank corresponds to a special case such as the case of non-ejection, and the sixth rank is not set for the identification numbers 1 to z.

For example, the controller 7 refers to the first table 1d and the second table 2d to execute the voltage setting method. In this method, the controller 7 creates the composition table 7a (see FIG. 9). Further, the controller 7 updates the first table 1d and the second table 2d according to the created synthesis table 7a. Note that the external device 9 accesses the first storage unit 1c and the second storage unit 2c via the interface, refers to the first table 1d and the second table 2d, and creates a composite table, and then creates the composite table. 2 The table 2d may be updated.

7 and 8 are flowcharts for explaining the voltage setting method, FIG. 9 is a conceptual diagram showing an example of the composition table 7a, and FIG. 10 is stored in the first storage unit 1c after the voltage setting method is executed. It is a conceptual diagram which shows an example of the 1st table 1d and the 2nd table 2d memorize|stored in the 2nd memory|storage part 2c.

A case will be described in which the voltage setting method executed by the controller 7 is executed using the first table 1d and the second table 2d shown in FIG. As described above, the external device 9 may execute the method for setting the power supply. As shown in FIG. 7, the controller 7 first refers to the first table 1d and the second table 2d to determine which rank has the largest number of channels, and determines the voltage value of that rank. (S1).

In step S1, the controller 7 measures the number of channels (the number of driving elements) of each of the first rank to the sixth rank from the first table 1d and selects the rank having the largest number of channels. Further, the number of channels of each of the first rank to the sixth rank is measured from the second table 2d, and the rank having the largest number of channels is selected. For example, in both the first table 1d and the second table 2d, the number of channels of the first rank is 180, the number of channels of the second rank is 420, and the number of channels of the third rank is 540. The number of channels in the 4th rank is 340, and the number of channels in the 5th rank is 180. In this case, the maximum number of channels is rank 540, and the controller 7 selects rank 3 as the rank with the largest number of channels. Here, the highest channel number of the first table 1d is prioritized, and the voltage value X(3) is determined as the voltage value of the highest channel number. The voltage value Y(3) of the second table 2d may be set to the voltage value of the maximum number of channels.

When a graph is created in which the horizontal axis indicates the rank and the vertical axis indicates the number of channels for some heads, the distribution of the number of channels becomes a normal distribution. This represents a general head tendency. In this embodiment, one of ranks 1 to 5 is set for each identification number 1 to z of the channel, and rank 3 is the median value. Therefore, the number of channels corresponding to rank 3 tends to be the largest.

Next, in the table in which the determined voltage value is stored, that is, in the first table 1d, the voltage value X(k of the rank k that is smaller than the rank of the maximum number of channels and has the second largest number of channels is next. ) Is selected by the controller 7 (S2). In the case of FIG. 6, the voltage value X(2) is selected. Next, the controller 7 determines whether or not the rank k of the selected voltage value is 2 or more (S3). When the rank k of the voltage value is 2 or more (S3: YES), the selected voltage value is selected. The controller 7 calculates the absolute value A of the difference between X(k) and the voltage value Y(k) of the second table 2d of the same rank as the voltage value X(k) (S4). In the case of FIG. 6, since k=2, the controller 7 calculates the absolute value A of the difference between the voltage value X(2) and the voltage value Y(2). Hereinafter, the absolute value A of the difference is also referred to as the difference A.

Next, the controller 7 calculates the absolute value B of the difference between the voltage value X(k) and the voltage value X(k-1) having a rank one less than the voltage value X(k) (S5). Hereinafter, the absolute value B of the difference is also referred to as the difference B. In the case of FIG. 6, the controller 7 calculates the difference between the voltage value X(2) and the voltage value X(1). Then, the controller 7 determines whether the difference A is less than or equal to the difference B (S6), and when the difference A is less than or equal to the difference B (S6: YES), the voltage value X(k) and the voltage value Y(k) are determined. The voltage value X(k-1) and the voltage value Y(k-1) are combined (S7).

When the difference A is less than or equal to the difference B, it is considered that the difference between the voltage value X(k) and the voltage value Y(k) is sufficiently small. In other words, it is considered that the voltage value X(k) and the voltage value Y(k) are highly similar. Therefore, even if the values of the voltage value X(k) and the voltage value Y(k) are made common, the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value Y(k) is small. Conceivable.

As a general tendency of the head, for example, the difference between the voltage value X(k) of the first head 1 and the voltage value X(k−1) is the voltage value Y(k) of the second head 2 and the voltage value Y. It is often the same as the difference from (k-1). Therefore, in the first table 1d, the difference between voltage values X(n) corresponding to two adjacent ranks, and in the second table 2d, the difference between voltage values Y(n) corresponding to two adjacent ranks. However, the voltage values X(n) and Y(n) are set so that they have substantially the same magnitude. That is, the difference between the voltage value X(k) and the voltage value X(k−1) and the difference between the voltage value Y(k) and the voltage value Y(k−1) are substantially the same. Therefore, when the difference between the voltage value X(k) and the voltage value Y(k) is sufficiently small, the difference between the voltage value X(k-1) and the voltage value Y(k-1) is also sufficiently small, and the voltage value X It is considered that the closeness of (k-1) and the voltage value Y(k-1) is also high. Therefore, in addition to making the voltage value X(k) and the voltage value Y(k) common, the voltage value X(k-1) and the voltage value Y(k-1) are made common. , The voltage value X(k−1) and the voltage value Y(k−1) have little influence on the ejection characteristics of the nozzle 11.

The combination of the voltage value X(k) and the voltage value Y(k) is executed by the following formula, for example.
(Voltage value X(k)*number of channels of voltage value X(k)+voltage value Y(k)*number of channels of voltage value Y(k))/(number of channels of voltage value X(k)+*voltage value Y(k) channels).

In the case of FIG. 6, |voltage value X(2)−voltage value Y(2)|=0.5<|voltage value X(2)−voltage value X(1)|=1, so voltage value X(2) And the controller 7 synthesizes the voltage value Y(2). Specifically, the controller 7 calculates (22*420+22.5*420)/(420+420) and obtains 22.25 as the value after combination. 22.25 is a common value of the voltage value X(2) and the voltage value Y(2), and corresponds to the average voltage value Axy(k). Further, the controller 7 combines the voltage value X(1) and the voltage value Y(1). Specifically, the controller 7 calculates (21*180+21.5*180)/(180+180) and obtains 21.25 as the value after combining. 21.25 is a common value of the voltage value X(1) and the voltage value Y(1), and corresponds to the average voltage value Axy(k-1).

Then, the controller 7 determines whether or not the rank k-1 is 3 or more (S9), and when the rank k-1 is 3 or more (S9: YES), the rank k is reduced by two (S10), The step is returned to S4. When the rank k-1 is not 3 or more (S9: NO), the controller 7 extracts the voltage value of the maximum number of channels (S11). In the case of FIG. 6, the controller 7 extracts the voltage value X(3) and the voltage value Y(3). In S3, if the rank k of the voltage value is not 2 or more (S3: NO), that is, if the rank k is rank 1, the controller 7 advances the process to S11. When the rank k is the rank 1, the rank 0 does not exist, so that the difference B cannot be calculated in S5. Therefore, the controller 7 advances the process to S11 without executing S4 to S10. When a predetermined value is set in advance instead of the difference B calculated in S5, the controller 7 may skip S3 after S2 and compare the difference A with the predetermined value in S6. ..

Next, in the table in which the voltage value determined in S1 is stored, that is, in the first table 1d, the voltage value of the rank k that is larger than the rank of the largest number of channels and has the next largest number of channels. The controller 7 selects X(k) (S12). In the case of FIG. 6, the controller 7 selects the voltage value X(4). Next, it is determined whether or not the rank k of the selected voltage value is equal to or lower than "kmax-2" (S13). kmax is the maximum rank. The maximum rank indicates the rank with the largest number, and in the case of FIG. 6, kmax is 6. When the rank k of the voltage value is kmax-2 or less (S13: YES), the selected voltage value X(k) and the voltage value Y(k of the second table 2d having the same rank as the voltage value X(k). The controller 7 calculates the absolute value C of the difference with () (S14). In the case of FIG. 6, kmax is 6, and the rank k of the selected voltage value is 4. Therefore, the controller 7 calculates the absolute value C of the difference between the voltage value X(2) and the voltage value Y(2). To do. Hereinafter, the absolute value C of the difference is also referred to as the difference C.

Next, the controller 7 calculates the absolute value D of the difference between the voltage value X(k) and the voltage value X(k+1) of one rank higher than the rank of the voltage value X(k) (S15). Hereinafter, the absolute value D of the difference is also referred to as the difference D. In the case of FIG. 6, the controller 7 calculates the difference between the voltage value X(4) and the voltage value X(5). Then, the controller 7 determines whether the difference C is less than or equal to the difference D (S16), and when the difference C is less than or equal to the difference D (S16: YES), the voltage value X(k) and the voltage value Y(k) are determined. The voltage value X(k+1) and the voltage value Y(k+1) are combined (S17).

As a general tendency of the head, the difference between the voltage value X(k) of the first head 1 and the voltage value X(k+1) is the difference between the voltage value Y(k) and the voltage value Y(k+1) of the second head 2. It is often almost the same as the difference. When the difference C is less than or equal to the difference D, the difference between the voltage value X(k) and the voltage value Y(k) is considered to be sufficiently small, and the approximation of the voltage value X(k) and the voltage value Y(k) is It is considered expensive. Similarly, it is considered that the voltage value X(k+1) and the voltage value Y(k+1) have high closeness. Therefore, even if the values of the voltage value X(k) and the voltage value Y(k) are made common, the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value Y(k) is small. Conceivable. Further, even if the voltage value X(k+1) and the voltage value Y(k+1) are made common, it is considered that the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k+1) and the voltage value Y(k+1) is small. To be

In the case of FIG. 6, since |voltage value X(4)−voltage value Y(4)|=0.5<|voltage value X(4)−voltage value X(5)|=1, the controller 7 determines the voltage value X(4) (4) and the voltage value Y(4) are combined. Specifically, the controller 7 calculates (24*360+24.5*360)/(360+360) based on the above-mentioned formula, and obtains 24.25 as the value after the combination. 24.25 is a common value of the voltage value X(4) and the voltage value Y(4), and corresponds to Axy(k+1). Further, the voltage value X(5) and the voltage value Y(5) are combined. Specifically, the controller 7 calculates (25*180+25.5*180)/(180+180) and obtains 25.25 as the value after combination. 25.25 is a common value of the voltage value X(5) and the voltage value Y(5).

Then, the controller 7 determines whether or not the rank k+1 is equal to or lower than "kmax-3" (S19), and when the rank k+1 is equal to or lower than kmax-3 (S19: YES), increases the rank k by two ( The step is returned to S20) and S14. When the rank k+1 is not equal to or lower than kmax-3 (S19: NO), the controller 7 selects the maximum voltage value (S21). Specifically, the maximum voltage value of the first table 1d is compared with the maximum voltage value of the second table 2d, and a larger value is selected. In the case of FIG. 6, since the voltage value Y(6) is 26.5 and the voltage value X(6) is 26, the controller 7 selects the voltage value Y(6) as the maximum voltage value.

Then, the controller 7 assigns each voltage value to the plurality of manufactured power supply circuits (S22). In the case of FIG. 6, the controller 7 controls the voltage value combined in S7, the voltage value of the maximum number of channels extracted in S11, the voltage value combined in S17, and the maximum voltage value selected in S21 to be plural power supply circuits. Assign to. More specifically, as shown in the composition table 7a of FIG. 9, the controller 7 assigns the voltage value 21.25 combined in S7 to the power supply circuit 21 of the first rank, and combines 22.25 into the second rank. Of the power supply circuit 22. Then, the controller 7 assigns the voltage value X(3) extracted in S11, that is, 23, to the power supply circuit 23 of the third rank, and the extracted voltage value Y(3), that is, 23.5, the power supply of the fourth rank. Assign to circuit 24. Further, the controller 7 assigns the combined voltage value 24.25 in S17 to the fifth rank power supply circuit 25, and assigns the combined voltage value 25.25 to the sixth rank power supply circuit 26. Further, the controller 7 assigns the voltage value Y(6) selected in S21, that is, 26.5 to the power circuit 27 of the seventh rank. The power supply numbers in FIG. 9 correspond to the first rank to the seventh rank, respectively. The power supply numbers in FIG. 9 correspond to the power supply circuits 21 to 27, respectively.
After executing S22, the controller 7 synthesizes the two voltage values having the smallest voltage difference from the ranks 1 to 6 of the synthesis table 7a, for example, the voltage value of the third rank and the voltage value of the fourth rank. The voltage values may be combined to further reduce the number of power supply circuits.

Then, the controller 7 assigns each nozzle 11 to the plurality of power supply circuits (S23). More specifically, 180 nozzles 11 corresponding to the voltage value X(1) of the first table 1d and 180 nozzles 11 corresponding to the voltage value Y(1) of the second table 2d (a total of 360 nozzles The nozzle 11) is assigned to the power supply circuit 21. The 420 nozzles 11 corresponding to the voltage value X(2) of the first table 1d and the 420 nozzles 11 corresponding to the voltage value Y(2) of the second table 2d (a total of 840 nozzles 11) are It is assigned to the power supply circuit 22. The 540 nozzles 11 corresponding to the voltage value X(3) of the first table 1d are assigned to the power supply circuit 23, and the 540 nozzles 11 corresponding to the voltage value Y(3) of the second table 2d are the power supply circuit. 24 are assigned. The 360 nozzles 11 corresponding to the voltage value X(4) of the first table 1d and the 360 nozzles 11 corresponding to the voltage value Y(4) of the second table 2d (total 720 nozzles 11) are It is assigned to the power supply circuit 25. The 180 nozzles 11 corresponding to the voltage value X(5) of the first table 1d and the 180 nozzles 11 corresponding to the voltage value Y(5) of the second table 2d (360 nozzles 11 in total) are It is assigned to the power supply circuit 26.

Then, the controller 7 updates the voltage values of the first table 1d and the second table 2d (S24), and ends the process. Specifically, as shown in FIG. 10, in the first table 1d, the voltage value X(1) of the first rank is updated to 21.25, and the voltage value X(2) of the second rank is 22.25. , The voltage value X(4) of the fourth rank is updated to 24.25, the voltage value X(5) of the fifth rank is updated to 25.25, and the voltage value X(6) of the sixth rank is updated. Is updated to 26.5. The voltage value X(3) of the third rank is not updated (see FIGS. 6 and 10).

Further, in the second table 2d, the voltage value Y(1) of the first rank is updated to 21.25, the voltage value Y(2) of the second rank is updated to 22.25, and the voltage value Y of the fourth rank is updated. (4) is updated to 24.25, and the voltage value Y(5) of the fifth rank is updated to 25.25. The voltage values Y(3) and Y(6) of the third rank and the sixth rank are not updated (see FIGS. 6 and 10). When the rank k of the voltage value is not equal to or lower than kmax-2 in S13 (S13: NO), for example, when the rank k is rank 5, the voltage value X(6) in S15 is the difference D in S15. Since it cannot be used for the calculation of, the controller 7 ends the process. The voltage value X(6) may be applied to the non-ejection nozzle 11 and is often set to a very large value as compared with the voltage values X(1) to X(5). It is unsuitable as a value used for the calculation of D. Note that, instead of the difference D calculated in S15, the controller 7 skips S13 and then S13 after setting an appropriate predetermined value in advance, and compares the difference C with the predetermined value in S15. May be.

In FIG. 10, the code in parentheses in the rank column indicates the rank of the synthesis table 7a, that is, the power supply circuits 21 to 27. In the first table 1d, the nozzles 11 of the first rank to the third rank are connected to the power supply circuits 21 to 23, respectively, and the nozzles 11 of the fourth rank to the sixth rank are connected to the power supply circuits 25 to 27. Indicates. In the second table 2d, the nozzles 11 of the first and second ranks are connected to the power supply circuits 21 and 22, respectively, and the nozzles 11 of the third rank to the sixth rank are connected to the power supply circuits 24-27, respectively. Indicates that it will be connected. In this way, when the power supply circuit is manufactured, the number of the power supply circuits 21 to 27 and the output voltage are determined. As a result, as shown in FIG. 2, the power supply circuits 21 to 27 have wirings VDD1 to VDD6 and HVDD. The driver IC 1b of the first head 1 and the driver IC 2b of the second head 2 are connected via.

Hereinafter, the case where the voltage values stored in the first table 1d and the second table 2d are different from the voltage values of FIG. 6 will be described. FIG. 11 is a conceptual diagram showing another example of the first table 1d stored in the first storage unit 1c and the second table 2d stored in the second storage unit 2c before the execution of the voltage setting method. 12 is a conceptual diagram showing another example of the composition table 7a, and FIG. 13 is stored in the first table 1d stored in the first storage unit 1c and the second storage unit 2c after the execution of the voltage setting method. It is a conceptual diagram which shows the other example of the 2nd table 2d.

As shown in FIG. 11, in the first table 1d, the voltage value X(1) is 21.5, the voltage value X(2) is 22, the voltage value X(3) is 23, and the voltage value X(4) is 24. The voltage value X(5) is 24.5 and the voltage value X(6) is 26. In the second table 2d, the voltage value Y(1) is 20.5, the voltage value Y(2) is 21, the voltage value Y(3) is 23.5, the voltage value Y(4) is 25, and the voltage value Y( 5) is 25.5, and the voltage value Y(6) is 26.5.

A case of executing the voltage setting method using the first table 1d and the second table 2d shown in FIG. 11 will be described. As shown in FIG. 7, the controller 7 first determines the voltage value X(3) as the voltage value of the maximum number of channels (S1), and selects the voltage value X(2) (S2). Then, after executing S3 (S3: YES), the controller 7 calculates the difference A=|voltage value X(2)−voltage value Y(2)| (S4), and the difference B=|voltage value X(2 )-Voltage value X(1)| is calculated by the controller 7 (S5). Then, the controller 7 determines whether the difference A is less than or equal to the difference B (S6). When using the first table 1d and the second table 2d shown in FIG. 11, the difference A=|22-21|=1> the difference B=|22-21.5|=0.5 (S6: NO). The controller 7 synthesizes the voltage value X(2) and the voltage value X(1), and synthesizes the voltage value Y(2) and the voltage value Y(1) (S8).

If the difference A is not less than the difference B, the difference between the voltage value X(k) and the voltage value Y(k) cannot be considered to be sufficiently small. In other words, the approximation of the voltage value X(k) and the voltage value Y(k) is considered to be low. Therefore, when the values of the voltage value X(k) and the voltage value Y(k) are made common, the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value Y(k) is large. Conceivable. It is considered inappropriate to make the voltage value X(k) and the voltage value Y(k) common.

On the other hand, the difference B is less than or equal to the difference A. Therefore, it is considered that the difference between X(k) and X(k-1) is sufficiently small, and the voltage value X(k) and the voltage value X(k-1) have high closeness. Therefore, even if the voltage value X(k) and the voltage value X(k−1) are made common, the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value X(k−1) are given. The impact is considered to be small.

As described above, as a general tendency of the head, the difference between the voltage value X(k) of the first head 1 and the voltage value X(k−1) is the same as the voltage value Y(k) of the second head 2. The difference from the voltage value Y(k-1) is often almost the same. Therefore, it is considered that the voltage value Y(k) and the voltage value Y(k−1) are also highly similar. Therefore, even if the voltage value Y(k) and the voltage value Y(k-1) are made common, the ejection characteristics of the nozzle 11 corresponding to the voltage value Y(k) and the voltage value Y(k-1) are given. The impact is considered to be small.

The combination of the voltage value X(k) and the voltage value X(k-1) is executed by the following formula, for example.
(Voltage value X(k)*Number of channels of voltage value X(k)+Voltage value X(k-1)*Number of channels of voltage value X(k-1))/(Number of channels of voltage value X(k) +* number of channels of voltage value X(k-1)).

Therefore, the controller 7 combines the voltage value X(2) and the voltage value X(1). Specifically, based on the above-mentioned formula, the controller 7 calculates (22*420+21.5*180)/(420+180) and obtains 21.85 as the value after combination. 21.85 is a common value of the voltage value X(1) and the voltage value X(2), and corresponds to Ax(k)(k-1). Further, the controller 7 synthesizes the voltage value Y(2) and the voltage value Y(1). Specifically, the controller 7 calculates (21*420+20.5*180)/(420+180) and obtains 20.85 as the value after combining. 20.85 is a common value of the voltage value Y(1) and the voltage value Y(2), and corresponds to Ay(k)(k-1). Then, the controller 7 executes S9 (S9: NO) and extracts the voltage value X(3) and the voltage value Y(3) as the voltage value of the maximum number of channels (S11).

Next, in the table in which the voltage value determined in S1 is stored, that is, in the first table 1d, the voltage value X(4, which is larger than the rank of the maximum number of channels and has the second largest number of channels next to the maximum number of channels. ) Is selected by the controller 7 (S12) and S13 is executed (S13: YES), and the selected voltage value X(4) and the voltage value Y of the second table 2d having the same rank as the voltage value X(4) are selected. The absolute value C of the difference from (4) is calculated (S14). Next, the controller 7 calculates the absolute value D of the difference between the voltage value X(4) and the voltage value X(5) of one rank higher than the rank of the voltage value X(4) (S15). Then, the controller 7 determines whether the difference C is less than or equal to the difference D (S16).

The difference C=|24-25|=1, the difference D=|24-24.5|=0.5, and the difference C>the difference D (S16: NO). When the difference C is not equal to or less than the difference D, the difference between the voltage value X(k) and the voltage value Y(k) cannot be considered to be sufficiently small. In other words, the approximation of the voltage value X(k) and the voltage value Y(k) is considered to be low. Therefore, when the values of the voltage value X(k) and the voltage value Y(k) are made common, the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value Y(k) is large. Conceivable. It is considered inappropriate to make the voltage value X(k) and the voltage value Y(k) common.

On the other hand, since the difference D is less than or equal to the difference C, the difference between X(k) and X(k+1) is sufficiently small, and it is considered that the voltage value X(k) and the voltage value X(k+1) are highly similar. Therefore, even if the values of the voltage value X(k) and the voltage value X(k+1) are made common, the influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value X(k) and the voltage value X(k+1) is small. Conceivable.

As described above, as a general tendency of the head, the difference between the voltage value X(k) of the first head 1 and the voltage value X(k+1) is the voltage value Y(k) of the second head 2 and the voltage value. It is often almost the same as the difference from Y(k+1). Therefore, it is considered that the voltage value Y(k) and the voltage value Y(k+1) are also highly similar. Therefore, even if the values of the voltage value Y(k) and the voltage value Y(k+1) are made common, there is little influence on the ejection characteristics of the nozzle 11 corresponding to the voltage value Y(k) and the voltage value Y(k+1). Conceivable.

Therefore, the controller 7 synthesizes the voltage value X(4) and the voltage value X(5) (S18). Specifically, the controller 7 calculates (24*360+24.5*180)/(360+180) based on the above-mentioned formula, and obtains 24.17 as the value after combination. 24.17 is a common value of the voltage value X(4) and the voltage value X(5), and corresponds to Ax(k)(k+1). Further, the controller 7 synthesizes the voltage value Y(4) and the voltage value Y(5) (S18). Specifically, the controller 7 calculates (25*360+25.5*180)/(360+180) and obtains 25.17 as the value after combination. 25.17 is a common value of the voltage value Y(4) and the voltage value Y(5), and corresponds to Ay(k)(k+1). Then, the controller 7 executes S19 (S19: NO) and selects the maximum voltage value (S21). Specifically, the controller 7 compares the maximum voltage values X(6), 26 of the first table 1d with the maximum voltage values Y(6), 26.5 of the second table 2d, and compares them with a larger value. A certain voltage value Y(6) is selected.

Then, the controller 7 assigns each voltage value to the plurality of manufactured power supply circuits (S22). Specifically, the controller 7 sets the voltage value combined in S8, the voltage value of the maximum number of channels extracted in S11, the voltage value combined in S18, and the maximum voltage value selected in S21 to a plurality of power supply circuits. Assign to. More specifically, as shown in the composition table 7a of FIG. 12, the controller 7 assigns the voltage value 20.85 synthesized in S8 to the power supply circuit 21 of the first rank and synthesizes 21.85 into the second rank. Of the power supply circuit 22. Then, the controller 7 allocates the voltage value Y(3) extracted in S11, that is, 23.5 to the fourth rank power supply circuit 24, and the extracted voltage value X(3), that is, 23, is the third rank power supply. Assign to circuit 23. Further, the controller 7 assigns the voltage value 25.17 synthesized in S18 to the sixth rank power supply circuit 26, and assigns the synthesized voltage value 24.17 to the fifth rank power supply circuit 25. Further, the controller 7 assigns the voltage value Y(6) selected in S21, that is, 26.5 to the power circuit 27 of the seventh rank. The power supply numbers in FIG. 12 correspond to the power supply circuits 21 to 27, respectively. The power supply numbers in FIG. 12 correspond to the first rank to the seventh rank, respectively.

Then, the controller 7 assigns each nozzle 11 to the plurality of power supply circuits (S23). More specifically, 180 nozzles 11 corresponding to the voltage value Y() of the second table 2d and 420 nozzles 11 corresponding to the voltage value Y(2) (a total of 600 nozzles 11) are the power source. It is assigned to the circuit 21. 180 nozzles 11 corresponding to the voltage value X(1) of the first table 1d and 420 nozzles 11 corresponding to the voltage value X(2) (a total of 600 nozzles 11) are assigned to the power supply circuit 22. To be The 540 nozzles 11 corresponding to the voltage value X(3) of the first table 1d are assigned to the power supply circuit 23. The 540 nozzles 11 corresponding to the voltage value Y(3) of the second table 2d are assigned to the power supply circuit 24. The 360 nozzles 11 corresponding to the voltage value X(4) of the first table 1d and the 180 nozzles 11 corresponding to the voltage value X(5) of the first table 1d (600 nozzles 11 in total) are It is assigned to the power supply circuit 25. The 360 nozzles 11 corresponding to the voltage value Y(4) of the second table 2d and the 180 nozzles 11 corresponding to the voltage value Y(5) (600 nozzles 11 in total) are allocated to the power supply circuit 26. To be

Then, the controller 7 updates the voltage values of the first table 1d and the second table 2d (S24), and ends the process. Specifically, as shown in FIG. 13, in the first table 1d, the voltage value X(1) of the first rank is updated to 21.85, and the voltage value X(2) of the second rank is 21.85. The voltage value X(4) of the fourth rank is updated to 24.17, and the voltage value X(5) of the fifth rank is updated to 24.17. The sixth rank voltage value X(6) is updated to 26.5. The voltage value X(3) of the third rank is not updated (see FIGS. 11 and 13).

In the second table 2d, the voltage value Y(1) of the first rank is updated to 20.85, the voltage value Y(2) of the second rank is updated to 20.85, and the voltage value Y of the fourth rank is (4) is updated to 25.17, and the voltage value Y(5) of the fifth rank is updated to 25.17. The voltage value Y(3) of the third rank and the voltage value Y(6) of the sixth rank are not updated (see FIGS. 11 and 13).

In FIG. 13, the parenthesized code in the rank column indicates the rank of the synthesis table 7a, that is, the power supply circuits 21 to 27 to which the nozzle 11 is connected. In the first table 1d, the nozzles 11 of the first rank and the second rank are connected to the power supply circuit 22, the nozzles 11 of the third rank are connected to the power supply circuit 23, and the nozzles 11 of the fourth rank and the fifth rank are It is connected to the power supply circuit 25. In the second table 2d, it is shown that the first and second rank nozzles 11 are connected to the power supply circuit 21, the third rank nozzles 11 are connected to the power supply circuit 24, and the fourth rank and the fourth rank are shown. The five-rank nozzle 11 is connected to the power supply circuit 26.

FIG. 14 is a block diagram showing a power supply board 6, a first circuit board 1a, a second circuit board 2a, etc. designed based on the first table 1d and the second table 2d shown in FIG. As a result of the execution of the voltage setting method as described above, the circuit is designed as shown in FIG. That is, the power supply circuit 22, the power supply circuit 23, the power supply circuit 25, and the power supply circuit 27 are connected to the driver IC 1b, and the power supply circuit 21, the power supply circuit 24, the power supply circuit 26, and the power supply circuit 27 are connected to the driver IC 2b. To be done.

In the voltage setting method, the calculation device, the head device, and the head unit according to the embodiment, the voltage value X(k) of the kth rank stored in the first storage unit 1c and the second storage unit 2c are stored. When the stored kth rank voltage value Y(k) is similar, the voltage values X(k) and Y(k) are updated with the average voltage value of the voltage values X(k) and Y(k). To do. Since the voltage values X(k) and Y(k) have the same value, it is possible to reduce the number of circuits by applying a voltage to the nozzle in common.

In the embodiment, the recording medium 5 is fixed and the printing device is moved, but the recording medium 5 may be conveyed and the printing device may be fixed.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The technical features described in each example can be combined with each other, and the scope of the present invention is intended to include all modifications within the scope of the claims and a scope equivalent to the scope of the claims. To be done.

1 1st head 1a 1st circuit board 1c 1st memory|storage part 1e 1st interface 2 2nd head 2a 2nd circuit board 2c 2nd memory|storage part 2e 2nd interface 4 Control device 11 Nozzle 9 External device 21-27 Power supply circuit

Claims (16)

A first storage unit that stores a first rank to an nth rank (n is a natural number of 2 or more) assigned to each of the plurality of first drive elements of the first head, and a plurality of voltage values assigned to each rank. Through the first interface, the voltage value X(k) of the kth rank (k is a natural number satisfying 1≦k≦n) is read out,
From a second storage unit that stores the first rank to the nth rank assigned to each of the plurality of second drive elements of the second head and the plurality of voltage values assigned to each rank, through the second interface, Read the voltage value Y(k) of the kth rank,
The strength of the closeness between the read voltage value X(k) and the read voltage value Y(k) is determined,
When it is determined that the closeness is strong, an average voltage value Axy(k) of the voltage value X(k) and the voltage value Y(k) is calculated,
Updating the voltage value X(k) stored in the first storage unit to a calculated average voltage value Axy(k),
A method of updating the voltage value Y(k) stored in the second storage unit to the calculated average voltage value Axy(k). When the magnitude of the difference between the voltage value X(k) and the voltage value Y(k) is less than a predetermined value, it is determined that the closeness is strong, and the voltage value X(k) and the voltage value Y(k) are The method according to claim 1, wherein the similarity is determined to be weak when the magnitude of the difference is equal to or larger than a predetermined value. Reading the voltage value X(k−1) of the k−1th rank from the first storage unit,
Reading the voltage value Y(k−1) of the k−1th rank from the second storage unit,
An average voltage value Axy(k-1) of the read voltage value X(k-1) and the read voltage value Y(k-1) is calculated,
Updating the voltage value X(k-1) stored in the first storage unit to the calculated average voltage value Axy(k-1),
The method according to claim 1, wherein the voltage value Y(k−1) stored in the second storage unit is updated to the calculated average voltage value Axy(k−1). Reading the voltage value X(k−1) of the k−1th rank from the first storage unit,
The method according to claim 2, wherein the predetermined value is an absolute value of a difference between the read voltage value X(k) and the read voltage value X(k-1). When it is determined that the closeness between the voltage value X(k) and the voltage value Y(k) is weak, the read voltage value X(k) and the read voltage value X(k−1) The average voltage value Ax(k)(k-1) of
Updating the voltage value X(k) stored in the first storage unit to the calculated average voltage value Ax(k)(k-1),
The method according to claim 4, wherein the voltage value X(k-1) stored in the first storage unit is updated to the calculated average voltage value Ax(k)(k-1). Reading the voltage value Y(k−1) of the k−1th rank from the second storage unit,
When it is determined that the closeness between the voltage value X(k) and the voltage value Y(k) is weak, the read voltage value Y(k) and the read voltage value Y(k-1) The average voltage value Ay(k)(k-1) of
Updating the voltage value Y(k) stored in the second storage unit to the calculated average voltage value Ay(k)(k-1),
The method according to claim 5, wherein the voltage value Y(k-1) stored in the second storage unit is updated to the calculated average voltage value Ay(k)(k-1). The method according to claim 3, wherein the k-th rank and the k−1-th rank are different from a rank corresponding to a voltage value to which the largest number of driving elements is assigned. Reading the voltage value X(k+1) of rank k+1 from the first storage unit,
Reading the voltage value Y(k+1) of the (k−1)th rank from the second storage unit,
An average voltage value Axy(k+1) of the read voltage value X(k+1) and the read voltage value Y(k+1) is calculated,
Updating the voltage value X(k+1) stored in the first storage unit to the calculated average voltage value Axy(k+1),
The method according to claim 1, wherein the voltage value Y(k+1) stored in the second storage unit is updated to the calculated average voltage value Axy(k+1). The method according to claim 2, wherein the predetermined value is an absolute value of a difference between the voltage value X(k) and the voltage value X(k+1) of the (k+1)th rank stored in the first storage unit. Reading the voltage value X(k+1) of rank k+1 from the first storage unit,
When it is determined that the closeness between the voltage value X(k) and the voltage value Y(k) is weak, an average of the read voltage value X(k) and the read voltage value X(k+1). The voltage value Ax(k)(k+1) is calculated,
Updating the voltage value X(k) stored in the first storage unit to the calculated average voltage value Ax(k)(k+1),
The method according to claim 9, wherein the voltage value X(k+1) stored in the first storage unit is updated to the calculated average voltage value Ax(k)(k+1). Reading the voltage value Y(k+1) of rank k+1 from the second storage unit,
When it is determined that the closeness between the voltage value X(k) and the voltage value Y(k) is weak, an average of the read voltage value Y(k) and the read voltage value Y(k+1). The voltage value Ay(k)(k+1) is calculated,
Updating the voltage value Y(k) stored in the second storage unit to the calculated average voltage value Ay(k)(k+1),
The method according to claim 10, wherein the voltage value Y(k+1) stored in the second storage unit is updated to the calculated average voltage value Ay(k)(k+1). The method according to claim 8, wherein the k-th rank and the k+1-th rank are different from a rank corresponding to a voltage value to which the largest number of driving elements is assigned. In the rank smaller than the p-th rank corresponding to the voltage value to which the largest number of driving elements is assigned, the strength of the similarity with the voltage value X(k) and the voltage value Y(k) is determined, If it is determined to be strong, the average voltage value Axy(k) of the voltage value X(k) and the voltage value Y(k) is calculated, and the voltage value X(k) is calculated. Value Axy(k), the voltage value Y(k) is updated to the calculated average voltage value Axy(k), and the voltage value X(k) is higher than the p-th rank. And the strength of the closeness to the voltage value Y(k) are determined, and when the closeness is determined to be strong, the average voltage value Axy( of the voltage value X(k) and the voltage value Y(k) k), the voltage value X(k) is updated to the calculated average voltage value Axy(k), and the voltage value Y(k) is updated to the calculated average voltage value Axy(k). The method according to any one of claims 1 to 12. A first memory that stores a first rank to an nth rank (n is a natural number of 2 or more) assigned to each of the plurality of first drive elements of the first head, and a plurality of voltage values assigned to each rank. Through the first interface, the voltage value X(k) of the kth rank (k is a natural number satisfying 1≦k≦n) is read from
From the second storage unit that stores the first rank to the nth rank assigned to each of the plurality of second drive elements of the second head and the plurality of voltage values assigned to each rank, through the second interface, Reading the voltage value Y(k) of the k-th rank,
The strength of the closeness between the read voltage value X(k) and the read voltage value Y(k) is determined,
When it is determined that the closeness is strong, an average voltage value Axy(k) of the voltage value X(k) and the voltage value Y(k) is calculated,
Updating the voltage value X(k) stored in the first storage unit to an average voltage value Axy(k) calculated through the first interface;
An arithmetic unit for updating the voltage value Y(k) stored in the second storage unit to the average voltage value Axy(k) calculated through the second interface. A first head to which a voltage is applied to a plurality of first drive elements arranged corresponding to a plurality of nozzles from a plurality of power supplies that output voltages of different magnitudes;
A second head in which voltages are applied to a plurality of second drive elements arranged corresponding to a plurality of nozzles from a plurality of power supplies that output different magnitudes of voltage;
A first memory storing first rank to nth rank (n is a natural number of 2 or more) assigned to each of the plurality of first drive elements of the first head, and a plurality of voltage values assigned to each rank. Department,
A second storage unit storing first rank to nth rank assigned to each of the plurality of second drive elements of the second head and a plurality of voltage values assigned to each rank;
The voltage value X(k) of the kth rank (k is a natural number) stored in the first storage unit and the voltage value of the kth rank stored in the second storage unit and the same as the voltage value X(k). A head device that is the same as Y(k). A head device according to claim 15;
With multiple power supplies,
The number of the plurality of power supplies is less than 2n.

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