JP2021158298A

JP2021158298A - Semiconductor device

Info

Publication number: JP2021158298A
Application number: JP2020059539A
Authority: JP
Inventors: 隆平小島; Ryuhei Kojima
Original assignee: Ablic Inc
Current assignee: Ablic Inc
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2021-10-07

Abstract

To provide a semiconductor device including a resistor element that suppresses an increase of a resistance value accompanied with a temperature rise.SOLUTION: A semiconductor device includes: a first diffusion resistance region; a second diffusion resistance region disposed over a predetermined length at a predetermined interval relative to the first diffusion resistance region; contact regions respectively provided at both ends of the first diffusion resistance region and a contact region provided at least at one end of the second diffusion resistance region; a first metal wire connecting the respective contact regions of one ends of the first diffusion resistance region and second diffusion resistance region; and a second metal wire connected to a contact region of the other end of the first diffusion resistance region. The predetermined interval is an interval at which punch-through starts between the first diffusion resistance region and the second diffusion resistance region at a predetermined temperature while a predetermined voltage is kept applied. The predetermined length is a length along which a region in which punch-through is to be performed increases in accordance with a rise in temperature from the predetermined temperature and along which a path in which current flows increases.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置に関し、特に抵抗素子を含む半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a resistance element.

半導体装置における抵抗素子は、不純物を注入した多結晶シリコンを用いた抵抗だけではなく、半導体基板に形成された拡散抵抗も使用される。拡散抵抗は、半導体基板あるいはウェル領域とは異なる導電型の不純物を半導体基板に注入し、その不純物が拡散することで形成された領域を抵抗として使用するものである。一般的に、拡散抵抗は正の温度特性を有することが知られている。そのため、動作時の温度が高温になるほど抵抗値が増大してしまう。 As the resistance element in the semiconductor device, not only the resistance using polycrystalline silicon injected with impurities but also the diffusion resistance formed on the semiconductor substrate is used. The diffusion resistance is a resistor in which a conductive type impurity different from the semiconductor substrate or the well region is injected into the semiconductor substrate, and the region formed by diffusing the impurities is used as a resistor. Generally, diffusion resistance is known to have positive temperature characteristics. Therefore, the higher the operating temperature, the higher the resistance value.

特許文献１に開示された従来技術では、拡散抵抗のコンタクト部分から拡散抵抗と同じ導電型の拡散領域からなるバイパス線を設けている。そのバイパス線の一部を拡散抵抗に接近させ、局所的に近接部を設定し、高温時にその近接部でパンチスルーが起こるようにすることで、高温時に抵抗値を下げ、温度特性を改善している。 In the prior art disclosed in Patent Document 1, a bypass wire formed from the contact portion of the diffusion resistance and the same conductive type diffusion region as the diffusion resistance is provided. By making a part of the bypass line close to the diffusion resistance and locally setting the proximity part so that punch-through occurs in the vicinity part at high temperature, the resistance value is lowered at high temperature and the temperature characteristics are improved. ing.

特開平５―１０２３９７号公報Japanese Unexamined Patent Publication No. 5-102397

特許文献１に開示された従来技術では、パンチスルーが起こった後の抵抗値は一度不連続に減少し、さらに温度が上昇すると、再び抵抗値が増大するため、温度上昇に対して抵抗値を一定にできない。図８にこの様子を示す。縦軸は抵抗値であり、横軸は温度である。Ｔｐはパンチスルーが発生する温度を示している。 In the prior art disclosed in Patent Document 1, the resistance value after punch-through decreases once discontinuously, and when the temperature rises further, the resistance value increases again. It cannot be constant. This is shown in FIG. The vertical axis is the resistance value, and the horizontal axis is the temperature. Tp indicates the temperature at which punch-through occurs.

本発明は、所定の温度における抵抗値の変化が連続的であり、その後の温度上昇に伴う抵抗値の増大が抑制された拡散抵抗素子を提供することを目的とする。 An object of the present invention is to provide a diffusion resistance element in which a change in resistance value at a predetermined temperature is continuous and an increase in resistance value with a subsequent temperature rise is suppressed.

本発明の一実施形態に係る半導体装置は、半導体基板と、前記半導体基板に設けられた、前記半導体基板とは導電型が異なる第１の拡散抵抗領域と、前記第１の拡散抵抗領域と同じ導電型を有し、前記第１の拡散抵抗領域に対して、所定の間隔を設けて所定の長さにわたって配置された第２の拡散抵抗領域と、前記第１の拡散抵抗領域の一端及び他端、及び前記第２の拡散抵抗領域の少なくとも一端に設けられたコンタクト領域と、前記第１の拡散抵抗領域の一端のコンタクト領域と前記第２の拡散抵抗領域の一端のコンタクト領域とを接続する第１の金属配線と前記第１の拡散抵抗領域の他端のコンタクト領域に接続された第２の金属配線を備え、前記所定の間隔は、前記第１の金属配線と前記第２の金属配線との間に所定の電圧を印加した状態で、所定の温度において前記第１の拡散抵抗領域と前記第２の拡散抵抗領域の間でパンチスルーが開始する間隔であり、前記所定の長さは、前記所定の温度からの温度の上昇に応じて、パンチスルーする領域が拡大し、前記第２の拡散抵抗領域に流れる電流が増大する長さであることを特徴とする。 The semiconductor device according to the embodiment of the present invention is the same as the semiconductor substrate, the first diffusion resistance region provided on the semiconductor substrate and having a different conductive type from the semiconductor substrate, and the first diffusion resistance region. A second diffusion resistance region having a conductive type and arranged over a predetermined length with a predetermined interval with respect to the first diffusion resistance region, one end of the first diffusion resistance region, and the like. The contact region provided at the end and at least one end of the second diffusion resistance region is connected to the contact region at one end of the first diffusion resistance region and the contact region at one end of the second diffusion resistance region. The first metal wiring and the second metal wiring connected to the contact region at the other end of the first diffusion resistance region are provided, and the predetermined interval is the first metal wiring and the second metal wiring. The interval at which punch-through starts between the first diffusion resistance region and the second diffusion resistance region at a predetermined temperature with a predetermined voltage applied between the two, and the predetermined length is The punch-through region expands as the temperature rises from the predetermined temperature, and the current flowing through the second diffusion resistance region increases.

本発明によれば、第１の拡散抵抗領域と第２の拡散抵抗領域の間でパンチスルーする領域が温度上昇に伴って広がっていくため、パンチスルーを開始する所定の温度における抵抗値の変化は連続的になるとともに、温度上昇に伴う抵抗値の増大を抑制することが可能になる。 According to the present invention, the punch-through region between the first diffusion resistance region and the second diffusion resistance region expands as the temperature rises, so that the resistance value changes at a predetermined temperature at which punch-through starts. Is continuous, and it becomes possible to suppress an increase in resistance value due to an increase in temperature.

本発明の第１の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 1st Embodiment of this invention. 本発明の第２の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 2nd Embodiment of this invention. 本発明の第３の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 3rd Embodiment of this invention. 本発明の第４の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 4th Embodiment of this invention. 本発明の第５の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 5th Embodiment of this invention. 本発明の第６の実施形態の半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device of 6th Embodiment of this invention. 本発明の半導体装置における抵抗素子の温度特性を表すグラフである。It is a graph which shows the temperature characteristic of the resistance element in the semiconductor device of this invention. 先行技術の抵抗素子の温度特性を表すグラフである。It is a graph which shows the temperature characteristic of the resistance element of the prior art.

以下、図面を参照しながら、本発明を実施するための形態について詳細に説明する。
＜第１の実施形態＞
図１は、本発明の半導体装置の第１の実施形態に係る半導体装置の構造を示す平面図である。半導体装置は、一般に、能動素子を含む領域と抵抗素子を含む領域を有するが、簡略化のため、抵抗素子を含む領域の一部分のみを図示し、説明する。説明に関係しない酸化膜、絶縁膜等は省略してある。 Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment of the semiconductor device of the present invention. A semiconductor device generally has a region including an active element and a region including a resistance element, but for simplification, only a part of the region including the resistance element will be illustrated and described. Oxidizing film, insulating film, etc. that are not related to the explanation are omitted.

図１に示すように、半導体装置１００は、半導体基板１の表面近傍に設けられた、半導体基板１と同じ導電型を有し、不純物濃度が高く設定された基板の電位を設定するための基板コンタクト領域２と、半導体基板１の表面近傍に同様に設けられた、平面視では概ね長方形となり、半導体基板１とは異なる導電型を有する第１の拡散抵抗領域３と、第１の拡散抵抗領域３と同じ導電型を有し、第１の拡散抵抗領域３に対して、所定の間隔を設けて所定の長さにわたって配置された第２の拡散抵抗領域４を有する。 As shown in FIG. 1, the semiconductor device 100 has the same conductive type as the semiconductor substrate 1 provided near the surface of the semiconductor substrate 1, and is a substrate for setting the potential of the substrate with a high impurity concentration. A first diffusion resistance region 3 and a first diffusion resistance region, which are similarly provided near the surface of the contact region 2 and the semiconductor substrate 1, which are substantially rectangular in plan view and have a conductive type different from that of the semiconductor substrate 1. It has the same conductive type as No. 3, and has a second diffusion resistance region 4 arranged over a predetermined length with a predetermined interval with respect to the first diffusion resistance region 3.

第１の拡散抵抗領域３の一端及び他端、及び第２の拡散抵抗領域４の一端には第１の拡散抵抗領域３及び第２の拡散抵抗領域４よりも不純物濃度が高く設定されたコンタクト領域５が設けられており、第１の拡散抵抗領域３の一端のコンタクト領域５と第２の拡散抵抗領域４の一端のコンタクト領域５とを接続する第１の金属配線６と第１の拡散抵抗領域の他端のコンタクト領域に接続された第２の金属配線７があり、それぞれ電位を与えられるようになっている。 A contact in which one end and the other end of the first diffusion resistance region 3 and one end of the second diffusion resistance region 4 are set to have higher impurity concentrations than the first diffusion resistance region 3 and the second diffusion resistance region 4. A region 5 is provided, and a first metal wiring 6 and a first diffusion connecting a contact region 5 at one end of the first diffusion resistance region 3 and a contact region 5 at one end of the second diffusion resistance region 4 are provided. There is a second metal wire 7 connected to the contact region at the other end of the resistance region, and each of them can be given an electric potential.

ここで、所定の間隔とは、第１の金属配線６と第２の金属配線７との間に所定の電圧を印加した状態で、所定の温度において第１の拡散抵抗領域３と第２の拡散抵抗領域４の間でパンチスルーが開始する間隔であることを意味する。パンチスルーは第１の拡散領域３に属する第１の辺に沿った領域とこの辺に対向する第２の拡散領域４の第２の辺に沿った領域の間で発生する。また、所定の長さとは、所定の温度からの温度の上昇に応じて、パンチスルーする領域が拡大し、第２の拡散抵抗領域４に流れる電流が増大する長さであることを意味する。 Here, the predetermined interval means the first diffusion resistance region 3 and the second diffusion resistance region 3 and the second at a predetermined temperature in a state where a predetermined voltage is applied between the first metal wiring 6 and the second metal wiring 7. This means that there is an interval at which punch-through starts between the diffusion resistance regions 4. Punch-through occurs between a region along the first side belonging to the first diffusion region 3 and a region along the second side of the second diffusion region 4 facing this side. Further, the predetermined length means that the punch-through region expands as the temperature rises from the predetermined temperature, and the current flowing through the second diffusion resistance region 4 increases.

通常の抵抗素子は、拡散抵抗領域とその両端に設けられたコンタクト領域および金属配線からなっている。拡散抵抗領域は不純物濃度が相対的に低く、抵抗素子の抵抗値を実質的に定めている。両端に設けられたコンタクト領域は、抵抗素子に所定の電圧を印加するために他の回路要素と接続される金属配線との間に良好なオーミック接合を形成できるように不純物濃度が高くなっている。従って、半導体装置１００に含まれる抵抗素子は、通常の抵抗素子の一端の金属配線６を介して接続されたコンタクト領域５を有する拡散抵抗領域４を隣接する位置に追加的に有する形状を有しているとも言える。拡散抵抗領域４の他端はどこにも接続されていない。 A normal resistance element consists of a diffusion resistance region, contact regions provided at both ends thereof, and metal wiring. The diffusion resistance region has a relatively low impurity concentration, and substantially determines the resistance value of the resistance element. The contact regions provided at both ends have a high impurity concentration so that a good ohmic contact can be formed between the metal wiring connected to other circuit elements in order to apply a predetermined voltage to the resistance element. .. Therefore, the resistance element included in the semiconductor device 100 has a shape in which a diffusion resistance region 4 having a contact region 5 connected via a metal wiring 6 at one end of a normal resistance element is additionally provided at an adjacent position. It can be said that it is. The other end of the diffusion resistance region 4 is not connected anywhere.

次に、図２ａと図２ｂを用いて電圧印加時の上記所定の温度の前後における動作の説明を行う。図２ａは、所定の温度以下の状態を、図２ｂは所定の温度以上の状態をそれぞれ表している。図２ａおよび図２ｂには、第１の拡散抵抗領域３と、第２の拡散抵抗領域４と、コンタクト領域５と、第１の金属配線６と、第２の金属配線７と、第１の拡散抵抗領域３と半導体基板１の間に発生する第１の空乏層８と第２の拡散抵抗領域４と半導体基板１の間に発生する第２の空乏層９が示されている。図中の矢印Ａは、外部からの電圧の印加によって流れる電流の方向を示している。従って、この例では第２の金属配線７の電位の方が第１の金属配線６の電位よりも高くなっている。 Next, the operation before and after the above-mentioned predetermined temperature when the voltage is applied will be described with reference to FIGS. 2a and 2b. FIG. 2a shows a state of a predetermined temperature or lower, and FIG. 2b shows a state of a predetermined temperature or higher. 2a and 2b show a first diffusion resistance region 3, a second diffusion resistance region 4, a contact region 5, a first metal wiring 6, a second metal wiring 7, and a first. The first depletion layer 8 generated between the diffusion resistance region 3 and the semiconductor substrate 1 and the second depletion layer 9 generated between the second diffusion resistance region 4 and the semiconductor substrate 1 are shown. The arrow A in the figure indicates the direction of the current flowing due to the application of a voltage from the outside. Therefore, in this example, the potential of the second metal wiring 7 is higher than the potential of the first metal wiring 6.

図２ａに示されているように、所定の温度以下では、第１の拡散抵抗領域３にのみ電流は流れる。従って、温度の上昇とともに拡散抵抗領域３の抵抗値は上り、流れる電流は少なくなる。第１の空乏層８と第２の空乏層９とは離間しており、接触することはない。第１の空乏層８においては、第１の拡散領域３が電位勾配を有しているので、電位の高い第２の金属配線７の周囲において空乏層の横方向の広がりである幅が、電位の低い第１の金属配線６の周囲における空乏層の幅よりも大きくなっている。一方、第２の空乏層９においては第２の拡散領域４に電流が流れていないので、第２の拡散領域４の電位は低い電位に固定されていて、一定である。そのため、第２の空乏層９の幅も一定である。 As shown in FIG. 2a, below a predetermined temperature, a current flows only in the first diffusion resistance region 3. Therefore, as the temperature rises, the resistance value of the diffusion resistance region 3 rises, and the flowing current decreases. The first depletion layer 8 and the second depletion layer 9 are separated from each other and do not come into contact with each other. In the first depletion layer 8, since the first diffusion region 3 has a potential gradient, the width that is the lateral spread of the depletion layer around the second metal wiring 7 having a high potential is the potential. It is larger than the width of the depletion layer around the low first metal wiring 6. On the other hand, in the second depletion layer 9, since no current flows in the second diffusion region 4, the potential of the second diffusion region 4 is fixed at a low potential and is constant. Therefore, the width of the second depletion layer 9 is also constant.

一方、温度の上昇とともに空乏層は概ね絶対温度の平方根に比例して拡大するので、図２ｂに示されている所定の温度では、空乏層８と空乏層９が接する箇所が生じ、つながった空乏層を介して電流がながれるパンチスルーによる別の電流経路Ｂができる。図中では電流経路を示す矢印は２本しか表していないが、温度上昇に伴って空乏層はさらに広がっていくため、結果として温度上昇とともに電流経路も増加し広がるので、第２の拡散領域４を流れる電流が増加することになる。即ち、パンチスルーによる電流の増大が、抵抗値の上昇による電流の減少を打ち消すようになる。これは、温度上昇による抵抗値の変化が継続して繰り返されることになるので、所定の温度以上における抵抗値の増大を抑制することが可能になることを示している。 On the other hand, as the temperature rises, the depletion layer expands in proportion to the square root of the absolute temperature. Therefore, at the predetermined temperature shown in FIG. Another current path B is created by punch-through in which current flows through the layers. Although only two arrows indicating the current path are shown in the figure, the depletion layer further expands as the temperature rises, and as a result, the current path also increases and expands as the temperature rises. Therefore, the second diffusion region 4 The current flowing through the will increase. That is, the increase in the current due to punch-through cancels out the decrease in the current due to the increase in the resistance value. This indicates that since the change in the resistance value due to the temperature rise is continuously repeated, it is possible to suppress the increase in the resistance value at a predetermined temperature or higher.

図７と図８は、それぞれ本発明の第１の実施形態に係る抵抗素子を含む半導体素子と特許文献１に開示された先行技術における抵抗器の抵抗値と温度の関係を表すグラフである。これらのグラフにより両者の特性の違いを説明する。まず、本発明の第１の実施形態に係る抵抗素子を含む半導体素子においては、図７に示すように所定の温度をＴｐとすると、温度Ｔｐまでは抵抗値が上昇する。温度Ｔｐにおいてパンチスルーが発生し電流が第２の拡散領域４を流れるようになり、流れる電流の和が増加することにより見かけの抵抗値の上昇が抑制される。さらに温度が上昇してもあらたなパンチスルーが継続的に発生することで、第２の拡散領域４を流れる電流が継続的に増加し、抵抗値の上昇は抑制されたままとなる。このように、温度上昇による抵抗値の変化が連続的になり、かつ、所定の温度以上における抵抗値の増大を抑制することが可能である。一方、先行技術における抵抗器においては、図８に示すように、所定の温度Ｔにおいてでパンチスルーが発生し、バイパス線を通る電流が増えることで全体の電流が増加し、見かけの抵抗値の低下が起きるが、その変化は大きいので不連続であり、さらに温度が上昇すると抵抗値は再び増大するようになる。このように、特許文献１に開示された先行技術における抵抗器においては、所定の温度以上における抵抗値の増大を抑制することは困難である。 7 and 8 are graphs showing the relationship between the resistance value and the temperature of the semiconductor element including the resistance element according to the first embodiment of the present invention and the resistor in the prior art disclosed in Patent Document 1, respectively. The differences in the characteristics of the two will be explained using these graphs. First, in the semiconductor device including the resistance element according to the first embodiment of the present invention, when a predetermined temperature is Tp as shown in FIG. 7, the resistance value rises up to the temperature Tp. Punch-through occurs at the temperature Tp, the current flows through the second diffusion region 4, and the sum of the flowing currents increases, so that the apparent increase in resistance value is suppressed. Further, even if the temperature rises, new punch-through occurs continuously, so that the current flowing through the second diffusion region 4 continuously increases, and the increase in the resistance value remains suppressed. In this way, it is possible to continuously change the resistance value due to the temperature rise and suppress the increase in the resistance value at a predetermined temperature or higher. On the other hand, in the resistor in the prior art, as shown in FIG. 8, punch-through occurs at a predetermined temperature T, and the total current increases as the current passing through the bypass line increases, so that the apparent resistance value is increased. There is a decrease, but the change is so large that it is discontinuous, and as the temperature rises further, the resistance value increases again. As described above, in the resistor in the prior art disclosed in Patent Document 1, it is difficult to suppress the increase in the resistance value at a predetermined temperature or higher.

図３は本発明の第２の実施形態に係る半導体装置の構造を示す平面図である。
半導体装置２００は、第１の実施形態の半導体装置１００に対し、第１の拡散抵抗領域３と第２の拡散抵抗領域４との間に濃度調整領域１０を有する点が異なっている。濃度調整領域１０は、例えば、半導体基板１０と同じ導電型の不純物を半導体基板１０よりも多く含む不純物領域であっても良い。濃度調整領域１０の存在によって、空乏層８、及び空乏層９の伸び方をさらに調整することが可能となり、結果として、より所望の温度特性を得ることができる。 FIG. 3 is a plan view showing the structure of the semiconductor device according to the second embodiment of the present invention.
The semiconductor device 200 is different from the semiconductor device 100 of the first embodiment in that it has a concentration adjusting region 10 between the first diffusion resistance region 3 and the second diffusion resistance region 4. The concentration adjustment region 10 may be, for example, an impurity region containing more conductive impurities as the semiconductor substrate 10 than the semiconductor substrate 10. The presence of the concentration adjusting region 10 makes it possible to further adjust the elongation of the depletion layer 8 and the depletion layer 9, and as a result, more desired temperature characteristics can be obtained.

図４は本発明の第３の実施形態に係る半導体装置の構造を示す平面図である。
半導体装置３００は、第１の実施形態の半導体装置１００に対し、第２の拡散抵抗領域４が斜めに配置されている点が異なっている。半導体装置３００では、動作時における空乏層８、及び空乏層９の伸び方は第１の実施形態の半導体装置１００と同じであるが、第２の拡散抵抗領域４が斜めに配置されていることにより、金属配線７に近い領域ではパンチスルーが起こりにくくなる方向、金属配線６に近い領域ではパンチスルーが起こりやすくなる方向に斜めに傾いているので、パンチスルーの起こりやすさをさらに調整することが可能になる。結果として、より所望の温度特性を得ることができる。 FIG. 4 is a plan view showing the structure of the semiconductor device according to the third embodiment of the present invention.
The semiconductor device 300 is different from the semiconductor device 100 of the first embodiment in that the second diffusion resistance region 4 is arranged obliquely. In the semiconductor device 300, the depletion layer 8 and the depletion layer 9 are stretched in the same manner as in the semiconductor device 100 of the first embodiment during operation, but the second diffusion resistance region 4 is diagonally arranged. As a result, the punch-through is less likely to occur in the region close to the metal wiring 7, and the punch-through is more likely to occur in the region close to the metal wiring 6. Therefore, the likelihood of punch-through should be further adjusted. Becomes possible. As a result, more desired temperature characteristics can be obtained.

図５は本発明の第４の実施形態に係る半導体装置の構造を示す平面図である。
半導体装置４００は、第１の実施形態の半導体装置１００に対し、第２の拡散抵抗領域４の１辺（第１の拡散抵抗領域３側）が斜辺になっている点が異なっている。この斜辺によって、第３の実施形態の半導体装置３００と同様に、パンチスルーの起こりやすさを部分的に調整することが可能になる。さらに、第２の拡散抵抗領域４が細くなっている個所は、細くなっていない箇所に比べ、空乏化により拡散領域自体の濃度が低くなるため、空乏層８、及び空乏層９の伸ばし方を調整することが可能になり、結果として、より所望の温度特性を得ることができる。 FIG. 5 is a plan view showing the structure of the semiconductor device according to the fourth embodiment of the present invention.
The semiconductor device 400 is different from the semiconductor device 100 of the first embodiment in that one side of the second diffusion resistance region 4 (the first diffusion resistance region 3 side) is an oblique side. This hypotenuse makes it possible to partially adjust the likelihood of punch-through, as in the semiconductor device 300 of the third embodiment. Further, in the portion where the second diffusion resistance region 4 is thinned, the concentration of the diffusion region itself becomes lower due to depletion than in the portion where the second diffusion resistance region 4 is thinned. It becomes possible to adjust, and as a result, more desired temperature characteristics can be obtained.

図６は本発明の第５の実施形態の半導体装置の構造を示す平面図である。
第５の実施形態の半導体装置５００は、第１の実施形態の半導体装置に対し、第２の拡散抵抗領域４の１辺（第１の拡散抵抗領域３側）が階段状になっている点が異なっている。この形状によって、第３の実施形態の半導体装置３００と同様に、パンチスルーの起こりやすさを部分的に調整することが可能になる。さらに、第２の拡散抵抗領域４が細くなっている個所は、細くなっていない箇所に比べ、空乏化により拡散領域自体の濃度が低くなるため、空乏層８、及び空乏層９の伸ばし方を調整することが可能になり、結果として、より所望の温度特性を得ることができる。第４の実施形態の半導体装置４００との違いは、斜辺が存在しないため、微細プロセスにおけるマスク作成で用いられるＯＰＣ（ＯｐｔｉｃａｌＰｒｏｘｉｍｉｔｙＣｏｒｒｅｃｔｉｏｎ：光近接効果補正）処理を施しても、意図しない形状になりにくい。 FIG. 6 is a plan view showing the structure of the semiconductor device according to the fifth embodiment of the present invention.
The semiconductor device 500 of the fifth embodiment has a stepped shape on one side of the second diffusion resistance region 4 (the first diffusion resistance region 3 side) with respect to the semiconductor device of the first embodiment. Is different. This shape makes it possible to partially adjust the likelihood of punch-through, as in the semiconductor device 300 of the third embodiment. Further, in the portion where the second diffusion resistance region 4 is thinned, the concentration of the diffusion region itself becomes lower due to depletion than in the portion where the second diffusion resistance region 4 is thinned. It becomes possible to adjust, and as a result, more desired temperature characteristics can be obtained. The difference from the semiconductor device 400 of the fourth embodiment is that there are no hypotenuses, so even if OPC (Optical Proximity Correction) processing used for mask creation in a fine process is performed, the shape becomes unintended. Hateful.

以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されず、趣旨を逸脱しない範囲においては種々の変更が可能であることは言うまでもない。 Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments and various changes can be made without departing from the spirit.

１半導体基板
２基板コンタクト領域
３第１の拡散抵抗領域
４第２の拡散抵抗領域
５コンタクト領域
６第１の金属配線
７第２の金属配線
８第１の拡散抵抗領域と半導体基板の間の空乏層（第１の空乏層）
９第２の拡散抵抗領域と半導体基板の間の空乏層（第２の空乏層）
１０濃度調整領域 1 Semiconductor substrate 2 Substrate contact region 3 First diffusion resistance region 4 Second diffusion resistance region 5 Contact region 6 First metal wiring 7 Second metal wiring 8 Depletion between the first diffusion resistance region and the semiconductor substrate Layer (first depletion layer)
9 Depletion layer between the second diffusion resistance region and the semiconductor substrate (second depletion layer)
10 Concentration adjustment area

Claims

With a semiconductor substrate
A first diffusion resistance region provided on the semiconductor substrate, which has a different conductive type from the semiconductor substrate,
A second diffusion resistance region having the same conductive type as the first diffusion resistance region and arranged over a predetermined length with a predetermined interval with respect to the first diffusion resistance region.
A contact region provided at one end and the other end of the first diffusion resistance region and at least one end of the second diffusion resistance region.
Connected to the first metal wiring that connects the contact region at one end of the first diffusion resistance region and the contact region at one end of the second diffusion resistance region and the contact region at the other end of the first diffusion resistance region. With the second metal wiring
With
The predetermined interval is a state in which a predetermined voltage is applied between the first metal wiring and the second metal wiring, and the first diffusion resistance region and the second diffusion resistance are formed at a predetermined temperature. The interval at which punch-through starts between regions, and the predetermined length is a length at which the punch-through region expands and the current flow path increases as the temperature rises from the predetermined temperature. A semiconductor device including a resistance element.

The semiconductor device according to claim 1, wherein the semiconductor substrate is a well region.

The semiconductor device according to claim 1 or 2, wherein a concentration adjusting region is provided in the semiconductor substrate between the first diffusion resistance region and the second diffusion resistance region.

The semiconductor device according to claim 1 or 2, wherein the second diffusion resistance region is arranged obliquely.

The semiconductor device according to claim 1 or 2, wherein one side of the second diffusion resistance region on the first diffusion resistance region side is oblique.

The semiconductor device according to claim 1 or 2, wherein one side of the second diffusion resistance region on the first diffusion resistance region side is stepped.

With a semiconductor substrate
A first diffusion resistance region provided on the semiconductor substrate, which has a different conductive type from the semiconductor substrate,
A second diffusion resistance region having the same conductive type as the first diffusion resistance region and arranged adjacent to the first diffusion resistance region,
A contact region provided at one end and the other end of the first diffusion resistance region and one end of the second diffusion resistance region, and
Connected to the first metal wiring that connects the contact region at one end of the first diffusion resistance region and the contact region at one end of the second diffusion resistance region and the contact region at the other end of the first diffusion resistance region. With a second metal wiring,
The first side belonging to the first diffusion region and the second side belonging to the second diffusion region are opposed to each other.
In a state where a predetermined voltage is applied between the first metal wiring and the second metal wiring, in a first region along the first side and the second side at a first temperature. Punch-through occurs between the second regions along the line, and as the temperature rises from the first temperature, the first region and the second region are adjacent to each other up to the second temperature. By further punching through the region, the current flowing between the first metal wiring and the second metal wiring is kept constant between the first temperature and the second temperature. A semiconductor device including a resistance element.

The first diffusion region and the second diffusion region are provided apart so that the depletion layer in the first diffusion region and the depletion layer in the second diffusion region overlap at the first temperature. The semiconductor device according to claim 7.