JP7433094B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Semiconductor integrated circuits (ICs) are built into many types of electrical equipment, such as computers, smartphones, automobiles, and air conditioners, and are equipped with various elements (such as transistors, capacitors, inductance, and resistance elements) depending on their functions. It is composed of a combination of Resistance elements include metal resistors, diffused resistors, etc., and diffused resistors in particular are widely used in semiconductor ICs.

Generally, a diffused resistance consists of a P-type or N-type diffusion layer formed in a semiconductor, and a metal layer formed on different parts (for example, both ends) of the diffusion layer and used as an electrode or a pad. We are prepared. The diffusion layer is formed by implanting ion species into the semiconductor and performing heat treatment, and the resistance value of the diffusion resistor can be adjusted by adjusting the conditions of the ion implantation and heat treatment. However, in order to suppress the contact resistance at the interface between the diffusion layer and the metal layer or to form an ohmic contact between the diffusion layer and the metal layer, ion species implanted into the semiconductor and impurities at the interface between the diffusion layer and the metal layer are Various parameters such as concentration and material of the metal layer need to be appropriately set. Therefore, a technique for suppressing variations in the resistance value of the diffused resistor and adjusting the resistance value of the diffused resistor to a desired value is very important.

In addition, since the work functions of semiconductors and metals are different, depending on conditions such as the conductivity type (P-type or N-type) of the diffusion layer, impurity concentration, and film quality and thickness of the metal layer, the voltage applied to the diffusion resistor may vary. When the change in current is no longer linear. Furthermore, a reaction layer between the semiconductor and the metal is formed at the interface between the diffusion layer and the metal layer by heat treatment. For example, when an electrode made of Ti is formed on a semiconductor diffusion layer made of Si and heat treatment is performed, titanium silicide (TiSi ₂ ) is formed as a reaction film. Therefore, the conductivity type and impurity concentration of the diffusion layer, the quality and thickness of the metal film, and the temperature and time of the heat treatment after metal film formation must be adjusted so that the resistance value of the diffusion resistor becomes the desired value. be.

Various methods have been devised for forming metal layer electrodes on the diffusion layer. For example, in Patent Document 1, an aluminum electrode is formed on the diffusion layer via a thin silicon film, and then heat treatment is performed. Discloses a technology that reduces the contact resistance between the diffusion layer and the electrode by causing a silicon film to react with aluminum to form a low-resistance silicide while preventing aluminum spikes from protruding into the semiconductor layer of the diffusion layer. has been done.

Furthermore, in the following non-patent document 1, it is stated that when the heat treatment temperature for forming titanium silicide is set to a low temperature of about 400°C, the crystal structure of titanium silicide becomes a C49 structure, and when the temperature is set to a high temperature of about 800°C, the crystal structure of titanium silicide becomes a C49 structure. It is shown that the structure is C54 structure.

Patent No. 2730458

“On the problem of structural phase transition in titanium silicide process” Surface Science Vo1.16, No. 4, pp.233-237, 1995

As described above, a technique for suppressing variations in the resistance value of a diffused resistor and adjusting the resistance value to a desired value is very important.

The present disclosure has been made to solve such problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can suppress variations in the resistance value of a diffused resistor.

A semiconductor device according to the present disclosure includes: a first diffusion layer of a first conductivity type formed in a surface layer portion of a semiconductor substrate; a metal film connected to each of different locations on the first diffusion layer; a diffusion resistor having a reaction layer formed by a reaction between the semiconductor of the diffusion layer and the metal film, wherein the thickness of the reaction layer is L, and the thickness of the region under the reaction layer in the first diffusion layer. When the length is M, the relationship L<M<4L is satisfied.

According to the diffused resistance according to the present disclosure, the thickness L of the reaction layer and the thickness M of the region under the reaction layer in the diffusion layer satisfy the relationship L<M, so that a wide current path can be secured. This prevents the resistance value of the diffused resistor from becoming too high. Furthermore, by satisfying the relationship M<4L, the resistance value of the diffused resistor is prevented from becoming too low. Therefore, variations in the resistance value of the diffused resistor are suppressed, and the resistance value of the diffused resistor can be controlled with high precision.

1 is a plan view of a diffused resistor according to Embodiment 1. FIG. 1 is a cross-sectional view of a diffused resistor according to Embodiment 1. FIG. FIG. 3 is an enlarged view of a connection portion between a diffusion layer and a metal film in the diffused resistor according to the first embodiment. FIG. 3 is a diagram for explaining the thickness of a silicide layer and a diffusion layer thereunder. 3 is a diagram showing an IV curve of contact resistance between a diffusion layer and a metal layer in the diffused resistor according to the first embodiment. FIG. FIG. 7 is a diagram showing an IV curve of contact resistance between a diffused layer and a metal layer in a diffused resistor of a comparative example. FIG. 3 is a plan view for explaining a process of forming a diffused resistor according to Embodiment 1. FIG. FIG. 3 is a cross-sectional view for explaining a process of forming a diffused resistor according to the first embodiment. FIG. 3 is a cross-sectional view for explaining a process of forming a diffused resistor according to the first embodiment. FIG. 3 is a cross-sectional view of a diffused resistor according to a second embodiment. FIG. 3 is a diagram showing the relationship between heat treatment temperature and variation in resistance value of diffused resistors. It is a figure which shows the nanobeam electron diffraction pattern of three points of the same cross section in _TiSi2 formed by the heat treatment of 680 degreeC or more and 740 degreeC or less. FIG. 3 is a diagram showing three-point nanobeam electron diffraction patterns of the same cross section in TiSi ₂ formed by heat treatment at a temperature higher than 800°C.

<Embodiment 1>
FIG. 1 is a plan view of a diffused resistor 100 included in the semiconductor device according to the first embodiment. The diffused resistor 100 is composed of a plurality of unit diffused resistors 10 connected in series, and each of the unit diffused resistors 10 is a diffusion layer that is a first diffusion layer of a first conductivity type formed in the semiconductor substrate 1. 2, and a pair of metal films 3 connected to mutually different locations on the diffusion layer 2 (here, both ends). Each of the metal films 3 is formed spanning two adjacent diffusion layers 2, whereby the diffusion layers 2 of the plurality of unit diffused resistors 10 are connected in series via the metal film 3. However, the metal films 3 provided at the outer ends of the diffusion layer 2 at both ends constitute pads 3a and 3b for connecting wires and the like, respectively.

Note that the conductivity type (first conductivity type) of the diffusion layer 2 may be P type or N type. Here, the material of the semiconductor substrate 1 is silicon (Si), but the material of the semiconductor substrate 1 may be another semiconductor, such as a wide bandgap semiconductor such as SiC or GaN. When a wide bandgap semiconductor is used as the material for the semiconductor substrate 1, a diffused resistor 100 with excellent characteristics at high voltage, large current, and high temperature can be obtained compared to when silicon is used. Further, the diffused resistor 100 does not necessarily have to include a plurality of unit diffused resistors 10, and may be composed of one unit diffused resistor 10.

FIG. 2 is a cross-sectional view of the diffused resistor 100 according to the first embodiment, and corresponds to a cross section taken along the line A1-A2 shown in FIG. That is, FIG. 2 shows the cross-sectional structure of one unit diffused resistor 10 in the length direction.

As shown in FIG. 2, the diffusion layer 2 of the unit diffused resistor 10 is formed on the surface layer of the semiconductor substrate 1. Further, although not shown in FIG. 1, an insulating layer 6 is formed on the semiconductor substrate 1. An opening reaching the upper surface of the diffusion layer 2 is formed in the insulating layer 6, and the metal film 3 is embedded in the opening. The metal film 3 has a barrier metal layer 3c on its lower surface that prevents the metal of the metal film 3 from diffusing into the semiconductor substrate 1. A silicide layer 5, which is a reaction layer formed by reaction between the semiconductor of the diffusion layer 2 and the metal film 3 (barrier metal layer 3c), is formed at the connection portion of the diffusion layer 2 with the metal film 3.

In the first embodiment, a Ti/TiN film formed by stacking TiN on a Ti film is used as the barrier metal layer 3c. However, the barrier metal layer 3c is not limited to the Ti/TiN film, and may be any metal that reacts with the silicon semiconductor substrate 1 to form the silicide layer 5, such as Co, Ni, Pt, Ta, or W, for example.

For example, when a higher voltage is applied to the pad 3a shown in FIG. 1 than to the pad 3b, the unit diffused resistor 10 shown in FIG. A current flows within the diffusion layer 2.

The resistance component of the unit diffused resistor 10 will be explained. The resistance value R of the unit diffused resistor 10 is determined by R _M representing the resistance of the metal film 3 (including the barrier metal layer 3c), R _D representing the resistance of the diffusion layer 2, and contact resistance between the metal film 3 and the diffusion layer 2 ( (resistance of silicide layer 5, etc.) is expressed as R = 2R _M + R _D + 2R _C (Since the unit diffused resistor 10 _has two metal films 3, R _M and R _C are each doubled. ing). Usually, among R _M , R _D , and R _C , R _D is the largest and dominant, and R _M is the smallest and hardly affects the resistance value R of the unit diffused resistor 10 . Since R _C is affected by the reaction between the metal film 3 and the diffusion layer 2, it is difficult to control the resistance value, which causes the resistance value R of the unit diffused resistor 10 to vary.

FIG. 3 is an enlarged view of the connecting portion between the diffusion layer 2 and the metal film 3. Hereinafter, with reference to FIG. 3, the contact resistance R _C between the metal film 3 and the diffusion layer 2 will be further analyzed. The contact resistance R _C is determined by R _C1 representing the resistance of the silicide layer 5, R _C2 representing the resistance at the interface between the silicide layer 5 and the diffusion layer 2, and a region 2a under the silicide layer 5 in the diffusion layer 2 (encircled by a dotted line in FIG. 3). When the resistance of the region) is R _C3 , it is expressed as R _C =R _C1 +R _C2 +R _C3 . Hereinafter, the region 2a under the silicide layer 5 in the diffusion layer 2 may be simply referred to as "region 2a."

The current flows in the direction shown by the arrow in FIG. 3, and the smaller the thickness M of the region 2a, the narrower the current path (path of conduction carriers in the metal film 3). Therefore, the resistance R _C3 of the region 2a is It is inversely proportional to the thickness M of 2a. In other words, there is a relationship of R _C3 ∝1/M between the resistance R _C3 of the region 2a and the thickness M of the region 2a. Therefore, as the thickness M of the region 2a decreases, the resistance _RC3 of the region 2a increases, and if M=0, the resistance _RC3 of the region 2a becomes infinite and loses its ability to flow current.

The values of the thickness L of the silicide layer 5 and the thickness M of the region 2a vary due to variations in processes such as ion implantation and subsequent heat treatment during the manufacturing process of the diffused resistor 100, and as a result, the resistance R of the region 2a Variations occur in _C3 . When the resistance R _C3 of the region 2a varies, the resistance R of the unit diffused resistor 10 also varies, and the stability of the resistance value of the entire diffused resistor 100 decreases.

To solve this problem, in the diffused resistor 100 according to the first embodiment, the thickness L of the silicide layer 5 and the thickness M of the region 2a are set to satisfy the relationship L<M<4L. Here, the thickness L of the silicide layer 5 and the thickness M of the region 2a are defined as the thickness where M/L is the minimum. For example, when the shape of the silicide layer 5 is not uniform as shown in FIG. 4, the location where M/L is minimum is the location where the silicide layer 5 is thickest, and L and M are defined at that location.

Since the thickness M of the region 2a is large enough to satisfy the relationship L<M, fluctuations in the resistance R _C3 of the region 2a caused by variations in the thickness L of the silicide layer 5 are reduced. This prevents the resistance value of the unit diffused resistor 10 from becoming too high when it is formed thicker than the designed value. Moreover, by not increasing the thickness M of the region 2a excessively and suppressing it to an extent that satisfies M<4L, the resistance value of the unit diffused resistor 10 is prevented from becoming too low. Therefore, by satisfying L<M<4L, variations in the contact resistance R _C between the metal film 3 and the diffusion layer 2 are suppressed. This suppresses variations in the resistance value of the unit diffused resistor 10, and as a result, the stability of the resistance value of the entire diffused resistor 100 is improved.

FIGS. 5 and 6 are graphs showing current-voltage curves (IV curves) of contact resistance between the diffusion layer and the silicide layer in actually created diffusion resistors. FIG. 5 shows the IV curve of the diffused resistance of the first embodiment that satisfies the relationship L<M<4L, and FIG. 6 shows the IV curve of the diffused resistance of the comparative example that satisfies the relationship L>M. There is. Each of FIGS. 5 and 6 shows contact resistance IV curves of eight unit diffused resistors incorporated into one diffused resistor. Further, in FIGS. 6 and 5, the scales of the horizontal and vertical axes are the same. The IV curve of the contact resistance of the diffused resistor in the comparative example (FIG. 6) has various slopes and the resistance value varies, whereas the slope of the IV curve of the contact resistance of the diffused resistor in Embodiment 1 is almost constant. It can be seen that the resistance value is stable.

A method for manufacturing the diffused resistor 100 according to the first embodiment will be described below. Here, it is assumed that the material of the semiconductor substrate 1 is Si and that the diffusion layer 2 is of P type.

First, the semiconductor substrate 1 is cleaned with a chemical solution to remove the natural oxide film and foreign matter on the surface of the semiconductor substrate 1, and then the semiconductor substrate 1 is placed in a diffusion furnace and heat-treated to form a thin oxide layer on the semiconductor substrate 1. A film 21 is formed. The oxide film 21 is for preventing damage to the semiconductor substrate 1 due to ion implantation for forming the diffusion layer 2, and its thickness may be approximately several hundred Å.

Next, a resist is applied and formed on the semiconductor substrate 1 on which the oxide film 21 is formed, and by exposing and developing the resist, an opening is formed in the formation region of the diffusion layer 2, as shown in the plan view of FIG. A resist pattern 22 is formed. Then, using the resist pattern 22 as a mask, a P-type dopant such as boron (B) is ion-implanted to form a diffusion layer 2 in the upper layer of the semiconductor substrate 1. Thereafter, heat treatment is performed to activate the implanted ion species. The temperature and time of this heat treatment are determined according to the target value (design value) of the resistance value of the diffused resistor 100.

After removing the resist pattern 22, the semiconductor substrate 1 is covered with an insulating layer 6. Then, by coating and forming a resist on the insulating layer 6 and exposing and developing the resist, a resist pattern having an opening in the region where the metal film 3 is formed (the region where the metal film 3 is connected to the diffusion layer 2) is formed. Form. Thereafter, by wet etching and dry etching using the resist pattern as a mask, an opening reaching the upper surface of the diffusion layer 2 is formed in the insulating layer 6, as shown in the cross-sectional view of FIG.

Subsequently, as shown in the cross-sectional view of FIG. 9, a Ti/TiN layer is formed on the semiconductor substrate 1 by, for example, a sputtering method to form a barrier metal layer 3c, and a layer of AlSi, AlCu, AlSiCu, etc. is formed on the barrier metal layer 3c. The metal film 3 is formed by depositing. As described above, the barrier metal layer 3c is not limited to Ti/TiN, but may be Co, Ni, Pt, Ta, W, or the like. Further, as the material of the metal film 3, for example, AlSi, AlCu, AlSiCu, etc. can be used.

Thereafter, heat treatment is performed to cause the Ti of the barrier metal layer 3c of the metal film 3 to react with the Si of the semiconductor substrate 1, thereby forming a silicide layer 5 made of _TiSi2 . At this time, the thickness L of the silicide layer 5 and the thickness M of the region 2a under the silicide layer 5 in the diffusion layer 2 are made to satisfy the relationship L<M<4L. For example, if it is desired to make the silicide layer 5 thicker, it is necessary to form the diffusion layer 2 that much deeper in advance.

Then, by removing unnecessary metal film 3 on the upper surface of insulating layer 6, diffused resistor 100 having the structure shown in FIGS. 1 and 2 is completed.

<Embodiment 2>
In the diffused resistor 100 of the first embodiment, for example, when the diffusion layer 2 is of P type, it is desirable that the semiconductor substrate 1 is an N type substrate. However, in an integrated circuit, both the diffused resistor 100 made of the P-type diffusion layer 2 and the diffused resistor 100 made of the N-type diffused layer 2 may be formed on the semiconductor substrate 1. For example, the P-type semiconductor substrate 1 It is also conceivable that a diffused resistor 100 made of a P-type diffused layer 2 is formed inside. In such a case, there is a risk that a leakage current flowing from the diffusion layer 2 to the semiconductor substrate 1 will occur. When a leakage current occurs, it causes a problem because the substantial resistance value of the diffusion layer 2 changes.

FIG. 10 is a cross-sectional view of a diffused resistor 100 according to the second embodiment. Similar to FIG. 2, FIG. 10 also corresponds to a cross section taken along the line A1-A2 shown in FIG. 1, and shows the cross-sectional structure of one unit diffused resistor 10 in the length direction.

Diffused resistor 100 of Embodiment 2 is a second diffusion layer formed in the surface layer of semiconductor substrate 1 and having a conductivity type opposite to that of diffusion layer 2 (second conductivity type), in contrast to the configuration shown in FIG. A diffusion layer 7 of opposite conductivity type is added. That is, when the diffusion layer 2 is of the P type, the opposite conductivity type diffusion layer 7 is of the N type, and when the diffusion layer 2 is of the N type, the opposite conductivity type of the diffusion layer 7 is of the P type. The diffusion layer 2 is formed within the opposite conductivity type diffusion layer 7. The thickness (depth) of the opposite conductivity type diffusion layer 7 may be about 1 to 6 μm, but it needs to be thicker than the diffusion layer 2.

The configuration of the diffused resistor 100 of the second embodiment is the same as that of the first embodiment except that the opposite conductivity type diffusion layer 7 is added. That is, also in the diffused resistor 100 of the second embodiment, the thickness L of the silicide layer 5 and the thickness M of the region 2a in the unit diffused resistor 10 are set so as to satisfy the relationship L<M<4L. .

In the diffused resistor 100 (FIG. 10) of the second embodiment, since a PN junction is formed between the diffusion layer 2 and the opposite conductivity type diffusion layer 7, the opposite conductivity type is formed so that the PN junction is always reverse biased. By adjusting the potential of the diffusion layer 7, current leakage from the diffusion layer 2 can be suppressed. For example, if the diffusion layer 2 is P type and the opposite conductivity type diffusion layer 7 is N type, the potential of the opposite conductivity type diffusion layer 7 should be set higher than the potential of the higher potential side of the pads 3a and 3b. Bye. Conversely, when the diffusion layer 2 is N type and the opposite conductivity type diffusion layer 7 is P type, the potential of the opposite conductivity type diffusion layer 7 is set to be lower than the potential of the lower potential side of the pads 3a and 3b. do it. Thereby, changes in the resistance value of the diffused resistor 100 due to leakage current can be prevented, and the resistance value of the diffused resistor 100 can be set with higher accuracy.

A method for manufacturing the diffused resistor 100 according to the second embodiment will be described below. Here again, it is assumed that the material of the semiconductor substrate 1 is Si and that the diffusion layer 2 is of P type.

First, as in Embodiment 1, after cleaning the semiconductor substrate 1, heat treatment is performed on the semiconductor substrate 1 to form a thin oxide film on the semiconductor substrate 1 to prevent damage caused by ion implantation.

Next, a resist is applied onto the semiconductor substrate 1, and the resist is exposed and developed to form a resist pattern having an opening in the region where the opposite conductivity type diffusion layer 7 is to be formed. Then, using the resist pattern as a mask, ions of N-type dopants such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi) are implanted into the semiconductor substrate. A diffusion layer 7 of opposite conductivity type is formed. Thereafter, heat treatment is performed to activate the implanted ion species.

Thereafter, the diffusion layer 2 is formed in the opposite conductivity type diffusion layer 7 using the same method as in the first embodiment. Further, in the same manner as in Embodiment 1, an insulating layer 6 having an opening reaching the diffusion layer 2 is formed, a metal film 3 having a barrier metal layer 3c is formed in the opening, and a barrier metal layer 3c of the metal film 3 is formed. By reacting the layer 3c and the semiconductor substrate 1 to form the silicide layer 5, the diffused resistor 100 shown in FIG. 10 is obtained.

<Embodiment 3>
In the third embodiment, in the diffused resistor 100 of the first or second embodiment, the silicide layer 5 is made of TiSi ₂ with a C49 structure. Since TiSi ₂ with C49 structure is formed by heat treatment at a relatively low temperature, high film thickness uniformity can be obtained. Therefore, by using TiSi ₂ with C49 structure as the silicide layer 5, Variations in the resistance value of the diffused resistor 100 are suppressed. Note that in this embodiment, the entire crystal structure of the silicide layer 5 (reaction layer) does not need to be the C49 structure, and the silicide layer 5 may be mainly composed of _TiSi2 having a C49 crystal structure. good. For example, the silicide layer 5 may contain about 5% of TiSi ₂ having a C54 structure.

As described in the first embodiment, if the thickness L of the silicide layer 5 and the thickness M of the region 2a satisfy the relationship L<M<4L, variations in the resistance value of the unit diffused resistor 10 can be suppressed. I can do it. However, when decreasing the thickness K (see FIG. 3) of the diffusion layer 2 in order to increase the resistance value of the unit diffused resistor 10, it is necessary to form the silicide layer 5 thinly in order to obtain the relationship L<M. There is. Even in such a case, if the silicide layer 5 is made of TiSi ₂ with a C49 structure, the thickness L of the silicide layer 5 can be adjusted with high accuracy, and the relationship L<M can be more reliably obtained. Furthermore, when the diffused resistor 100 is incorporated into an integrated circuit that requires current to flow through the surface of the semiconductor substrate 1, the thickness K of the diffused layer 2 needs to be reduced, so the silicide layer 5 is replaced with TiSi ₂ having a C49 structure. It is effective to do so. As shown in Non-Patent Document 1, the resistivity of the C49 structure as a TiSi ₂ crystal is higher than that of the C54 structure, but as mentioned above, the thickness of the region 2a under the silicide layer 5 in the diffusion layer 2 By increasing M, the resistance of the diffusion layer 2 can be lowered.

The method for manufacturing a semiconductor device according to the third embodiment is basically the same as that in the first or second embodiment, except that Ti of the metal film 3 (barrier metal layer 3c) and Si of the semiconductor substrate 1 are made to react. In the step of forming the silicide layer 5 made of TiSi ₂ , it is necessary to form TiSi ₂ with a C49 structure. As shown in the above-mentioned Non-Patent Document 1, when the heat treatment temperature is set to a high temperature of about 800° C., the crystal structure of TiSi ₂ transforms to the C54 structure. Therefore, in the present embodiment, the temperature of the heat treatment for forming the silicide layer 5 is set to 680° C. or higher and 740° C. or lower, thereby forming the silicide layer 5 made of TiSi ₂ having a C49 structure.

FIG. 11 is a graph showing the relationship between the temperature of the heat treatment for forming the silicide layer 5 of TiSi ₂ and the variation in the resistance value of the silicide layer 5 formed. TiSi ₂ having a C49 structure has higher film thickness uniformity than TiSi ₂ having a C54 structure, and therefore has smaller variations in resistance value. As shown in Figure 11, when the heat treatment temperature is between 680°C and 740°C, C49 structure _TiSi2 with small resistance variation is formed, and when it is above 800°C, C54 structure TiSi2 with large resistance value variation is formed. It can be seen that ₂ is formed.

FIG. 12 shows a nanobeam electron diffraction pattern at three points on the same cross section of the silicide layer 5 made of TiSi ₂ formed by heat treatment at 680° C. or higher and 740° C. or lower. Moreover, FIG. 13 is a three-point nanobeam electron diffraction pattern of the same cross section of the silicide layer 5 made of TiSi ₂ formed by heat treatment at a temperature higher than 800° C. From the values of these diffraction patterns, it can be seen that TiSi ₂ has a C49 structure in FIG. 12 and that TiSi ₂ has a C54 structure in FIG. 13.

Note that it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

100 diffused resistance, 10 unit diffused resistance, 1 semiconductor substrate, 2 diffused layer, 2a region under the silicide layer in the diffused layer, 3 metal film, 3a, 3b pad, 3c barrier metal layer, 5 silicide layer, 6 insulating layer, 7 Opposite conductivity type diffusion layer, 21 oxide film, 22 resist pattern.

Claims (4)

a first diffusion layer of a first conductivity type formed in a surface layer of a semiconductor substrate;
a metal film connected to each of different locations on the first diffusion layer;
a reaction layer formed by a reaction between the semiconductor of the first diffusion layer and the metal film;
equipped with a diffused resistance having
When the thickness of the reaction layer is L and the thickness of the region under the reaction layer in the first diffusion layer is M, the relationship L<M<4L is satisfied.
Semiconductor equipment. further comprising a second diffusion layer of a second conductivity type formed in a surface layer portion of the semiconductor substrate,
the first diffusion layer is formed within the second diffusion layer,
The semiconductor device according to claim 1. The semiconductor substrate includes Si,
The metal film contains Ti,
The reaction layer is _TiSi2 having a C49 crystal structure.
The semiconductor device according to claim 1 or 2. a step of forming a diffusion layer in a surface layer portion of a semiconductor substrate containing Si;
forming a metal film containing Ti at different locations on the diffusion layer;
By heat treatment at 680° C. or higher and 740° C. or lower, Si in the diffusion layer and Ti in the metal film are reacted to form a reaction layer made of TiSi ₂ , thereby removing the diffusion layer, the metal film, and the reaction layer. a step of forming a diffused resistor ,
Equipped with
When the thickness of the reaction layer is L and the thickness of the region under the reaction layer in the diffusion layer is M, the relationship L<M<4L is satisfied.
A method for manufacturing a semiconductor device.

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