JP2011124502A - Resistive element, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: a conventional resistive element using a polysilicon layer for a resistance layer cannot provide desired sheet resistance when the sheet resistance of the resistive element is intended to be increased to, for instance, 10 MΩ/square or higher, the cause thereof may be attributed to charging of an insulating film on the polysilicon layer during a manufacturing process, and thereby only sheet resistance lower by two or more digits than a design value can be obtained; and dispersion of resistance layers is increased on a resistive element basis even in the same wafer. <P>SOLUTION: In this resistive element using a polysilicon layer for a resistance layer, a protective layer is formed on an insulating film covering the resistance layer. The protective layer is a metal layer, and can be formed with a wiring layer of the resistive element, or a metal layer identical to a metal layer of an electrode or the like. The protective layer is formed in a pattern with a bent part of the polysilicon layer exposed therefrom. Fixed potential is applied to the protective layer. Different sheet resistance is provided in accordance with the fixed potential. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a resistance element and a method for manufacturing the same, and more particularly to a resistance element that achieves a high sheet resistance of 10 MΩ / □ or more in a resistance element having a polysilicon layer as a resistance layer, and a method for manufacturing the same.

  As a resistance element integrated with an active element or the like on a semiconductor substrate, a resistance element using a polysilicon layer is known.

  FIG. 9 is a cross-sectional view showing a conventional resistance element 50.

  A polysilicon layer 53 doped with impurities is provided on the semiconductor substrate 51 via an insulating film 52. The polysilicon layer 53 is designed so as to obtain a desired sheet resistance depending on its shape (length and width) and the doped impurity concentration.

  The polysilicon layer 53 is covered with an insulating film 54, and a desired position is opened to provide a high-concentration impurity region 55, and a first wiring layer 57 and a second wiring layer 58 connected to an active element or the like (for example, Patent Document 1).

  With reference to FIG. 10, the manufacturing method of said resistance element is as follows.

An insulating film 52 is formed on the semiconductor substrate 51, and a polysilicon layer 53 is deposited. Impurities (for example, phosphorus (P), dose: about 1E13 cm ⁻² ) are introduced into the polysilicon layer 53. The polysilicon layer 53 is patterned into a desired shape by a photolithography process (FIG. 10A).

  The polysilicon layer 53 is covered with an insulating film 54, and an opening is provided at a desired position. Impurities are implanted into the openings to form high concentration impurity regions 55. Thereafter, a metal layer 56 such as an aluminum layer is formed on the entire surface, a resist mask M6 is provided on the first wiring layer 57 and the second wiring layer 57 by a photolithography process, and dry etching is performed (FIG. 10B). Thereby, the metal layer 56 is patterned, and the first wiring layer 57 and the second wiring layer 58 are formed. Thereafter, the resist mask PR is removed by O 2 plasma ashing or the like (FIG. 10C).

JP 2009-38100 A

  The conventional resistance element 50 using the polysilicon layer 53 as a resistance layer has a problem that a desired sheet resistance cannot be obtained when it is desired to increase the sheet resistance of the polysilicon layer 53 to, for example, 10 MΩ / □ or more.

  The reason was considered as follows. Both ends of the resistance element 50 are provided with metal layers (aluminum layers) 56 serving as electrodes or wirings. After the metal layer 56 is provided on the entire surface of the resistance element 50, a resist mask PR is provided so as to leave only a necessary shape as an electrode or a wiring, and then the metal layer 56 is patterned. That is, in the region where the resist mask PR is not provided, the characteristics may vary due to the influence of dry etching of the metal layer 56 or O2 plasma ashing for removing the resist mask PR.

  Specifically, when the first wiring layer 57 and the second wiring layer 58 are formed at both ends of the resistance element 50, a resist is formed on the insulating film 54 on the polysilicon layer 53 extending between the two electrodes. The mask PR is not provided (see FIG. 10B).

  When dry etching of the metal layer 56 is performed in this state, positive charges enter the insulating film (eg, oxide film) 54 at the final stage of dry etching, and the insulating film is charged. Also, O2 plasma ashing when removing the resist mask M6 (FIG. 10C) also causes positive charges to enter the insulating film 54, which also charges the insulating film 54.

  FIG. 11 is a cross-sectional view showing how the insulating film 54 is charged in the final structure. When the insulating film 54 is charged, the surface (exposed side) is positively polarized, and the side in contact with the polysilicon layer is negatively polarized.

  Due to the influence of charges in the polarized insulating film 54, electrons near the surface of the polysilicon layer 53 are driven downward, a depleted region 61 is generated near the surface, and electrons are accumulated in the polysilicon layer 53 at a high concentration. A region 62 appears. In the polysilicon layer 53 having a thickness of about 5000 mm, the resistance decrease due to the region 62 in which electrons are accumulated at a higher concentration is superior to the resistance that is increased by narrowing the current path due to the depleted region 61, and the electrons are accumulated at a higher concentration. It is considered that the sheet resistance of the resistance element 50 decreases because the specific resistance of the polysilicon decreases in the region 62.

  Specifically, even when trying to obtain a high sheet resistance of 10 MΩ / □ or more with the resistance layer formed of the polysilicon layer 53, only a sheet resistance smaller than the design value by two digits or more was obtained. In such a case, the pattern of the polysilicon layer had to be lengthened, and a considerable occupation area had to be secured on the chip.

  Further, when a plurality of resistance elements 50a and 50b having different sheet resistances are arranged on the same semiconductor substrate (chip), it is necessary to make the impurity concentration doped in the polysilicon layer 53 different.

  FIG. 12 is a diagram showing a manufacturing process of a plurality of conventional resistance layers 53a and 53b, which will be described. In the manufacturing process, it is necessary to pattern the polysilicon layer 53 after doping with impurities. In order to obtain the resistance layers 53a and 53b having different sheet resistances, a mask M7 having an opening in a desired region is provided and ion implantation is performed ( 12A, a plurality of ion implantation steps in which the mask M7 is removed, a new mask M8 having an opening in another region is provided, and ion implantation is performed under other conditions (FIG. 12B), and impurity diffusion is performed. It was necessary to go through.

  In this case, the impurities diffuse as indicated by broken lines in FIG. 12C, and differ from each other due to the lateral diffusion of impurities (diffusion in the horizontal direction with respect to the substrate surface) at the ends of the adjacent resistance layers 53a and 53b. May be affected by concentration of impurities. Therefore, the distance after patterning needs to be separated by a predetermined distance L ′.

  Specifically, when patterning the polysilicon layer 53 in a subsequent process, the distance L ′ between the resistance layers 53a and 53b is 10 μm or more (the thickness of the polysilicon layer) even if the end portion where the impurity concentration fluctuates is removed. In the case of 5,000 mm).

  For this reason, there is a limit to miniaturization of the resistance elements 0a and 50b on the chip, and there is a problem that the chip size cannot be reduced.

  Furthermore, the photolithography process and the ion implantation process are required a plurality of times (for the number of resistance elements) in the manufacturing process, and there is a problem that the number of processes increases.

  The present invention has been made in view of the various circumstances described above. First, a semiconductor substrate, a first insulating film provided on the semiconductor substrate, and a linear portion provided on the first insulating film. And a polysilicon layer into which impurities are introduced, a first wiring layer in contact with one end of the polysilicon layer, and a contact with the other end of the polysilicon layer apart from the first wiring layer The bent portion is exposed on the second wiring layer, the second insulating film provided on the polysilicon layer, and the polysilicon layer extending between the first wiring layer and the second wiring layer. Thus, the problem is solved by including a protective layer provided via the second insulating film.

  Second, a step of forming a first insulating film on a semiconductor substrate, a step of forming a polysilicon layer having a straight portion and a bent portion on which impurities are introduced, and the polysilicon. Forming a second insulating film on the layer; forming a first opening and a second opening in which part of the polysilicon layer is exposed on a part of the second insulating film; Forming a protective layer via the second insulating film so that the bent portion is exposed on the polysilicon layer extending between the first opening and the second opening. It solves by.

  According to this embodiment, the following effects can be obtained.

  First, by covering the upper side of the resistance layer of the resistance element with a protective layer, the influence of the charging on the resistance layer by dry etching for patterning a metal layer such as an electrode of the resistance element or O2 plasma ashing for removing the resist mask is affected. It can be greatly reduced. Thereby, a high sheet resistance of 10 MΩ / □ or more can be ensured.

  At this time, in the resistance layer having the straight portion and the bent portion, if the protective layer is also provided in the bent portion having many fluctuation factors, the sheet resistance is increased in the bent portion. That is, when the sheet resistance fluctuates in the bent portion, there is a problem that the fluctuation of the entire resistance layer is increased.

  Therefore, the sheet resistance of the bent portion is reduced by exposing the bent portion without providing a protective layer in the bent portion. Even when the sheet resistance of the bent portion varies due to various fluctuation factors, since the sheet resistance of this portion is small, the influence on the entire resistance layer can be reduced.

  Second, a desired sheet resistance can be obtained by applying a desired fixed potential to the protective layer, and the sheet resistance can be adjusted by applying a fixed potential. Can be reduced.

  Third, one resistor element having a polysilicon layer with the same impurity concentration and another resistor element are provided on the same semiconductor substrate, and different potentials are applied to the respective protective layers, thereby being integrated on the same substrate. Different sheet resistances can be provided in the plurality of resistance elements.

  Conventionally, in order to obtain resistance layers having different sheet resistances, the impurity concentration doped in the polysilicon layer is made different, and the polysilicon layer has to be separated by a predetermined distance (for example, 10 μm or more). It was not possible to reduce the size.

  However, according to the present embodiment, a plurality of resistance layers can be obtained even with a polysilicon layer formed under the same impurity implantation conditions, so that the separation distance of the polysilicon layer can be reduced, and the chip can be reduced by downsizing the resistance element. The upper occupied area can be reduced.

  Fourth, the protective layer covering the resistance layer is the same metal layer as the metal layer that becomes the electrode or wiring of the resistance element, and can be formed only by changing the patterning mask of the electrode or wiring.

  Fifth, resistance layers (polysilicon layers) of a plurality of resistance elements integrated on the same substrate and having different sheet resistances can be formed in the same process and under the same conditions. That is, even if a plurality of polysilicon layers are formed under the same conditions, different sheet resistances can be given by different fixed potentials applied to the respective protective layers.

  Conventionally, in order to obtain resistance layers having different sheet resistances, it has been necessary to provide a mask for each resistance layer and introduce an impurity having a desired impurity concentration. It is only necessary to perform the implantation and diffusion process and patterning into a desired shape, thereby simplifying the manufacturing process.

It is (A) top view and (B) sectional drawing explaining the resistive element of this embodiment. It is a characteristic view explaining the resistive element of this embodiment. It is a top view explaining the resistance element of this embodiment. It is (A) sectional drawing, (B) characteristic view, (C) top view explaining the resistive element of this embodiment. It is a top view explaining the resistance element of this embodiment. It is sectional drawing explaining the manufacturing method of the resistive element of this embodiment. It is sectional drawing explaining the manufacturing method of the resistive element of this embodiment. It is sectional drawing explaining the manufacturing method of the resistive element of this embodiment. It is sectional drawing explaining the conventional resistive element. It is sectional drawing explaining the manufacturing method of the conventional resistive element. It is sectional drawing explaining the conventional resistive element. It is (A) sectional drawing, (B) sectional drawing, (C) sectional drawing, (D) top view explaining the manufacturing method of the conventional resistive element.

  An embodiment of the present invention will be described in detail with reference to FIGS.

  First, a first embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams illustrating a resistance element according to a first embodiment, in which FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line aa in FIG.

  For example, the resistance element 10 is integrated on the same substrate as the J-FET 20 that is connected to an electret condenser microphone (ECM: not shown) and constitutes an amplifying element that performs impedance conversion and amplification. The gate G and the ground are connected in parallel. In the J-FET 20, the gate G, the source S, and the drain D are arranged in a comb shape, the gate G is connected to one end of the ECM, and the source S is grounded.

  The resistance element 10 includes a semiconductor substrate 1, a first insulating film 2, a polysilicon layer 3, a first wiring layer 7, a second wiring layer 8, a second insulating film 4, and a protective layer 9. Have.

  The semiconductor substrate 1 is a p-type or n-type, for example, a silicon semiconductor substrate. The semiconductor substrate 1 may be non-doped, or may be a silicon carbide (SiC) semiconductor substrate, a compound semiconductor substrate, or a sapphire substrate.

  The first insulating film 2 is, for example, a CVD oxide film provided on the semiconductor substrate 1. The polysilicon layer 3 is provided on the first insulating film 2, has a straight part 3 s and a bent part 3 t, and is patterned into a continuous shape. The polysilicon layer 3 extends (meanders) with a plurality of straight portions 3s bent back, for example, as shown in FIG. 1 (A), in order to ensure the necessary length as a resistance layer within a limited chip area. In addition to the pattern, it is provided in a pattern extending in an L shape, a U shape, or a substantially rectangular shape along the chip side.

  Here, the straight portion 3s of the present embodiment refers to a portion where the pattern of the polysilicon layer 3 is longer than the line width w and extends in the first direction.

  The bent portion 3t is a bent portion when the extending direction changes from the first direction to the second direction at an angle of, for example, approximately a right angle or less from the first direction, that is, a portion where folding occurs.

Impurities (for example, phosphorus (P), dose: about 1E13 cm ⁻² ) are implanted into the polysilicon layer 3 to make it conductive. The thickness of the polysilicon layer 3 is, for example, 5000 mm. The polysilicon layer 3 is covered with a second insulating film (for example, an oxide film) 4, and the second insulating film 4 has a first opening OP1 and a second opening OP2 from which a part of the polysilicon layer 3 is exposed. They are provided separately from each other.

The first wiring layer 7 is in contact with one end of the polysilicon layer 3 through the first opening OP1, and the second wiring layer 8 is in contact with the other end of the polysilicon layer 3 through the second opening OP2. . For example, arsenic (As) or the like is implanted into the contact portion between the first wiring layer 7 and the second wiring layer 8 and the polysilicon layer 3 to a high concentration (dose amount: about 1E15 cm ⁻² ) to thereby form a high concentration impurity. Region 5 is provided to reduce contact resistance.

  The first wiring layer 7 and the second wiring layer 8 serve as wiring for connecting the resistance element 10 to other elements or electrodes at both ends of the resistance element 10. The polysilicon layer 3 extending between them has an impurity concentration to be implanted and a pattern (length, width, film thickness) so as to have a desired sheet resistance (for example, 10 MΩ / □) as a resistance layer. It is selected appropriately. Hereinafter, the polysilicon layer 3 extending between the first wiring layer 7 and the second wiring layer 8 is referred to as a resistance layer 3r. As described above, the resistance layer 3r includes the straight portion 3s and the bent portion 3t.

  Here, the protective layer 9 is the same metal layer (for example, aluminum (Al)) as the first wiring layer 7 and the second wiring layer 8 and has a thickness of about 1.1 μm.

  The protective layer 9 may be other than a metal layer as long as it has a high electrical conductivity, such as a polysilicon layer doped with impurities at a high concentration.

  The protective layer 9 is provided above the straight portion 3s via the second insulating film 4 so that the bent portion 3t of the resistance layer 3r is exposed.

  In the present embodiment, the upper part of the straight portion 3s of the resistance layer 3r is covered with the protective layer 9 during the manufacturing process described later. Therefore, in the dry etching of the first wiring layer 7 and the second wiring layer 8 and the subsequent resist mask removal process by O2 ashing, the region where the insulating film 4 on the straight portion 3s of the resistance layer 3r is charged is compared with the conventional one. Can be greatly reduced.

  Specifically, the region where the insulating film 4 is charged is only the region exposed from the protective layer 9 such as the first wiring layer 7, the second wiring layer 8, and the bent portion 3t as shown in FIG. As a result, the region 11 depleted in the vicinity of the surface of the polysilicon layer 3 and the region 12 in which electrons are accumulated at a high concentration in the polysilicon layer 3 are also only the regions where the insulating film 4 is exposed. . As a result, the resistance layer 3r is hardly affected by charging in the straight portion 3s, and a sheet resistance as designed is obtained.

  FIG. 2 is a diagram showing current I-voltage V characteristics of the resistance element 10 of the present embodiment and the conventional resistance element. The horizontal axis is voltage [V], and the vertical axis is current [I]. Further, this characteristic is a result of measuring the characteristic by forming a resistance element (broken line) having a conventional structure (without a protective layer) and the resistance element (solid line) of the present embodiment in the vicinity of the same wafer. Except for the presence or absence of the protective layer 9, the configuration (for example, the width, length, and impurity implantation amount of the resistance layer 3r) is the same.

  As is clear from this result, by providing the protective layer 9 of this embodiment, the sheet resistance can be increased by two digits or more, and the resistance element is a polysilicon layer having a sheet resistance of 10 MΩ / □ to 100 MΩ / □. It was found that can be realized. Note that the sheet resistance of 100 MΩ / □ or more is close to the sheet resistance of the 5000 自 体 thick polysilicon layer itself of this embodiment, so that it is difficult to dope impurities.

  FIG. 3 is a plan view showing an example of the pattern of the bent portion 3t and the protective layer 9, and FIG. 3A is a diagram showing the pattern of the protective layer 9 when two bent portions 3t are close to each other. 3 (B) is a diagram showing a pattern of one bent portion 3t and the protective layer 9. FIG.

  For example, as shown in FIG. 3A, when two bent portions 3t are close to each other, the protective layer 9 is provided so as to be exposed including the straight portion 3s therebetween. On the other hand, when there is one bent portion 3t, or when there are a plurality of bent portions 3t and the straight portion 3s between them is long, the protective layer 9 is provided so as to expose only the bent portion 3t.

  Hereinafter, the reason why the bent portion 3t of the resistance layer 3r is exposed without being covered with the protective layer 9 will be described with reference to FIG.

  The bent portion 3t is susceptible to variations in the thickness of the polysilicon layer 3 and the line width during patterning. Further, because of the bent shape, as shown by the arrow in FIG. 3A, current flows more easily on the inner side than on the outer side, and the current concentrates on the inner side. That is, in the bent portion 3t, the variation in sheet resistance due to the location where current flows is larger than that in the straight portion 3s. For this reason, the sheet resistance of the resistance layer 3r becomes unstable, which causes variations in sheet resistance.

  On the other hand, there is also a method in which a polysilicon layer consisting only of a plurality of straight portions that are separated and extended in parallel is connected in series with a metal layer to form a resistance layer having a meandering pattern in which no bent portion is formed by the polysilicon layer. Conceivable. However, since the contact resistance between the polysilicon layer and the metal layer is added by the number of times of folding, this also causes variation in sheet resistance.

  In this embodiment, by providing the protective layer 9 on the resistive layer 3r as described above, the sheet resistance of the resistive layer 3r can be increased by two digits or more. However, if the protective layer 9 is also provided on the bent portion 3t, Similarly, the sheet resistance increases.

  In other words, the bent portion 3t, which is a variation factor, can be reduced in the resistance layer 3r as a whole by keeping the sheet resistance low by not providing a protective layer.

  By providing the protective layer 9, the sheet resistance of the resistance layer 3 r can be increased in the straight line portion 3 s, and therefore it is desirable that the protective layer 9 covers the straight line portion 3 s as much as possible. The bent portion 3t is exposed from the protective layer 9 in order to minimize the influence of the fluctuation of the sheet resistance on the resistance value of the entire resistance layer 3r. A mask for patterning the polysilicon layer 3 and the protective layer 9 is used. In consideration of alignment accuracy and etching accuracy, the minimum necessary region may be exposed.

  Specifically, for example, as shown in FIGS. 3A and 3B, in the case of the patterning line width w of the resistance layer 3r (polysilicon layer 3), the linear portion 3s is covered from the outer end portion of the bent portion 3t. It is sufficient to secure a distance of at least 2w to the end of the protective layer 9 to expose the bent portion 3t. Depending on the characteristics and pattern of the resistance layer 3r, the bent portion 3t may be secured.

  Although FIG. 1 shows an example in which the first wiring layer 7 and the second wiring layer 8 are disposed at both ends of the resistance element 10, the pattern of the polysilicon layer 3 is not limited to this.

  A second embodiment of the present invention will be described with reference to FIGS.

  Since the protective layer 9 is made of a conductive material, the potential may change. Therefore, it is conceivable to stabilize the resistance of the resistance element by applying a constant potential to the protective layer 9.

  FIG. 4 is a diagram for explaining a case where a predetermined potential is applied to the protective layer 9. FIG. 4A is a sectional view of the resistance element 10, and the patterns of the resistive layer 3r and the protective layer 9 are the same as those in FIG. It is the same. Here, the same potential as that of the first wiring layer 7 (pad on the input side) of the resistance element is applied. FIG. 4B is a diagram illustrating the current-voltage characteristics of the resistance element 10, where the horizontal axis represents voltage [V] and the vertical axis represents current [I]. FIG. 4C is a plan view showing an example of a specific pattern of the protective layer 9 in the second embodiment.

  FIG. 4B shows a case where a protective layer 9 made of an Al layer is provided on the resistance layer 3r formed by the same method as in the first embodiment, and a potential from −10 V to 10 V is applied to the protective layer 9 for resistance. The current flowing through the device was measured.

  From this, it can be seen that the slope of the current-voltage characteristic (the resistance value of the wiring, that is, the sheet resistance) changes depending on the voltage applied to the protective layer 9. Therefore, even in the resistance layer 3r formed under the same conditions (impurity concentration and pattern (width, length, film thickness, shape)), the sheet resistance can be varied depending on the voltage applied to the protective layer 9.

  In FIG. 4C, the output side pad and the protective layer 9 are integrated. As described above, when the fixed potential of one of the first wiring layer 7 and the second wiring layer 8 can be used depending on the sheet resistance of the resistance layer 3r, any of the first wiring layer 7 and the second wiring layer 8 is used. One of them and the protective layer 9 can be provided continuously.

  A third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a plan view showing the resistance element 10 of the third embodiment.

  In the third embodiment, a plurality of resistance elements 10 a and 10 b are integrated on the same semiconductor substrate (chip) 1. These configurations are the same as those shown in the first embodiment. The resistance layer 3ra of the resistance element 10a and the resistance layer 3rb of the resistance element 10b are formed under the same conditions (the same impurity is ion-implanted with the same impurity concentration). Further, for example, they are patterned in the same shape and have the same sheet resistance in the floating state.

  Then, as described above with reference to FIG. 4B, the sheet resistance of the resistance element can be changed by the voltage applied to the protective layer 9. Utilizing this, by applying different desired fixed potentials V1 and V2 to these protective layers 9a and 9ba, respectively, the resistance elements 10a and 10b can be made to have different sheet resistances.

  As described above, in the present embodiment, the length of patterning and the fixed potential applied to the protective layer 9 are appropriately selected for one polysilicon layer 3 formed in one impurity injection step and having a predetermined impurity concentration. Thus, a plurality of resistance elements having different sheet resistances can be integrated on the same substrate.

  Conventionally, when a plurality of resistance elements 50a and 50b having different sheet resistances are integrated on the same substrate (chip) as shown in FIG. 12C, the impurity concentration of the resistance layer 53 is varied in addition to the pattern. In view of the influence of the lateral diffusion of impurities, it is necessary to secure the mutual separation distance L ′ to be equal to or greater than the thickness of the resistance layer 53.

  However, in the present embodiment, the plurality of resistance layers 3ra and 3rb can be simultaneously formed under the same conditions (the same impurity and the same impurity concentration). Thereby, the separation distance L between the resistance layers 3ra and 3rb can be reduced.

  Note that the same fixed potentials V1 and V2 may be applied to the resistance elements 10a and 10b to obtain equivalent sheet resistance.

  The manufacturing method of the present embodiment will be described with reference to FIGS.

  First Step (FIG. 6A): A p-type or n-type silicon semiconductor substrate is prepared as the semiconductor substrate 1, and a first insulating film 2 is formed on the semiconductor substrate 1.

  The first insulating film 2 is an oxide film, for example, and is formed to a film thickness of, for example, about 3500 mm by a CVD method or the like.

Second step (FIG. 6B): A polysilicon layer 3 is formed on the first insulating film 2. The thickness of the polysilicon layer 3 is, for example, about 5000 mm. For example, phosphorus (P) having a dose of about 1E13 cm ⁻² is ion-implanted into the entire surface of the polysilicon layer 3, and heat treatment (1000 ° C., 45 minutes) is performed to diffuse impurities.

  Third step (FIGS. 6C and 6D): The polysilicon layer 3 is patterned by a photolithography process into a desired shape having a straight portion and a bent portion, and these continuously extend ( (See FIG. 1A). Since the polysilicon layer 3 constitutes the resistance layer of the resistance element, the resistance value is selected by selecting the film thickness and dose in the second step and the shape (length and width) in the photolithography step. decide. The sheet resistance of the resistance element of this embodiment is, for example, 10 MΩ / □.

  Thereafter, a second insulating film 4 is formed on the polysilicon layer 3 so as to cover the entire polysilicon layer 3. The second insulating film 4 is an oxide film, for example, and is formed to, for example, 8500 mm by CVD (FIG. 6C).

  When a plurality of resistance elements are integrated on the same substrate (chip) as in the third embodiment, a mask M1 having a plurality of desired regions opened in this step is provided, and a plurality of polysilicon layers 3 are formed. Then, patterning is performed in a desired shape (FIG. 6D).

  The plurality of polysilicon layers 3a and 3b have the same impurity concentration, but differ in sheet resistance by applying different fixed potentials to the pattern (length) and a protective layer formed in a later step. Can be held.

  In the conventional manufacturing method, in order to maintain a plurality of sheet resistances, it is necessary to perform the mask formation by photolithography and the ion implantation process of impurities a plurality of times according to the sheet resistance of the resistance element. According to this, even in the polysilicon layer 3 (resistive layer) formed by a single photolithography process and impurity ion implantation process, different sheet resistances can be maintained, and the manufacturing process can be simplified and shortened. I can plan.

  Fourth step (FIG. 7): A mask M2 is formed on a part of the second insulating film 4, and the second insulating film 4 is partially etched, whereby a part of the polysilicon layer 3 is exposed. A first opening OP1 and a second opening OP2 are formed (FIG. 7A).

While the mask M2 is left as it is, an n-type impurity (for example, arsenic (As), dose amount: 1E15 cm ⁻² ) having a high concentration is ion-implanted, and the impurity is diffused by heat treatment (800 ° C., 30 minutes).

  An n-type impurity is implanted into the exposed surface of the polysilicon layer 3 from the first opening OP1 and the second opening OP2, and the high-concentration impurity region 5 reduces contact resistance with a wiring layer formed in a later process. Is formed (FIG. 7B).

  Fifth step (FIG. 8A): A metal layer 6 covering the second insulating film 4 is formed. The metal layer 6 is, for example, aluminum (Al) and has a thickness of, for example, 1.1 μm. The metal layer 6 is formed on the first opening OP1, the second opening OP2, and the polysilicon layer 3 therebetween.

  Thereafter, the first resist mask M3 covering the upper part of the first opening OP1, the second resist mask M4 covering the upper part of the second opening OP2, and the first opening OP1 and the second opening OP2 by a photolithography process. A third resist mask M5 is formed to cover the polysilicon layer 3 extending between and the second insulating film 4 thereon.

  At this time, the polysilicon layer 3 extending between the first opening OP1 and the second opening OP2 is covered with the straight portion 3s, and the bent portion 3t is exposed (see FIG. 1). A resist mask M5 is provided.

  Sixth step (FIG. 8B): Thereafter, the metal layer 6 is patterned. Thus, the first wiring layer 7 that contacts one end of the polysilicon layer 3 through the first opening OP1 and the second wiring layer 8 that contacts the other end of the polysilicon layer 3 through the second opening OP2. Form. At the same time, the protective layer 9 is formed on the polysilicon layer 3 (resistive layer 3r) extending between the first opening OP1 and the second opening OP2 and the second insulating film 4 thereon. Only the straight portion 3 t of the resistance layer 3 r is covered with the protective layer 9, and the bent portion 3 t is exposed from the protective layer 9. Thereafter, the resist masks M3 to M5 are removed by O2 plasma ashing to obtain the final structure shown in FIG.

  The third mask M5 is made continuous with either the first mask M3 or the second mask M4, whereby the first wiring layer 7 or the second wiring layer 8 and the protective layer 9 are continuously (separated). Without).

  According to this embodiment, it is possible to provide a method for manufacturing a resistance element having a high sheet resistance (10 MΩ / □ or more) using a polysilicon layer only by changing the mask for patterning the metal layer from the conventional manufacturing method.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st insulating film 3 Polysilicon layer 3r Resistance layer 4 2nd insulating film 5 High concentration impurity region 6 Metal layer 7 1st wiring layer 8 2nd wiring layer 9 Protective layer 10 Resistance element

Claims (12)

A semiconductor substrate;
A first insulating film provided on the semiconductor substrate;
A polysilicon layer provided on the first insulating film, having a straight portion and a bent portion, and having impurities introduced therein;
A first wiring layer in contact with one end of the polysilicon layer;
A second wiring layer in contact with the other end of the polysilicon layer apart from the first wiring layer;
A second insulating film provided on the polysilicon layer;
A protective layer provided via the second insulating film so that the bent portion is exposed on the polysilicon layer extending between the first wiring layer and the second wiring layer;
A resistance element comprising:   The resistance element according to claim 1, wherein the protective layer is a conductor layer.   The resistance element according to claim 2, wherein the protective layer is a metal layer.   The resistance element according to claim 2, wherein a fixed potential is applied to the protective layer.   The resistance element according to claim 4, wherein the protective layer is the same metal layer as the first wiring layer and the second wiring layer.   6. The resistance element according to claim 4, wherein the polysilicon layer has a sheet resistance of 10 MΩ / □ to 100 MΩ / □.   Another first insulating film, another polysilicon layer, another first wiring layer, another second wiring layer, another second insulating film, and another protective layer are formed on the semiconductor substrate. The resistive element according to claim 6, further comprising: a resistive element having a first fixed potential applied to the protective layer, and a second fixed potential applied to the other protective layer.   The resistance element according to claim 7, wherein the polysilicon layer and the other polysilicon layer have the same impurity concentration. Forming a first insulating film on the semiconductor substrate;
Forming a polysilicon layer having a straight portion and a bent portion on which the impurity is introduced on the first insulating film;
Forming a second insulating film on the polysilicon layer;
Forming a first opening and a second opening in which part of the polysilicon layer is exposed on a part of the second insulating film;
Forming a protective layer via the second insulating film so that the bent portion is exposed on the polysilicon layer extending between the first opening and the second opening;
A method of manufacturing a resistance element, comprising: Forming a metal layer covering the second insulating film, covering the upper part of the first opening; a second mask covering the upper part of the second opening; the first opening; Forming a third mask covering above the straight portion of the polysilicon layer extending between the second openings;
The metal layer is patterned to contact the first wiring layer in contact with one end of the polysilicon layer through the first opening, and in contact with the other end of the polysilicon layer through the second opening. The method for manufacturing a resistance element according to claim 9, further comprising a step of forming the second wiring layer and the protective layer. The method of manufacturing a resistance element according to claim 10, wherein an impurity of about 1.0E13 cm ⁻² is introduced into the polysilicon layer.   12. The method of manufacturing a resistance element according to claim 11, wherein the polysilicon layer is patterned to form one polysilicon layer and another polysilicon layer separated from each other.

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