JP5963549B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used for a semiconductor device having an MIM capacitor, for example.

  A so-called MIM (Metal Insulator Metal) capacitor in which a metal layer having a long shape similar to the wiring layer formed in the same layer as the wiring layer formed in the semiconductor device is used as an electrode of the capacitor is widely used. Yes. The metal layer is in contact with both the low potential electrode to which a lower potential is applied among the electrodes of the MIM capacitor of the semiconductor device and the high potential electrode to which a higher potential is applied among the electrodes of the MIM capacitor. Foreign matter may adhere to the surface. At this time, the foreign substance may short-circuit the low potential electrode and the high potential electrode of the MIM capacitor, thereby impairing the function as the MIM capacitor. As a result, the yield of the semiconductor device may be reduced.

  By the way, as a means for suppressing a decrease in reliability due to dielectric breakdown of a capacitor (capacitance element), a semiconductor integrated circuit device having a configuration in which a capacitor and a wiring are connected by a fuse element is disclosed in, for example, Japanese Patent Laid-Open No. 11-87614. (Patent Document 1). A semiconductor integrated circuit device having a CMOS transistor, a so-called PIP (Poly-silicon Insulator Poly-silicon) capacitor, and a resistance element on the same substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-26271 (Patent Document 2). ).

JP-A-11-87614 JP 2002-26271 A

  Although it is required to suppress a decrease in reliability due to the dielectric breakdown of the MIM capacitor as described above, since the capacitor disclosed in Patent Document 1 has a plate-like conductive layer, it is the same as the wiring layer described above. The configuration is different from that of the MIM capacitor in which electrodes are formed as layers. The semiconductor integrated circuit device of Patent Document 2 does not disclose whether or not the resistance element has an action of suppressing a short circuit of the PIP capacitor. MIM capacitors are also required to suppress a decrease in yield due to dielectric breakdown.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, a semiconductor device includes a semiconductor substrate, a plurality of capacitive elements, a first electrode portion, and a second electrode portion. The capacitor element includes a first capacitor electrode, a second capacitor electrode formed in the same layer as the first capacitor electrode with a space therebetween, and an insulator layer. The first electrode portion is connected to the first capacitor electrode. The second electrode portion is connected to the second capacitor electrode. Both the pair of first capacitor electrode and the second capacitor electrodes of adjacent each other and are connected to the first electrode portion or second electrode portion, respectively by the resistive portion made of polycrystalline silicon. The resistance portion made of polycrystalline silicon has an electric resistance different from the electric resistance value in any one selected from the group consisting of the first capacitance electrode, the second capacitance electrode, the first electrode portion, and the second electrode portion. Has the value of

  According to one embodiment, when a current flows through a resistance portion through a portion of one capacitor element due to foreign matter or the like between the first capacitor electrode and the second capacitor electrode, the electrode through which the current flows Only the resistance portion connected in between is melted and the capacitive element is disconnected from the circuit. Since the other first capacitor electrode and the second capacitor electrode can continue to function as a capacitor element without being affected by the current, a decrease in yield due to one capacitor element can be suppressed.

It is a floor view of the circuit of the semiconductor device of one embodiment. 1 is a schematic perspective view illustrating a configuration of an MIM capacitor according to a first embodiment. 3 is a schematic top view showing the configuration of the MIM capacitor of the first embodiment. FIG. 1 is a schematic cross-sectional view showing a configuration of an MIM capacitor according to a first embodiment. 2 is a schematic cross-sectional view showing the configuration of the semiconductor device of First Embodiment in more detail. FIG. 6 is a schematic cross-sectional view showing a first step of a manufacturing method including the MIM capacitor shown in FIG. 5. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the structure containing the MIM capacitor of FIG. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the structure containing the MIM capacitor of FIG. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the structure containing the MIM capacitor of FIG. FIG. 6 is a schematic cross-sectional view showing a fifth step of the manufacturing method having the structure including the MIM capacitor of FIG. 5. FIG. 10 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the configuration including the MIM capacitor of FIG. 5. FIG. 10 is a schematic cross-sectional view showing a seventh step of the manufacturing method having the structure including the MIM capacitor of FIG. 5. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the structure containing the MIM capacitor of FIG. FIG. 6 is a schematic cross-sectional view showing a modification of the fuse resistor of the first embodiment with respect to FIG. FIG. 3 is a schematic top view showing a configuration of an MIM capacitor as a related technique of the first embodiment. FIG. 16 is a schematic top view showing a state in which foreign matter is attached to the capacitance electrode of the MIM capacitor of the related technology of FIG. 15. FIG. 4 is a schematic top view showing a state in which foreign matter is attached to the capacitor electrode of the MIM capacitor of the first embodiment shown in FIG. 3. 6 is a schematic top view showing a configuration of an MIM capacitor according to a second embodiment. FIG. 6 is a schematic top view showing a configuration of an MIM capacitor according to a third embodiment. FIG. 6 is a schematic top view showing a configuration of an MIM capacitor according to a fourth embodiment. FIG. FIG. 10 is a schematic top view showing a configuration of an MIM capacitor according to a fifth embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of an MIM capacitor according to a fifth embodiment. FIG. 3 is a schematic top view showing an example of a planar shape of the fuse resistor of the first embodiment. FIG. 10 is a schematic top view showing a first example of a planar shape of a fuse resistor of a sixth embodiment. FIG. 22 is a schematic top view showing a second example of the planar shape of the fuse resistor of the sixth embodiment. FIG. 20 is a schematic top view showing a third example of the planar shape of the fuse resistor of the sixth embodiment. FIG. 10 is a schematic top view showing a fourth example of a planar shape of the fuse resistor of the sixth embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of an MIM capacitor according to a seventh embodiment. FIG. 20 is a schematic top view showing a first example of a planar shape of a fuse resistor in a seventh embodiment. FIG. 20 is a schematic top view showing a second example of the planar shape of the fuse resistor according to the seventh embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment in more detail. It is a schematic sectional drawing which shows the structure of the MIM capacitor of a reference example. It is a schematic top view which shows the 1st example of the planar shape of the fuse resistor of a reference example. It is a schematic top view which shows the 2nd example of the planar shape of the fuse resistance of a reference example. It is the schematic sectional drawing which extracted the principal part of one Embodiment.

Hereinafter, an embodiment will be described with reference to the drawings.
(Embodiment 1)
First, a floor view in a plan view of a circuit of a semiconductor device according to an embodiment will be described with reference to FIG.

  Referring to FIG. 1, a semiconductor device DEV according to an embodiment is formed on a main surface of a semiconductor substrate SUB, and roughly includes a low voltage logic circuit and a high voltage analog circuit. Among these, a high-voltage analog circuit is formed with a charge pump circuit. The charge pump circuit is a circuit for outputting a voltage higher than the input voltage.

  The charge pump circuit is mainly composed of a switch and a capacitor, and the connection of the capacitor is switched by the switch. By switching the connection of the capacitors in this way, the voltage of the charge pump circuit rises, so that a voltage higher than the input voltage can be output.

  The capacitor of the charge pump circuit has a fringe MIM capacitor MM (capacitor) as a capacitive element. As the MIM capacitor MM, an element having a high breakdown voltage and high reliability is used as an element constituting the power supply circuit.

  The arrangement of the low voltage logic circuit and the high voltage analog circuit in FIG. 1 is an example, and the actual arrangement is not limited to this.

  2 to 4, capacitor MM includes a plurality of electrodes M1, M2, M3, M4 formed on the main surface of semiconductor substrate SUB having a main surface, and interlayer insulating film II (insulator layer). It consists of. In FIG. 2, a total of four layers of M1 to M4 are stacked, but this is an example, and any number other than four layers may be used. For example, one layer of the electrode M1 is arranged in the same plane. Only the structure may be sufficient. FIG. 4 is a schematic cross-sectional view taken along a line IV-IV in FIG.

  The electrodes M1, M2, M3, and M4 of the MIM capacitor MM are spaced from each other with respect to the vertical direction (that is, the direction in which the thin film is stacked) and the horizontal direction (that is, the direction along the main surface MS of the semiconductor substrate SUB) in FIGS. It is arranged so as to be adjacent to each other. Among the electrodes M1, M2, M3, and M4, an interlayer insulating film II is sandwiched between a pair of electrodes adjacent to each other in the stacking direction. Specifically, for example, the interlayer insulating film II is sandwiched between the electrode M1 and the electrode M2, between the electrode M2 and the electrode M3, and between the electrode M3 and the electrode M4.

  A plurality of pairs of stacked electrodes M1 to M4 are arranged on the main surface MS of the semiconductor substrate SUB so that a plurality of sets are arranged at intervals with respect to the direction along the main surface MS (for example, the left-right direction in FIGS. 3 and 4). Has been. Specifically, for example, a set of a plurality of stacked electrodes M1 to M4 may be arranged so as to be arranged in a line in a straight line. For example, a plurality of stacked electrodes M1 may be arranged in an array. A group of ~ M4 may be arranged. In FIG. 3, they are arranged in a line in the vertical direction of the figure.

  Electrode portions are formed around the electrodes M1 to M4 stacked on each other. The electrode part has a low potential electrode part VL as a first electrode part and a high potential electrode part VH as a second electrode part. The potential values of the low potential electrode portion VL and the high potential electrode portion VH are different from each other, and the potential of the high potential electrode portion VH is higher than the potential of the low potential electrode portion VL. The low potential electrode part VL and the high potential electrode part VH apply a low potential (relatively low) or a high potential (higher than the upper low potential) to the electrodes M1 to M4 by being connected to the electrodes M1 to M4.

  Here, a pair of electrodes M1 to M4 that are adjacent to each other in a plan view and that are adjacent to each other in the vertical direction of FIG. 3, that is, the direction along the main surface of the semiconductor substrate SUB, is a low potential electrode ML (first 1 capacitor electrode) and a high potential electrode MH (second capacitor electrode) connected to the high potential electrode portion VH. The low potential electrode portion VL is electrically connected to the low potential electrode ML of the MIM capacitor MM, thereby applying a relatively low potential to the low potential electrode ML. Similarly, the high potential electrode portion VH is connected to the high potential electrode ML of the MIM capacitor MM. By being electrically connected to the potential electrode MH, a relatively high potential is applied to the high potential electrode MH.

  In the set of electrodes M1 to M4, the low potential electrodes ML and the high potential electrodes MH are alternately arranged in the direction along the main surface MS. This is true for both the first direction along the main surface MS and the second direction along the main surface MS but intersecting the first direction (not shown in FIG. 3). For this reason, one of a pair of any pair of electrodes M1 to M4 adjacent in the direction along the main surface of the semiconductor substrate SUB is a low potential electrode ML, and the other of the pair is a high potential electrode MH.

  More specifically, for example, if each of the pair of electrodes M1 to M4 disposed at positions overlapping each other in plan view is the low potential electrode ML, the pair disposed adjacent to each other with a space therebetween. Each of the electrodes M1 to M4 becomes a high potential electrode MH.

  The potential applied to the high potential electrode MH is different from the potential applied to the low potential electrode ML, and the potential applied to the high potential electrode MH by the high potential electrode portion VH is reduced by the low potential electrode portion VL. It becomes higher than the potential applied to the electrode ML. Each of the electrodes M1 to M4 that are the low potential electrodes ML, each of the electrodes M1 to M4 that are the high potential electrodes MH adjacent to the electrodes M1 to M4 in the direction of the main surface, and the interlayer insulating film II therebetween are fringe. An MIM capacitor MM (capacitor) is formed.

  The electrodes M1, M2, M3, and M4 are all formed as the same layer as the (metal) material wiring layer formed in the semiconductor device DEV, and have a long planar shape like the wiring layer. Yes. Therefore, the electrodes M1 to M4 are formed of the same material as each wiring layer of the (metal) material. For example, when the wiring layer of the same layer is made of aluminum, the electrode of the same layer is also made of aluminum. Here, all of the plurality of electrodes formed in the same layer are referred to as an electrode M1, an electrode M2, an electrode M3, and an electrode M4 in order from the lower layer.

  Referring particularly to FIGS. 3 and 4, the MIM capacitor MM is formed on the element isolation insulating film FO formed on the main surface MS of the semiconductor substrate SUB. As described above, the pair of electrodes M1 to M4 constituting the MIM capacitor MM is spaced apart from each other on the main surface MS of the semiconductor substrate SUB with respect to the direction along the main surface MS (for example, the left-right direction in FIGS. 3 and 4). It is arranged so that there are multiple lines. Therefore, a plurality (large number) of MIM capacitors MM are arranged on the main surface MS of the semiconductor substrate SUB. The MIM capacitors MM are preferably arranged so that a plurality (a large number) of MIM capacitors MM are arranged in at least one of the stacking direction and the direction along the main surface MS. 3 to 4, only one of the low potential electrode ML and the high potential electrode MH is arranged as the electrodes M1 to M4, and the low potential electrode ML and the high potential electrode MH are alternately arranged in the left-right direction in FIG. Yes.

  The electrodes M1 to M4 constituting the electrodes ML and MH of the MIM capacitor MM and the wirings M1 to M4 constituting the electrode portions VL and VH all have a long planar shape. In the direction intersecting with each other. 3 and 4, the electrodes M1 to M4 constituting the MIM capacitor MM extend in the left-right direction in FIG. 3, and the wirings M1 to M4 constituting the electrode portions VL and VH are arranged in the vertical direction (depth) in FIG. Direction). Further, for example, electrodes M1 to M4 which are all at the same potential (low potential electrode ML) and overlap each other in plan view are electrically connected to each other by vias V1, V2 and V3 made of a metal material such as tungsten or copper. Has been.

  The electrode portions VL and VH and the electrodes M1 to M4 of the MIM capacitor MM are connected by a fuse resistor HR made of, for example, polycrystalline silicon, so that the low potential electrode ML and the high potential electrode MH are arranged as described above. ing. In FIG. 3, one of a pair of electrodes M1 to M4 adjacent to each other in plan view is connected to the low potential electrode portion VL by the fuse resistor HR, and the other is connected to the high potential electrode portion VH by the fuse resistor HR. Has been. That is, both of the pair of electrodes M1 to M4 adjacent to each other in plan view are connected to the low potential electrode portion VL or the high potential electrode portion VH by the fuse resistor HR.

  Of the pair of electrodes M1 to M4 of the MIM capacitor MM, the one connected to the low potential electrode portion VL by the fuse resistor HR is the low potential electrode ML, and the one connected to the high potential electrode portion VH by the fuse resistor HR A high potential electrode MH. The fuse resistor HR is formed below the electrode M1, for example, on the main surface of the semiconductor substrate SUB. The fuse resistor HR and the electrode portions VL and VH are connected by a contact CT formed of a metal material such as tungsten or copper.

  As described above, in the electrodes M1 to M4 of the MIM capacitor MM, the low potential electrodes ML and the high potential electrodes MH are alternately arranged in the direction along the main surface MS. Therefore, the fuse resistors HR connecting the electrodes M1 to M4 and the low potential electrode portion VL and the fuse resistors HR connecting the electrodes M1 to M4 and the high potential electrode portion VH are alternately (alternately) in plan view. Has been placed. The fuse resistance HR connects the electrodes M1 to M4 and the electrode portions VL and VH alternately, so that the electrodes M1 to M4 and the electrode portions VL and VH are connected so as to have a comb-like planar shape.

  In FIG. 4, the lowermost electrode M1 in the set of electrodes M1 to M4 of the MIM capacitor MM is connected to the electrode part VL by being directly connected to the fuse resistor HR via the contact CT. However, the connection between the fuse resistor HR and the set of electrodes M1 to M4 may be any of the electrodes M1, M2, M3, and M4.

FIG. 5 is a schematic cross-sectional view taken along the line VV in FIG. 3, and shows the MIM capacitor MM described in FIG. 4 and its peripheral portion in more detail. The MIM capacitor MM shown in FIG. 4 corresponds to a part of the MIM capacitor MM surrounded by a dotted rectangle in FIG. Referring to FIG. 5, the semiconductor substrate SUB of one embodiment has a p ⁻ region PSR containing a p-type impurity therein. An n-type well region NWR and a p-type well region PWR are formed in the semiconductor substrate SUB and on the main surface MS side (upper side in the drawing) of the p ⁻ region PSR.

  An element isolation insulating film FO is formed on the main surface MS of the semiconductor substrate SUB in the p-type well region PWR, and a fuse resistor HR (resistance part) is formed in contact with the upper surface of the element isolation insulating film FO. Yes. The fuse resistor HR includes a resistance silicon portion RS (resistance body portion made of polycrystalline silicon) and a sidewall insulating film SW2, and the resistance silicon portion RS includes a high resistance silicon portion RS1 and a low resistance silicon portion RS2. Have.

  Specifically, the high resistance silicon part RS1 of the resistance silicon part RS has a sheet resistance of several kΩ to several tens of kΩ and the low resistance silicon part RS2 has a sheet resistance of several Ω to several tens of Ω, and the MIM capacitor MM It is preferable that the high resistance silicon portion RS1 has a sufficiently high electric resistance value as compared with the electrodes M1 to M4.

  The resistance silicon portion RS of the fuse resistor HR has an optimum electric resistance value because it has a high resistance silicon portion RS1 and a low resistance silicon portion RS2 and is thus more easily blown when a current flows therethrough. doing. That is, the electric resistance value in the fuse resistor HR is different from the electric resistance value in any one selected from the group consisting of the electrodes M1 to M4 of the MIM capacitor MM and the electrode portions VL and VH.

Above the fuse resistor HR, as shown in FIG. 4, the MIM capacitor MM having the electrodes M1 to M4, the low potential electrode portion VL and the high potential electrode portion VH having the wirings M1 to M5 are formed. These layers are arranged so as to be sandwiched between the interlayer insulating films II, thereby forming the MIM capacitor MM. A region where the MIM capacitor MM is formed, a region where the low potential electrode portion VL is formed, and a region where the high potential electrode portion VH is formed in the direction along the main surface MS are a fringe MIM capacitor portion and a V _L application, respectively. This is called a fuse region or a V _H application fuse region.

  On the main surface MS of the semiconductor substrate SUB in the n-type well region NWR, for example, a MOS (Metal Oxide Semiconductor) transistor MT (control element) is formed. The MOS transistor MT has a gate electrode GT, a source region SR, and a drain region DR. Here, the region where the MOS transistor MT is formed is called a MOS transistor formation region.

  The gate electrode GT includes a gate voltage application unit GE, a gate insulating film GI, a sidewall insulating film SW1, and a silicide layer SC. Among these, the silicide layer SC is formed so as to cover the surface of the gate voltage application portion GE, the source region SR, the drain region DR, and the low resistance silicon portion RS2 of the fuse resistance HR. The gate voltage application unit GE is a control electrode for applying a voltage to the MOS transistor GT. These are formed of generally known materials. The silicide layer SC makes it easy to draw the potential of the fuse resistor HR upward.

  Above the MOS transistor MT, wirings M1 to M5 are formed as the same layer as the electrodes M1 to M4 of the MIM capacitor MM. The MOS transistor MT and the electrode M1 are formed by a contact CT, and the wirings M2 to M5 on the MOS transistor MT are formed by vias V1 to V4, respectively.

  The above-described configuration of the MIM capacitor MM is such that, for example, a set of electrodes M1 to M4 arranged at positions overlapping each other in a plan view (all stacked) is a low potential electrode ML or a high potential electrode MH. Each of the pair of electrodes M1 to M4 adjacent to each other in the direction along the MS is a low potential electrode ML and a high potential electrode MH. However, the configuration of the MIM capacitor MM may be a configuration other than that shown in FIGS. 3 to 5, for example, there may be vias V1 to V3 in the region of the MIM capacitor MM for increasing the capacitance, or in plan view. 1 may be configured such that a pair of electrodes M1 to M4 arranged (stacked on each other) at positions overlapping each other are stacked such that the low potential electrode ML and the high potential electrode MH are adjacent to each other.

  Next, a method for manufacturing the semiconductor device DEV of the embodiment shown in FIG. 5 will be described with reference to FIGS.

  Referring to FIG. 6, first, a semiconductor substrate SUB made of a semiconductor material such as silicon is prepared. In FIG. 6, a p-type semiconductor substrate SUB is prepared, but an n-type semiconductor substrate SUB may be used. An element isolation insulating film FO is formed on the main surface MS of the semiconductor substrate SUB by a normal LOCOS (LOCal Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method, and the p-type well regions PWR and n are formed by a generally known method. A type well region NWR is formed.

  Referring to FIG. 7, a gate insulating film GI made of, for example, a silicon oxide film is formed in the MOS transistor formation region by a normal thermal oxidation method, photoengraving technique and etching technique. Thereafter, the gate voltage application portion GE and the resistance silicon portion RS made of polycrystalline silicon are simultaneously formed by a normal CVD (Chemical Vapor Deposition) method and photolithography. Although not shown, a so-called LDD (Lightly Doped Drain) is formed by a normal self-alignment technique using the pattern of the formed gate voltage application unit GE as a mask. Note that the LDD is not shown in FIG.

  Referring to FIG. 8, side wall insulating films SW1 and SW2 of a silicon oxide film and / or a silicon nitride film are simultaneously formed in gate voltage application part GE and resistance silicon part RS by a normal CVD method and etch back. By this process, the gate electrode GT and the fuse resistor HR are formed.

  Referring to FIG. 9, impurity ions are implanted into resistance silicon portion RS using ordinary photoengraving technology and ion implantation technology (that is, in a state where gate electrode GT in the MOS transistor formation region is covered with photoresist PHR). The Here, an amount of impurity ions necessary to form the high resistance silicon portion RS1 is implanted.

  Referring to FIG. 10, after the photoresist PHR in FIG. 9 is removed, a photoresist PHR in contact with the upper surface of the region where the high resistance silicon portion RS1 is formed is formed. In this state, impurity ions are simultaneously implanted into a region where the low-resistance silicon portion RS2 is formed in the gate voltage application portion GE and the resistance silicon portion RS using a normal ion implantation technique. Impurity ions before forming the source region SR and the drain region DR are implanted.

  Referring to FIG. 11, after removal of photoresist PHR in FIG. 10, high-resistance silicon protective film PT is formed so as to be in contact with the upper surface of high-resistance silicon portion RS1 by a normal photolithography technique and etching technique. . The high resistance silicon protective film PT is formed of a silicon oxide film or the like. Next, a photoresist PHR in contact with the upper surface of the high-resistance silicon protective film PT is formed by a normal photoengraving technique, and the protective film PT is formed on the upper surface of the high-resistance silicon portion RS1 by normal etching.

  Referring to FIG. 12, a thin film of a refractory metal such as cobalt or nickel is first formed so as to cover the entire upper surface. Thereafter, by applying heat treatment, the upper surface of the silicon (gate voltage application portion GE, source region SR, drain region DR, and low resistance silicon portion RS2) on which the thin film is formed reacts with the thin film to form a silicide layer SC. The At this time, since the upper surface of the high resistance silicon portion RS1 is covered with the high resistance silicon protective film PT, the silicide layer SC is not formed.

  Referring to FIG. 13, an interlayer insulating film II made of a silicon oxide film is formed so as to cover the entire upper surface of FIG. Thereafter, a part of the interlayer insulating film II is etched from its uppermost surface to form a hole, and the hole is filled with a metal material such as tungsten, thereby forming a contact CT.

  Referring to FIG. 5, a pattern of metal layer M1 made of a (metal) material such as aluminum is formed so as to cover the upper surface of contact CT of FIG. 13 by a normal photolithography technique and etching technique. The pattern of the metal layer M1 has a long planar shape. Thereafter, the interlayer insulating film II is further stacked by the same process as the step of forming the contact CT in FIG. 13, and the via V1 in contact with the upper surface of the metal layer M1 is formed in the interlayer insulating film II.

  Thereafter, by repeating the same process, the metal layers M1 to M5 having a long planar shape, the interlayer insulating film II and the vias V1 to V4 are formed, and the MOS transistor MT and the same layer as the metal layers M1 to M5 are formed. The low potential electrode portion VL and the high potential electrode portion VH having the plurality of MIM capacitors MM are formed, and the semiconductor device DEV of one embodiment is formed.

  If the configuration of the fuse resistor HR is sufficiently higher than that of the electrodes M1 to M4 of the MIM capacitor MM, referring to FIG. 14, the fuse resistor HR does not have the high resistance silicon portion RS1, and is made of polycrystalline silicon. The entire resistance silicon part RS may be the low resistance silicon part RS2. Further, the silicide layer SC may be formed so as to be in contact with the upper surface of the low-resistance silicon part RS2.

  Next, the effects of the embodiment will be described with reference to the related art of the embodiment.

  Referring to FIG. 15, the configuration shown in the schematic top view of this MIM capacitor MM is basically the same as the configuration of MIM capacitor MM of one embodiment of FIG. That is, the electrodes M1 to M4 are arranged in the same manner as the MIM capacitor MM of FIG. 15, and each set of the electrodes M1 to M4 is alternately (alternately) connected to the low potential electrode portion VL or the high potential electrode portion VH in a plan view. Has been. As a result, the electrodes M1 to M4 of the MIM capacitor MM are alternately arranged with the low potential electrode ML and the high potential electrode MH in a plan view.

  However, in FIG. 15, the electrode parts VL and VH and the electrodes M1 to M4 of the MIM capacitor MM are connected by the electrodes M1 to M4. That is, a (metal) material such as aluminum constituting the electrodes M1 to M4 extends from the region constituting the MIM capacitor MM to the electrode portions VL and VH, and is connected to the electrode portions VL and VH. In this respect, FIG. 15 differs from FIG.

  Referring to FIG. 16, for example, conductive foreign material FN is formed in a part of a region where a plurality of MIM capacitors MM in FIG. 15 are arranged, and contacts so as to straddle both adjacent pairs of electrodes M <b> 1 to M <b> 4. Consider the case. At this time, one of the pair of the electrodes M1 to M4 in contact with the foreign substance FN is connected to the low potential electrode portion VL and the other is connected to the high potential electrode portion VH, so the low potential electrode portion VL and the high potential electrode portion are connected. A short circuit occurs between VH and a current flows between the two, causing an interlayer dielectric film II to break down. As a result, all the electrodes M1 to M4 connected to the low potential electrode portion VL and all the electrodes M1 to M4 connected to the high potential electrode portion VH become the same potential and become non-functional. MM will not work.

  Next, referring to FIG. 17, when the electrodes M1 to M4 and the electrode portions VL and VH are connected by the fuse resistor HR of polycrystalline silicon as in the embodiment, the conductive state is the same as in FIG. Let us consider a case in which a foreign material FN is formed and is in contact with both of a pair of adjacent electrodes M1 to M4.

  The value of the electrical resistance of polycrystalline silicon (resistive silicon part RS: see FIG. 5) of the fuse resistor HR is different from the electrical resistance values of the electrodes M1 to M4 and the electrode parts VL and VH, and is usually the electrode M1. Electrical resistance is sufficiently large compared to In particular, by adjusting the concentration of impurity ions, the value of electrical resistance in the high resistance silicon portion RS1 may become very large. Therefore, if a current flows through the fuse resistor HR, the low potential electrode portion VL and the high potential electrode portion VH applied between each pair of adjacent electrodes M1 to M4 as the MIM capacitor MM, Most of the potential difference between is applied to the fuse resistor HR. Accordingly, the foreign substance FN is attached, and the fuse resistor HR connected to the MIM capacitor MM that has caused the dielectric breakdown due to the short-circuit current flows in a self-selective manner. As a result, the electrodes M1 to M4 (including the MIM capacitor MM) to which the foreign substance FN is attached are separated from the electrode portions VL and VH.

  Since only the electrodes M1 to M4 (including the MIM capacitor MM) causing the short circuit to which the foreign matter FN is attached are separated from the electrode portions VL and VH other than the electrodes, the other electrodes M1 to M4 (including the MIM capacitors including the electrodes) MM) can continue to function as a normal MIM capacitor MM without being affected by the short circuit.

  Therefore, according to the configuration of the embodiment, even when the short circuit occurs, the number of MIM capacitors MM that are not used can be minimized. A significant decrease in the yield of the semiconductor device DEV in which a plurality (many) of MIM capacitors MM are arranged can be suppressed.

  Consider the variation of the capacitance value before and after fusing, taking as an example the case of an MIM capacitor formed by a wiring as the same layer as the (metal) wiring in one embodiment. For example, even if the fuse resistor HR connected to the set of the electrodes M1 to M4 is blown and the four MIM capacitors MM formed by the electrodes M1 to M4 are disconnected from the circuit, for example, a total of 400 pieces are provided in the entire semiconductor device DEV. When the MIM capacitor MM exists, the capacity of the entire semiconductor device DEV fluctuates by about 1% or less. For this reason as well, the semiconductor device according to the embodiment can suppress a decrease in yield without affecting the capacitance value unless a highly accurate capacitance value is required for circuit design.

  Further, as in the embodiment, both of the pair of electrodes M1 to M4 adjacent to each other in plan view are connected to the low potential electrode portion VL or the high potential electrode portion VH by the fuse resistor HR. If only the fuse resistor HR connected to one of the pair of adjacent pairs of electrodes M1 to M4 is blown, the effect of the embodiment is exhibited even if the other is not blown. Therefore, the effect of fusing the MIM capacitor MM in which an abnormal current flows as described above from the electrode portion can be further enhanced.

  In the manufacturing method of the embodiment, the fuse resistor HR is simultaneously formed as the same layer as the gate voltage application unit GE. Therefore, the fuse resistor HR (gate voltage application unit GE) can be formed using the same mask as that for forming the gate voltage application unit GE.

  For example, when a so-called PIP capacitor, which is a capacitive element having a pair of polycrystalline silicon electrodes and an interlayer insulating film sandwiched between them, and an electrode portion are connected using the above fuse resistor HR, a pair of Even if one of the electrodes and the fuse resistor can be formed simultaneously, a polycrystalline silicon processing mask for forming the other electrode is required separately.

  On the other hand, in one embodiment, only one type of mask for forming the gate voltage application unit GE is sufficient for the polycrystalline silicon processing mask, and a pair of electrodes of the MIM capacitor is used for the semiconductor device DEV. Since it is formed as the same layer as the (metal) wiring, only a mask for forming the (metal) wiring is sufficient. Accordingly, in one embodiment, it is not necessary to prepare an additional processing mask when forming the semiconductor device DEV that does not form the fuse resistor HR, so that the cost can be reduced without increasing the number of processes and the number of masks. Can be processed.

(Embodiment 2)
The second embodiment differs from the first embodiment in the configuration of the fuse resistor HR. Hereinafter, the second embodiment will be described with reference to FIG.

  Referring to FIG. 18, also in the second embodiment, as in the first embodiment, a pair of adjacent electrodes M1 to M4 in a plan view is divided into a low potential electrode portion VL by a fuse resistance HR of polycrystalline silicon. Alternatively, the high potential electrode portions VH are alternately connected. However, in the second embodiment, both the low potential electrode ML and the low potential electrode ML adjacent to the low potential electrode ML (in a position exceeding one high potential electrode MH) in plan view have the same fuse resistance. It is connected to the low potential electrode part VL by HR.

  Therefore, the fuse resistance of the second embodiment includes one of the low-potential electrodes ML (first electrode layer) formed at a distance from each other in plan view and the other low-potential electrodes ML. One (second electrode layer) is connected to the low potential electrode portion VL by sharing the same fuse resistance HR. More specifically, in particular, the first electrode layer and the second electrode layer are low potential electrodes ML that are adjacent to each other in plan view.

  The same applies to the high potential electrode MH. Specifically, one of the plurality of high potential electrodes MH (third electrode layer) formed at intervals from each other in plan view and one of the other high potential electrodes MH (fourth electrode). Are connected to the high potential electrode portion VH by sharing the same fuse resistance HR. More specifically, in particular, the first electrode layer and the second electrode layer are high potential electrodes MH that are adjacent to each other in plan view.

  Since the first electrode layer and the second electrode layer adjacent to the first electrode layer in plan view supply the same fuse resistance HR, the electrodes M1 to M4 of the fuse resistance HR are extended (in plan view). The width (in the direction intersecting the existing direction) becomes wider. That is, in the first embodiment, each fuse resistor HR has a width corresponding to approximately one of the electrodes M1 to M4, whereas in the second embodiment, each fuse resistor HR is approximately three of the electrodes M1 to M4. It has the width of this. For example, the fuse resistor HR connected to the low potential electrode ML includes a pair of low potential electrodes ML that are adjacent to each other in a plan view and a single high potential electrode MH disposed therebetween. This is because it has a width corresponding to the region.

  The second embodiment is different from the first embodiment only in the above points. Therefore, all configurations, conditions, procedures, effects, and the like not described above for the second embodiment are the same as those of the first embodiment.

  The fuse resistor HR of the second embodiment has basically the same function and effect as the fuse resistor HR of the first embodiment. However, the fuse resistor HR of the second embodiment is wider than the width of the fuse resistor HR of the first embodiment. Since an arbitrary width value between the width value of the fuse resistor HR of the first embodiment and the width value of the fuse resistor HR of the second embodiment can be used, the range of the width value of the fuse resistor HR It can be said that can be designed more freely.

(Embodiment 3)
The third embodiment differs from the first embodiment in the configuration of the fuse resistor HR. Hereinafter, the third embodiment will be described with reference to FIG.

  Referring to FIG. 19, the third embodiment also has basically the same configuration as that of the first embodiment. However, in the first embodiment, both the pair of electrodes M1 to M4 adjacent to each other in plan view are connected to the electrode portions VL and VH by the fuse resistor HR made of polycrystalline silicon. In Mode 3, only one of the pair of electrodes M1 to M4 adjacent to each other in plan view is connected to the electrode portions VL and VH by the fuse resistor HR made of polycrystalline silicon.

  Specifically, in the third embodiment, the connection between the electrodes M1 to M4 and the high potential electrode MH is made by the fuse resistance HR, whereas the connection between the electrodes M1 to M4 and the low potential electrode ML is, for example, As in the related art of FIG. 15, the extended electrodes M1 to M4 are used. Conversely, the electrodes M1 to M4 and the low potential electrode ML may be connected by the fuse resistor HR, and the electrodes M1 to M4 and the high potential electrode MH may be connected by the electrodes M1 to M4. In some capacitors MM, only the connection to the low potential electrode ML may be made by the fuse resistor HR, and in other capacitors MM, only the connection to the high potential electrode MH may be made by the fuse resistor HR. .

  In FIG. 19, the electrodes M1 to M4 that are directly connected to the low potential electrode portion VL without interposing the fuse resistor HR are slightly longer than the electrodes M1 to M4 that are not directly connected to the low potential electrode portion VL. It can be connected to the low potential electrode portion VL. On the other hand, the fuse resistor HR needs to have a length in the extending direction so that the fuse resistor HR can be blown when a current flows therethrough. For this reason, the connection by the fuse resistor HR (connection to the high potential electrode portion VH on the right side in FIG. 19) is flatter than the direct connection by the electrodes M1 to M4 (connection to the low potential electrode portion VL on the left side in FIG. 19). Occupying a large area.

  Accordingly, as shown in FIG. 19, when some of the electrodes M1 to M4 are connected to the electrode portions VL and VH without using the fuse resistor HR, the planar occupation area of the connection portion can be reduced. Therefore, the utilization efficiency of the element area can be improved.

  The third embodiment is different from the first embodiment only in the above points. Therefore, the configurations, conditions, procedures, effects, and the like not described above for the third embodiment are all the same as those of the first embodiment.

  As described above, in the third embodiment, only one of the pair of electrodes M1 to M4 adjacent to each other in plan view is connected to the electrode portions VL and VH by the fuse resistor HR made of polycrystalline silicon. On the other hand, the electrodes M1 to M4 are directly connected to the electrode portions VL and VH without interposing the fuse resistor HR. Even in this case, when a conductive foreign substance that contacts both of the adjacent pair of electrodes M1 to M4 adheres, a current flows through the MIM capacitor MM formed by the pair of electrodes M1 to M4. As a result, the same effect as that of the first embodiment in which the fuse resistor HR is blown out in a selective manner can be obtained.

(Embodiment 4)
The fourth embodiment is different from the second embodiment in the configuration of the fuse resistor HR. Hereinafter, the fourth embodiment will be described with reference to FIG.

  Referring to FIG. 20, also in the fourth embodiment, as in the second embodiment, one of the electrodes ML and MH (first electrode layer) formed in plural in spaced-apart relation in plan view The other electrodes ML and MH (second electrode layer) are connected to the electrode portions VL and VH by sharing the same fuse resistance HR. However, in the fourth embodiment, the electrode layers ML and MH sandwiched between the first electrode layers ML and MH and the second electrode layers ML and MH include the electrode portions VL and VH and the extended electrodes. Connected by M1 to M4.

  That is, in the fourth embodiment, a wide fuse resistance HR is provided as in the second embodiment, but only a part of the electrodes M1 to M4 is formed of the electrode portion by the fuse resistance HR as in the third embodiment. Connected to VL and VH.

  Therefore, in the second embodiment, the fuse resistor HR connected to the electrode portion VL and the fuse resistor HR connected to the electrode portion VH are opposed to each other in the direction in which the electrodes M1 to M4 extend in a plane. On the other hand, in Embodiment 4, these do not oppose each other. For example, the fuse resistor HR on the upper right in FIG. 20 connects a set of two electrodes M1 to M4 and a high potential electrode portion VH, and a set of one electrode M1 to M4 sandwiched between them is Is connected to the low potential electrode portion VL. For this reason, the lower set of the electrodes M1 to M4 of the total of the three electrodes M1 to M4 is not opposed to the fuse resistance HR of the set of the three electrodes M1 to M4, and the electrode is formed by the fuse resistance HR. Connected to the part VL.

  In the fourth embodiment, the interval between adjacent fuse resistors HR is wider than that in the second embodiment in the vertical direction of FIG. For this reason, for example, it is possible to suppress the occurrence of problems such as the polycrystalline silicon melted when the fuse resistor HR is blown and brought into contact with the adjacent fuse resistors HR and the electrodes M1 to M4 in the vertical direction. it can.

  In the fourth embodiment, at least one of a pair of electrodes M1 to M4 adjacent to each other in the vertical direction of FIG. 20 is connected to the electrode portions VL and VH by the fuse resistor HR. For this reason, as in the third embodiment, there is an effect obtained by fusing the fuse resistor HR.

  The fourth embodiment is different from the second embodiment only in the above points. Therefore, all configurations, conditions, procedures, effects, and the like not described above for the fourth embodiment are the same as those for the second embodiment.

(Embodiment 5)
The fifth embodiment differs from the first embodiment in the configuration of the low potential electrode portion VL and the high potential electrode portion VH. Hereinafter, the fifth embodiment will be described with reference to FIGS. 21 and 22.

  Referring to FIG. 21, in the fifth embodiment, low potential electrode portion VL and high potential electrode portion VH are arranged at positions overlapping with electrodes M2-M4 of MIM capacitor MM in plan view so as to cross electrodes M2-M4. Is arranged. That is, the extending directions in the plan view of the low potential electrode portion VL and the high potential electrode portion VH are the same as those in the first embodiment.

  FIG. 22 is a schematic cross-sectional view taken along a line XXII-XXII in FIG. Referring to FIG. 22, electrode portions VL and VH are formed, for example, as the same layer as electrode M1 (wiring M1) and are made of a (metal) material such as aluminum, for example, similarly to electrode M1 (wiring M1). Is done. The electrode portions VL and VH are connected to the fuse resistor HR through the contact CT similarly to the electrode M1. Accordingly, the electrode portions VL and VH are arranged so as to be buried under the electrodes M2 to M4 of the MIM capacitor MM (so as to be sandwiched between the MIM capacitor MM and the semiconductor substrate SUB below it).

  In FIG. 21 and FIG. 22, the lowermost electrode M1 of the set of electrodes M1 to M4 of the MIM capacitor MM is directly connected to the fuse resistor HR via the contact CT, thereby being connected to the electrode portion VL. ing.

  As described above, in the fifth embodiment, the electrode portions VL and VH are formed between the capacitor MM and the semiconductor substrate SUB. As a result, at least a part of the fuse resistor HR is formed between the capacitor MM and the semiconductor substrate SUB.

  22, the electrode M1 of the MIM capacitor MM, which is formed as the same layer as the electrode portion VL, extends in the left-right direction of FIG. 22 like the electrodes M2 to M4 of the capacitor MM (however, the arrangement of the electrode portion VL) The configuration may be a configuration that extends in a direction perpendicular to the paper surface of FIG. 22.

  In the first embodiment, the electrode portions VL and VH arranged outside the MIM capacitor MM in plan view are arranged so as to at least partially overlap the MIM capacitor MM in the fifth embodiment. For this reason, the configuration of the fifth embodiment can reduce the planar occupation area as compared with the configuration of the first embodiment. Therefore, the utilization efficiency of the element area can be improved.

(Embodiment 6)
The sixth embodiment differs from the first embodiment in the planar shape of the fuse resistor HR.

  23 to 27, these all show the left end portion of FIG. 3, that is, the low potential electrode portion VL, the fuse resistor HR connected thereto, and a part of the electrodes M1 to M4 of the MIM capacitor MM. Yes. Referring to FIG. 23, this shows the shape of the above-mentioned part of FIG. 3, and the fuse resistor HR extending in the left-right direction of the drawing in which the electrodes M1 to M4 extend has a rectangular shape.

  Referring to FIG. 24, the fuse resistor HR has a width in the center (vertical direction) intersecting the extending direction in the central portion in the extending direction (left and right direction) of the other region (central portion). Other end portions, etc.) are narrower than the above-mentioned width and have a narrow planar shape.

  As described above, in the sixth embodiment, the fuse resistor HR is related to the first direction in which the fuse resistor HR extends (the horizontal direction in FIG. 23 extending from the low potential electrode portion VL or the high potential electrode portion VH to the electrodes M1 to M4). The width in the second direction (vertical direction in FIG. 23) intersecting the first direction in the partial region (center portion) is the second width in the other region (such as the end portion) other than the partial region. The width is preferably narrower than the width in the direction.

  For example, the fuse resistor HR in FIG. 23 has a rectangular shape in plan view, and the width in the vertical direction is substantially constant. Therefore, the value of the electrical resistance in the high resistance silicon part RS1 and the low resistance silicon part RS2 is substantially constant if the concentration of impurity ions in the resistance silicon parts RS1 and RS2 is substantially constant.

  However, in the case of having a narrow region such as the fuse resistor HR in FIG. 24, even if the concentration of impurity ions in the resistance silicon portions RS1 and RS2 is substantially constant, the electric resistance value in the narrow region has a width. It becomes larger than the electric resistance value in a wide area. For this reason, when a current flows, the potential difference is larger in the narrow and narrow region than in the other regions, so that it is easily blown out. Further, since the width is narrow, the fuse resistor HR can be easily blown even with a small current.

  The width of the fuse resistor HR in FIG. 24 is steeply narrowed at one point (a certain position) in the left-right direction in which the fuse resistor HR extends. However, referring to FIG. 25, the width of the fuse resistor HR is not narrowed sharply at one point (a certain position) in the left-right direction, but gradually narrows so as to be inclined. The fuse resistor HR may have such a planar shape.

  Referring to FIG. 26, the fuse resistor HR is asymmetric with respect to the central axis C in the central portion with respect to the extending direction (left-right direction), and extends to the left of the central axis C (upward and downward in the figure). The width in the vertical direction in the figure on the electrode portion VL side is wider than the width in the vertical direction in the figure on the right side of the central axis C (on the electrodes M1 to M4 side).

  As described above, in the sixth embodiment, the fuse resistor HR has a first portion in the center in the first direction in which it extends (the direction extending from the low potential electrode portion VL or the high potential electrode portion VH to the electrodes M1 to M4). It may be asymmetric with respect to an axis extending in a second direction (vertical direction in the drawing) intersecting the direction of 1.

  Also in this case, for example, in the right region of the fuse resistor HR in FIG. 26, the width is narrower than that of the left region, and therefore, in this region, the electric resistance value is larger than that of the wide region. For this reason, when a current flows, the potential difference is larger in the narrow and narrow region than in the other regions, so that it is easily blown out. Further, since the width is narrow, the fuse resistor HR can be easily blown even with a small current.

  The width of the fuse resistor HR in FIG. 26 is steeply narrowed at one point (a certain position) in the left-right direction in which the fuse resistor HR extends. However, referring to FIG. 27, the width of the fuse resistor HR is not narrowed sharply at one point (a certain position) in the left-right direction, but gradually narrows so as to be inclined. The fuse resistor HR may have such a planar shape.

(Embodiment 7)
The seventh embodiment is different from the first embodiment in the configuration of the fuse resistor. Hereinafter, the seventh embodiment will be described with reference to FIGS. 28 to 31.

  FIG. 28 is a schematic cross-sectional view corresponding to FIG. 4 of the first embodiment. Referring to FIG. 28, in the seventh embodiment, fuse resistor HRM is electrically connected to a set of low potential electrode portion VL and electrodes M1 to M4 through contact CT, and fuse resistor HR is connected to electrodes M1 to M1. It has a configuration extending in the left-right direction in the figure so as to overlap with the set of M4 in a plan view. The fuse resistor HRM (resistive silicon portion RS: see FIG. 5) of the seventh embodiment is made of polycrystalline silicon as in the first embodiment, but this extends directly under the set of the electrodes M1 to M4, so that the electrode M1 The fuse resistor HRM directly below the group of .about.M4 is arranged to be equivalent to the electrode M0 constituting the MIM capacitor MM, similarly to the electrodes M1 to M4. Although not shown, the fuse resistor HR that is electrically connected to the set of the high-potential electrode portion VH and the electrodes M1 to M4 by the contact CT is similarly configured to extend directly below the set of the electrodes M1 to M4. You may have.

  Therefore, in the seventh embodiment, the fuse resistor HRM is arranged as the low potential electrode ML or the high potential electrode MH of the MIM capacitor MM. The fuse resistor HRM is formed so as to be in contact with the upper surface of the element isolation insulating film FO, similarly to the fuse resistor HR of the first embodiment.

  Of the fuse resistor HRM, a region sandwiched between the contact CT on the left side and the contact CT on the right side in FIG. 28 (generally, the region between the electrode portions VL and VH and the MIM capacitor MM) It is a region that is melted by self-selection. The planar shape in this region may be the same as the planar shape of the fuse resistor HR in FIGS. 23 to 27, for example, but particularly in some regions as compared to other regions as in FIGS. 29 and 30. A planar shape having a narrow width is particularly preferable. 29 and FIG. 30 are substantially the same planar shapes as FIG. 24 and FIG.

  FIG. 31 shows the MIM capacitor MM described in FIG. 28 and its peripheral part in more detail, and corresponds to FIG. 5 of the first embodiment. The MIM capacitor MM shown in FIG. 28 corresponds to the MIM capacitor MM surrounded by a dotted line rectangle in FIG. Referring to FIG. 31, the fuse resistor HRM of the seventh embodiment is more specifically described. In the region between the electrode portions VL and VH and the MIM capacitor MM, the high resistance silicon portion RS1 and the high resistance silicon protective film PT The electrode M0 composed of the low-resistance silicon portion RS2 and the silicide layer SC is formed in a region almost directly below the electrodes M1 to M4 of the MIM capacitor MM. However, the low resistance silicon portion RS2 and the silicide layer SC are formed immediately below the contacts CT and vias V1 to V3. The set of the electrode M0 and the electrodes M1 to M4 as the low resistance silicon part RS2 is connected by a contact CT.

  The electrode M0 as the low resistance silicon part RS2 functions as the low potential electrode ML when connected to the low potential electrode part VL as shown in FIGS. 28 and 31, and is connected to the high potential electrode part VH. Functions as a high potential electrode MH.

  The electrode M0 as the low resistance silicon part RS2 is formed at the same time as the gate voltage application part GE as the same layer as the gate voltage application part GE of the MOS transistor GT, similarly to the high resistance silicon part RS1.

  By using a part of the fuse resistor HRM as an electrode of the MIM capacitor MM as in the seventh embodiment, a larger number of MIM capacitors MM can be formed. Therefore, the utilization efficiency of the element area of the semiconductor device DEV can be improved.

(Reference example)
32 is a schematic cross-sectional view corresponding to FIG. 4 of the first embodiment. Referring to FIG. 32, the configuration of each of these figures is basically the same as the configuration of FIGS. 3 and 4, except that the fuse resistor HRA (resistor portion) is a wiring (such as aluminum instead of polycrystalline silicon). Electrode) It is made of the same metal material as M1 to M4. As with the fuse resistor HR of the first embodiment, the fuse resistor HRA formed of a (metal) material such as aluminum is fused with the electrodes M1 to M4 and the electrode portions VL and VH so as to be blown when a current flows. It has a configuration with a different electrical resistance value. Specifically, as shown in FIG. 33 and FIG. 34, for example, the width in some regions is narrower than the width in other regions, thereby reducing the electrical resistance of the narrow regions to other regions and It is larger than the electrical resistance of an aluminum wiring or the like, and has a configuration in which fusing is likely to occur.

  With the above configuration, the fuse resistor HRA can be made of a metal material (such as aluminum) instead of polycrystalline silicon.

Finally, the main points of the embodiment will be described with reference to FIG.
Referring to FIG. 35, the semiconductor device of one embodiment supplies a potential to semiconductor substrate SUB having a main surface, MIM capacitor MM formed on the main surface of semiconductor substrate SUB, and an electrode of MIM capacitor MM. The electrode portions VL and VH are provided.

  The electrode part VL is an electrode part that supplies a relatively low potential, and the electrode part VH is an electrode part that supplies a relatively high potential (than the electrode part VL). The MIM capacitor MM includes a low potential electrode ML to which a relatively low potential is applied by being connected to the electrode portion VL, and a high potential electrode MH to which a relatively high potential is applied by being connected to the electrode portion VH. have. The MIM capacitor MM is formed by the low potential electrode ML, the high potential electrode MH, and the interlayer insulating film II between them. Connection between at least one of a pair of adjacent low potential electrodes ML and high potential electrodes MH in the direction along the main surface of the semiconductor substrate SUB and the electrode portions VL and VH is made by a fuse resistor HR made of polycrystalline silicon. Made. The fuse resistor HR is blown by current flow, and has a configuration in which only the capacitor MM formed by the electrodes ML and MH to which the fuse resistor HR is connected can be disabled.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CT contact, DEV semiconductor device, FN foreign material, FO element isolation insulating film, HR, HRA, HRM fuse resistance, II interlayer insulating film, M0, M1, M2, M3, M4 electrode, MH high potential electrode, ML low potential electrode, MM MIM capacitor, MS main surface, MT transistor, NWR n-type well region, PSR p ^- region, PT high resistance silicon protective film, PWR p-type well region, RS resistance silicon part, RS1 high resistance silicon part, RS2 low resistance silicon Part, SC silicide layer, SUB semiconductor substrate, SW1, SW2 side wall insulating film, V1, V2, V3, V4 via, VH high potential electrode part, VL low potential electrode part.

Claims (13)

A semiconductor substrate having a main surface;
A first capacitor electrode formed on the main surface of the semiconductor substrate, and a second capacitor formed on the main surface of the semiconductor substrate with a gap in the same layer as the first capacitor electrode A capacitive element comprising: an electrode; and an insulator layer formed between the first capacitive electrode and the second capacitive electrode;
A first electrode connected to the first capacitor electrode;
A second electrode portion connected to the second capacitance electrode,
The first capacitor electrode and the second capacitor electrode are the same layer as the wiring arranged around the capacitor element and have a long planar shape,
A plurality of the capacitive elements are formed on the main surface of the semiconductor substrate,
Both the adjacent pair of the first capacitor electrode and the second capacitor electrode to each other, by the resistive portion of polycrystalline silicon are respectively connected to the first electrode portion or said second electrode portion,
A value of electrical resistance in the resistance portion is different from a value of electrical resistance in any one selected from the group consisting of the first capacitance electrode, the second capacitance electrode, the first electrode portion, or the second electrode portion; Semiconductor device. A control element formed on the main surface of the semiconductor substrate;
The control element includes a control electrode for applying a voltage to the control element,
The semiconductor device according to claim 1, wherein the resistance portion is formed as the same layer as the control electrode.   A first electrode layer that is one of the plurality of first capacitor electrodes, and a second electrode layer that is one of the first capacitor electrodes other than the first electrode layer. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the first electrode portion by sharing the same resistance portion.   A third electrode layer that is one of the plurality of second capacitor electrodes, and a fourth electrode layer that is one of the second capacitor electrodes other than the third electrode layer. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the second electrode unit by sharing the same resistance unit.   The first electrode portion or the second electrode portion is formed between the capacitive element and the semiconductor substrate, and at least a part of the resistance portion is formed between the capacitive element and the semiconductor substrate. The semiconductor device according to claim 1.   The resistance portion includes the first direction in a part of the first direction extending from the first electrode portion or the second electrode portion to the first capacitance electrode or the second capacitance electrode. 2. The semiconductor device according to claim 1, wherein a width in a second direction intersecting with the second direction is narrower than a width in the second direction in a region other than the partial region with respect to the first direction.   The resistance portion intersects the first direction at a central portion in a first direction extending from the first electrode portion or the second electrode portion to the first capacitance electrode or the second capacitance electrode. The semiconductor device according to claim 1, wherein the semiconductor device is asymmetric with respect to an axis extending in a second direction.   The semiconductor device according to claim 1, wherein the resistance portion includes a resistance main body portion made of the polycrystalline silicon and a silicide layer that covers a surface of the resistance main body portion.   2. The semiconductor device according to claim 1, wherein the resistance portion is disposed as the first capacitor electrode or the second capacitor electrode of the capacitor element. The resistance portion includes a high resistance silicon portion and a low resistance silicon portion,
The low resistance silicon portion is formed on the same layer as the high resistance silicon portion so as to be in contact with the high resistance silicon portion, and has a sheet resistance smaller than that of the high resistance silicon portion,
A pair of the first capacitor electrode and the second capacitor electrode adjacent to each other are connected to the first electrode unit or the second electrode unit by the low-resistance silicon unit, respectively. Item 14. The semiconductor device according to Item 1. Preparing a semiconductor substrate having a main surface;
A first capacitor electrode formed on the main surface of the semiconductor substrate, and a second capacitor formed on the main surface of the semiconductor substrate with a gap in the same layer as the first capacitor electrode Forming a capacitive element including an electrode and an insulator layer formed between the first capacitive electrode and the second capacitive electrode;
Forming a first electrode portion that is connected to the first capacitor electrode to apply a low potential to the first capacitor electrode;
Forming a second electrode portion for applying a high potential higher than the low potential to the second capacitor electrode by being connected to the second capacitor electrode;
The first capacitor electrode and the second capacitor electrode are the same layer as the wiring arranged around the capacitor element and have a long planar shape,
A plurality of the capacitive elements are formed on the main surface of the semiconductor substrate,
Both the adjacent pair of the first capacitor electrode and the second capacitor electrode to each other, by the resistive portion of polycrystalline silicon are respectively connected to the first electrode portion or said second electrode portion,
A value of electrical resistance in the resistance portion is different from a value of electrical resistance in any one selected from the group consisting of the first capacitance electrode, the second capacitance electrode, the first electrode portion, or the second electrode portion; A method for manufacturing a semiconductor device. Further comprising a step of forming a control element formed on the main surface of the semiconductor substrate,
The control element includes a control electrode;
The method of manufacturing a semiconductor device according to claim 11, wherein the resistance portion and the control electrode are simultaneously formed as the same layer. The resistance portion includes a high resistance silicon portion and a low resistance silicon portion,
The low resistance silicon portion is formed on the same layer as the high resistance silicon portion so as to be in contact with the high resistance silicon portion, and has a sheet resistance smaller than that of the high resistance silicon portion,
A pair of the first capacitor electrode and the second capacitor electrode adjacent to each other are connected to the first electrode unit or the second electrode unit by the low-resistance silicon unit, respectively. Item 14. A method for manufacturing a semiconductor device according to Item 1.

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