JP2017163013A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves a stable resistance value of a resistive element or stable capacitance value of a capacitor without forming an element isolation region which surrounds the resistive element or an electrode of the capacitor in plan view thereby to enable effective use and high density of a substrate area.SOLUTION: A semiconductor device comprises: a first conductivity type first element isolation region which surrounds a first element region in plan view; a first conductivity type second element isolation region which surrounds a second element region in plan view; a second conductivity type well arranged between the first element isolation region and the second element isolation region; an insulation film arranged on the second conductivity type well; and a resistor film or a conductor film arranged on the insulation film.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device provided with a plurality of circuit elements such as a resistance element or a capacitor, a method for manufacturing such a semiconductor device, and the like.

  For example, in a manufacturing process of a semiconductor device in which element isolation is performed in a high concentration impurity diffusion region such as a BCD (bipolar CMOS DMOS) process, etc., it is surrounded by a deep impurity diffusion region (plug) reaching from the epitaxial layer to the underlying substrate Resistive elements or capacitor electrodes are arranged in the element region. However, since such a plug occupies a large area, it is difficult to increase the density of the semiconductor device.

  On the other hand, when the electrode of the resistor element or capacitor is arranged without being surrounded by the plug, the resistance value of the resistor element or the capacitance between the electrode of the resistor element or capacitor and the other plug depends on the potential of the other adjacent plug. The value may fluctuate. In addition, when a high potential is applied to the electrode of the resistor element or capacitor, field inversion occurs in a region between a plurality of adjacent plugs, and a leakage current may flow.

  As a related technique, Patent Document 1 discloses that an oxide film formed on the surface of the epitaxial layer and the element isolation region, a polysilicon resistor formed on the oxide film, and a surface of the oxide film and the polysilicon resistor are formed. A semiconductor device having an interlayer insulating film is disclosed. In order to stabilize the resistance value of the polysilicon resistor, an impurity layer is formed inside the annular shape of the element isolation region, and an electrode formed at a desired position of the interlayer insulating film on the surface of the polysilicon resistor is electrically connected to the impurity layer. It is connected. However, the element isolation region occupies a large area, and it is still difficult to increase the density of the semiconductor device.

JP 2003-282725 A (paragraph 0014, FIG. 1)

  In some embodiments of the present invention, the resistance value of the resistance element is stable without providing an element isolation region surrounding the periphery of the resistance element in plan view, and the substrate area is effectively utilized to increase the density. The present invention relates to providing a semiconductor device capable of achieving the above. In addition, some aspects of the present invention can stabilize the capacitance value of the capacitor without providing an element isolation region that surrounds the periphery of the electrode of the capacitor in a plan view. The present invention relates to providing a semiconductor device capable of doing so. Furthermore, some other aspects of the present invention relate to providing a method for manufacturing such a semiconductor device.

  A semiconductor device according to a first aspect of the present invention includes a first conductivity type first element isolation region surrounding a first element region in a plan view, and a first conductivity type surrounding a second element region in a plan view. A second element isolation region, a second conductivity type well disposed between the first element isolation region and the second element isolation region, and an insulating film disposed on the second conductivity type well And a resistor film or a conductor film disposed on the insulating film. In the present application, the first conductivity type may be N-type and the second conductivity type may be P-type, the first conductivity type may be P-type, and the second conductivity type may be N-type.

  According to the first aspect of the present invention, the resistor film is disposed on the second conductivity type well disposed between the first and second element isolation regions of the first conductivity type via the insulating film. This stabilizes the resistance value of the resistance element without providing an element isolation region surrounding the resistor film in plan view. Or you may arrange | position the conductor film which comprises one electrode of a capacitor on an insulating film instead of a resistor film. In that case, the capacitance value of the capacitor is stabilized without providing an element isolation region surrounding the conductor film in plan view. Therefore, it is possible to provide a semiconductor device capable of increasing the density by effectively utilizing the substrate area.

  Here, the semiconductor device may further include a second conductivity type impurity region disposed in the second conductivity type well and surrounding the resistor film or the conductor film in a plan view. By applying a constant potential to the second conductivity type well through the second conductivity type impurity region, the resistor is applied in a state where different potentials are applied to the first element isolation region and the second element isolation region. Even if a high potential is applied to the body film or the conductor film, field inversion hardly occurs in the second conductivity type well. As a result, it is difficult for a leakage current to flow through the parasitic transistor including the first element isolation region, the second conductivity type well, and the second element isolation region.

  The semiconductor device is further disposed on the second conductivity type well via at least an insulating film, and further includes a second conductor film or a second resistor film surrounding the resistor film or the conductor film in a plan view. You may make it prepare. By applying a constant potential to the second conductor film or the second resistor film, the electric field in the second conductivity type well can be stabilized. Therefore, even if a high potential is applied to the resistor film or the conductor film in a state where different potentials are applied to the first element isolation region and the second element isolation region, the field is generated in the second conductivity type well. Inversion is less likely to occur. As a result, it is difficult for a leakage current to flow through the parasitic transistor including the first element isolation region, the second conductivity type well, and the second element isolation region.

  In the above, the semiconductor device may further include a second conductivity type buried diffusion layer disposed below the second conductivity type well. In that case, the influence of the potential of the first or second element isolation region on the electric field in the second conductivity type well can be reduced.

  In the method for manufacturing a semiconductor device according to the second aspect of the present invention, the first element isolation region of the first conductivity type surrounding the first element region in plan view and the second element region in plan view are enclosed. Forming a first conductivity type second element isolation region; forming an insulating film and a second conductivity type well between the first element isolation region and the second element isolation region; A step of disposing an insulating film on the well of the mold, and a step of forming a resistor film or a conductor film on the insulating film.

  According to the second aspect of the present invention, the resistor film is formed via the insulating film on the second conductivity type well formed between the first conductivity type first and second element isolation regions. This stabilizes the resistance value of the resistance element without providing an element isolation region surrounding the resistor film in plan view. Alternatively, a conductor film constituting one electrode of the capacitor may be formed on the insulating film instead of the resistor film. In that case, the capacitance value of the capacitor is stabilized. Therefore, it is possible to manufacture a semiconductor device capable of increasing the density by effectively utilizing the substrate area.

1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment of the present invention. Sectional drawing in the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a diagram showing a part of a semiconductor device according to a modification of the first embodiment of the present invention. The figure which shows the structural example of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 9 is a diagram illustrating a configuration example of a semiconductor device according to a third embodiment of the present invention.

Embodiments of the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
<First Embodiment>
FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the first embodiment of the present invention. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line BB in FIG. 1A. As shown in FIG. 1B, this semiconductor device includes, as a semiconductor substrate, a P-type base substrate 10 and an epitaxial layer 20 provided by epitaxially growing a P-type semiconductor on the base substrate 10. Yes.

  As a material for the base substrate 10 and the epitaxial layer 20, for example, silicon (Si) is used. Field oxide films 31 to 33 are arranged in a plurality of regions in the surface layer portion of epitaxial layer 20. An interlayer insulating film 50 is disposed on the epitaxial layer 20. In FIG. 1A, the field oxide films 31 to 33, the interlayer insulating film 50, and the like are omitted for easy understanding of the layout of each region.

  Further, the semiconductor device includes N type buried diffusion layers (NBL) 11 and 12 in the surface layer portion of the base substrate 10, and may further include P type buried diffusion layers (PBL) 13 to 15. Part of the buried diffusion layers 11 to 15 may extend to the epitaxial layer 20.

  Further, in the epitaxial layer 20, the semiconductor device has a high concentration N type impurity diffusion region (N plug) 21 reaching the N type buried diffusion layer 11 and a high concentration N type reaching the N type buried diffusion layer 12. Impurity diffusion region (N plug) 22. Here, the N plug 21 corresponds to a first element isolation region surrounding the first element region A1 in plan view, and the N plug 22 is a second element isolation surrounding the second element region A2 in plan view. Corresponds to the area. In the present application, the “plan view” means that each part is seen through from a direction perpendicular to the main surface (upper surface in the drawing) of the epitaxial layer 20.

  In a P-type semiconductor substrate, an N-type buried diffusion layer 11 and an N plug 21 that separates the first element region A1 from the surrounding region, and an N-type buried that separates the second element region A2 from the surrounding region. The diffusion layer 12 and the N plug 22 are also called an N tab. N-type contact regions 21a and 22a are arranged in the N plugs 21 and 22 to apply a potential to the N tab, respectively.

In the element regions A1 and A2, a deep N well is formed, and a plurality of circuit elements such as MOS field effect transistors are arranged. For example, in the first element region A1, a P-channel MOS transistor QP1 and an N-type contact region (N ⁺ ) are arranged. The transistor QP1 has a P-type source region S and drain region D disposed in the deep N well, and a gate electrode G such as polysilicon disposed on the deep N well via a gate insulating film. Yes.

In the second element region A2, a P-channel MOS transistor QP2 and an N-type contact region (N ⁺ ) are arranged. The transistor QP2 has a P-type source region S and drain region D disposed in the deep N well, and a gate electrode G such as polysilicon disposed on the deep N well via a gate insulating film. Yes.

  Normally, the space between the N plug 21 and the N plug 22 is a dead space in which no circuit element is disposed, but in this embodiment, a P well 23 is interposed between the N plug 21 and the N plug 22. Is arranged. The P well 23 may be in contact with the N plug 21 or 22 or may be separated from the N plugs 21 and 22. In the latter case, the breakdown voltage between the P well 23 and the N plugs 21 and 22 can be increased.

A field oxide film 33 such as silicon oxide (SiO ₂ ) is disposed as an insulating film on the P well 23, and a resistor film 40 is disposed on the field oxide film 33. The resistor film 40 is made of, for example, polysilicon doped with impurities and having a predetermined conductivity (specific resistance).

  For example, P-type contact regions 41 and 42 having an impurity concentration higher than that of the resistor film 40 are disposed in the resistor film 40. A wiring layer such as aluminum (Al) or copper (Cu) is disposed on the interlayer insulating film 50, and the wirings 61 and 62 included in the wiring layer are electrically connected to the contact regions 41 and 42, respectively. It is connected. Thereby, the resistor film 40 functions as a resistance element.

  In this way, by disposing the resistor film 40 via the insulating film on the P well 23 disposed between the N plug 21 and the N plug 22, N surrounding the periphery of the resistor film 40 in a plan view. Even if a plug is not provided, the resistance value of the resistance element is stabilized. Therefore, it is possible to provide a semiconductor device capable of increasing the density by effectively utilizing the substrate area.

  A P-type impurity region 24 that surrounds the resistor film 40 in a plan view is disposed in the P well 23. Further, the wiring 63 included in the wiring layer disposed on the interlayer insulating film 50 is electrically connected to the P-type impurity region 24, and the wiring 63 and the P-type impurity region 24 are used to connect the wiring 63. A constant potential can be applied to the P well 23.

  By applying a constant potential to the P well 23, field inversion occurs in the P well 23 even when a high potential is applied to the resistor film 40 while different potentials are applied to the N plug 21 and the N plug 22. It becomes difficult to occur. As a result, the leakage current is less likely to flow through the parasitic transistor composed of the N plug 21, the P well 23, and the N plug 22. Note that since a low-potential power supply potential is applied to the P-type semiconductor substrate, it is desirable that the potential applied to the P well 23 is also a low-potential power supply potential.

  Furthermore, when the P type buried diffusion layer 13 is disposed below the P well 23, the influence of the potential of the N plug 21 or 22 on the electric field in the P well 23 can be reduced. The P type buried diffusion layer 13 may be in contact with the P well 23 or may be separated from the P well 23.

  Further, an N-type semiconductor layer may be provided as the epitaxial layer 20 instead of the P-type semiconductor layer. In that case, it is not necessary to form deep N wells in the element regions A1 and A2, but in order to avoid conduction between the N plug 21 and the N plug 22, the P type buried diffusion layer 13 is in contact with the P well 23. Need to be.

<Manufacturing method>
FIG. 2 is a cross-sectional view in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. First, as the P-type base substrate 10, for example, a silicon (Si) substrate containing boron (B) or the like as a P-type impurity is prepared.

  Next, in the step shown in FIG. 2A, antimony (Sb) or phosphorus (P) is added to the first region B1 and the second region B2 of the base substrate 10 using a mask formed by a photolithography method. ) N-type impurities such as ions are implanted. Further, as shown in FIG. 2B, P-type impurities such as boron (B) ions are implanted into the third region B3 to the fifth region B5 of the base substrate 10.

  Next, in the step shown in FIG. 2C, a P-type or N-type semiconductor layer is formed as an epitaxial layer 20 on the base substrate 10 by epitaxial growth. For example, when a silicon layer is epitaxially grown on a silicon substrate, a P-type semiconductor layer having a desired specific resistance can be formed by mixing a gas of a P-type impurity such as boron (B).

  Next, in the step shown in FIG. 2D, N-type impurities such as phosphorus (P) ions are implanted into a plurality of regions of the epitaxial layer 20 using a mask formed by photolithography.

  Thereafter, the impurities implanted into the base substrate 10 and the epitaxial layer 20 are diffused by heat, so that N-type buried diffusion layers (NBL) 11 and 12 and a P-type buried layer are formed as shown in FIG. Diffusion layers (PBL) 13 to 15 are formed. At that time, part of the buried diffusion layers 11 to 15 may extend to the epitaxial layer 20 by thermal diffusion of impurities.

  Further, the N-type impurities implanted into the epitaxial layer 20 reach the N-type buried diffusion layers 11 and 12, and N plugs 21 and 22 are formed. Here, the N plug 21 corresponds to a first element isolation region surrounding the first element region A1 in plan view, and the N plug 22 is a second element isolation surrounding the second element region A2 in plan view. Corresponds to the area. Further, when a P-type semiconductor layer is provided as the epitaxial layer 20, deep N wells are formed in the element regions A1 and A2.

  Next, in the step shown in FIG. 2F, field oxide films 31 to 33 are formed in a plurality of regions on the main surface (upper surface in the drawing) of the epitaxial layer 20 by, for example, the LOCOS method. The field oxide film 33 is formed between the N plug 21 and the N plug 22. The field oxide films 31 to 33 may be formed after the P well 23 and the like are formed.

  Further, as shown in FIG. 2G, a P-type impurity such as boron (B) ions is implanted into a partial region of the epitaxial layer 20 using a mask formed by a photolithography method. As a result, a P well 23 is formed between the N plug 21 and the N plug 22. As a result, the field oxide film 33 is disposed on a partial region of the P well 23.

  Next, in the step shown in FIG. 2H, the resistor film 40 is formed on a partial region of the field oxide film 33 using a mask formed by photolithography. The resistor film 40 is formed of, for example, polysilicon doped with impurities and having a predetermined conductivity (specific resistance).

Next, in the process shown in FIG. 2I, a gate insulating film such as silicon oxide (SiO ₂ ) is formed on the main surface of the epitaxial layer 20 by, for example, thermally oxidizing the main surface of the epitaxial layer 20. . Further, polysilicon doped with impurities is formed on the gate insulating film, and the polysilicon and the gate insulating film are patterned using a mask formed by a photolithography method. Thereby, the gate electrodes G of the transistors QP1 and QP2 are respectively formed on the partial regions of the element regions A1 and A2 via the gate insulating film.

Further, N-type impurities such as phosphorus (P) ions are implanted into the N plugs 21 and 22 and part of the element regions A1 and A2 using a mask formed by photolithography. Thereby, N-type contact regions 21a and 22a are formed in the N plugs 21 and 22, respectively, and N-type contact regions (N ⁺ ) are formed in the element regions A1 and A2.

Also, a P-type impurity such as boron (B) ions is implanted into the element regions A1 and A2, the P well 23, and a partial region of the resistor film 40 using a mask formed by photolithography. The Thereby, the source region S and the drain region D of the transistor QP1 are formed in the first element region A1, and the source region S and the drain region D of the transistor QP2 are formed in the second element region A2. In addition, a P-type contact region (P ⁺ ) is formed in the P well 23. Further, P-type contact regions 41 and 42 are formed in the resistor film 40.

  In the step of implanting impurities, the field oxide films 31 to 33 and the gate electrode G are used as a hard mask. Subsequent processes are the same as those of a normal semiconductor device manufacturing process. That is, a predetermined number of interlayer insulating films and wiring layers are formed. On each contact region and gate electrode, a contact hole is formed in the interlayer insulating film, and a wiring such as aluminum (Al) or a plug such as tungsten (W) is connected to the contact region and the gate electrode.

  According to the present embodiment, the resistor film 40 is formed on the P well 23 formed between the N plug 21 and the N plug 22 via the insulating film, so that the periphery of the resistor film 40 is viewed in plan view. The resistance value of the resistance element can be stabilized without providing the N plug surrounded by. Therefore, it is possible to manufacture a semiconductor device capable of increasing the density by effectively utilizing the substrate area.

<Modification of First Embodiment>
In the first embodiment, the case where the resistor film 40 is disposed on the insulating film has been described. However, instead of the resistor film 40, as an electrode of a capacitor having a MOS structure or a PIP (polysilicon interlayer) capacitor, A conductor film may be disposed over the insulating film.

  FIG. 3 is a diagram illustrating a configuration example of a part of the semiconductor device according to the modification of the first embodiment of the present invention. In FIG. 3, a capacitor having a MOS structure is shown as an example. An N type impurity region 25 is arranged in a P well 23 arranged between the N plug 21 and the N plug 22 shown in FIG. An N-type contact region 26 having an impurity concentration higher than that of the N-type impurity region 25 is disposed in the N-type impurity region 25. The contact region 26 is used for applying a potential to the N-type impurity region 25.

An insulating film 34 such as silicon oxide (SiO ₂ ) is disposed on the N-type impurity region 25, and a conductor film 40 a is disposed on the insulating film 34. The conductor film 40a is composed of, for example, polysilicon doped with impurities and having conductivity. The conductor film 40a disposed on the insulating film 34 constitutes one electrode of the capacitor, and the N-type impurity region 25 and the contact region 26 constitute the other electrode of the capacitor. In the example shown in FIG. 3, it is necessary to apply a potential higher than the potential of the P well 23 to the contact region 26.

  According to the modification of the first embodiment, the conductor film 40 a is disposed on the P well 23 disposed between the N plug 21 and the N plug 22 via the insulating film 34, whereby the conductor film The capacitance value of the capacitor is stabilized without providing an N plug that surrounds the periphery of 40a in plan view. Therefore, it is possible to provide a semiconductor device capable of increasing the density by effectively utilizing the substrate area.

<Second Embodiment>
FIG. 4 is a diagram illustrating a configuration example of a semiconductor device according to the second embodiment of the present invention. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line BB in FIG. 4A. In FIG. 4A, the field oxide films 31 to 33, the interlayer insulating film 50, and the like are omitted for easy understanding of the layout of each region.

  In the second embodiment, the P-type impurity region 24 in the semiconductor device according to the first embodiment shown in FIG. 1 is omitted, and the field oxide film 33 is expanded. In other respects, the second embodiment may be the same as the first embodiment or its modification.

  As shown in FIG. 4, wiring (conductor film) 63 surrounding the resistor film 40 in plan view is disposed on the P well 23 via the field oxide film 33 and the interlayer insulating film 50. By applying a constant potential to the wiring 63, the electric field in the P well 23 can be stabilized. Therefore, even if a high potential is applied to the resistor film 40 while different potentials are applied to the N plug 21 and the N plug 22, field inversion hardly occurs in the P well 23. As a result, the leakage current is less likely to flow through the parasitic transistor composed of the N plug 21, the P well 23, and the N plug 22.

<Third Embodiment>
FIG. 5 is a diagram showing a configuration example of a semiconductor device according to the third embodiment of the present invention. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line BB in FIG. 5A. In FIG. 5A, the field oxide films 31 to 33, the interlayer insulating film 50, and the like are omitted for easy understanding of the layout of each region.

  In the third embodiment, a resistor film 43 is added to the semiconductor device according to the second embodiment shown in FIG. In other respects, the third embodiment may be the same as the second embodiment.

  As shown in FIG. 5, a resistor film 43 surrounding the resistor film 40 in a plan view is arranged on the P well 23 with a distance from the resistor film 40 via a field oxide film 33. The resistor film 43 can be formed at the same time as the resistor film 40 is formed. A wiring 63 is electrically connected to the resistor film 43. By applying a constant potential to the resistor film 43 via the wiring 63, the electric field in the P well 23 can be further stabilized.

  Therefore, even if a high potential is applied to the resistor film 40 while different potentials are applied to the N plug 21 and the N plug 22, field inversion hardly occurs in the P well 23. As a result, the leakage current is less likely to flow through the parasitic transistor composed of the N plug 21, the P well 23, and the N plug 22. Alternatively, a conductor film may be arranged in place of the resistor film 43.

  In the above embodiment, an example using a P-type semiconductor substrate has been described. However, an N-type semiconductor substrate may be used. In that case, the P-type and the N-type are reversed in the other semiconductor layers and impurity layers. Furthermore, the present invention can be applied not only to a semiconductor device including a MOS field effect transistor but also to a semiconductor device including a circuit element such as another transistor. Thus, the present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those who have ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 10 ... Base substrate, 11, 12 ... N type buried diffused layer, 13-15 ... P type buried diffused layer, 20 ... Epitaxial layer, 21, 22 ... N plug, 21a, 22a ... Contact region, 23 ... P well 24 ... P-type impurity region, 25 ... N-type impurity region, 26 ... contact region, 31-33 ... field oxide film, 34 ... insulating film, 40, 43 ... resistor film, 40a ... conductor film, 41 42, contact region, 50, interlayer insulating film, 61 to 63, wiring, QP1, QP2, P channel MOS transistor.

Claims (6)

A first element isolation region of a first conductivity type surrounding the first element region in plan view;
A second element isolation region of the first conductivity type surrounding the second element region in plan view;
A second conductivity type well disposed between the first element isolation region and the second element isolation region;
An insulating film disposed on the second conductivity type well;
A resistor film or a conductor film disposed on the insulating film;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising a second conductivity type impurity region disposed in the second conductivity type well and surrounding the resistor film or the conductor film in a plan view.   A second conductor film or a second resistor film disposed on the well of the second conductivity type via at least the insulating film and surrounding the resistor film or the conductor film in a plan view; The semiconductor device according to claim 1.   4. The semiconductor device according to claim 1, further comprising a second conductivity type buried diffusion layer disposed below the second conductivity type well. 5.   The semiconductor device according to claim 1, wherein the conductor film disposed on the insulating film constitutes one electrode of a capacitor. Forming a first conductivity type first element isolation region surrounding the first element region in plan view, and forming a first conductivity type second element isolation region surrounding the second element region in plan view; ,
An insulating film and a second conductivity type well are formed between the first element isolation region and the second element isolation region, and the insulating film is disposed on the second conductivity type well. And a process of
Forming a resistor film or a conductor film on the insulating film;
A method for manufacturing a semiconductor device comprising:

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