JP2021153077A - Substrate processing method and substrate processing device - Google Patents

Substrate processing method and substrate processing device Download PDF

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JP2021153077A
JP2021153077A JP2020052159A JP2020052159A JP2021153077A JP 2021153077 A JP2021153077 A JP 2021153077A JP 2020052159 A JP2020052159 A JP 2020052159A JP 2020052159 A JP2020052159 A JP 2020052159A JP 2021153077 A JP2021153077 A JP 2021153077A
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thin film
substrate
substrate processing
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laminated structure
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JP7389693B2 (en
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大 上田
Masaru Ueda
大 上田
洋祐 塙
Yosuke Hanawa
洋祐 塙
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Screen Holdings Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

To efficiently perform etching on a thin film by supplying process liquid for selectively performing etching removal of the thin film to a laminated structure including the thin film in a state where at least only a part of the side surface is exposed.SOLUTION: A substrate proposing system includes: supplying process liquid containing an etchant for selectively performing etching on a thin film to a laminated structure to perform the etching on the thin film from an exposed portion of the thin film; and an electric field application step of giving an alternating electric field to the laminated structure by applying an alternating current voltage to a pair of electrodes arranged so as to sandwich the laminated structure in a state where the process liquid is in contact.SELECTED DRAWING: Figure 3

Description

この発明は、積層構造体に含まれる薄膜を側面よりウェットエッチングする基板処理方法および基板処理装置に関するものである。 The present invention relates to a substrate processing method and a substrate processing apparatus for wet-etching a thin film contained in a laminated structure from a side surface.

半導体装置や液晶表示装置などの電子部品の製造工程には、基板を部分的にエッチング除去して所望のパターンを形成するエッチング工程が含まれる。例えば半導体装置の製造においては、シリコン基材上に形成されたシリコン酸化膜（ＳｉＯ２）をエッチングする際には、ＨＦ２ −等のエッチャントを含む処理液が用いられる（例えば特許文献１、２）。 The manufacturing process of an electronic component such as a semiconductor device or a liquid crystal display device includes an etching step of partially etching and removing a substrate to form a desired pattern. For example, in the manufacture of semiconductor devices, when etching the silicon oxide film formed on a silicon substrate (SiO2), the HF 2 - treatment liquid containing an etchant or the like is used (for example, Patent Documents 1 and 2) ..

特開平９−２２８９１号公報Japanese Unexamined Patent Publication No. 9-22891 特開平９−１１５８７５号公報Japanese Unexamined Patent Publication No. 9-115875

エッチングにより形成しようとするパターン形状は種々である。特にパターンの微細化や電子部品の三次元構造化に伴い、エッチング工程にて、比較的広い開口を有する従前サイズの凹部を形成するだけでなく、開口が狭く且つ深い形状の細長サイズの凹部を形成することが要求されることがある。例えば基材の表面上に互いに異なる組成を有する２種類の薄膜を繰り返して積層して形成された基板（本発明の「積層構造体」の一例に相当）に対して処理液を供給して一方の薄膜（以下「被エッチング薄膜」という）のみをエッチングするという狭所エッチングプロセスが存在する。ここでは、エッチング初期段階では、被エッチング薄膜の露出部位、つまり側面に処理液が接液してエッチング除去する。これにより被エッチング薄膜の膜厚と同サイズの小開口を有する凹部が形成される。そして、被エッチング薄膜に沿って、つまり薄膜の積層方向と直交する方向に上記エッチングを深く進行させて所望の細長サイズの凹部を形成する必要がある。 There are various pattern shapes to be formed by etching. In particular, with the miniaturization of patterns and the three-dimensional structure of electronic components, in the etching process, not only the conventional size recesses with relatively wide openings are formed, but also the elongated recesses with narrow and deep openings are formed. It may be required to form. For example, a treatment liquid is supplied to a substrate (corresponding to an example of the "laminated structure" of the present invention) formed by repeatedly laminating two types of thin films having different compositions on the surface of a base material. There is a narrow space etching process in which only the thin film (hereinafter referred to as "thin film to be etched") is etched. Here, in the initial stage of etching, the treatment liquid comes into contact with the exposed portion of the thin film to be etched, that is, the side surface to remove the etching. As a result, a recess having a small opening having the same size as the film thickness of the thin film to be etched is formed. Then, it is necessary to deeply advance the etching along the thin film to be etched, that is, in the direction orthogonal to the stacking direction of the thin films, to form a recess having a desired elongated size.

しかしながら、被エッチング薄膜の膜厚サイズが１０ｎｍ以下になると、上記狭所エッチングプロセスは後で詳述するように凹部の内部で発生する電気二重層の影響を大きく受ける。より具体的には、処理液に含まれるエッチャントが小開口を有する凹部の内部に移動しようとするのを電気二重層が阻害し、単に上記積層構造体に処理液を供給するのみでは、エッチャントによる薄膜のエッチング除去を効率的に行うことは難しい。その結果、細長サイズの凹部でのエッチングレートが従前サイズの凹部でのエッチングレートよりも大幅に低くなり、所望構造が得られないという問題があった。 However, when the film thickness size of the thin film to be etched becomes 10 nm or less, the narrow space etching process is greatly affected by the electric double layer generated inside the recess as will be described in detail later. More specifically, the electric double layer prevents the etchant contained in the treatment liquid from moving into the recess having a small opening, and simply supplying the treatment liquid to the laminated structure depends on the etching. It is difficult to efficiently remove the etching of the thin film. As a result, there is a problem that the etching rate in the elongated recess is significantly lower than the etching rate in the conventional size recess, and the desired structure cannot be obtained.

この発明は、上記課題に鑑みなされたものであり、側面の少なくとも一部のみが露出された状態の薄膜を含む積層構造体に薄膜を選択的にエッチング除去するための処理液を供給して薄膜を効率良くエッチングする基板処理方法および基板処理装置を提供することを目的とする。 The present invention has been made in view of the above problems, and a thin film is provided by supplying a treatment liquid for selectively etching and removing the thin film to a laminated structure containing the thin film in a state where at least a part of the side surface is exposed. It is an object of the present invention to provide a substrate processing method and a substrate processing apparatus for efficiently etching a thin film.

この発明の一態様は、基板処理方法であって、側面の少なくとも一部のみが露出された状態の薄膜を含む積層構造体に薄膜を選択的にエッチングするエッチャントを含む処理液を供給して薄膜の露出部位より薄膜をエッチングするエッチング工程と、エッチング工程と並行して、処理液が接液している状態の積層構造体を挟み込むように配置された一対の電極に交流電圧を印加して積層構造体に交流電場を与える電場印加工程と、を備えることを特徴としている。 One aspect of the present invention is a substrate processing method, in which a processing liquid containing an etchant for selectively etching a thin film is supplied to a laminated structure containing the thin film in a state where at least a part of the side surface is exposed to form the thin film. In parallel with the etching process of etching the thin film from the exposed part of the surface, and the etching process, an AC voltage is applied to a pair of electrodes arranged so as to sandwich the laminated structure in which the treatment liquid is in contact with the etching process. It is characterized by including an electric field application step of applying an AC electric field to the structure.

また、この発明の他の態様は、側面の少なくとも一部のみが露出された状態の薄膜を含む積層構造体をエッチングする基板処理装置であって、基板を水平に保持する保持機構と、水平に保持された基板に、薄膜を選択的にエッチングするエッチャントを含む処理液を供給する供給ノズルと、処理液が基板に供給された状態において、基板に交流電圧を印加する交流電圧供給機構と、基板の開回路電圧を測定する開回路電圧測定機構と、開回路電圧測定機構により測定された開回路電圧の値に応じて、基板に印加する交流電圧の値を変化させる制御機構と、を備えることを特徴としている。 Another aspect of the present invention is a substrate processing apparatus that etches a laminated structure containing a thin film in which at least a part of a side surface is exposed, and a holding mechanism that holds the substrate horizontally and horizontally. A supply nozzle that supplies a processing liquid containing an etchant that selectively etches a thin film to the held substrate, an AC voltage supply mechanism that applies an AC voltage to the substrate while the treatment liquid is supplied to the substrate, and a substrate. It is provided with an open circuit voltage measuring mechanism for measuring the open circuit voltage of the above and a control mechanism for changing the value of the AC voltage applied to the substrate according to the value of the open circuit voltage measured by the open circuit voltage measuring mechanism. It is characterized by.

このように構成された発明によれば、積層構造体に交流電場が与えられることで薄膜のエッチングに対する電気二重層の影響を抑制し、薄膜にエッチャントを効率的に移動させて薄膜を効率良くエッチングすることができる。 According to the invention configured in this way, an AC electric field is applied to the laminated structure to suppress the influence of the electric double layer on the etching of the thin film, and the etchant is efficiently moved to the thin film to efficiently etch the thin film. can do.

本発明の係る基板処理方法の一実施形態を用いて積層構造体に含まれる薄膜をエッチング除去する基板処理装置の一例を示す模式図である。It is a schematic diagram which shows an example of the substrate processing apparatus which etches and removes a thin film contained in a laminated structure using one Embodiment of the substrate processing method which concerns on this invention. 図１に示す基板処理装置の断面構造を示す図である。It is a figure which shows the cross-sectional structure of the substrate processing apparatus shown in FIG. 一対の電極への電圧印加に応じた電気二重層の変化を模式的に示すモデル図である。It is a model diagram which shows typically the change of the electric double layer in response to voltage application to a pair of electrodes. ＯＣＰ基準で電圧設定を行わなかった際にシリコン基材に与えられるダメージを模式的に示す図である。It is a figure which shows typically the damage which is given to the silicon base material when the voltage is not set by the OCP standard. 本発明に係る基板処理装置の他の実施形態を模式的に示す断面構造図である。It is sectional drawing which shows typically the other embodiment of the substrate processing apparatus which concerns on this invention.

図１は本発明の係る基板処理方法の一実施形態を用いて積層構造体に含まれる薄膜をエッチング除去する基板処理装置の一例を示す模式図であり、本発明に係る基板処理装置の一実施形態に相当する。また、図２は図１に示す基板処理装置の断面構造を示す図である。ここで、エッチング除去の対象となる薄膜１２はシリコン基材１１の表面に形成された厚み１０ｎｍ以下のシリコン酸化膜である。また、薄膜１２上にはポリシリコン層１３が積層方向Ｚに積層されている。このポリシリコン層１３には、例えば内径６０ｎｍの貫通孔１３１が複数個設けられている。このように、本実施形態では、互いに異なる組成を有するシリコン基材１１と、薄膜１２と、ポリシリコン層１３とがこの順序で積層された基板１が本発明の「積層構造体」の一例に相当している。 FIG. 1 is a schematic view showing an example of a substrate processing apparatus for etching and removing a thin film contained in a laminated structure using an embodiment of the substrate processing method according to the present invention, and is an embodiment of the substrate processing apparatus according to the present invention. Corresponds to the form. Further, FIG. 2 is a diagram showing a cross-sectional structure of the substrate processing apparatus shown in FIG. Here, the thin film 12 to be removed by etching is a silicon oxide film having a thickness of 10 nm or less formed on the surface of the silicon base material 11. Further, the polysilicon layer 13 is laminated on the thin film 12 in the lamination direction Z. The polysilicon layer 13 is provided with, for example, a plurality of through holes 131 having an inner diameter of 60 nm. As described above, in the present embodiment, the substrate 1 in which the silicon base material 11, the thin film 12, and the polysilicon layer 13 having different compositions are laminated in this order is an example of the "laminated structure" of the present invention. It is equivalent.

基板１は電極２１で下方から支持されている。また、電極２１で支持された基板１の表面、つまりポリシリコン層１３の表面中央部上に中空構造の枠体３が載置されている。このため、基板１の表面と枠体３の内壁面とでボックス状の空間５が形成され、薄膜１２を選択的にエッチング除去するための処理液、本実施形態では希フッ酸（dHF：Diluted Hydrofluoric acid）４を上記空間５に貯留可能となっている。 The substrate 1 is supported from below by the electrodes 21. Further, a hollow frame 3 is placed on the surface of the substrate 1 supported by the electrodes 21, that is, on the central portion of the surface of the polysilicon layer 13. Therefore, a box-shaped space 5 is formed between the surface of the substrate 1 and the inner wall surface of the frame 3, and a treatment liquid for selectively etching and removing the thin film 12, diluted hydrofluoric acid (dHF: Diluted) in the present embodiment. Hydrofluoric acid) 4 can be stored in the space 5.

上記空間５に対し、希フッ酸４が供給されて貯留されると、一部はポリシリコン層１３に形成された貫通孔１３１を介して薄膜１２に供給され、希フッ酸中に含まれるエッチャント（ＨＦ２ −）により薄膜１２のうち貫通孔１３１に面している領域がエッチングされる。その結果、薄膜１２の側面のうち貫通孔１３１に露出する露出部位が貫通孔１３１を介して供給された処理液と接液する。このため、さらなる時間経過とともに開口（つまり、シリコン基材１１とポリシリコン層１３と間の隙間部分）を介して処理液がシリコン基材１１とポリシリコン層１３とに挟まれた微細領域１４、つまり薄膜１２の膜厚と同サイズの開口から積層方向Ｚと直交する方向に延びる領域に侵入する。これによって、薄膜１２のエッチングが進行する。 When the dilute hydrofluoric acid 4 is supplied and stored in the space 5, a part of the dilute hydrofluoric acid is supplied to the thin film 12 through the through holes 131 formed in the polysilicon layer 13, and the etching is contained in the dilute hydrofluoric acid. (HF 2 -) region facing the through-hole 131 of the thin film 12 is etched by. As a result, the exposed portion of the side surface of the thin film 12 exposed to the through hole 131 comes into contact with the treatment liquid supplied through the through hole 131. Therefore, with the passage of further time, the treatment liquid is sandwiched between the silicon base material 11 and the polysilicon layer 13 through the openings (that is, the gap portion between the silicon base material 11 and the polysilicon layer 13). That is, it penetrates into a region extending in a direction orthogonal to the stacking direction Z from an opening having the same size as the film thickness of the thin film 12. As a result, the etching of the thin film 12 proceeds.

しかしながら、薄膜１２の膜厚は１０ｎｍ以下であるため、処理液で満たされた微細領域１４において電気二重層が形成される。つまり、後の図３に示すように、微細領域１４（図３）とシリコン基材１１との界面近傍、ならびに微細領域１４（図３）とポリシリコン層１３との界面近傍で電気二重層が形成される。特に、シリコン基材１１とポリシリコン層１３との間隔（つまり薄膜１２の厚みに相当）が比較的広い、例えば５０ｎｍ程度である場合には両電気二重層は十分に離間しており、その間をイオンは自由に移動可能となっている。しかしながら、上記間隔が１０ｎｍ程度である場合、両電気二重層が相互に近接してオーバーラップしていることが報告されている（A. Okuyama, et al., Solid State Phenomena, 2015, 219, 115参照）。この電気二重層の影響によって、イオンの移動は制限され、微細領域１４へのエッチャント（ＨＦ２ −）の侵入が抑制されると本願発明者は考察する。 However, since the film thickness of the thin film 12 is 10 nm or less, an electric double layer is formed in the fine region 14 filled with the treatment liquid. That is, as shown in FIG. 3 later, the electric double layer is formed in the vicinity of the interface between the fine region 14 (FIG. 3) and the silicon base material 11, and in the vicinity of the interface between the fine region 14 (FIG. 3) and the polysilicon layer 13. It is formed. In particular, when the distance between the silicon base material 11 and the polysilicon layer 13 (that is, corresponding to the thickness of the thin film 12) is relatively wide, for example, about 50 nm, the two electric double layers are sufficiently separated from each other. Ions can move freely. However, it has been reported that when the above interval is about 10 nm, both electric double layers are close to each other and overlap each other (A. Okuyama, et al., Solid State Phenomena, 2015, 219, 115). reference). The influence of the electric double layer, the movement of ions is restricted, the etchant to fine regions 14 (HF 2 -) of the intrusion is inhibited inventors are discussed.

そこで、本実施形態では、微細領域１４に交流電場Ｅacを印加することで電気二重層による影響を抑制して微細領域１４へのエッチャント（ＨＦ２ −）の侵入を高めている。より詳しくは、図１および図２に示すように、空間５に貯留された希フッ酸４中にプラチナ製の電極２２の先端部が浸漬される。また、電極２１、２２が交流電源６に接続されている。そして、希フッ酸４によるエッチング工程と並行して装置全体を制御する制御部１００からの指令に応じて交流電源６から交流電圧を電極２１、２２の間に印加する。 Therefore, in the present embodiment, by suppressing the influence of the electric double layer by applying an alternating electric field Eac fine region 14 etchant to fine regions 14 - to enhance the penetration of (HF 2). More specifically, as shown in FIGS. 1 and 2, the tip of the platinum electrode 22 is immersed in the dilute hydrofluoric acid 4 stored in the space 5. Further, the electrodes 21 and 22 are connected to the AC power supply 6. Then, in parallel with the etching process using the dilute hydrofluoric acid 4, an AC voltage is applied between the electrodes 21 and 22 from the AC power supply 6 in response to a command from the control unit 100 that controls the entire apparatus.

図３は一対の電極への電圧印加に応じた電気二重層の変化を模式的に示すモデル図であり、同図の（ａ）欄には直流電圧を印加した際の電気二重層の様子が示され、同図の（ｂ）欄には直流電圧を印加した際の電気二重層の様子が示されている。同図中の丸印中にプラス文字が付された記号はカチオン（Ｈ＋）を示し、丸印中にマイナス文字が付された記号はアニオン（ＨＦ２ −）を示している。ここでは、まず電極２１、２２の間に電圧を印加しない場合を説明する。そして、一対の電極２１、２２の間に直流電源を接続して開回路電圧（Open Circuit Potential；ＯＣＰ）に電圧Ｖ１を重畳した直流電圧を電極２１、２２に印加した場合について説明する。その後で電極２１、２２の間にＯＣＰを中心に電圧±Ｖ２で振幅する交流電圧を一対の電極２１、２２に印加した場合について説明する。 FIG. 3 is a model diagram schematically showing the change of the electric double layer according to the voltage application to the pair of electrodes, and the state of the electric double layer when a DC voltage is applied is shown in the column (a) of the figure. It is shown, and the state of the electric double layer when a DC voltage is applied is shown in the column (b) of the figure. Symbols plus characters in circles in the figure is attached represents a cation (H +), the symbol minus character is attached in circle anion - shows (HF 2). Here, first, a case where no voltage is applied between the electrodes 21 and 22 will be described. Then, a case where a DC power supply is connected between the pair of electrodes 21 and 22 and a DC voltage obtained by superimposing the voltage V1 on the open circuit voltage (OCP) is applied to the electrodes 21 and 22 will be described. After that, a case where an AC voltage oscillating with a voltage ± V2 centered on the OCP is applied between the electrodes 21 and 22 to the pair of electrodes 21 and 22 will be described.

電極２１、２２に電圧を印加しない、つまり従来技術では、シリコン基材１１とポリシリコン層１３の表面近傍にカチオンが配列される。このようなカチオンの分布中心となる面は外部ヘルムホルツ面（Outer Helmholtz plane；ＯＨＰ）と呼ばれており、図３では破線で示されている。同図に示すように、微細領域１４に存在するシリコン基材１１に近い外部ヘルムホルツ面とポリシリコン層１３に近い外部ヘルムホルツ面とは、シリコン基材１１とポリシリコン層１３との間隔、つまり薄膜１２の膜厚が小さくになるにしたがって互いに近接する。薄膜１２の膜厚が１０ｎｍ以下になると、両外部ヘルムホルツ面の間に侵入することができるアニオン、つまり薄膜１２のエッチャント（ＨＦ２ −）の数は少なく、微細領域１４におけるエッチャント濃度は低いまま維持される。このため、従来技術により薄膜１２のエッチングを効率的に行うことは困難であったと考えられる。 No voltage is applied to the electrodes 21 and 22, that is, in the prior art, cations are arranged near the surfaces of the silicon substrate 11 and the polysilicon layer 13. The plane that serves as the distribution center of such cations is called the Outer Helmholtz plane (OHP), and is shown by a broken line in FIG. As shown in the figure, the outer Helmholtz surface close to the silicon base material 11 and the outer Helmholtz surface close to the polysilicon layer 13 existing in the fine region 14 are the distance between the silicon base material 11 and the polysilicon layer 13, that is, a thin film. As the film thickness of 12 becomes smaller, they come closer to each other. When the thickness of the thin film 12 is 10nm or less, anion capable of entering between the two external Helmholtz plane, i.e. etchant thin film 12 (HF 2 -) Number of small, maintains the etchant concentration remains low in the fine region 14 Will be done. Therefore, it is considered that it was difficult to efficiently etch the thin film 12 by the conventional technique.

ここで、図３の（ａ）欄に示すように、電極２１、２２の間に直流電圧を印加することで微細領域１４において積層方向Ｚと平行に直流電場Ｅdcが発生する。これにより、シリコン基材１１およびポリシリコン層１３の表面近傍において、カチオンはシリコン基材１１およびポリシリコン層１３の一方側（同図ではポリシリコン層１３側）にシフトし、そのシフト状態が電圧印加中も維持される。つまり、両外部ヘルムホルツ面（図３において微細領域１４に付された実線）は、それらの間隔を維持したまま、単にポリシリコン層１３側にシフトしている（図３の（ａ）欄中の白抜き矢印参照）。したがって、直流電圧を印加したとしても、電気二重層の影響はそのまま残っており、両外部ヘルムホルツ面の間に侵入することができるエッチャント（ＨＦ２ −）の数は依然として少ない。したがって、直流電場Ｅdcの印加によりエッチング効率の向上を図るのは難しいと考えられる。また、後の比較例２で説明するように直流電圧（Ｖ１＝ＯＣＰ＋０．１Ｖ）の印加によってもエッチング量の向上は認められなかった。 Here, as shown in the column (a) of FIG. 3, by applying a DC voltage between the electrodes 21 and 22, a DC electric field Edc is generated in the fine region 14 in parallel with the stacking direction Z. As a result, in the vicinity of the surfaces of the silicon base material 11 and the polysilicon layer 13, the cation shifts to one side of the silicon base material 11 and the polysilicon layer 13 (in the figure, the polysilicon layer 13 side), and the shift state is the voltage. It is maintained during application. That is, both outer Helmholtz planes (solid lines attached to the fine region 14 in FIG. 3) are simply shifted to the polysilicon layer 13 side while maintaining their spacing (in column (a) of FIG. 3). See white arrow). Accordingly, even when a DC voltage is applied, the influence of the electric double layer is left intact, an etchant can penetrate between the two outer Helmholtz plane (HF 2 -) The number of still smaller. Therefore, it is considered difficult to improve the etching efficiency by applying the DC electric field Edc. Further, as described in Comparative Example 2 later, no improvement in the etching amount was observed even by applying a DC voltage (V1 = OCP + 0.1V).

一方、図３の（ｂ）欄に示すように、電極２１、２２の間に交流電圧（ＯＣＰ±Ｖ２）を印加すると、微細領域１４において積層方向Ｚと平行に交流電場Ｅacが発生する。これにより、シリコン基材１１およびポリシリコン層１３の表面近傍において、カチオンは交流電場Ｅacの向きの変化に応じてシリコン基材１１側およびポリシリコン層１３側に向けて交互に移動する。つまり、両外部ヘルムホルツ面（図３において微細領域１４に付された実線）は時間経過に伴って微細領域１４内を振動する（図３の（ｂ）欄中の白抜き矢印参照）。このように本実施形態では、エッチング工程と並行して交流電場Ｅacを印加する、つまり本発明の「電場印加工程」の一例を実行して微細領域１４を電気的に振動させている。これによって電気二重層の影響は抑制され、微細領域１４へのエッチャント（ＨＦ２ −）の侵入を促進させることができ、エッチング効率を向上させることができると考えられる。この点については、後で説明する実施例においても確認されている。 On the other hand, as shown in column (b) of FIG. 3, when an AC voltage (OCP ± V2) is applied between the electrodes 21 and 22, an AC electric field Eac is generated in the fine region 14 in parallel with the stacking direction Z. As a result, in the vicinity of the surfaces of the silicon base material 11 and the polysilicon layer 13, the cations alternately move toward the silicon base material 11 side and the polysilicon layer 13 side according to the change in the direction of the AC electric field Eac. That is, both outer Helmholtz planes (solid lines attached to the fine region 14 in FIG. 3) vibrate in the fine region 14 with the passage of time (see the white arrows in the column (b) of FIG. 3). As described above, in the present embodiment, the AC electric field Eac is applied in parallel with the etching step, that is, an example of the "electric field application step" of the present invention is executed to electrically vibrate the fine region 14. This electric double layer effect is suppressed, the etchant to fine regions 14 (HF 2 -) invasion can be promoted in, it is considered possible to improve the etching efficiency. This point is also confirmed in the examples described later.

なお、エッチング工程において、基板のＯＣＰ値は変動する。後述の実施例に示すように、エッチング工程においては、基板のＯＣＰ値の変動に合わせて交流電場Ｅacを調整することが望ましい。 In the etching process, the OCP value of the substrate fluctuates. As shown in Examples described later, in the etching step, it is desirable to adjust the AC electric field Eac according to the fluctuation of the OCP value of the substrate.

以上のように、本実施形態によれば、本発明の「積層構造体」の一例である基板１に交流電場Ｅacを与えることで薄膜１２のエッチングに対する電気二重層の影響を抑制することができ、その結果、微細領域１４にエッチャントを効率的に移動させて薄膜１２を効率良くエッチングすることができる。このように本実施形態では、ポリシリコン層１３が本発明の「第１膜」の一例に相当している。 As described above, according to the present embodiment, by applying an AC electric field Eac to the substrate 1 which is an example of the "laminated structure" of the present invention, the influence of the electric double layer on the etching of the thin film 12 can be suppressed. As a result, the thin film 12 can be efficiently etched by efficiently moving the etchant to the fine region 14. As described above, in the present embodiment, the polysilicon layer 13 corresponds to an example of the "first film" of the present invention.

なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて上述したもの以外に種々の変更を行うことが可能である。例えば、上記実施形態では、シリコン基材１１、薄膜（シリコン酸化膜）１２およびポリシリコン層１３を積層した基板（積層構造体）１に対して本発明の処理液として希フッ酸４を供給して薄膜１２をエッチングしているが、積層構造体の構成や処理液の種類などについては上記実施形態に限定されるものではない。例えば三次元ＮＡＮＤ型不揮発性半導体装置の製造工程には、互いに異なる組成を有する２種類の薄膜を繰り返して積層して形成された多層膜を有する基板（積層構造体）に処理液を供給して一方の薄膜のみを当該薄膜の側面からエッチング除去する狭所エッチングプロセスが含まれる。この狭所エッチングプロセスに対しても本発明を適用することができる。 The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above embodiment, dilute phosphoric acid 4 is supplied as the treatment liquid of the present invention to the substrate (laminated structure) 1 in which the silicon base material 11, the thin film (silicon oxide film) 12, and the polysilicon layer 13 are laminated. However, the structure of the laminated structure, the type of the treatment liquid, and the like are not limited to the above-described embodiment. For example, in the manufacturing process of a three-dimensional NAND non-volatile semiconductor device, a treatment liquid is supplied to a substrate (laminated structure) having a multilayer film formed by repeatedly laminating two types of thin films having different compositions. A narrow space etching process is included in which only one thin film is etched and removed from the side surface of the thin film. The present invention can also be applied to this narrow space etching process.

また、上記実施形態では、基板１の表面に枠体３を載置することで形成された空間５に希フッ酸４を貯留して基板処理を行う基板処理装置に本発明を適用しているが、その他の構成を有する基板処理装置に対しても本発明を適用可能である。例えば図５に示すように、水平姿勢の基板１の周縁部を導電性チャック２３で保持しながら希フッ酸４を基板１の表面に供給してエッチングする基板処理装置に対しても本発明を適用することができる。 Further, in the above embodiment, the present invention is applied to a substrate processing apparatus that performs substrate processing by storing dilute hydrofluoric acid 4 in a space 5 formed by placing a frame 3 on the surface of the substrate 1. However, the present invention can also be applied to a substrate processing apparatus having other configurations. For example, as shown in FIG. 5, the present invention is also applied to a substrate processing apparatus for etching by supplying dilute hydrofluoric acid 4 to the surface of the substrate 1 while holding the peripheral edge of the substrate 1 in a horizontal posture with a conductive chuck 23. Can be applied.

図５は本発明に係る基板処理装置の他の実施形態を模式的に示す断面構造図である。この基板処理装置が図１および図２に示す装置と大きく相違する点は希フッ酸４の供給態様である。すなわち、本実施形態では、図５に示すように、本発明の「電極」として機能する導電性チャック２３により水平姿勢で保持された基板１の上方位置に供給ノズル２４が配置されている。供給ノズル２４には、処理液供給部２５が接続されている。そして、装置全体を制御する制御部１００からの供給指令に応じて処理液供給部２５が処理液として希フッ酸４を供給ノズル２４に圧送して供給ノズル２４の吐出口２４１から希フッ酸４を基板１の表面に吐出する。これにより、基板１の表面に希フッ酸４の液膜４１が形成され、基板１の表面全体にわたってエッチング工程が進行する。 FIG. 5 is a cross-sectional structure diagram schematically showing another embodiment of the substrate processing apparatus according to the present invention. The major difference between this substrate processing apparatus and the apparatus shown in FIGS. 1 and 2 is the mode of supplying dilute hydrofluoric acid 4. That is, in the present embodiment, as shown in FIG. 5, the supply nozzle 24 is arranged at an upper position of the substrate 1 held in a horizontal position by the conductive chuck 23 functioning as the “electrode” of the present invention. A processing liquid supply unit 25 is connected to the supply nozzle 24. Then, the processing liquid supply unit 25 pumps the dilute hydrofluoric acid 4 as the processing liquid to the supply nozzle 24 in response to the supply command from the control unit 100 that controls the entire apparatus, and the dilute hydrofluoric acid 4 is pumped from the discharge port 241 of the supply nozzle 24. Is discharged onto the surface of the substrate 1. As a result, a liquid film 41 of dilute hydrofluoric acid 4 is formed on the surface of the substrate 1, and the etching process proceeds over the entire surface of the substrate 1.

また、図５に示すように、上記のように供給ノズル２４の吐出口２４１の近傍にプラチナ製の電極２２が配設されている。この電極２２と導電性チャック２３との間に交流電源６が接続されている。そして、制御部１００からの電圧印加指令が交流電源６に与えられることで希フッ酸４によるエッチング工程と並行して交流電源６から交流電圧が電極２２と導電性チャック２３との間に印加される。これによって、基板１に交流電場が与えられ、電気二重層の影響を抑制して基板１の薄膜１２（図２参照）を効率良くエッチングすることができる。 Further, as shown in FIG. 5, a platinum electrode 22 is arranged in the vicinity of the discharge port 241 of the supply nozzle 24 as described above. An AC power supply 6 is connected between the electrode 22 and the conductive chuck 23. Then, a voltage application command from the control unit 100 is given to the AC power supply 6, so that an AC voltage is applied between the electrode 22 and the conductive chuck 23 from the AC power supply 6 in parallel with the etching process by the dilute phosphoric acid 4. NS. As a result, an AC electric field is applied to the substrate 1, the influence of the electric double layer can be suppressed, and the thin film 12 (see FIG. 2) of the substrate 1 can be efficiently etched.

また、図５に示すように、エッチング工程においては基板のＯＣＰ値の変動に合わせて交流電場Ｅacを調整している。すなわち、ポテンショスタットＰは、作用電極（Working
Electrode）ＷＥと、対電極ＣＥ（Counter Electrode）と、参照電極（Reference Electrode）ＲＥを有しており、参照電極ＲＥが基板１の表面に形成された希フッ酸４の液膜に接液される。そして、ポテンショスタットＰが参照電極ＲＥと作用電極ＷＥとの間に生じる電圧の値、つまり希フッ酸４でエッチング処理される基板１のＯＣＰを検出し、その検出結果を制御部１００に与える。一方、制御部１００は基板１のＯＣＰ値の変動に合わせて交流電源６を制御して交流電圧を変化させる。こうして交流電場を調整するため、基板１の薄膜１２（図２参照）をさらに効率良く、安定的にエッチングすることができる。 Further, as shown in FIG. 5, in the etching process, the AC electric field Eac is adjusted according to the fluctuation of the OCP value of the substrate. That is, the potentiostat P is a working electrode (Working).
It has an Electrode) WE, a counter electrode CE (Counter Electrode), and a reference electrode (Reference Electrode) RE, and the reference electrode RE is brought into contact with the liquid film of dilute phosphoric acid 4 formed on the surface of the substrate 1. NS. Then, the potentiostat P detects the value of the voltage generated between the reference electrode RE and the working electrode WE, that is, the OCP of the substrate 1 to be etched with the dilute hydrofluoric acid 4, and gives the detection result to the control unit 100. On the other hand, the control unit 100 controls the AC power supply 6 to change the AC voltage according to the fluctuation of the OCP value of the substrate 1. Since the AC electric field is adjusted in this way, the thin film 12 (see FIG. 2) of the substrate 1 can be etched more efficiently and stably.

このように図５に示す実施形態では、交流電源６が本発明の「交流電圧供給機構」の一例に相当している。また、導電性チャック２３は本発明の「保持機構」の一例に相当している。また、ポテンショスタットＰは本発明の「開回路電圧測定機構」の一例に相当している。さらに、制御部１００は本発明の「制御機構」の一例に相当している。 As described above, in the embodiment shown in FIG. 5, the AC power supply 6 corresponds to an example of the "AC voltage supply mechanism" of the present invention. Further, the conductive chuck 23 corresponds to an example of the "holding mechanism" of the present invention. Further, the potentiostat P corresponds to an example of the "open circuit voltage measuring mechanism" of the present invention. Further, the control unit 100 corresponds to an example of the "control mechanism" of the present invention.

以下、本発明の好ましい態様について、実施例を参照しつつより具体的に説明する。ただし、本発明はもとより下記の実施例によって制限を受けるものではない。したがって、前後記の趣旨に適合しうる範囲で適当に変更を加えて実施することももちろん可能であり、それらはいずれも本発明の技術的範囲に含まれる。 Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to Examples. However, the present invention is not limited by the following examples. Therefore, it is of course possible to make appropriate changes within the range that can be adapted to the gist of the preceding and following description, and all of them are included in the technical scope of the present invention.

ここでは、図２の部分拡大図に示すようにシリコン基材１１、薄膜（シリコン酸化膜）１２およびポリシリコン層１３を積層した基板１を準備した。薄膜１２の膜厚として、５ｎｍと１０ｎｍとの２種類を準備した。また、本発明の「処理液」としてＨＦ（４６〜４８％）とＤＩＷ（脱イオン水：deionized water）を１：５０で混合した希フッ酸４を準備した。ここで、「ＨＦ（４６〜４８％）」とは、濃度が４６〜４８％のフッ化水素酸を意味している。 Here, as shown in the partially enlarged view of FIG. 2, the substrate 1 in which the silicon base material 11, the thin film (silicon oxide film) 12, and the polysilicon layer 13 are laminated was prepared. Two types of film thicknesses, 5 nm and 10 nm, were prepared for the thin film 12. Further, as the "treatment liquid" of the present invention, dilute hydrofluoric acid 4 was prepared by mixing HF (46 to 48%) and DIW (deionized water) at a ratio of 1:50. Here, "HF (46 to 48%)" means hydrofluoric acid having a concentration of 46 to 48%.

また、表１に示すように、エッチング工程を単独で実行し（比較例１）、エッチング工程と並行して電極２１、２２に直流電圧を印加し（比較例２）、エッチング工程と並行して振幅および周波数を多段階に変更しながら電極２１、２２に交流電圧を印加した（実施例１〜実施例６）。そして、電圧追従、膜厚５ｎｍの薄膜１２のエッチング量（図２中の符号ＥＭ）、膜厚１０ｎｍの薄膜１２のエッチング量（図２中の符号ＥＭ）、およびそれらの比（表１中の「５ｎｍ／１０ｎｍ」）を検証し、それらの結果を表１にまとめた。ここで、ＯＣＰは次のようにして事前に求めている。 Further, as shown in Table 1, the etching step is executed independently (Comparative Example 1), a DC voltage is applied to the electrodes 21 and 22 in parallel with the etching step (Comparative Example 2), and in parallel with the etching step. An AC voltage was applied to the electrodes 21 and 22 while changing the amplitude and frequency in multiple stages (Examples 1 to 6). Then, voltage tracking, the amount of etching of the thin film 12 having a film thickness of 5 nm (reference numeral EM in FIG. 2), the amount of etching of the thin film 12 having a film thickness of 10 nm (reference numeral EM in FIG. 2), and their ratios (in Table 1). “5 nm / 10 nm”) was verified, and the results are summarized in Table 1. Here, OCP is obtained in advance as follows.

Figure 2021153077
Figure 2021153077

ＯＣＰの測定は、エッチング工程を行う直前にポテンショスタットやガルバノスタットなどの電気化学測定装置を用いて行う。ここでは、ポテンショスタットを用いてＯＣＰを測定する方法を説明する。 The OCP is measured using an electrochemical measuring device such as a potentiostat or a galvanostat immediately before the etching step. Here, a method of measuring OCP using a potentiostat will be described.

図２に示すポテンショスタットＰは、作用電極ＷＥと、対電極ＣＥと、参照電極ＲＥを有する。作用電極ＷＥは、基板１に電気的に連通状態となっている電極２１から延伸する配線６ｂに接続される。対電極ＣＥは、基板１の上方に配置された電極２２から延伸する配線６ａに接続される。参照電極ＲＥは、空間５に貯留された希フッ酸４中に接液される。ポテンショスタットＰは、参照電極ＲＥと作用電極ＷＥとの間に生じる電圧の値を表示する。この値が希フッ酸４でエッチング処理される基板１のＯＣＰである。 The potentiostat P shown in FIG. 2 has a working electrode WE, a counter electrode CE, and a reference electrode RE. The working electrode WE is connected to the wiring 6b extending from the electrode 21 which is electrically communicated with the substrate 1. The counter electrode CE is connected to the wiring 6a extending from the electrode 22 arranged above the substrate 1. The reference electrode RE is brought into contact with the dilute hydrofluoric acid 4 stored in the space 5. The potentiostat P displays the value of the voltage generated between the reference electrode RE and the working electrode WE. This value is the OCP of the substrate 1 that is etched with the dilute hydrofluoric acid 4.

また、表１中の「電圧追従」とは、エッチング工程においてＯＣＰが変動した場合に、印加電圧とＯＣＰとの差が一定となるように印加電圧の値を変動させることを意味する。ここで印加電圧とは、図２の装置においては、電極２２と電極２１の間の電圧値を意味する。図２の基板処理装置においては、ポテンショスタットＰにより測定されたＯＣＰの値に応じて、制御部１００がＯＣＰの値の変動を相殺するように印加電圧の値を変動させる。なお、基板１に行うエッチング処理において、ＯＣＰの時間変化を予め実験的に求めておき、ＯＣＰをエッチング処理中に測定するかわりに、予め行った測定データをＯＣＰ値として参照しても良い。この点については図５に示す実施形態においても同様である。 Further, "voltage tracking" in Table 1 means that when the OCP fluctuates in the etching process, the value of the applied voltage is fluctuated so that the difference between the applied voltage and the OCP becomes constant. Here, the applied voltage means a voltage value between the electrodes 22 and 21 in the device of FIG. In the substrate processing apparatus of FIG. 2, the control unit 100 fluctuates the value of the applied voltage according to the value of OCP measured by the potentiostat P so as to cancel the fluctuation of the value of OCP. In the etching process performed on the substrate 1, the time change of the OCP may be experimentally obtained in advance, and instead of measuring the OCP during the etching process, the measured data performed in advance may be referred to as the OCP value. This point is the same in the embodiment shown in FIG.

表１に示すように、エッチング工程と並行して直流電場Ｅdcを印加した比較例２では、従来技術（比較例１）と大きな変化はなく、直流電場Ｅdcを印加してもエッチング効率の向上は望めない。 As shown in Table 1, in Comparative Example 2 in which the DC electric field Edc was applied in parallel with the etching process, there was no significant change from the conventional technique (Comparative Example 1), and the etching efficiency was improved even when the DC electric field Edc was applied. I can't hope.

これに対し、実施例２においては、エッチング工程と並行して交流電場Ｅac を印加することでエッチング効率が向上している。このことは、ヘルムホルツ面を振動させることにより微細領域１４へのエッチャント（ＨＦ２ −）の侵入が促進されているとの仮説に整合する。ヘルムホルツ面を、微細領域１４へのエッチャント（ＨＦ２ −）の侵入を許すような振幅および周波数をもって振動させるためには、交流電圧を印加するのみでは足りず、交流電圧の印加電圧の値をエッチング条件に合わせて適正な値に調整する必要がある。 On the other hand, in the second embodiment, the etching efficiency is improved by applying the AC electric field Eac in parallel with the etching step. This etchant to fine regions 14 by vibrating the Helmholtz plane (HF 2 -) invasion is aligned on the hypothesis that has been promoted. Helmholtz surface, the etchant to fine regions 14 (HF 2 -) to vibrate with the amplitude and frequency that permits the penetration alone is not sufficient to apply an AC voltage, etching the value of the applied voltage of the AC voltage It is necessary to adjust to an appropriate value according to the conditions.

実施例１〜６では様々な条件下でのエッチング効率を調べている。 In Examples 1 to 6, the etching efficiency under various conditions is investigated.

実施例１〜６のうち、実施例２、３、４、６は１０ｎｍ厚でのエッチング量に対する１５ｎｍ厚でのエッチング量の比率が増大している。 Of Examples 1 to 6, in Examples 2, 3, 4, and 6, the ratio of the etching amount at 15 nm thickness to the etching amount at 10 nm thickness is increased.

実施例３では、５ｎｍ厚でのエッチング量と、１０ｎｍ厚でのエッチング量がいずれも増大している。実施例６では、５ｎｍ厚でのエッチング量が増大している。 In Example 3, the etching amount at 5 nm thickness and the etching amount at 10 nm thickness are both increased. In Example 6, the amount of etching at a thickness of 5 nm is increased.

実施例３は、５ｎｍ厚でのエッチング量と、１０ｎｍ厚でのエッチング量、１０ｎｍ厚でのエッチング量に対する１５ｎｍ厚でのエッチング量の比率の全てが増大している。このように、実施例６にみられるように、エッチング工程と並行して交流電圧を印加することに加え、電圧追従を行い、さらに印加電圧および交流周波数を適正な値に調整することでエッチング効率を向上させ、かつエッチングの膜厚依存性を抑制しうる。 In Example 3, the ratio of the etching amount at 5 nm thickness, the etching amount at 10 nm thickness, and the etching amount at 10 nm thickness to the etching amount at 10 nm thickness is all increased. In this way, as seen in Example 6, in addition to applying an AC voltage in parallel with the etching process, voltage tracking is performed, and the applied voltage and AC frequency are adjusted to appropriate values to achieve etching efficiency. Can be improved and the etching film thickness dependence can be suppressed.

なお、表１には示していないが、エッチング工程と並行して電場印加工程を実行する場合であっても、ＯＣＰ基準で電圧印加を行わない場合には図４に示すようにシリコン基材１１にダメージ１１ａが発生することがあった。すなわち、電場印加工程においてはＯＣＰ基準で交流電圧を設定するのが望ましい。 Although not shown in Table 1, even when the electric field application step is executed in parallel with the etching step, the silicon base material 11 is shown in FIG. 4 when the voltage is not applied based on the OCP standard. Damage 11a may occur. That is, it is desirable to set the AC voltage based on the OCP in the electric field application process.

本発明は、積層構造体に含まれる薄膜を側面よりウェットエッチングする基板処理方法および基板処理装置全般に適用することができる。 The present invention can be applied to a substrate processing method for wet-etching a thin film contained in a laminated structure from a side surface and a substrate processing apparatus in general.

１…基板（積層構造体）
４…希フッ酸（処理液）
６…交流電源（交流電圧供給機構）
１１…シリコン基材
１２…薄膜（シリコン酸化膜）
１３…ポリシリコン層（第１膜）
２１、２２…（一対の）電極
２３…導電性チャック（電極、保持機構）
２４…供給ノズル
４１…（希フッ酸の）液膜
１００…制御部（制御機構）
Ｅac…交流電場
Ｐ…ポテンショスタット（開回路電圧測定機構）
Ｚ…積層方向
1 ... Substrate (laminated structure)
4 ... Dilute hydrofluoric acid (treatment liquid)
6 ... AC power supply (AC voltage supply mechanism)
11 ... Silicon base material 12 ... Thin film (silicon oxide film)
13 ... Polysilicon layer (first film)
21, 22 ... (pair of) electrodes 23 ... Conductive chuck (electrode, holding mechanism)
24 ... Supply nozzle 41 ... Liquid film (of dilute hydrofluoric acid) 100 ... Control unit (control mechanism)
Eac ... AC electric field P ... Potentiometer (open circuit voltage measurement mechanism)
Z ... Lamination direction

Claims (6)

側面の少なくとも一部のみが露出された状態の薄膜を含む積層構造体に前記薄膜を選択的にエッチングするエッチャントを含む処理液を供給して前記薄膜の露出部位より前記薄膜をエッチングするエッチング工程と、
前記エッチング工程と並行して、前記処理液が接液している状態の前記積層構造体を挟み込むように配置された一対の電極に交流電圧を印加して前記積層構造体に交流電場を与える電場印加工程と、
を備えることを特徴とする基板処理方法。 An etching step in which a treatment liquid containing an etchant for selectively etching the thin film is supplied to a laminated structure containing the thin film in which at least a part of the side surface is exposed, and the thin film is etched from the exposed portion of the thin film. ,
In parallel with the etching step, an electric field that applies an AC voltage to a pair of electrodes arranged so as to sandwich the laminated structure in a state where the processing liquid is in contact with the processing liquid to give an AC electric field to the laminated structure. Application process and
A substrate processing method comprising. 請求項１に記載の基板処理方法であって、
前記積層構造体は、前記薄膜と異なる組成の基材と、前記薄膜と、前記薄膜と異なる組成の第１膜とを積層したものであり、
前記電場印加工程は、前記基材、前記薄膜および第１膜の積層方向において前記積層構造体を挟み込むように前記一対の電極を配置し、前記積層方向と平行に前記交流電場を与える基板処理方法。 The substrate processing method according to claim 1.
The laminated structure is obtained by laminating a base material having a composition different from that of the thin film, the thin film, and a first film having a composition different from that of the thin film.
In the electric field application step, a substrate processing method in which the pair of electrodes are arranged so as to sandwich the laminated structure in the laminating direction of the base material, the thin film, and the first film, and the AC electric field is applied in parallel with the laminating direction. .. 請求項１に記載の基板処理方法であって、
前記積層構造体は前記薄膜と異なる組成の第１膜と前記薄膜とを交互に積層した多層膜を有し、
前記電場印加工程は、前記第１膜と前記薄膜との積層方向において前記積層構造体を挟み込むように前記一対の電極を配置し、前記積層方向と平行に前記交流電場を与える基板処理方法。 The substrate processing method according to claim 1.
The laminated structure has a first film having a composition different from that of the thin film and a multilayer film in which the thin films are alternately laminated.
The electric field application step is a substrate processing method in which the pair of electrodes are arranged so as to sandwich the laminated structure in the laminating direction of the first film and the thin film, and the AC electric field is applied in parallel with the laminating direction. 請求項２または３に記載の基板処理方法であって、
前記電場印加工程は、前記一対の電極の間の開回路電圧を中心に振幅する前記交流電圧を前記一対の電極に印加する基板処理方法。 The substrate processing method according to claim 2 or 3.
The electric field application step is a substrate processing method in which the AC voltage oscillating around the open circuit voltage between the pair of electrodes is applied to the pair of electrodes. 請求項１ないし４のいずれか一項に記載の基板処理方法であって、
前記基板の開回路電圧を計測する工程と、
計測された前記開回路電圧の変動に追従して前記交流電圧を変化させる、基板処理方法。 The substrate processing method according to any one of claims 1 to 4.
The process of measuring the open circuit voltage of the substrate and
A substrate processing method in which the AC voltage is changed according to the measured fluctuation of the open circuit voltage. 側面の少なくとも一部のみが露出された状態の薄膜を含む積層構造体をエッチングする基板処理装置であって、
前記基板を水平に保持する保持機構と、
前記水平に保持された基板に、前記薄膜を選択的にエッチングするエッチャントを含む処理液を供給する供給ノズルと、
前記処理液が基板に供給された状態において、前記基板に交流電圧を印加する交流電圧供給機構と、
前記基板の開回路電圧を測定する開回路電圧測定機構と、
前記開回路電圧測定機構により測定された開回路電圧の値に応じて、前記基板に印加する交流電圧の値を変化させる制御機構と、
を備えることを特徴とする基板処理装置。
A substrate processing device that etches a laminated structure containing a thin film with only a part of the side surface exposed.
A holding mechanism that holds the substrate horizontally,
A supply nozzle that supplies a processing liquid containing an etchant that selectively etches the thin film to the horizontally held substrate, and a supply nozzle.
An AC voltage supply mechanism that applies an AC voltage to the substrate while the treatment liquid is supplied to the substrate.
An open circuit voltage measuring mechanism for measuring the open circuit voltage of the substrate, and an open circuit voltage measuring mechanism.
A control mechanism that changes the value of the AC voltage applied to the substrate according to the value of the open circuit voltage measured by the open circuit voltage measuring mechanism.
A substrate processing apparatus comprising.
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