JP2021152511A - Inspection device and inspection method - Google Patents

Abstract

To provide an inspection device and an inspection method capable of facilitating determination of a wiring capacitance.SOLUTION: A substrate 100 includes a first pattern P1 having a first width W1, a second pattern P2 having a second width W2, and a planar pattern P3. A substrate inspection device 1 is provided with a reference capacitance measurement unit 22 that measures a first capacitance C1 between the first pattern P1 and the planar pattern P3 and measures a second capacitance C2 between the second pattern P2 and the planar pattern P3, an error calculation unit 23 that calculates a difference Δef between design widths and actual widths of the first and second patterns P1 and P2 based on the first capacitance C1 and the second capacitance C2, a correction unit 25 that corrects a reference value for determining wiring A and a wiring capacitance CW based on the difference Δef, a wiring capacity measuring unit 26 that measures the wiring capacity CW, and a determination unit 27 that determines the wiring capacity CW based on the corrected reference value.SELECTED DRAWING: Figure 2

Description

The present invention relates to an inspection device for inspecting a substrate and an inspection method.

Conventionally, a substrate inspection device for inspecting a substrate on which a first wiring and a second wiring are formed adjacent to each other and facing each other has been known (see, for example, Patent Document 1). The substrate inspection apparatus described in Patent Document 1 includes a first probe for contacting one end of the first wiring, a second probe for contacting one end of the second wiring, and first and second probes. A capacitance measuring unit that measures the capacitance between the first wiring and the second wiring as the line capacitance, and at least one of the first wiring and the second wiring based on the line capacitance. It is equipped with a first determination unit for determining the state.

Japanese Unexamined Patent Publication No. 2019-60627

By the way, the line capacitance also changes depending on the facing area of the wiring. Therefore, if the actual wiring width changes with respect to the design wiring width due to variations in the manufacturing of the substrate, the line capacitance also changes. Therefore, the line capacitance changes even if the wiring is not broken or short-circuited, and conventionally, the quality of the wiring is determined in consideration of such a change in the line capacitance. On the other hand, there is a need to make the judgment considering the change in the line capacitance easier.

An object of the present invention is to provide an inspection device and an inspection method capable of facilitating the determination of the capacitance of wiring.

The inspection device according to an example of the present invention is an inspection device for inspecting wiring formed on a substrate, and the substrate has a substantially rectangular shape and has first and second patterns having equal design lengths. And a planar pattern arranged to face the first and second patterns at preset facing intervals, the design width of the first pattern is the first width, and the design of the second pattern. The upper width is a second width different from the first width, and the inspection device measures the capacitance between the first pattern and the planar pattern as the first capacitance, and the second pattern. Based on the reference capacitance measuring unit that measures the capacitance between the surface pattern and the planar pattern as the second capacitance, and the first capacitance and the second capacitance, the design of the first and second patterns An error calculation unit that calculates the difference between the width and the actual width, a storage unit that stores in advance a reference value for determining the capacitance of the wiring, and a correction unit that corrects the reference value based on the difference. A wiring capacity measuring unit that measures the capacitance of the wiring, and a determination unit that determines the capacitance measured by the wiring capacity measuring unit based on a reference value corrected by the correction unit.

Further, the inspection method according to an example of the present invention is an inspection method for inspecting the wiring formed on the substrate, in which the substrate has a substantially rectangular shape and the design lengths are equal to each other. The two patterns and the planar patterns arranged to face each other at preset facing intervals with respect to the first and second patterns are provided, and the design width of the first pattern is the first width and the second pattern. The design width of is a second width different from the first width, and the capacitance between the first pattern and the planar pattern is measured as the first capacitance, and the second pattern and the surface are measured. The design width and practice of the first and second patterns based on the reference capacitance measuring step of measuring the capacitance between the shape patterns as the second capacitance and the first capacitance and the second capacitance. An error calculation step for calculating the difference from the width of the wire, a correction step for correcting the reference value for determining the capacitance of the wiring based on the difference, and a wiring capacitance measurement for measuring the capacitance of the wiring. The step includes a step and a determination step of determining the capacitance measured by the wiring capacitance measuring step based on the reference value corrected by the correction step.

An inspection device and an inspection method having such a configuration can facilitate determination of the capacitance of wiring.

It is a conceptual diagram which shows schematic structure of the substrate inspection apparatus which uses the inspection method which concerns on one Embodiment of this invention. It is explanatory drawing which shows an example of the substrate 100 shown in FIG. 1 and an example of the electric structure of the inspection part 3. It is a top view of the first pattern PA1, PB1, PC1 and the second pattern PA2, PB2, PC2. It is explanatory drawing for demonstrating the measurement of the 1st capacity C1 and the 2nd capacity C2. It is a flowchart which shows an example of the operation of the substrate inspection apparatus shown in FIG. It is a flowchart which shows an example of the operation of the substrate inspection apparatus shown in FIG.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. It should be noted that the configurations with the same reference numerals in the respective figures indicate that they are the same configurations, and the description thereof will be omitted. The substrate inspection device 1 shown in FIG. 1 is an apparatus for inspecting the wiring formed on the substrate 100. The substrate inspection device 1 corresponds to an example of the inspection device.

The substrate inspection device 1 shown in FIG. 1 has a housing 11. The board fixing device 12, the inspection unit 3, the control unit 2, and the inspection unit moving mechanism 15 for appropriately moving the inspection unit 3 in the housing 11 are mainly provided in the internal space of the housing 11. ing. The board fixing device 12 is configured to fix the board 100 to be inspected at a predetermined position.

The inspection unit 3 is located above the substrate 100 fixed to the substrate fixing device 12. An inspection jig 4 for inspecting a circuit pattern formed on the substrate 100 is attached to the inspection unit 3. A plurality of probes Pr are attached to the inspection jig 4.

With reference to FIG. 2, in the substrate 100, for example, when a fan-out package, which is a kind of semiconductor chip package, is manufactured in the RDL (Redistribution Layer) first step, after the RDL is formed on the carrier, the chip die is RDL. It is a board before it is mounted on.

The substrate 100 is composed of a carrier substrate 102, a release layer 103, and an RDL 101 laminated in this order. The RDL101 is, for example, a multilayer substrate including a plurality of wiring layers of the first layer L1, the second layer L2, and the third layer L3.

Wiring A1 to A4 from the first layer L1 to the third layer L3 are formed on the RDL 101. However, after the RDL 101 is formed on the carrier substrate 102 and before the chip die is mounted on the RDL 101, the carrier is attached to one surface (third layer L3) of the RDL 101, so that the carrier is attached to both sides of the RDL. It is not possible to inspect the continuity of the wiring by contacting the probes.

Therefore, the substrate inspection device 1 inspects the wiring by bringing the probe Pr into contact with the exposed side surface (first layer L1) of the RDL 101 and measuring the capacitance of the wiring.

The substrate 100 is not limited to the substrate after the RDL is formed on the carrier and before the chip die is mounted on the RDL. Hereinafter, the wirings A1 to A4 are collectively referred to as wiring A.

Further, the first pattern PA1 and the second pattern PA2 are formed on the first layer L1 of the RDL 101, and the second layer L2 of the RDL 101 faces the first pattern PA1 and the second pattern PA2 in a planar shape. An expanding planar pattern PA3 is formed. A via VA3 extending to the first layer L1 is connected to the planar pattern PA3.

The first pattern PB1 and the second pattern PB2 are formed on the second layer L2 of the RDL 101, and the third layer L3 of the RDL 101 is a surface that spreads in a plane facing the first pattern PB1 and the second pattern PB2. The shape pattern PB3 is formed. Vias VB1, VB2, and VB3 extending to the first layer L1 are connected to the first pattern PB1, the second pattern PB2, and the planar pattern PB3. The planar pattern PB3 may be formed on the first layer L1 as long as it is arranged to face the first pattern PB1 and the second pattern PB2.

A first pattern PC1 and a second pattern PC2 are formed on the third layer L3 of the RDL 101, and a surface of the second layer L2 of the RDL 101 that spreads in a plane facing the first pattern PC1 and the second pattern PC2. The shape pattern PC3 is formed. Vias VC1, VC2, and VC3 extending to the first layer L1 are connected to the first pattern PC1, the second pattern PC2, and the planar pattern PC3. Hereinafter, vias VA3, VB1, VB2, VB3, VC1, VC2, and VC3 are collectively referred to as via V.

With reference to FIG. 3, the first pattern PA1, PB1, PC1 and the second pattern PA2, PB2, PC2 have a rectangular shape in a plan view, and the design length thereof is L. The design width of the first pattern PA1, PB1, PC1 is the first width W1. The design width of the second pattern PA2, PB2, PC2 is the second width W2. The second width W2 is different from the first width W1.

Hereinafter, the first pattern PA1, PB1 and PC1 are collectively referred to as the first pattern P1, the second pattern PA2, PB2 and PC2 are collectively referred to as the second pattern P2, and the planar patterns PA3, PB3 and PC3 are collectively referred to. This is referred to as a planar pattern P3.

The substrate 100 includes, for example, a package substrate or film carrier for a semiconductor package, a printed wiring board, a glass epoxy substrate, a flexible substrate, a ceramic multilayer wiring board, an electrode plate for a display such as a liquid crystal display or an EL (Electro-Luminescence) display, and a touch panel. It may be various substrates such as a transparent conductive plate for use, a semiconductor wafer, a semiconductor chip, a semiconductor substrate such as a CSP (Chip size package), and the like. Inspection points such as wiring patterns, pads, lands, solder bumps, vias, and terminals are formed on the substrate 100.

With reference to FIG. 2, the inspection unit 3 includes a plurality of probe Prs, a scanner unit 31, an AC power supply 32, and a plurality of ammeters 33. Each probe Pr, one end of the AC power supply 32, one end of each ammeter 33, and the circuit ground are connected to the scanner unit 31. The other end of the AC power supply 32 and the other end of each ammeter 33 are connected to the circuit ground.

The scanner unit 31 is a switching circuit configured by using a switching element such as a transistor or a relay switch. The scanner unit 31 connects the AC power supply 32 and each ammeter 33 to an arbitrary probe Pr in response to the control signal from the control unit 2.

The AC power supply 32 is an AC power supply circuit that outputs an AC voltage V having a preset frequency f to the probe Pr via the scanner unit 31. The ammeter 33 is an AC ammeter configured by using, for example, a shunt resistor, a Hall element, an analog-digital converter, or the like. The ammeter 33 detects the current I flowing from the probe Pr connected via the scanner unit 31 to the circuit ground, and transmits a signal indicating the current I to the control unit 2. The voltage V and the current I may be effective values or peak values.

With reference to FIG. 1, the control unit 2 stores in advance, for example, a CPU (Central Processing Unit) that executes a predetermined logical operation, a RAM (Random Access Memory) that temporarily stores data, a predetermined control program, and the like. It is configured by using a non-volatile storage device and a microcomputer equipped with peripheral circuits thereof and the like. The above-mentioned storage device is also used as a storage unit 28.

By executing the above-mentioned control program, for example, the control unit 2 has an inspection control unit 21, a reference capacity measurement unit 22, an error calculation unit 23, a facing interval calculation unit 24, a correction unit 25, a wiring capacity measurement unit 26, and a determination. It functions as a unit 27.

In the storage unit 28, for example, an upper limit reference value RefH (reference value) and a lower limit reference value RefL (reference value) for determining the wiring capacity CW of each wiring A to be inspected are experimentally measured and in advance. It is remembered. The wiring capacitance CW of the wiring A may be the capacitance between the wiring A and all other wirings A, and the wiring A and one or more preset wirings A. It may be a capacitance between. Alternatively, when the carrier substrate 102 is a conductor substrate, the wiring capacitance CW of the wiring A may be the capacitance between the wiring A and the carrier substrate 102. The upper limit reference value RefH and the lower limit reference value RefL are determined based on the capacitance measured on the reference substrate at the same location as the wiring capacitance CW measured by the wiring capacitance measuring unit 26.

The inspection control unit 21 appropriately moves the inspection unit 3 to bring each probe Pr into contact with each inspection point such as a via V on the substrate 100 fixed to the substrate fixing device 12.

The reference capacitance measuring unit 22 measures the capacitance between the first pattern PA1, PB1, PC1 and the planar pattern PA3, PB3, PC3 as the first capacitance C1, and measures the second pattern PA2, PB2, PC2 and the surface. The capacitance between the shape patterns PA3, PB3, and PC3 is measured as the second capacitance C2.

Strictly speaking, the capacitance measured by bringing the probe Pr into contact with the first pattern P1 and the planar pattern P3 also includes the capacitance generated between the first pattern P1 and the surrounding material. Similarly, the capacitance measured by bringing the probe Pr into contact with the second pattern P2 and the planar pattern P3 also includes the capacitance generated between the second pattern P2 and the material surrounding the second pattern P2. However, capacitance is inversely proportional to distance and proportional to area. Therefore, if the distance between the first pattern P1 and the second pattern P2 and the wiring around them is large, the capacitance between the first pattern P1 and the planar pattern P3, which have a large area, and the second pattern The capacitance between P2 and the planar pattern P3 becomes dominant.

Therefore, the capacitance measured by bringing the probe Pr into contact with the first pattern P1 and the planar pattern P3 can be approximated as the capacitance between the first pattern P1 and the planar pattern P3. The capacitance measured by bringing the probe Pr into contact with the second pattern P2 and the planar pattern P3 can be approximated as the capacitance between the second pattern P2 and the planar pattern P3.

Also in the following description, the capacitance between the first pattern P1 and the planar pattern P3 and the capacitance between the second pattern P2 and the planar pattern P3 are based on the above approximation. Explaining.

With reference to FIG. 4, the reference capacitance measuring unit 22 connects the ammeter 33 to the probe Pr in contact with the first pattern P1 to be measured or the via connected to the first pattern P1 by the scanner unit 31. .. Further, the reference capacitance measuring unit 22 connects the AC power supply 32 to the probe Pr in contact with the planar pattern P3 facing the first pattern P1 or the via connected to the planar pattern P3 by the scanner unit 31.

Then, the voltage V of the frequency f output from the AC power supply 32 is applied to the planar pattern P3. As a result, a current I flows through the first capacitance C1 generated between the first pattern P1 and the planar pattern P3, and the current I is measured by the ammeter 33.

When the current I flows when the voltage V of the frequency f is applied to the capacitance C, the capacitance C is given by the following equation (1).
Capacitance C = I / (V × 2πf) ・ ・ ・ (1)

In this case, since V and 2πf are known, the capacitance C can be known if the current I is obtained. Therefore, the reference capacity measuring unit 22 can measure the first capacity C1.

Similarly, the reference capacitance measuring unit 22 connects the ammeter 33 by the scanner unit 31 to the probe Pr in contact with the second pattern P2 to be measured or the via connected to the second pattern P2. Further, the reference capacitance measuring unit 22 connects the AC power supply 32 to the probe Pr in contact with the planar pattern P3 facing the second pattern P2 or the via connected to the planar pattern P3 by the scanner unit 31.

Then, the voltage V of the frequency f output from the AC power supply 32 is applied to the planar pattern P3, and the current I flows through the second capacitance C2 generated between the second pattern P2 and the planar pattern P3. The current I is measured by the ammeter 33. From the current I measured in this way, the reference capacitance measuring unit 22 can measure the second capacitance C2 based on the equation (1).

Hereinafter, the reference capacity measuring unit 22 or the wiring capacity measuring unit 26 measures the first capacity C1, the second capacity C2, and the wiring capacity CW using the scanner unit 31, the AC power supply 32, and the ammeter 33. It is simply described that the reference capacity measuring unit 22 or the wiring capacity measuring unit 26 measures the first capacity C1, the second capacity C2, and the wiring capacity CW.

Further, it is described that bringing the probe Pr into contact with the first pattern P1 or the via connected to the first pattern P1 is simply bringing the probe Pr into contact with the first pattern P1, and the second pattern P2 or the second pattern P2 thereof. Contacting the probe Pr with the via connected to the pattern P2 is described as simply bringing the probe Pr with the second pattern P2, and the probe is attached to the planar pattern P3 or the via connected to the planar pattern P3. Contacting Pr is simply described as bringing probe Pr into contact with the planar pattern P3.

The error calculation unit 23 calculates the difference Δef between the design width and the actual width of the first pattern P1 and the second pattern P2 based on the first capacitance C1 and the second capacitance C2.

Specifically, the error calculation unit 23 calculates the difference Δef based on the first width W1, the second width W2, the first capacitance C1, the second capacitance C2, and the following formula (A).

Difference Δef = (W1-W2 × C1 / C2) / (1-C1 / C2) ... (A)
The formula (A) is obtained as follows. First, assuming that the electrode area S and the capacitance C of the parallel plate capacitor having the distance d between the electrodes are the relative permittivity εr between the electrodes and the permittivity ε0 of the vacuum, the following equation (2) is obtained.
Capacitance C = εr × ε0 × S / d ・ ・ ・ (2)

Since the design area of the first pattern P1 is L × W1 and the area of the first pattern P1 in the actual RDL101 to be inspected is L × (W1-Δef), the first capacitance C1 is expressed by the following formula ( It is represented by 3).

First capacitance C1 = εr × ε0 × L × (W1-Δef) / d ・ ・ ・ (3)
Here, d is the opposite distance between the first pattern P1 and the second pattern P2, and is the distance between adjacent layers in the RDL 101.

Similarly, the second capacity C2 is represented by the following formula (4).

Second capacity C2 = εr × ε0 × L × (W2-Δef) / d ・ ・ ・ (4)

The area of the conductor pattern in the first layer L1, the second layer L2, and the third layer L3 varies depending on the state of the manufacturing process such as etching when forming a pattern on each layer. At this time, not only the pattern width but also the length varies. However, since the width of the wiring pattern is extremely small with respect to the length, the effect of the variation in length on the area of the wiring pattern is extremely smaller than the effect of the variation in width on the area of the wiring pattern. Therefore, as shown in the equations (3) and (4), the difference with respect to the length L can be ignored.

From equations (3) and (4),
C1 / C2 = (W1-Δef) / (W2-Δef) ... (5)

By modifying the formula (5), the above formula (A) is obtained.

The variation in the manufacturing process such as etching when forming a pattern on each layer of the first layer L1, the second layer L2, and the third layer L3 is different between the first pattern P1 and the second pattern P2 and the wiring A in the same layer. , Considered to be about equal. Therefore, it can be considered that the difference Δef obtained by the equation (A) indicates the difference between the design width and the actual width in the wiring A.

If the difference Δef is a negative value less than 0, it means that the actual width is wider than the design width, and if the difference Δef is larger than 0, it means that the actual width is narrower than the design width. Shown.

The facing distance calculation unit 24 calculates the facing distance d based on the following formula (B). Equation (B) is obtained by modifying Equation (3).
Opposing distance d = εr × ε0 × L × (W1-Δef) / C1 ・ ・ ・ (B)

The facing distance calculation unit 24 may calculate the facing distance d based on the following formula (C). Equation (C) is obtained by modifying Equation (4).
Opposing distance d = εr × ε0 × L × (W2-Δef) / C2 ・ ・ ・ (C)

The correction unit 25 corrects the upper limit reference value RefH and the lower limit reference value RefL stored in the storage unit 28 based on the difference Δef.

The wiring capacity measuring unit 26 measures the capacitance C of the wiring A.

The determination unit 27 determines the capacitance C measured by the wiring capacitance measurement unit 26 based on the upper limit reference value RefHc and the lower limit reference value RefLc corrected by the correction unit 25.

Next, the operation of the substrate inspection device 1 configured as described above will be described. With reference to FIG. 5, the inspection control unit 21 brings each probe Pr into contact with the first layer L1 of the substrate 100 (step S1). Specifically, each probe Pr is brought into contact with each first pattern P1, each second pattern P2, each planar pattern P3, and each wiring A.

Next, the reference capacitance measuring unit 22 initializes the variable i to 1 (step S2). Hereinafter, the layer having the number i will be referred to as an L (i) layer. The L (1) layer is the first layer L1, the L (2) layer is the second layer L2, and the L (3) layer is the third layer L3.

Next, the reference capacitance measuring unit 22 measures the first capacitance C1 and the second capacitance C2 with respect to the first pattern P1 and the second pattern P2 of the L (i) layer, and the planar pattern P3 facing them (the first capacitance C1 and the second capacitance C2). Step S3).

Next, the error calculation unit 23 calculates the difference Δef corresponding to the layer L (i) from the formula (A) based on the first capacitance C1 and the second capacitance C2 measured in step S3 (step S4). ).

Next, the correction unit 25 compares the difference Δef with 0 (step S5). If the difference Δef is 0 (YES in step S5), the correction unit 25 sets the upper limit reference value RefH corresponding to the wiring A belonging to the L (i) layer as it is as the upper limit reference value RefHc and belongs to the L (i) layer. The lower limit reference value RefL corresponding to the wiring A is set as the lower limit reference value RefLc as it is (step S6), and the process proceeds to step S10.

As shown in FIG. 2, the wiring A1 belongs to the second layer L2 because it is wired to the second layer L2, the wiring A2 belongs to the third layer L3 because it is wired to the third layer L3, and the wiring A4 belongs to the third layer L3. Since it is wired to the first layer L1, it belongs to the first layer L1.

On the other hand, if the difference Δef is not 0 (NO in step S5) and the difference Δef exceeds 0 (YES in step S7), the correction unit 25 determines the upper limit reference value RefH of the wiring A belonging to the L (i) layer. Is reduced to the upper limit reference value RefHc, and the lower limit reference value RefL of the wiring A belonging to the layer L (i) is reduced to the lower limit reference value RefLc (step S8), and the process proceeds to step S10. Migrate processing.

When the difference Δef is larger than 0 (YES in step S7), it indicates that the actual width is narrower than the design width. If the actual width is narrower than the designed width, the range of the normal wiring capacitance CW of the wiring A is lowered as a whole. Therefore, the reference value can be appropriately corrected by reducing the upper limit reference value RefH and the lower limit reference value RefL.

On the other hand, if the difference Δef does not exceed 0 (NO in step S7), the difference Δef is less than 0. When NO in step S7, the correction unit 25 increases the upper limit reference value RefH of the wiring A belonging to the L (i) layer to obtain the upper limit reference value RefHc, and the lower limit of the wiring A belonging to the L (i) layer. The correction of increasing the reference value RefL to set the lower limit reference value RefLc is executed (step S9), and the process shifts to step S10.

The fact that the difference Δef is less than 0 (NO in step S7) indicates that the actual width is wider than the design width. If the actual width is wider than the design width, the range of the normal wiring capacitance CW of the wiring A increases as a whole. Therefore, the reference value can be appropriately corrected by increasing the upper limit reference value RefH and the lower limit reference value RefL.

In step S10, if the variable i is not 3 (NO in step S10), that is, if there is a layer for which the reference value has not been corrected yet, 1 is added to the variable i (step S11), and steps S3 to S3 again. Repeat S10. On the other hand, when the variable i is 3 (YES in step S10), that is, when the correction processing of the reference values for all of the first layer L1, the second layer L2, and the third layer L3 is completed, the process proceeds to step S21.

With reference to FIG. 6, in step S21, the facing distance calculation unit 24 calculates the facing distance d based on the formula (B) or the formula (C) (step S21).

In this case, the facing distance d between the first layer L1 and the second layer L2 is calculated from the first capacitance C1 or the second capacitance C2 based on the first pattern PA1, the second pattern PA2, and the planar pattern PA3. From the first capacitance C1 or the second capacitance C2 based on the first pattern PB1, the second pattern PB2, and the planar pattern PB3, the facing distance d between the second layer L2 and the third layer L3 is calculated, and the first pattern From the first capacitance C1 or the second capacitance C2 based on the PC1, the second pattern PC2, and the planar pattern PC3, the facing distance d between the second layer L2 and the third layer L3 is calculated.

Next, the wiring capacity measuring unit 26 initializes the variable i to 1 (step S22). Hereinafter, the wiring having the number i will be referred to as wiring A (i). Wiring A (1) is wiring A1, wiring A (2) is wiring A2, and so on.

Next, the wiring capacity measuring unit 26 measures the wiring capacity CW of the wiring A (i) (step S23).

Next, the determination unit 27 compares the wiring capacitance CW of the wiring A (i) with the lower limit reference value RefLc of the wiring A (i) (step S24). If the wiring capacitance CW does not meet the lower limit reference value RefLc (YES in step S24), the determination unit 27 determines that the wiring A (i) is broken (step S25), and shifts the process to step S29.

If the wiring A is broken, the wiring capacity CW decreases. Therefore, if the wiring capacitance CW does not meet the lower limit reference value RefLc, it can be determined that the wiring A is broken. Further, if the width of the wiring A is narrower than the design value due to manufacturing variations, the wiring capacity CW decreases even if the wiring is not broken. Therefore, there is a risk that it may be determined that the wire is broken by mistake. However, since the determination unit 27 makes a determination based on the lower limit reference value RefLc corrected by the correction unit 25, the determination accuracy is improved.

On the other hand, if the wiring capacity CW is equal to or higher than the lower limit reference value RefLc (NOS in step S24), the determination unit 27 compares the wiring capacity CW of the wiring A (i) with the upper limit reference value RefHc of the wiring A (i). (Step S26).

If the wiring capacitance CW exceeds the upper limit reference value RefHc (YES in step S26), the determination unit 27 determines that the wiring A (i) is short-circuited with another conductor (step S27), and proceeds to step S29. Migrate processing.

If the wiring A is short-circuited with a conductor such as another wiring, the wiring capacity CW increases. Therefore, if the wiring capacitance CW exceeds the upper limit reference value RefHc, it can be determined that the wiring A is short-circuited. Further, if the width of the wiring A is larger than the design value due to manufacturing variations, the wiring capacity CW increases even if there is no short circuit. Therefore, there is a risk that it may be erroneously determined that the circuit is short-circuited. However, since the determination unit 27 makes a determination based on the upper limit reference value RefHc corrected by the correction unit 25, the determination accuracy is improved.

On the other hand, if the wiring capacity CW is equal to or less than the upper limit reference value RefHc (NO in step S26), the determination unit 27 determines that the wiring A (i) is normal (step S28), and proceeds to step S29.

In step S29, when the variable i is not 4 (NO in step S29), that is, when the wiring A for which the wiring capacity CW has not been determined remains, 1 is added to the variable i (step S30), and the step is performed again. S23 to S29 are repeated. On the other hand, when the variable i is 4 (YES in step S29), that is, when the determination is completed for all the wirings A, the process ends.

The inspection control unit 21 may display the determination result of steps S25, S27, S28 and / or the facing interval d of step S21 on, for example, a display device (not shown), for example, a wired or wireless communication device (not shown). It may be notified to the outside via.

As described above, according to the processes of steps S1 to S30, the upper limit reference value RefH and the lower limit reference value RefL can be corrected according to the manufacturing variation of the wiring A. Then, since the wiring capacitance CW of the wiring A is determined based on the corrected upper limit reference value RefHc and the lower limit reference value RefLc, it is possible to facilitate the determination of the capacitance of the wiring.

In steps S25 and S27, it is not necessary to determine disconnection or short circuit, and it may be simply determined to be defective. Further, the present invention is not limited to the example in which both the determination of steps S24 and S25 and the determination of steps S26 and S27 are executed. Only one of the determinations may be executed. Further, the substrate to be inspected does not have to have a plurality of wiring layers, and the processes of steps S1 to S30 may be executed only for a single wiring layer in which wiring is formed.

Further, it is not necessary to execute step S21 because the facing interval calculation unit 24 is not provided. Further, the error calculation unit 23 is not necessarily limited to the example of calculating the difference Δef using the equation (A).

That is, the inspection device according to an example of the present invention is an inspection device that inspects the wiring formed on the substrate, and the substrate has a substantially rectangular shape and has the same design lengths of the first and the first. The two patterns and the planar patterns arranged to face each other at preset facing intervals with respect to the first and second patterns are provided, and the design width of the first pattern is the first width and the second pattern. The design width of is a second width different from the first width, and the inspection device measures the capacitance between the first pattern and the planar pattern as the first capacity, and the first capacity is measured. Design of the first and second patterns based on the reference capacitance measuring unit that measures the capacitance between the two patterns and the planar pattern as the second capacitance, and the first capacitance and the second capacitance. An error calculation unit that calculates the difference between the upper width and the actual width, a storage unit that stores in advance a reference value for determining the capacitance of the wiring, and the reference value are corrected based on the difference. A correction unit, a wiring capacity measuring unit that measures the capacitance of the wiring, and a determination unit that determines the capacitance measured by the wiring capacity measuring unit based on a reference value corrected by the correction unit. Be prepared.

Further, the inspection method according to an example of the present invention is an inspection method for inspecting the wiring formed on the substrate, in which the substrate has a substantially rectangular shape and the design lengths are equal to each other. The two patterns and the planar patterns arranged to face each other at preset facing intervals with respect to the first and second patterns are provided, and the design width of the first pattern is the first width and the second pattern. The design width of is a second width different from the first width, and the capacitance between the first pattern and the planar pattern is measured as the first capacitance, and the second pattern and the surface are measured. The design width and practice of the first and second patterns based on the reference capacitance measuring step of measuring the capacitance between the shape patterns as the second capacitance and the first capacitance and the second capacitance. An error calculation step for calculating the difference from the width of the wire, a correction step for correcting the reference value for determining the capacitance of the wiring based on the difference, and a wiring capacitance measurement for measuring the capacitance of the wiring. The step includes a step and a determination step of determining the capacitance measured by the wiring capacitance measuring step based on the reference value corrected by the correction step.

According to these configurations, the reference value can be corrected according to the difference between the design width and the actual width of the first and second patterns, that is, the manufacturing variation of the wiring. Then, since the capacitance of the wiring is determined based on the corrected reference value, it is possible to facilitate the determination of the capacitance of the wiring.

Further, when the correction unit indicates that the actual width is wider than the design width as the correction, the correction unit increases the reference value and the difference is larger than the design width. Also, when it indicates that the actual width is narrow, it is preferable to reduce the reference value.

If the actual width is wider than the designed width, the range of normal capacitance of the wiring will be increased overall. Therefore, the reference value can be appropriately corrected by increasing the reference value. If the actual width is narrower than the designed width, the range of normal capacitance of the wiring is reduced overall. Therefore, the reference value can be appropriately corrected by reducing the reference value.

Further, when the first width is W1, the second width is W2, the first capacity is C1, the second capacity is C2, and the difference is Δef, the error calculation unit has the following formula (A). It is preferable to calculate the difference Δef based on.
Difference Δef = (W1-W2 × C1 / C2) / (1-C1 / C2) ... (A)

According to the formula (A), the difference Δef can be calculated.

Further, when the design length is L, the facing distance is d, the relative permittivity of the substrate of the substrate is εr, and the permittivity of vacuum is ε0, the following formula (B) or formula (C) It is preferable to further include a facing interval calculation unit that calculates the facing spacing d based on the above.
Opposing distance d = εr × ε0 × L × (W1-Δef) / C1 ・ ・ ・ (B)
Opposing distance d = εr × ε0 × L × (W2-Δef) / C2 ・ ・ ・ (C)

According to the formula (B) or the formula (C), the facing distance d can be calculated. Depending on the manufacturing process, the facing distance d may vary. It is also possible to feed back the calculated facing interval d to the manufacturer and use it for quality improvement.

Further, the substrate includes a plurality of wiring layers, the first and second patterns are formed for each of the wiring layers, and the planar pattern is provided corresponding to each of the first and second patterns. The error calculation unit calculates the error for each wiring layer, and the correction unit calculates the reference value based on the error calculated for the wiring layer on which the corresponding wiring is formed. It is preferable to do so.

According to this configuration, even for a substrate provided with a plurality of wiring layers, it is possible to easily determine the capacitance of the wiring formed in each wiring layer by reflecting the manufacturing variation for each layer.

1 Board inspection device (inspection device)
2 Control unit 3 Inspection unit 4 Inspection jig 11 Housing 12 Board fixing device 15 Inspection unit movement mechanism 21 Inspection control unit 22 Reference capacity measurement unit 23 Error calculation unit 24 Facing interval calculation unit 25 Correction unit 26 Wiring capacity measurement unit 27 Judgment Part 28 Storage part 31 Scanner part 32 AC power supply 33 Ammeter 100 Board 102 Carrier board 103 Peeling layer A, A1 to A4 Wiring C1 First capacity C2 Second capacity CW Wiring capacity I Current L1 First layer (wiring layer)
L2 second layer (wiring layer)
L3 third layer (wiring layer)
P1, PA1, PB1, PC1 First pattern P2, PA2, PB2, PC2 Second pattern P3, PA3, PB3, PC3 Planar pattern Pr probe RefH Upper limit reference value (reference value)
RefHc upper limit reference value (correction value)
RefL lower limit reference value (reference value)
RefLc lower limit reference value (correction value)
V Voltage W1 First width W2 Second width d Opposing distance f Frequency Δef Difference ε0 Permittivity εr Relative permittivity

Claims (6)

An inspection device that inspects the wiring formed on the board.
The substrate has a substantially rectangular shape, and has a surface shape in which the first and second patterns having the same design length and the first and second patterns are arranged to face each other at a preset facing interval with respect to the first and second patterns. A pattern is provided, the design width of the first pattern is the first width, and the design width of the second pattern is a second width different from the first width.
The inspection device is
Reference capacitance measurement in which the capacitance between the first pattern and the planar pattern is measured as the first capacitance, and the capacitance between the second pattern and the planar pattern is measured as the second capacitance. Department and
An error calculation unit that calculates the difference between the design width and the actual width of the first and second patterns based on the first capacity and the second capacity.
A storage unit that stores in advance a reference value for determining the capacitance of the wiring, and
A correction unit that corrects the reference value based on the difference,
A wiring capacity measuring unit that measures the capacitance of the wiring,
An inspection device including a determination unit that determines the capacitance measured by the wiring capacity measurement unit based on a reference value corrected by the correction unit. The correction unit serves as the correction.
When the difference indicates that the actual width is wider than the design width, the reference value is increased.
The inspection device according to claim 1, wherein when the difference indicates that the actual width is narrower than the design width, the reference value is reduced. The error calculation unit is based on the following formula (A) when the first width is W1, the second width is W2, the first capacity is C1, the second capacity is C2, and the difference is Δef. The inspection device according to claim 1 or 2, wherein the difference Δef is calculated.
Difference Δef = (W1-W2 × C1 / C2) / (1-C1 / C2) ... (A) When the design length is L, the facing distance is d, the relative permittivity of the substrate of the substrate is εr, and the permittivity of vacuum is ε0, it is based on the following formula (B) or formula (C). The inspection device according to claim 3, further comprising a facing interval calculating unit for calculating the facing interval d.
Opposing distance d = εr × ε0 × L × (W1-Δef) / C1 ・ ・ ・ (B)
Opposing distance d = εr × ε0 × L × (W2-Δef) / C2 ・ ・ ・ (C) The substrate includes a plurality of wiring layers, the first and second patterns are formed for each of the wiring layers, and the planar pattern is provided corresponding to each of the first and second patterns.
The error calculation unit calculates the error for each wiring layer.
The inspection device according to any one of claims 1 to 4, wherein the correction unit calculates the reference value based on the error calculated for the wiring layer on which the corresponding wiring is formed. It is an inspection method that inspects the wiring formed on the board.
The substrate has a substantially rectangular shape, and has a surface shape in which the first and second patterns having the same design length and the first and second patterns are arranged to face each other at a preset facing interval with respect to the first and second patterns. A pattern is provided, the design width of the first pattern is the first width, and the design width of the second pattern is a second width different from the first width.
Reference capacitance measurement in which the capacitance between the first pattern and the planar pattern is measured as the first capacitance, and the capacitance between the second pattern and the planar pattern is measured as the second capacitance. Process and
An error calculation step of calculating the difference between the design width and the actual width of the first and second patterns based on the first capacity and the second capacity, and
A correction step of correcting a reference value for determining the capacitance of the wiring based on the difference, and
The wiring capacity measuring process for measuring the capacitance of the wiring and
An inspection method including a determination step of determining a capacitance measured by the wiring capacitance measuring step based on a reference value corrected by the correction step.

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