JP2021125507A - Wiring board and method for manufacturing wiring board - Google Patents

Abstract

To provide a wiring board and a method for manufacturing a wiring board that can mount a semiconductor chip well and can suppress a decrease in yield in an encapsulating resin formation process and a semiconductor chip mounting process, and a method for manufacturing the semiconductor chip.SOLUTION: A wiring board has a first wiring board and a second wiring board with finer wiring than the first wiring board bonded to the first wiring board, and in a semiconductor device that is mounted on the opposite side of the bonding surface of the second wiring board with the first wiring board, the second wiring board contains at least two kinds of insulating resin with different storage moduli.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

In recent years, with the progress of high speed and high integration of semiconductor devices, the pitch of connection terminals with semiconductor chips has been narrowed and the board wiring has become finer for FC-BGA (Flip Chip-Ball Grid Array) wiring boards. It has been demanded. On the other hand, the connection between the FC-BGA wiring board and the motherboard is required to be connected with connection terminals having a pitch that is almost the same as the conventional one. In order to narrow the pitch of the semiconductor chip and connection terminals and miniaturize the board wiring, a method of forming wiring on silicon and connecting it to the FC-BGA wiring board as a chip connection board (silicon interposer) is patented. It is disclosed in Document 1. Further, Patent Document 2 discloses a method of forming fine wiring after flattening the surface of a wiring board for FC-BGA by CMP (Chemical Mechanical Polishing) or the like. Further, Patent Document 3 discloses a method in which a fine wiring layer is formed on a support substrate, mounted on an FC-BGA substrate, and then the support substrate is peeled off to form a narrow-pitch wiring board.

JP-A-2002-280490 Japanese Unexamined Patent Publication No. 2014-225671 WO2018 / 047861

The silicon interposer is manufactured by using a silicon wafer and using equipment for a semiconductor front-end process. Silicon wafers are limited in shape and size, the number of interposers that can be manufactured from a single wafer is small, and the manufacturing equipment is expensive, so the interposers are also expensive. Further, since the silicon wafer is a semiconductor, there is a problem that the transmission characteristics are also deteriorated.

Further, in the method of flattening the surface of the FC-BGA wiring board and forming a fine wiring layer on the surface, there is no problem of deterioration of transmission characteristics seen in the silicon interposer, but the FC-BGA wiring board is manufactured. There is a problem that the yield is lowered by the sum of the defect and the defect at the time of forming the fine wiring with high difficulty, and there is a problem in mounting the semiconductor element due to the warp and distortion of the wiring board for FC-BGA.

On the other hand, in the method of forming a fine wiring layer on the support board and mounting it on the FC-BGA board, there is a problem of transmission special deterioration and the FC-BGA wiring board and the fine wiring layer are formed separately, so that the total is total. There is no problem that the yield decreases. However, when a fine wiring layer is formed on the support substrate and mounted on the FC-BGA substrate, there are the following problems. That is, when the support substrate is peeled off after being mounted on the FC-BGA wiring board, defects occur in the sealing resin forming process and the semiconductor chip mounting process due to the deformation of the thin and low-rigidity fine wiring layer, resulting in a high yield. There was a problem of decline. Even after the support substrate was peeled off, it did not deform, and it was necessary to form a fine wiring layer having excellent shape stability.

Therefore, the present invention has been made in view of the above problems, and in a method of forming a fine wiring layer on a support substrate and mounting it on an FC-BGA substrate, a method for manufacturing a wiring board and a wiring board that can be manufactured with good yield is provided. It is an object of the present invention to form a fine wiring layer having excellent shape stability and to improve the yield in the process of forming a sealing resin and the process of mounting a semiconductor chip.

As a means for solving the above problems, one aspect of the wiring board of the present invention is to provide a first wiring board and a second wiring board in which finer wiring is formed than the first wiring board joined to the first wiring board. A wiring board in which a semiconductor element is mounted on the surface of the second wiring board facing the joint surface with the first wiring board, and the second wiring board has at least two types having different storage elasticity. It is characterized by containing an insulating resin.

Further, in one aspect of the wiring board of the present invention, in the wiring board, the insulating resin contains the first insulating resin and the second insulating resin, and the storage elastic coefficient at 25 ° C. is that the first insulating resin has the second insulation. It is larger than the resin, and the storage elasticity at 200 ° C. is larger in the second insulating resin than in the first insulating resin.

Further, in one aspect of the wiring board of the present invention, in the wiring board, the first insulating resin of the second wiring board is arranged on the first wiring board side.

Further, in one aspect of the wiring board of the present invention, in the wiring board, the surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin. The surface of the second electrode of the second wiring board to be bonded to the semiconductor element is flush with the surface of the second insulating resin.

Further, in one aspect of the wiring board of the present invention, in the wiring board, the surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin. The surface of the second electrode of the second wiring board to be bonded to the semiconductor element has a shape protruding from the surface of the second insulating resin.

Further, in one aspect of the wiring board of the present invention, in the wiring board, the surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin. The surface of the second electrode of the second wiring board to be bonded to the semiconductor element has a shape recessed from the surface of the second insulating resin.

Further, one aspect of the method for manufacturing a wiring board of the present invention is a second wiring in which finer wiring is formed than the first wiring board, the first wiring board, and the first wiring board joined to the first wiring board. A method for manufacturing a wiring board having a substrate and mounting a semiconductor element on a surface facing the joint surface of the second wiring board with the first wiring board, which comprises a step of forming a release layer on one surface of a support. , A step of forming a second electrode to be bonded to a semiconductor element on the upper part of the release layer, and a multilayer wiring consisting of an insulating resin layer and a wiring layer containing at least two kinds of insulating resins having different storage elastic coefficients on the upper part of the second electrode. A step of forming a second wiring board having a step of forming a layer, a step of forming a first electrode to be joined to the first wiring board on the side facing the support of the multilayer wiring board, and a step of forming a first wiring board. A step of forming a third electrode to be joined to the second wiring board on one surface, joining the second wiring board and the first wiring board with the first electrode and the third electrode, and a support by a release layer. A step of peeling from the second wiring board to expose the second electrode and the second insulating resin to the surface, a step of forming a first sealing resin between the first wiring board and the second wiring board, and a first step. The step of curing the sealing resin, the step of joining the second wiring board and the semiconductor element with the second electrode and the fourth electrode of the semiconductor element, and the second sealing between the second wiring board and the semiconductor element. It is characterized by including a step of forming a resin and a step of curing a second sealing resin.

Further, in one aspect of the method for manufacturing a wiring board of the present invention, in the above method for manufacturing a wiring board, at least the first insulating resin and the second insulating resin contained in the second wiring board have a storage elastic modulus at 25 ° C. The 1 insulating resin is larger than the 2nd insulating resin, and the storage elastic modulus at 200 ° C. is larger in the 2nd insulating resin than in the 1st insulating resin.

Further, one aspect of the method for manufacturing a wiring board of the present invention is to wire the first insulating resin layer on the upper part of the second electrode in the step of forming the multilayer wiring layer of the second wiring board in the method for manufacturing the wiring board. After forming the layer, the second insulating resin layer is formed.

Further, in one aspect of the wiring board manufacturing method of the present invention, in the wiring board manufacturing method, the step of joining the second wiring board and the first wiring board with the first electrode and the third electrode is a batch reflow. It is a method.

Further, in one aspect of the wiring board manufacturing method of the present invention, in the wiring board manufacturing method, the step of forming the first sealing resin between the first wiring board and the second wiring board is a capillary flow method. The step of forming the second sealing resin between the second wiring board and the semiconductor element is a capillary flow method.

Further, in one aspect of the wiring board manufacturing method of the present invention, in the wiring board manufacturing method, the step of forming the first sealing resin between the first wiring board and the second wiring board is a capillary flow method. In the step of forming the second sealing resin between the second wiring substrate and the semiconductor element, the second sealing resin is a film-like connecting material, and the surface of the semiconductor element having the fourth electrode is previously formed. This is performed together with the step of joining the second electrode of the second wiring substrate and the fourth electrode of the semiconductor element using the formed second sealing resin.

According to the present invention, in a method in which a fine wiring layer is formed on a support substrate and mounted on an FC-BGA substrate, a fine wiring layer having excellent shape stability is formed, a sealing resin forming process and a semiconductor. It is possible to improve the yield in the chip mounting process.

It is sectional drawing which shows an example which mounted the semiconductor chip on the wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the 2nd wiring board which follows FIG. It is sectional drawing which shows the manufacturing method of the 2nd wiring board which follows FIG. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 1st wiring board and the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the shape of the 2nd electrode of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 2nd wiring board and a semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 2nd wiring board and a semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 2nd wiring board and a semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the 2nd electrode of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the manufacturing method of the 2nd electrode of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the shape of the 2nd electrode of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the shape of the 2nd electrode of the 2nd wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 2nd wiring board and a semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the joining method of the 2nd wiring board and a semiconductor element which concerns on one Embodiment of this invention.

Hereinafter, a wiring board according to an embodiment of the present invention will be described with reference to the drawings. However, in each of the figures described below, the parts corresponding to each other are designated by the same reference numerals, and the description below will be omitted as appropriate in the overlapping parts. In addition, each drawing is exaggerated as appropriate for ease of explanation.

<First Embodiment>
FIG. 1 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to the present invention.
The semiconductor package according to the embodiment of the present invention is a fine structure formed only by a build-up wiring layer formed by laminating resin and wiring on one surface of a wiring board (first wiring board) 1 for FC-BGA. A thin interposer (second wiring board) 3 provided with a wiring layer is joined (joint portion 18) with solder bumps, copper pillars (copper posts), gold bumps, or the like. At least two types of insulating resins, an insulating resin layer for fine wiring (second insulating resin) 11 and an outermost surface insulating resin layer (first insulating resin) 16, are used for the interposer 3. Further, the gap between the FC-BGA wiring board 1 and the interposer 3 is embedded with an underfill 2 as an insulating adhesive member. Further, the semiconductor element 4 is joined (joined portion 20) to the surface of the interposer 3 opposite to the FC-BGA wiring board 1 by copper pillars or solder bumps, and the gap between the semiconductor element 4 and the interposer 3 is underfilled. It is embedded in 21. The interposer 3 may be provided with an insulating resin layer other than the insulating resin layer 11 for fine wiring and the outermost surface insulating resin layer 16.

The storage elastic modulus of the outermost surface insulating resin layer 16 at 25 ° C. is larger than the storage elastic modulus of the insulating resin layer 11 for fine wiring, and the storage elastic modulus of the outermost surface insulating resin layer 16 at 200 ° C. is the insulating resin for fine wiring. It is smaller than the storage elastic modulus of layer 11.
As described above, the individual distance between the joint portion 20 between the interposer 3 and the semiconductor element 4 is generally narrower than the individual distance between the joint portions 18 between the interposer 3 and the FC-BGA wiring board 1. Therefore, in the interposer 3, the side where the semiconductor element 4 is joined requires finer wiring than the side where the semiconductor element 4 is joined with the FC-BGA wiring board 1. Therefore, it is preferable to arrange the outermost surface insulating resin layer 16 on the FC-BGA wiring board 1 side.

The underfill 2 is an adhesive material used for fixing the FC-BGA wiring board 1 and the interposer 3 and sealing the joint portion 18. The underfill 2 includes, for example, an epoxy resin, a urethane resin, a silicon resin, a polyester resin, an oxetane resin, and a resin obtained by mixing one kind of maleimide resin or two or more kinds of these resins with silica as a filler and oxidation. A material to which titanium, aluminum oxide, magnesium oxide, zinc oxide or the like is added is used. The underfill 2 is formed by filling with a liquid resin.
The underfill 21 is an adhesive used for fixing the semiconductor element 4 and the interposer 3 and sealing the joint portion 20, and is made of the same material as the underfill 2. The underfill 2 is formed by filling a liquid resin after joining by utilizing the capillary phenomenon.

The individual distance between the joint portion 20 between the interposer 3 and the semiconductor element 4 is generally narrower than the individual distance between the joint portions 18 between the interposer 3 and the FC-BGA wiring board 1. Therefore, in the interposer 3, the side where the semiconductor element 4 is joined requires finer wiring than the side where the semiconductor element 4 is joined with the FC-BGA wiring board 1. For example, in order to comply with the current specifications of high band memory (HBM), it is necessary for the interposer 3 to have a wiring width of 2 μm or more and 6 μm or less. In order to match the characteristic impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wirings is 2.5 μm. The thickness of one layer including wiring is 4.5 μm. When forming a five-layer interposer 3 with this thickness, the total thickness of the insulating resin layer 11 for fine wiring is about 25 μm, the outermost surface insulating resin layer 16 is about 25 μm, and the interposer 3 is an interposer with a total thickness of about 50 μm. It becomes 3.

As described above, the thickness of the interposer 3 is as thin as about 50 μm, and it is difficult to join the interposer 3 to the FC-BGA wiring board 1 as it is. Therefore, the support 5 can be used to ensure the rigidity. It is valid. Further, in order to form a wiring having a width and height of about 2 μm, a flat support 5 is required. For the above reasons, as shown in FIG. 2, the interposer 3 is formed on a rigid and flat support 5 via a release layer 6, a protective layer 7, and a seed layer 8. A layer other than the release layer 6, the protective layer 7, and the seed layer 8 may be provided on the support.

The support 5 is peeled off after joining the interposer 3 formed on the support 5 and the FC-BGA wiring board 1. After the support 5 is peeled off, the thin interposer 3 is connected to the FC-BGA wiring board 1 via the joint 18 as described above. The interposer 3 has an insulating resin layer 11 for fine wiring and an outermost surface insulating resin layer 16. The materials used for the insulating resin layer 11 for fine wiring and the outermost surface insulating resin layer 16 are insulating resins having different storage elastic moduli. The storage elastic modulus reflects the elastic properties of the material and is a value indicating the difficulty of deformation of the material. The storage elastic modulus is obtained by measurement using a dynamic viscoelasticity measuring device. By measuring while heating, the storage elastic modulus at a desired temperature can be measured.
The storage elastic modulus can be measured based on JIS K7244 (plastic-dynamic mechanical property test method). As the insulating resin layer 11 for fine wiring and the outermost surface insulating resin layer 16, for example, an insulating resin having material characteristics as shown in Table 1 can be used.

Next, an example of the manufacturing process of the interposer (second wiring board) 3 on the support 5 according to the embodiment of the present invention will be described with reference to FIGS. 3 to 5.
First, as shown in FIG. 3A, a peeling layer 6 necessary for peeling the support 5 in a later step is formed on one surface of the support 5.

The peeling layer 6 may be, for example, a resin that absorbs light such as UV light and generates heat or can be peeled off by alteration, or may be a resin that can be peeled off by foaming due to heat. When a resin that can be peeled off by light such as UV light is used, the support 5 is irradiated with light from the surface opposite to the side on which the peeling layer 6 is provided, and the interposer 3 and the FC-BGA wiring board 1 are irradiated. The support 5 is removed from the joint with. In this case, the support 5 needs to have transparency, and glass can be used, for example. Glass has excellent flatness and is suitable for forming fine patterns of interposer 3, and since glass has a small CTE (coefficient of thermal expansion) and is not easily distorted, pattern arrangement accuracy and flatness are improved. Excellent for securing. When glass is used as the support 5, the thickness of the glass is preferably thick from the viewpoint of suppressing the occurrence of warpage in the manufacturing process, and is, for example, 0.7 mm or more, preferably 1.1 mm or more. The CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and more preferably about 9 ppm from the viewpoint of the CTE of the FC-BGA wiring board 1 and the semiconductor element 4. Here, for example, glass is used as the support 5. On the other hand, when the resin foamed by the heat is used for the release layer 6, the support 5 is removed by heating the joint between the interposer 3 and the FC-BGA wiring board 1. In this case, for the support 5, for example, metal or ceramics having less distortion can be used. In one embodiment of the present invention, a resin capable of absorbing UV light and peeling is used as the peeling layer 6, and glass is used as the support 5.

Next, as shown in FIG. 3B, a protective layer 7 is formed on the release layer 6. The protective layer 7 is a layer for protecting the interposer 3 when the support 5 is peeled off in a later step, and is, for example, one of an epoxy resin, an acrylic resin, a urethane resin, a silicon resin, a polyester resin, and an oxetane resin. Alternatively, it is a resin in which two or more of these resins are mixed, and the interposer 3 can be removed after peeling from the support 5. The protective layer 7 may be appropriately formed depending on the shape of the resin, such as spin coating and laminating. It is also possible not to form the protective layer 7. In one embodiment of the present invention, an acrylic resin is formed by a laminating method.

Next, as shown in FIG. 3 (c), the seed layer 8 is formed on the protective layer 7 in vacuum. The seed layer 8 acts as a feeding layer for electrolytic plating in forming wiring. The seed layer 8 is formed by, for example, a sputtering method, a CVD method, or the like, and for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloy alone or a combination of two or more can be applied. In the present invention, the titanium layer and then the copper layer are sequentially formed by a sputtering method in consideration of electrical characteristics, ease of manufacture, and cost. The total film thickness of the titanium and copper layers is preferably 1 μm or less as the feeding layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm were formed.

Next, as shown in FIG. 3D, a resist pattern 9 is formed, and a conductor layer (second electrode) 10 is formed by electrolytic plating. The conductor layer 10 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 1 μm or more and 30 μm or less from the viewpoint of circuit connection reliability and manufacturing cost. After that, the resist pattern 9 is removed as shown in FIG. 3 (e).

Next, as shown in FIG. 3 (f), the insulating resin layer (second insulating resin) 11 for fine wiring is formed. The insulating resin layer 11 for fine wiring is formed so that the conductor layer 10 is embedded in the layer of the insulating resin layer 11 for fine wiring. In the present embodiment, for example, a photosensitive epoxy resin is formed as the insulating resin layer 11 for fine wiring by a spin coating method. The photosensitive epoxy resin can be cured at a relatively low temperature, and shrinkage due to curing after formation is small, so that it is excellent in subsequent fine pattern formation. Further, as the insulating resin layer 11 for fine wiring, a material that does not contain an inorganic filler such as silica is more preferable because it is excellent in fine wiring formability. The insulating resin layer 11 for fine wiring can be formed by a spin coating method using a photosensitive epoxy resin, or can be formed by compressing and curing an insulating resin film with a vacuum laminator. In this case, the insulating resin layer 11 can be formed by compression curing with a vacuum laminator. An insulating film having good flatness can be formed. In addition, for example, polyimide can be used as an insulating resin for fine wiring.

Next, as shown in FIG. 4 (g), an opening is provided on the conductor layer 10 by photolithography. The openings may be subjected to plasma treatment for the purpose of removing residues during development.
Next, as shown in FIG. 4 (h), the seed layer 12 is provided on the surface of the opening. The structure of the seed layer 12 is the same as that of the seed layer 8 described above, and the structure and thickness can be changed as appropriate. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm were formed by a sputtering method.

Next, as shown in FIG. 4 (i), a resist pattern 13 is formed on the seed layer 12, and a conductor layer (wiring layer) 14 is formed in the opening thereof by electrolytic plating. The conductor layer 14 is a wiring layer inside the interposer 3. In one embodiment of the present invention, copper was formed as the conductor layer 14. After that, the resist pattern 13 is removed as shown in FIG. 4 (j). After that, the unnecessary seed layer 12 is removed by etching.
Next, the steps of FIGS. 3 (f) to 4 (j) are repeated to obtain a substrate in which the conductor layer (wiring layer) 14 is multi-layered as shown in FIG. 4 (k). Of the conductor layers 14, the conductor layer (first electrode) 15 arranged on the outermost surface serves as an electrode for bonding to the FC-BGA wiring board 1.

Next, as shown in FIG. 4 (l), the outermost surface insulating resin layer (first insulating resin) 16 is formed on the interposer 3. The outermost surface insulating resin layer 16 is formed so as to cover the insulating resin layer 11 for fine wiring and to have an opening so that the conductor layer 15 is exposed by exposure and development. The conductor layer 15 is located lower than the surface of the outermost surface insulating resin layer 16 and has a concave shape. In the present embodiment, the outermost surface insulating resin layer 16 is formed by, for example, compressing and curing a film-shaped photosensitive epoxy resin with a vacuum laminator. When a film-shaped photosensitive epoxy resin is used, an insulating film having good flatness can be formed. The outermost surface insulating resin layer 16 may contain an inorganic filler such as silica. In this case, an insulating film having a large storage elastic modulus at 25 ° C. and high rigidity can be formed. The outermost surface insulating resin layer 16 is formed by compressing and curing a film-shaped photosensitive epoxy resin with a vacuum laminator, and a spin coating method, a roll coating method, and screen printing using a liquid photosensitive epoxy resin. It can also be formed by law or the like.

Next, as shown in FIG. 5 (m), a surface treatment layer 17 is provided in order to prevent oxidation of the surface of the conductor layer 15 and improve the wettability of the solder bumps. In the embodiment of the present invention, an OSP (Organic Soiderability Preservative surface treatment) film is formed on the surface treatment layer 17. Electroless Ni / Pd / Au plating may be formed as the surface treatment layer 17. Further, electroless tin plating, electroless Ni / Au plating and the like may be appropriately selected depending on the intended use.
Next, as shown in FIG. 5 (n), the solder material is mounted on the surface treatment layer 17, and then melt-cooled and fixed once to fix the solder bumps for FC-BGA wiring on the interposer 3 side. A joint portion 18a between the substrate 1 and the interposer 3 is obtained. As a result, the interposer (second wiring board) 3 formed on the support 5 is completed.

Subsequently, using FIGS. 6A to 6F, the interposer (second wiring board) 3 and the FC-BGA wiring board (first wiring board) 1 formed on the support 5 are set to one embodiment of the present invention. An example of such a joining process will be described.
As shown in FIG. 6A, with respect to the FC-BGA wiring board 1 in which the FC-BGA wiring board 1 joint 18b is designed and manufactured in accordance with the interposer 3 joint 18a formed on the support 5. The interposer 3 formed on the support 5 is arranged.
Next, as shown in FIG. 6B, the interposer 3 formed on the support 5 and the FC-BGA wiring board 1 are joined to form the interposer-FC-BGA joint portion 18. As a method for forming the joint portion 18, for example, a batch reflow (mass reflow) method using a reflow furnace is possible.

Next, as shown in FIG. 6C, the support 5 is peeled off. The peeling layer 6 is peeled by irradiating UV light with a laser beam 19. The peeling layer 6 formed at the interface with the support 5 can be peeled by irradiating the laser beam 19 from the back surface of the support 5, that is, from the surface of the support 5 opposite to the FC-BGA wiring board 1. In this state, the support 5 can be removed as shown in FIG. 6D.
Next, as shown in FIG. 6E, the underfill 2 is formed, the interposer 3 and the FC-BGA wiring board 1 are fixed, and the joint portion 18 is sealed. As a method for forming the underfill 2, a capillary flow method in which a liquid resin is filled after joining by utilizing the capillary phenomenon is possible.

Next, the protective layer 7 and the seed layer 8 are removed to obtain a substrate as shown in FIG. 6F. In the embodiment of the present invention, the protective layer 7 uses an acrylic resin and is removed with an alkaline solvent (1% NaOH, 2.3% TMAH). Further, the seed layer 8 uses titanium and copper from the protective layer 7 side, and can be dissolved and removed by an alkaline etching agent and an acid etching agent, respectively. In this way, the wiring board 22 to which the interposer (second wiring board) 3 and the FC-BGA wiring board (first wiring board) 1 are joined is obtained.

At this time, as shown in FIG. 7, the conductor layer 10 exposed on the surface has a flat shape that is flush with the surface of the insulating resin layer 11 for fine wiring. Surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating are performed on the conductor layer 10 exposed on the surface in order to prevent oxidation and improve the wettability of solder bumps. May be applied. With the above, the wiring board 22 is completed.

Further, with reference to FIGS. 8A to 8C and FIG. 1, an example of the joining process according to the embodiment of the present invention of the interposer (second wiring board) 3 of the wiring board 22 and the semiconductor element 4 will be described.
As shown in FIG. 8A, the joint portion 20a of the semiconductor element 4 is arranged with respect to the joint portion 20b of the interposer 3 of the wiring board 22.
Next, as shown in FIG. 8B, the interposer 3 of the wiring board 22 and the semiconductor element 4 are joined to form an interposer-semiconductor element joining portion 20. As a method for forming the joint portion 20, for example, a local reflow method using a flip chip mounting machine having a heating and pressurizing function and a batch reflow (mass reflow) method using a reflow furnace are possible. In this embodiment, the joint portion 20 is formed by a local reflow method.

Next, as shown in FIG. 8C, the underfill 21 is formed, the interposer 3 and the semiconductor element 4 are fixed, and the joint portion 20 is sealed. As a method for forming the underfill 21, for example, a capillary flow method in which a liquid resin is filled after joining by utilizing the capillary phenomenon is possible.
Next, the steps of FIGS. 8A to 8C are repeated as necessary, and a plurality of semiconductor elements 4 are mounted on the interposer 3 of the wiring board 22, whereby the semiconductor package on which the semiconductor elements shown in FIG. 1 are mounted is completed.

<Effect>
Next, the configuration of the wiring board 22 as described above and the operation and effect when the manufacturing method thereof is used will be described.
According to one aspect of the present invention, in a method in which the support 5 is peeled off after being mounted on the FC-BGA wiring board 1, the fine wiring that does not deform even after the support 5 is peeled off and has excellent shape stability. Layers can be formed. Therefore, it is possible to improve the yield in the sealing resin forming step and the semiconductor chip mounting step.

By using at least two types of insulating resins having different storage elastic moduli for the interposer 3, it is possible to suppress deformation such that the end portion of the interposer 3 is lowered or the surface of the interposer 3 is undulated after the support 5 is peeled off. The storage elastic coefficient at 25 ° C. is larger in the outermost surface insulating resin layer 16 (first insulating resin) than in the insulating resin layer 11 for fine wiring (second insulating resin), and the outermost surface insulating resin layer 16 is insulated for fine wiring. Harder than the resin layer 11. In the steps of peeling the support 5 and forming the sealing resin, the presence of the outermost surface insulating resin layer 16 makes it difficult for the insulating resin layer 11 for fine wiring to be deformed, and it is easy to maintain the shape. Further, since the storage elastic modulus at 200 ° C. is larger in the insulating resin layer 11 for fine wiring than in the outermost surface insulating resin layer 16, the warp of the wiring substrate 22 can be suppressed in the mounting process of the semiconductor element 4. Further, in the interposer 3, the side where the semiconductor element 4 is joined requires finer wiring than the side where the semiconductor element 4 is joined, so that the outermost surface insulating resin layer 16 is placed on the FC-BGA side. It is preferable to arrange it in.

The conductor layer 15 to be joined to the FC-BGA wiring board 1 of the interposer 3 is located at a position lower than the surface of the outermost surface insulating resin layer 16 and has a concave shape. After the joint portion 18a of the interposer 3 comes into contact with the joint portion 18b of the FC-BGA wiring board 1 by the concave electrode, the region where the solder wets and spreads due to the side surface of the outermost surface insulating resin layer 16 is the conductor layer 15 It is only on the top, and it is suppressed that the solder flows out around the outermost surface insulating resin layer 16. This makes it possible to reduce the risk of short-circuiting the joint portion 18. Further, since the concave electrode has a shape in which the end portion of the conductor layer 15 is embedded in the outermost surface insulating resin layer 16, it is possible to prevent the conductor layer 15 from peeling off.

The conductor layer 10 bonded to the semiconductor element 4 of the interposer 3 is a flat electrode that is flush with the surface of the insulating resin layer 11 for fine wiring. Since the flat electrode has little variation in height and is less likely to be displaced when the semiconductor element 4 is mounted, the semiconductor element 4 can be mounted with a high yield.
The formation of the interposer-FC-BGA joint 18 is a batch reflow method. The batch reflow method is excellent in productivity because a plurality of interposers 3 and FC-BGA wiring boards 1 can be joined at the same time. Further, the batch reflow method is more preferable because it is used for joining a conventional wiring board and a semiconductor element or the like and can be produced using the same equipment.

<Second embodiment>
Next, the wiring board according to the second embodiment will be described.
The wiring board according to the second embodiment is similar to the wiring board according to the first embodiment, but is characterized in that the second electrode is different. Therefore, the second electrode will be described with reference to FIGS. 9 (a) to 9 (c), FIGS. 10 (a) to 10 (b), and FIGS. 11 and 12, and the description of the other electrodes will be omitted.

As shown in FIG. 9A, a resist pattern 30 is formed on the conductor layer 10 exposed on the surface and the insulating resin layer 11 for fine wiring. Next, as shown in FIG. 9B, the pillar 31 is formed by electrolytic plating. The pillar 31 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 3 μm or more and 20 μm or less from the viewpoint of connection reliability and manufacturing cost. After that, the resist pattern 30 is removed as shown in FIG. 9 (c). Further, the pillar 31 may be subjected to surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating in order to prevent oxidation and improve the wettability of solder bumps. ..

Further, after FIG. 3 (c), the pillar 33 can also be formed by the method shown in FIGS. 10 (a) to 10 (b). As shown in FIG. 10A, the resist pattern 32 is formed, and the pillar 33 is formed by electrolytic plating. The pillar 33 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 3 μm or more and 20 μm or less from the viewpoint of circuit connection reliability and manufacturing cost. Next, as shown in FIG. 10B, the insulating resin layer (second insulating resin) 11 is formed. After that, the interposer 3 is manufactured by the method shown in FIG. 4 (g) and thereafter. By removing the resist pattern 32 exposed on the surface after peeling off the support 5, the interposer 3 having a convex electrode is completed as shown in FIG. Furthermore, in order to prevent oxidation and improve the wettability of solder bumps, the pillars 31 and 33 are subjected to surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating. May be good.

<Effect>
The convex electrode having pillars 31 and 33 can widen the space between the interposer 3 and the semiconductor element 4. Therefore, the liquid underfill 21 easily flows, and voids (voids) are less likely to be generated between the interposer 3 and the semiconductor element 4. That is, the underfill 21 can be easily formed by the capillary flow method.

<Third embodiment>
Next, the wiring board according to the third embodiment will be described.
The wiring board according to the third embodiment is similar to the wiring board according to the first embodiment, but is characterized in that it differs with respect to the second electrode. Therefore, the second electrode will be described with reference to FIG. 12, and the description of the other electrodes will be omitted.
By etching the surface of the conductor layer 10 exposed on the surface, a concave electrode can be formed as shown in FIG. The etching method can be either wet or dry. Further, in order to prevent oxidation and improve the wettability of the solder bumps, surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating may be performed.

<Effect>
When the semiconductor element 4 is mounted by the concave electrode, after the joint portion 20a of the semiconductor element 4 comes into contact with the interposer 3 side, the solder of the joint portion 20a gets wet due to the side surface of the insulating resin layer 11 for fine wiring. The expanding region is only on the conductor layer 10, and it is possible to prevent the solder of the joint portion 20a from flowing out around the conductor layer 10. It is more effective when the shape of the conductor layer 10 is not circular, such as a rectangle or an oval.

<Fourth Embodiment>
Next, the wiring board according to the fourth embodiment will be described.
The method for manufacturing the wiring board according to the fourth embodiment is similar to the method for manufacturing the wiring board according to the first embodiment, but is characterized in that the formation of the underfill 21 is different. Instead of the underfill 21, a film-like connecting material (Non Connective Film, NCF) is used, in which a sheet-shaped film is arranged in advance before joining and a space is filled at the time of joining. Therefore, the formation of the film-like connecting material will be described with reference to FIGS. 13A to 13B, and the description of the others will be omitted.

As shown in FIG. 13A, the joint portion 20a of the semiconductor element 4 is arranged with respect to the joint portion 20b of the interposer 3 of the wiring board 22. A film-like connecting material (NCF) 34 is arranged on the surface of the semiconductor element 4 having the joint portion 20a. The film-like connecting material (NCF) 34 is made of the same material as the underfills 2 and 21.
Next, as shown in FIG. 13B, the interposer 3 of the wiring board 22 and the semiconductor element 4 are joined. As a method for forming the joint portion 20, for example, a local reflow method using a flip-chip mounting machine having a heating and pressurizing function is possible. As a result, the semiconductor element 4 and the interposer 3 can be fixed and the joint portion 20 can be sealed using the film-like connecting material (NCF) 34.

Next, the steps of FIGS. 13A to 13B are repeated as necessary, and a plurality of semiconductor elements 4 are mounted on the interposer 3 of the wiring board 22, thereby completing a semiconductor package on which the semiconductor elements as shown in FIG. 1 are mounted. do.

<Effect>
By using the film-like connecting material (NCF) 34, the distance (gap) between the semiconductor element 4 and the interposer 3 can be uniformly controlled, and voids can be suppressed, so that a highly reliable semiconductor package can be obtained.
The above-described embodiment is an example, and it goes without saying that the specific detailed structure and the like can be appropriately changed.

The present invention can be used in a semiconductor device having a wiring board provided with an interposer or the like interposed between a main board and an IC chip.

1 ... Wiring board for FC-BGA (first wiring board)
2, 21 ... Underfill 3 ... Interposer (second wiring board)
4 ... Semiconductor element 5 ... Support 6 ... Release layer 7 ... Protective layers 8, 12 ... Seed layers 9, 13, 30, 32 ... Resist pattern 10 ... Conductor layer (first electrode)
11 ... Insulating resin layer for fine wiring 14 ... Conductor layer (wiring layer)
15 ... Conductor layer (second electrode)
16 ... Outermost surface insulating resin layer 17 ... Surface treatment layer 18 ... Interposer-FC-BGA joint 18a ... Interposer joint 18b ... FC-BGA wiring board joint 19 ... Laser light 20 ... Semiconductor element-interposer joint 20a ... Semiconductor element junction 20b ... Interposer junction 22 ... Wiring board 31, 33 ... Pillar 34 ... Film-like connection material (NCF)

Claims (12)

With the first wiring board
A second wiring board which is joined to the first wiring board and has finer wiring than the first wiring board is provided.
A wiring board in which a semiconductor element is mounted on a surface facing the second wiring board facing the joint surface with the first wiring board.
A wiring board characterized in that the second wiring board contains at least two types of insulating resins having different storage elastic moduli. The insulating resin contains a first insulating resin and a second insulating resin.
The storage elastic modulus at 25 ° C. is larger in the first insulating resin than in the second insulating resin.
The wiring board according to claim 1, wherein the storage elastic modulus at 200 ° C. is larger in the second insulating resin than in the first insulating resin. The wiring board according to claim 1 or 2, wherein the first insulating resin is arranged on the side of the first wiring board. The surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin.
The wiring board according to any one of claims 1 to 3, wherein the surface of the second electrode of the second wiring board to be bonded to the semiconductor element is flush with the surface of the second insulating resin. The surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin.
The wiring board according to any one of claims 1 to 3, wherein the surface of the second electrode of the second wiring board to be bonded to the semiconductor element has a shape protruding from the surface of the second insulating resin. .. The surface of the first electrode of the second wiring board to be joined to the first wiring board has a shape recessed from the surface of the first insulating resin.
The wiring board according to any one of claims 1 to 3, wherein the surface of the second electrode of the second wiring board to be bonded to the semiconductor element has a shape recessed from the surface of the second insulating resin. .. With the first wiring board
The first wiring board and the first wiring board of the second wiring board are provided with the first wiring board and the second wiring board in which finer wiring is formed than the first wiring board joined to the first wiring board. A method for manufacturing a wiring board in which a semiconductor element is mounted on a surface facing a joint surface.
The process of forming a release layer on one surface of the support and
A step of forming the second electrode to be bonded to the semiconductor element on the upper part of the release layer, and
A step of forming a multilayer wiring layer composed of an insulating resin layer containing at least two types of insulating resins having different storage elastic moduli and a wiring layer on the upper part of the second electrode.
A step of forming the first electrode to be joined to the first wiring board on the side of the multilayer wiring layer facing the support, and a step of forming the second wiring board having the first electrode.
A third electrode to be joined to the second wiring board is formed on one surface of the first wiring board, and the second wiring board and the first wiring board are joined by the first electrode and the third electrode. And the process to do
A step of peeling the support from the second wiring board by the peeling layer to expose the second electrode and the second insulating resin on the surface.
A step of forming a first sealing resin between the first wiring board and the second wiring board, and
The step of curing the first sealing resin and
A step of joining the second wiring board and the semiconductor element with the second electrode and the fourth electrode of the semiconductor element.
A step of forming a second sealing resin between the second wiring board and the semiconductor element, and
The step of curing the second sealing resin and
A method for manufacturing a wiring board, which comprises. In the first insulating resin and the second insulating resin contained at least in the second wiring board,
The storage elastic modulus at 25 ° C. is larger in the first insulating resin than in the second insulating resin.
The method for manufacturing a wiring board according to claim 7, wherein the storage elastic modulus at 200 ° C. is larger in the second insulating resin than in the first insulating resin. In the step of forming the multilayer wiring layer of the second wiring board,
The method for manufacturing a wiring board according to claim 7 or 8, wherein the first insulating resin layer and the wiring layer are formed on the upper portion of the second electrode, and then the second insulating resin layer is formed. The wiring according to any one of claims 7 to 9, wherein the step of joining the second wiring board and the first wiring board at the first electrode and the third electrode is a batch reflow method. Substrate manufacturing method. The step of forming the first sealing resin between the first wiring board and the second wiring board is a capillary flow method.
The method for manufacturing a wiring board according to any one of claims 7 to 10, wherein the step of forming the second sealing resin between the second wiring board and the semiconductor element is a capillary flow method. .. The step of forming the first sealing resin between the first wiring board and the second wiring board is a capillary flow method.
The step of forming the second sealing resin between the second wiring board and the semiconductor element is
The second sealing resin is a film-like connecting material, and is
A claim performed together with a step of joining the second electrode of the second wiring substrate and the fourth electrode of the semiconductor element using the second sealing resin previously formed on the surface of the semiconductor element having the fourth electrode. The method for manufacturing a wiring board according to any one of claims 7 to 10.

Images