JP2021125565A - Wiring board and method for manufacturing wiring board - Google Patents

Wiring board and method for manufacturing wiring board Download PDF

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JP2021125565A
JP2021125565A JP2020018134A JP2020018134A JP2021125565A JP 2021125565 A JP2021125565 A JP 2021125565A JP 2020018134 A JP2020018134 A JP 2020018134A JP 2020018134 A JP2020018134 A JP 2020018134A JP 2021125565 A JP2021125565 A JP 2021125565A
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wiring board
wiring
insulating resin
semiconductor element
electrode
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優樹 梅村
Yuki Umemura
優樹 梅村
茜 小林
Akane Kobayashi
茜 小林
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

To provide a wiring board with excellent mountability and reliability by suppressing waviness and cracks in a method where a fine wiring layer is formed on a support board and mounted on a FC-BGA board.SOLUTION: A wiring board has a first wiring board and a second wiring board that is bonded to the first wiring board and has finer wiring than the first wiring board; a semiconductor device is mounted on the opposite side of the second wiring board that faces the bonding surface with the first wiring board, and an insulating resin whose storage modulus is larger than that of the insulating resin for wiring is formed on the front and back of the insulating resin for wiring used in the second wiring board.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板及び配線基板の製造方法に関する。 The present invention relates to a wiring board and a method for manufacturing a wiring board.

近年半導体装置の高速、高集積化が進む中で、ＦＣ−ＢＧＡ（Ｆｌｉｐ Ｃｈｉｐ−Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）用配線基板に対しても、半導体チップとの接続端子の狭ピッチ化、基板配線の微細化が求められている。一方、ＦＣ−ＢＧＡ用配線基板とマザーボードとの接続は、従来とほぼ変わらないピッチの接続端子での接続が要求されている。この半導体チップと接続端子の狭ピッチ化、基板配線の微細化のため、シリコン上に配線形成してチップ接続用の基板（シリコンインターポーザ）として、それぞれＦＣ−ＢＧＡ用配線基板に接続する方式が特許文献１に開示されている。また、ＦＣ−ＢＧＡ用配線基板の表面をＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ、化学機械研磨）等で平坦化してから微細配線を形成する方式が特許文献２に開示されている。また、支持基板の上に微細な配線層を形成しＦＣ−ＢＧＡ基板に搭載した後、支持基板を剥離することで狭ピッチな配線基板な形成する方式が特許文献３に開示されている。 In recent years, with the progress of high speed and high integration of semiconductor devices, the pitch of connection terminals with semiconductor chips has been narrowed and the board wiring has become finer for FC-BGA (Flip Chip-Ball Grid Array) wiring boards. It has been demanded. On the other hand, the connection between the FC-BGA wiring board and the motherboard is required to be connected with connection terminals having a pitch that is almost the same as the conventional one. In order to narrow the pitch of the semiconductor chip and connection terminals and miniaturize the board wiring, a method of forming wiring on silicon and connecting it to the FC-BGA wiring board as a chip connection board (silicon interposer) is patented. It is disclosed in Document 1. Further, Patent Document 2 discloses a method of forming fine wiring after flattening the surface of a wiring board for FC-BGA by CMP (Chemical Mechanical Polishing) or the like. Further, Patent Document 3 discloses a method in which a fine wiring layer is formed on a support substrate, mounted on an FC-BGA substrate, and then the support substrate is peeled off to form a narrow-pitch wiring board.

特開２００２−２８０４９０号JP-A-2002-280490 特開２０１４−２２５６７１号Japanese Unexamined Patent Publication No. 2014-225671 ＷＯ２０１８／０４７８６１WO2018 / 047861

シリコンインターポーザは、シリコンウェハを利用して、半導体前工程用の設備を用いて製作されている。シリコンウェハは形状、サイズに制限があり、１枚のウェハから製作できるインターポーザの数が少なく、製造設備も高価であるため、インターポーザも高価となる。また、シリコンウェハが半導体であることから、伝送特性も劣化するという問題がある。 The silicon interposer is manufactured by using a silicon wafer and using equipment for a semiconductor front-end process. Silicon wafers are limited in shape and size, the number of interposers that can be manufactured from a single wafer is small, and the manufacturing equipment is expensive, so the interposers are also expensive. Further, since the silicon wafer is a semiconductor, there is a problem that the transmission characteristics are also deteriorated.

また、ＦＣ−ＢＧＡ用配線基板の表面の平坦化を行いその上に微細配線層を形成する方式においては、シリコンインターポーザに見られる伝送特性劣化の問題は無いが、ＦＣ−ＢＧＡ用配線基板の製造不良と、難易度の高い微細配線形成時の不良との合算で収率が低下する問題や、ＦＣ−ＢＧＡ用配線基板の反り、歪みに起因した半導体素子の実装における問題がある。 Further, in the method of flattening the surface of the FC-BGA wiring board and forming a fine wiring layer on the surface, there is no problem of deterioration of transmission characteristics seen in the silicon interposer, but the FC-BGA wiring board is manufactured. There is a problem that the yield is lowered by the sum of the defect and the defect at the time of forming the fine wiring with high difficulty, and there is a problem in mounting the semiconductor element due to the warp and distortion of the wiring board for FC-BGA.

一方、支持基板の上に微細な配線層を形成しＦＣ−ＢＧＡ基板に搭載する方式では、伝送特劣化の問題や、ＦＣ−ＢＧＡ用配線基板と微細な配線層を別々に形成するため合算で収率が低下する問題はない。しかしながら、支持基板の上に微細な配線層を形成しＦＣ−ＢＧＡ基板に搭載しようとすると、次のような問題があった。すなわち、微細な配線層を形成する為の絶縁樹脂として加工性が優れた柔らかい樹脂を選択すると、絶縁樹脂表面にうねりが発生し半導体素子の実装性が低下する問題、製造途中や信頼性試験時に樹脂にクラックが発生しやすい問題があった。 On the other hand, in the method of forming a fine wiring layer on the support board and mounting it on the FC-BGA board, there is a problem of transmission special deterioration and the FC-BGA wiring board and the fine wiring layer are formed separately, so that the total is total. There is no problem that the yield decreases. However, when a fine wiring layer is formed on the support substrate and mounted on the FC-BGA substrate, there are the following problems. That is, if a soft resin having excellent workability is selected as the insulating resin for forming a fine wiring layer, waviness occurs on the surface of the insulating resin and the mountability of the semiconductor element deteriorates. There was a problem that cracks were likely to occur in the resin.

そこで本発明は、上記問題に鑑みなされたものであり、支持基板の上に微細な配線層を形成しＦＣ−ＢＧＡ基板に搭載する方式において、うねりおよびクラックを抑制することで実装性、信頼性に優れた配線基板を提供すること目的とする。 Therefore, the present invention has been made in view of the above problems, and in a method of forming a fine wiring layer on a support substrate and mounting it on an FC-BGA substrate, mountability and reliability are achieved by suppressing waviness and cracks. It is an object of the present invention to provide an excellent wiring board.

上記の課題を解決する手段として、本発明の配線基板の一態様は、第１配線基板と、上記第１配線基板に接合され、上記第１配線基板より微細な配線が形成された第２配線基板を備え、上記第１配線基板との接合面に対向する上記第２配線基板の対向面に半導体素子が実装される配線基板であって、上記第２配線基板に用いる微細な配線を形成する為の配線用絶縁樹脂の表裏に、貯蔵弾性率が上記配線用絶縁樹脂よりも大きな絶縁樹脂が形成されていることを特徴とする。 As a means for solving the above problems, one aspect of the wiring board of the present invention is a second wiring that is joined to the first wiring board and the first wiring board to form finer wiring than the first wiring board. A wiring board having a board and having a semiconductor element mounted on the surface facing the second wiring board facing the joint surface with the first wiring board, and forming fine wiring used for the second wiring board. It is characterized in that an insulating resin having a storage elastic coefficient larger than that of the wiring insulating resin is formed on the front and back surfaces of the wiring insulating resin.

また、本発明の配線基板の一態様は、上記配線基板において、上記配線用絶縁樹脂の表裏に形成する上記絶縁樹脂は、貯蔵弾性率の異なる第１絶縁樹脂と第２絶縁樹脂を含む。
また、本発明の配線基板の一態様は、上記配線基板において、上記半導体素子の実装面側から見て上記第２絶縁樹脂、上記配線用絶縁樹脂、上記第１絶縁樹脂の順に積層されており、上記第１絶縁樹脂の貯蔵弾性率をＡとし、上記配線用絶縁樹脂の貯蔵弾性率をＢとし、上記第２絶縁樹脂の貯蔵弾性率をＣとしたとき、Ｂ＜Ｃ＜Ａの関係である。 Further, in one aspect of the wiring board of the present invention, in the wiring board, the insulating resin formed on the front and back surfaces of the wiring insulating resin includes a first insulating resin and a second insulating resin having different storage elastic moduli.
Further, in one aspect of the wiring board of the present invention, the second insulating resin, the insulating resin for wiring, and the first insulating resin are laminated in this order on the wiring board when viewed from the mounting surface side of the semiconductor element. When the storage elastic modulus of the first insulating resin is A, the storage elastic modulus of the wiring insulating resin is B, and the storage elastic modulus of the second insulating resin is C, the relationship of B <C <A. be.

また、本発明の配線基板の一態様は、上記配線基板において、上記配線用絶縁樹脂が感光性樹脂である。
また、本発明の配線基板の一態様は、上記配線基板において、上記第１配線基板と上記第２配線基板との接続ピッチが上記半導体素子の接続ピッチよりも大きい。
また、本発明の配線基板の一態様は、上記配線基板において、上記第２配線基板のＣｕ電極形状が、上記第１配線基板との接続側は凹み形状であり、上記半導体素子との接続側が平坦形状である。 Further, in one aspect of the wiring board of the present invention, the insulating resin for wiring is a photosensitive resin in the wiring board.
Further, in one aspect of the wiring board of the present invention, in the wiring board, the connection pitch between the first wiring board and the second wiring board is larger than the connection pitch of the semiconductor element.
Further, in one aspect of the wiring board of the present invention, in the wiring board, the Cu electrode shape of the second wiring board has a concave shape on the connection side with the first wiring board, and the connection side with the semiconductor element has a concave shape. It has a flat shape.

また、本発明の配線基板の一態様は、上記配線基板において、上記第２配線基板のＣｕ電極形状が、上記第１配線基板との接続側は凹み形状であり、上記半導体素子との接続側が凸形状である。
また、本発明の配線基板の一態様は、上記配線基板において、上記第２配線基板のＣｕ電極形状が、上記第１配線基板との接続側、および上記半導体素子との接続側が共に凹み形状である。 Further, in one aspect of the wiring board of the present invention, in the wiring board, the Cu electrode shape of the second wiring board has a concave shape on the connection side with the first wiring board, and the connection side with the semiconductor element has a concave shape. It has a convex shape.
Further, in one aspect of the wiring board of the present invention, in the wiring board, the Cu electrode shape of the second wiring board has a concave shape on both the connection side with the first wiring board and the connection side with the semiconductor element. be.

また、本発明の配線基板の製造方法の一態様は、第１配線基板と、上記第１配線基板と、上記第１配線基板に接合された上記第１配線基板より微細な配線が形成された第２配線基板とを備え、上記第２配線基板の上記第１配線基板との接合面の対向面に半導体素子が実装される配線基板の製造方法であって、支持体の一面上に剥離層を形成する工程と、上記剥離層の上部に上記半導体素子と接合する上記第２電極を形成する工程と、第２絶縁樹脂を形成する工程と、配線用絶縁樹脂と配線層からなる微細配線層を形成する工程と、上記微細配線層の上記支持体と対向する側に上記第１配線基板と接合する上記第１電極を形成する工程と、第１絶縁樹脂を形成する工程を有する上記第２配線基板を形成する工程と、上記第１配線基板の一方の面に上記第２配線基板と接合する第３電極を形成し、上記第２配線基板と上記第１配線基板を、上記第１電極と上記第３電極とで接合する工程と、上記支持体を上記剥離層により上記第２配線基板から剥離し、上記第２電極と上記第２絶縁樹脂を表面に露出させる工程と、上記第１配線基板と上記第２配線基板との間に第１封止樹脂を形成する工程と、上記第１封止樹脂を硬化させる工程と、上記第２配線基板と上記半導体素子を、上記第２電極と上記半導体素子の第４電極とで接合する工程と、上記第２配線基板と上記半導体素子との間に第２封止樹脂を形成する工程と、上記第２封止樹脂を硬化させる工程と、を含むことを特徴とする。 Further, in one aspect of the method for manufacturing a wiring board of the present invention, finer wiring is formed than the first wiring board, the first wiring board, and the first wiring board joined to the first wiring board. A method for manufacturing a wiring board including a second wiring board and mounting a semiconductor element on a surface facing the joint surface of the second wiring board with the first wiring board, wherein a release layer is provided on one surface of a support. A step of forming the second electrode to be bonded to the semiconductor element on the upper part of the peeling layer, a step of forming the second insulating resin, and a fine wiring layer composed of an insulating resin for wiring and a wiring layer. The second step of forming the first electrode to be bonded to the first wiring board on the side of the fine wiring layer facing the support, and the step of forming the first insulating resin. In the process of forming a wiring board, a third electrode to be joined to the second wiring board is formed on one surface of the first wiring board, and the second wiring board and the first wiring board are attached to the first electrode. The step of joining with the third electrode, the step of peeling the support from the second wiring board by the peeling layer, and the step of exposing the second electrode and the second insulating resin to the surface, and the first. The step of forming the first sealing resin between the wiring board and the second wiring board, the step of curing the first sealing resin, the second wiring board and the semiconductor element, and the second electrode. A step of joining the semiconductor element with the fourth electrode, a step of forming a second sealing resin between the second wiring board and the semiconductor element, and a step of curing the second sealing resin. , Is included.

また、本発明の配線基板の製造方法の一態様は、上記配線基板の製造方法において、上記第２配線基板と上記第１配線基板とはマスリフロー方式で接合する。
また、本発明の配線基板の製造方法の一態様は、上記配線基板の製造方法において、上記第２配線基板と上記第１配線基板との接合部、半導体素子の接合部共にキャピラリーフローアンダーフィルで封止する。
また、本発明の配線基板の製造方法の一態様は、上記配線基板の製造方法において、上記第２配線基板と上記第１配線基板との接合部はキャピラリーフローアンダーフィルで封止され、半導体素子の接合部はフィルム状接続材料（ＮＣＦ）で封止される。 Further, in one aspect of the method for manufacturing a wiring board of the present invention, in the method for manufacturing a wiring board, the second wiring board and the first wiring board are joined by a mass reflow method.
Further, in one aspect of the method for manufacturing a wiring board of the present invention, in the method for manufacturing a wiring board, both the joint portion between the second wiring board and the first wiring board and the joint portion of the semiconductor element are formed by capillary flow underfill. Seal.
Further, in one aspect of the wiring board manufacturing method of the present invention, in the wiring board manufacturing method, the joint portion between the second wiring board and the first wiring board is sealed with a capillary flow underfill, and the semiconductor element. The joint is sealed with a film-like connecting material (NCF).

本発明によれば、支持基板の上に微細な配線層を形成しＦＣ−ＢＧＡ基板に搭載する方式において、実装性、信頼性に優れた配線基板を提供することが可能となる。 According to the present invention, it is possible to provide a wiring board having excellent mountability and reliability in a method in which a fine wiring layer is formed on a support substrate and mounted on an FC-BGA substrate.

本発明の一実施形態に係る配線基板に半導体チップを実装した一例を示す断面図である。It is sectional drawing which shows an example which mounted the semiconductor chip on the wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第２配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第２配線基板の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the 2nd wiring board which concerns on one Embodiment of this invention. 図３に続く第２配線基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the 2nd wiring board which follows FIG. 図４に続く第２配線基板の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the 2nd wiring board which follows FIG. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る第１配線基板と第２配線基板の接合方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the joining method of the 1st wiring board and 2nd wiring board which concerns on one Embodiment of this invention. 本発明の一実施形態に係る配線基板と半導体素子の接合方法の一例を示す断面図である。It is sectional drawing which shows an example of the joining method of a wiring board and a semiconductor element which concerns on one Embodiment of this invention. 本発明の第２の実施形態に係る第２電極形状および製造方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る第２電極形状および製造方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る第２電極形状および製造方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る第２電極形状および製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る第２電極形状および製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 2nd Embodiment of this invention. 本発明の第２の実施形態に係る配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the wiring board which concerns on 2nd Embodiment of this invention. 本発明の第３の実施形態に係る第２電極形状および製造方法の一例を示す断面拡大図である。It is sectional drawing which shows an example of the 2nd electrode shape and manufacturing method which concerns on 3rd Embodiment of this invention. 本発明の第４の実施形態に係るアンダーフィル形成方法の一例を示す断面図である。It is sectional drawing which shows an example of the underfill forming method which concerns on 4th Embodiment of this invention. 本発明の第４の実施形態に係るアンダーフィル形成方法の一例を示す断面図である。It is sectional drawing which shows an example of the underfill forming method which concerns on 4th Embodiment of this invention.

以下に、本発明の一実施形態に関わる配線基板について図面を参照して説明する。ただし、以下に説明する各図において相互に対応する部分には同一符号を付し、重複部分においては後述での説明を適宜省略する。また、各図面は説明を容易にするために適宜誇張して表現している。 Hereinafter, a wiring board according to an embodiment of the present invention will be described with reference to the drawings. However, in each of the figures described below, the parts corresponding to each other are designated by the same reference numerals, and the description below will be omitted as appropriate in the overlapping parts. In addition, each drawing is exaggerated as appropriate for ease of explanation.

＜第１の実施形態＞
図１は、本発明に係る配線基板に半導体チップを実装した半導体パッケージの一例を示す断面図である。
本発明の一実施形態に係る半導体パッケージは、ＦＣ−ＢＧＡ用配線基板（第１配線基板）１の一方の面に、樹脂と配線とが積層されてなる微細配線層２２を備えた薄いインターポーザ（第２配線基板）３が、はんだバンプまたは銅ポスト（銅ピラー）などで接合（接合部１９）されている。インターポーザ３には、微細配線層２２形成用の絶縁樹脂層Ｂとチップ側の接続パッドを形成する絶縁樹脂層Ｃ、第一配線基板と接合する面に絶縁樹脂層Ａの３種類の絶縁樹脂が用いられている。また、ＦＣ−ＢＧＡ用配線基板１とインターポーザ３との間隙が絶縁性の接着部材としてのアンダーフィル２で埋め込まれている。さらにインターポーザ３の、ＦＣ−ＢＧＡ用配線基板１とは逆側の面に半導体素子４が銅ピラー２０ａ及びその先端の半田２０ｂで接合（接合部２０）され、半導体素子４とインターポーザ３との間隙がアンダーフィル２１で埋め込まれている。 <First Embodiment>
FIG. 1 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to the present invention.
The semiconductor package according to the embodiment of the present invention is a thin interposer having a fine wiring layer 22 in which a resin and a wiring are laminated on one surface of a wiring board (first wiring board) 1 for FC-BGA. The second wiring board) 3 is joined (joined portion 19) with a solder bump, a copper post (copper pillar), or the like. The interposer 3 has three types of insulating resins: an insulating resin layer B for forming the fine wiring layer 22, an insulating resin layer C forming a connection pad on the chip side, and an insulating resin layer A on the surface to be joined to the first wiring board. It is used. Further, the gap between the FC-BGA wiring board 1 and the interposer 3 is embedded with an underfill 2 as an insulating adhesive member. Further, the semiconductor element 4 is joined to the surface of the interposer 3 opposite to the FC-BGA wiring board 1 by the copper pillar 20a and the solder 20b at the tip thereof (joint portion 20), and the gap between the semiconductor element 4 and the interposer 3 is formed. Is embedded in the underfill 21.

アンダーフィル２は、ＦＣ−ＢＧＡ用配線基板１とインターポーザ３とを固定及び接合部１９を封止するために用いられる接着材料である。アンダーフィル２としては、例えば、エポキシ樹脂、ウレタン樹脂、シリコン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂の１種又はこれらの樹脂の２種類以上が混合された樹脂に、フィラーとしてのシリカ、酸化チタン、酸化アルミニウム、酸化マグネシウム、又は酸化亜鉛等が加えられた材料が用いられる。アンダーフィル２は、液状の樹脂を充填させることで形成される。
アンダーフィル２１は半導体チップ４とインターポーザ３とを固定及び接合部２０を封止するために用いられる接着剤であり、アンダーフィル２と同様の材料で構成される。 The underfill 2 is an adhesive material used for fixing the FC-BGA wiring board 1 and the interposer 3 and sealing the joint portion 19. The underfill 2 includes, for example, an epoxy resin, a urethane resin, a silicon resin, a polyester resin, an oxetane resin, and a resin obtained by mixing one kind of maleimide resin or two or more kinds of these resins with silica as a filler and oxidation. A material to which titanium, aluminum oxide, magnesium oxide, zinc oxide or the like is added is used. The underfill 2 is formed by filling with a liquid resin.
The underfill 21 is an adhesive used for fixing the semiconductor chip 4 and the interposer 3 and sealing the joint portion 20, and is made of the same material as the underfill 2.

インターポーザ３と半導体素子４との接合部２０の個々の間隔は、インターポーザ３とＦＣ−ＢＧＡ配線基板１との接合部１９の個々の間隔よりも狭いことが一般的である。そのため、インターポーザ３において、半導体素子４を接合する側の方が、ＦＣ−ＢＧＡ用配線基板１と接合する側よりも微細な配線が必要となる。例えば、現在のハイバンドメモリ（ＨＢＭ）の使用に対応するためには、インターポーザ３では配線幅を２μｍ以上６μｍ以下にする必要がある。特性インピーダンスを５０Ωにあわせるためには、配線幅が２μｍ、配線高さ２μｍの場合、配線間の絶縁膜厚は２．５μｍとなる。配線も含めた１層の厚さは４．５μｍとなり、この厚さで５層のインターポーザ３を形成する場合、微細配線層２２は、総厚２５μｍ程度、チップ側の接続パッドを形成する絶縁樹脂層Ｃの厚みは２０μｍ程度、第一配線基板と接合する面に絶縁樹脂層Ａの厚みは２５μｍ程度となり、インターポーザ３は、総厚７０μｍ程度のインターポーザ３となる。 The individual distance between the interposer 3 and the joint portion 20 of the semiconductor element 4 is generally narrower than the individual distance between the interposer 3 and the joint portion 19 between the FC-BGA wiring board 1. Therefore, in the interposer 3, the side where the semiconductor element 4 is joined requires finer wiring than the side where the semiconductor element 4 is joined with the FC-BGA wiring board 1. For example, in order to support the current use of high band memory (HBM), the wiring width of the interposer 3 needs to be 2 μm or more and 6 μm or less. In order to match the characteristic impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulating film thickness between the wirings is 2.5 μm. The thickness of one layer including wiring is 4.5 μm, and when forming a five-layer interposer 3 with this thickness, the fine wiring layer 22 has a total thickness of about 25 μm and is an insulating resin that forms a connection pad on the chip side. The thickness of the layer C is about 20 μm, the thickness of the insulating resin layer A on the surface to be joined to the first wiring board is about 25 μm, and the interposer 3 is an interposer 3 having a total thickness of about 70 μm.

上記の通り、インターポーザ３の厚みは総厚７０μｍ程度と薄く、そのままの状態ではＦＣ−ＢＧＡ用配線基板１と接合するのが困難であるため、支持体５を用いて剛直性を担保することが有効である。また、２μｍ程度の幅と高さを有する配線を形成するには、平坦な支持体５が必要となる。上記理由により、図２に示すように、インターポーザ３は、剛直で平坦な支持体５上に形成される。なお、支持体上には、シード層８を設けてもよいし、それ以外の層を設けてもよい。 As described above, the thickness of the interposer 3 is as thin as about 70 μm, and it is difficult to join the interposer 3 to the FC-BGA wiring board 1 as it is. Therefore, the support 5 can be used to ensure rigidity. It is valid. Further, in order to form a wiring having a width and height of about 2 μm, a flat support 5 is required. For the above reasons, as shown in FIG. 2, the interposer 3 is formed on a rigid and flat support 5. The seed layer 8 may be provided on the support, or other layers may be provided.

支持体５は、支持体５上に形成されたインターポーザ３とＦＣ−ＢＧＡ用配線基板１を接合した後に、剥離される。支持体５を剥離した後は、上記の通り薄いインターポーザ３が接合部１９を介してＦＣ−ＢＧＡ用配線基板１に接続されている。インターポーザ３は、絶縁樹脂層Ａ（第２絶縁樹脂）、絶縁樹脂層Ｂ（配線用絶縁樹脂）、絶縁樹脂層Ｃ（第１絶縁樹脂）を有している。絶縁樹脂層Ｂに比べ絶縁樹脂層ＡとＣの貯蔵弾性率は大きい。なお、貯蔵弾性率とは、材料の弾性としての特性を反映しており、材料の変形しにくさを表す値である。貯蔵弾性率は、動的粘弾性測定装置を用いた測定によって得られる。 The support 5 is peeled off after joining the interposer 3 formed on the support 5 and the FC-BGA wiring board 1. After the support 5 is peeled off, the thin interposer 3 is connected to the FC-BGA wiring board 1 via the joint portion 19 as described above. The interposer 3 has an insulating resin layer A (second insulating resin), an insulating resin layer B (insulating resin for wiring), and an insulating resin layer C (first insulating resin). The storage elastic modulus of the insulating resin layers A and C is larger than that of the insulating resin layer B. The storage elastic modulus reflects the elastic properties of the material and is a value indicating the difficulty of deformation of the material. The storage elastic modulus is obtained by measurement using a dynamic viscoelasticity measuring device.

絶縁樹脂層ＡとＣは同じでもよいが、信頼性向上の観点からは貯蔵弾性率の異なる別の樹脂であることが望ましい。また絶縁樹脂層Ａ、Ｂ、Ｃの貯蔵弾性率の大きさはＢ＜Ｃ＜Ａとなることが望ましい。前述した微細配線層２２を形成する絶縁樹脂Ｂは、その加工性から弾性率の小さな材料を選択する場合があるが、その外側に貯蔵弾性率の高い絶縁樹脂Ａ、Ｃを配置することで、うねりを抑制することができる。また、貯蔵弾性率の高い絶縁樹脂を半導体チップ４側、ＦＣ−ＢＧＡ用配線基板１側の両側に配置することで、半導体チップ４とインターポーザ３とのＣＴＥ差、インターポーザ３とＦＣ−ＢＧＡ用配線基板１のＣＴＥ差に起因したクラックを抑制することができる。一方、一般的に微細配線形成性と変形しにくさ、割れにくさはトレードオフの関係性になる場合があるが、半導体チップ４側の電極形成に求められる樹脂加工性よりもＦＣ−ＢＧＡ用配線基板１側のパッド形成に求められる樹脂加工性の方が寛容であり、より広い範囲で貯蔵弾性率の異なる樹脂を選択できる。それぞれの層に適した樹脂を選択することで加工性を確保した上で最も剛直なインターポーザ３が得られ、うねり、クラックを抑制することができ、実装性、信頼性に優れた配線基板を提供することができる。特に絶縁樹脂層Ｂが感光性樹脂である場合は、貯蔵弾性率が小さい場合が多く、その効果を得られる。一方で配線基板の用途により求められる信頼性は異なる。要求に足る信頼性を確保できるのであれば、製造コスト、材料調達コストの観点から絶縁樹脂ＡとＣに同じ樹脂を用いてもよい。 The insulating resin layers A and C may be the same, but from the viewpoint of improving reliability, it is desirable that they are different resins having different storage elastic moduli. Further, it is desirable that the magnitude of the storage elastic modulus of the insulating resin layers A, B, and C is B <C <A. As the insulating resin B forming the fine wiring layer 22 described above, a material having a small elastic modulus may be selected from its workability, but by arranging the insulating resins A and C having a high storage elastic modulus on the outside thereof, the insulating resin B has a high storage elastic modulus. Waviness can be suppressed. Further, by arranging insulating resins having a high storage elastic modulus on both sides of the semiconductor chip 4 side and the FC-BGA wiring board 1 side, the CTE difference between the semiconductor chip 4 and the interposer 3 and the wiring between the interposer 3 and the FC-BGA Cracks caused by the CTE difference of the substrate 1 can be suppressed. On the other hand, in general, fine wiring formability, deformation resistance, and crack resistance may have a trade-off relationship, but for FC-BGA rather than the resin workability required for electrode formation on the semiconductor chip 4 side. The resin processability required for pad formation on the wiring board 1 side is more forgiving, and resins having different storage elastic moduli can be selected in a wider range. By selecting a resin suitable for each layer, the most rigid interposer 3 can be obtained while ensuring workability, waviness and cracks can be suppressed, and a wiring board with excellent mountability and reliability is provided. can do. In particular, when the insulating resin layer B is a photosensitive resin, the storage elastic modulus is often small, and the effect can be obtained. On the other hand, the required reliability differs depending on the application of the wiring board. The same resin may be used for the insulating resins A and C from the viewpoint of manufacturing cost and material procurement cost as long as the required reliability can be ensured.

次に図３から図５を用いて、本発明の一実施形態に係る支持体５上へのインターポーザ（第２配線基板）３の製造工程の一例を説明する。
まず、図３（ａ）に示すように、支持体５の一方の面に、後の工程で支持体５を剥離するために必要な剥離層６を形成する。 Next, an example of the manufacturing process of the interposer (second wiring board) 3 on the support 5 according to the embodiment of the present invention will be described with reference to FIGS. 3 to 5.
First, as shown in FIG. 3A, a peeling layer 6 necessary for peeling the support 5 in a later step is formed on one surface of the support 5.

剥離層６は、例えば、ＵＶ光などの光を吸収して発熱、もしくは、変質によって剥離可能となる樹脂でもよく、熱によって発泡により剥離可能となる樹脂でもよい。ＵＶ光などの光によって剥離可能となる樹脂を用いる場合、剥離層６を設けた側とは反対側の面から支持体５に光を照射して、インターポーザ３と、ＦＣ−ＢＧＡ用配線基板１との接合体から支持体５を取り去る。この場合、支持体５は、透明性を有する必要があり、例えばガラスを用いることができる。ガラスは平坦性に優れており、インターポーザ３の微細なパターン形成に向いている、また、ガラスはＣＴＥ（ｃｏｅｆｆｉｃｉｅｎｔ ｏｆ ｔｈｅｒｍａｌ ｅｘｐａｎｓｉｏｎ、熱膨張率）が小さく歪みにくいことから、パターン配置精度及び平坦性の確保に優れている。支持体５としてガラスを用いる場合、ガラスの厚さは、製造プロセスにおける反りの発生を抑制する観点から厚い方が望ましく、例えば０．７ｍｍ以上、好ましくは１．１ｍｍ以上の厚みである。また、ガラスのＣＴＥは３ｐｐｍ以上１５ｐｐｍ以下が好ましく、ＦＣ−ＢＧＡ用配線基板１、半導体素子４のＣＴＥの観点から９ｐｐｍ程度がより好ましい。ここでは、支持体５として、例えばガラスを用いる。一方、剥離層６に上記熱によって発泡する樹脂を用いた場合は、インターポーザ３と、ＦＣ−ＢＧＡ用配線基板１との接合体を加熱する事で支持体５を取り去る。この場合、支持体５には、歪みの少ない例えばメタルやセラミックスなどを用いることができる。本発明の一実施形態では、剥離層６としてＵＶ光を吸収して剥離可能となる樹脂を用い、支持体５にはガラスを用いる。 The peeling layer 6 may be, for example, a resin that absorbs light such as UV light and generates heat or can be peeled off by alteration, or may be a resin that can be peeled off by foaming due to heat. When a resin that can be peeled off by light such as UV light is used, the support 5 is irradiated with light from the surface opposite to the side on which the peeling layer 6 is provided, and the interposer 3 and the FC-BGA wiring board 1 are irradiated. The support 5 is removed from the joint with. In this case, the support 5 needs to have transparency, and glass can be used, for example. Glass has excellent flatness and is suitable for forming fine patterns of interposer 3, and since glass has a small CTE (coefficient of thermal expansion) and is not easily distorted, pattern arrangement accuracy and flatness are improved. Excellent for securing. When glass is used as the support 5, the thickness of the glass is preferably thick from the viewpoint of suppressing the occurrence of warpage in the manufacturing process, and is, for example, 0.7 mm or more, preferably 1.1 mm or more. The CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and more preferably about 9 ppm from the viewpoint of the CTE of the FC-BGA wiring board 1 and the semiconductor element 4. Here, for example, glass is used as the support 5. On the other hand, when the resin foamed by the heat is used for the release layer 6, the support 5 is removed by heating the joint between the interposer 3 and the FC-BGA wiring board 1. In this case, for the support 5, for example, metal or ceramics having less distortion can be used. In one embodiment of the present invention, a resin capable of absorbing UV light and peeling is used as the peeling layer 6, and glass is used as the support 5.

次いで、図３（ｂ）に示すように、真空中で、シード層８を形成する。シード層８は配線形成用において、電解めっきの給電層として作用する。シード層８は、例えば、スパッタ法、またはＣＶＤ法などにより形成され、例えば、Ｃｕ、Ｎｉ、Ａｌ、Ｔｉ、Ｃｒ、Ｍｏ、Ｗ、Ｔａ、Ａｕ、Ｉｒ、Ｒｕ、Ｐｄ、Ｐｔ、ＡｌＳｉ、ＡｌＳｉＣｕ、ＡｌＣｕ、ＮｉＦｅ、ＩＴＯ、ＩＺＯ、ＡＺＯ、ＺｎＯ、ＰＺＴ、ＴｉＮ、Ｃｕ３Ｎ４、Ｃｕ合金単体もしくは複数組み合わせたものを適用することができる。本発明では、電気特性、製造の容易性の観点およびコスト面を考慮して、チタン層、続いて銅層を順次スパッタリング法で形成する。チタンと銅層の合計の膜厚は、電解めっきの給電層として１μｍ以下とするのが好ましい。本発明の一実施形態ではＴｉ：５０ｎｍ、Ｃｕ：３００ｎｍを形成した。 Then, as shown in FIG. 3 (b), the seed layer 8 is formed in vacuum. The seed layer 8 acts as a feeding layer for electrolytic plating in forming wiring. The seed layer 8 is formed by, for example, a sputtering method, a CVD method, or the like, and for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloy alone or a combination of two or more can be applied. In the present invention, the titanium layer and then the copper layer are sequentially formed by a sputtering method in consideration of electrical characteristics, ease of manufacture, and cost. The total film thickness of the titanium and copper layers is preferably 1 μm or less as the feeding layer for electrolytic plating. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm were formed.

次に図３（ｃ）に示すようにレジストパターン９を形成し、電解めっきにより導体層（第１電極）１０を形成する。導体層１０は半導体素子４と接合用の電極となる。電解めっき法は電解ニッケルめっき、電解銅めっき、電解クロムめっき、電解Ｐｄめっき、電解金めっき、電解ロジウムめっき、電解イリジウムめっき等が挙げられるが、電解銅めっきであることが簡便で安価で、電気伝導性が良好であることから望ましい。電解銅めっきの厚みは、回路の接続信頼性、及び、製造コストの観点から、１μｍ以上３０μｍ以下であることが望ましい。その後、図３（ｄ）に示すようにレジストパターン９を除去する。 Next, as shown in FIG. 3C, a resist pattern 9 is formed, and a conductor layer (first electrode) 10 is formed by electrolytic plating. The conductor layer 10 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 1 μm or more and 30 μm or less from the viewpoint of circuit connection reliability and manufacturing cost. After that, the resist pattern 9 is removed as shown in FIG. 3 (d).

次に、図３（ｅ）に示すように絶縁樹脂層Ｃを形成する。絶縁樹脂層Ｃは導体層１０が絶縁樹脂層Ｃの層内に埋め込まれるように形成する。本実施形態では、絶縁樹脂層Ｃとして例えば、感光性のエポキシ系樹脂をスピンコート法により形成する。絶縁樹脂層Ｃとしては、感光性のエポキシ系樹脂を用いてスピンコート法により形成する他、絶縁樹脂フィルムを真空ラミネータで圧縮キュアを行って形成することも可能であり、この場合は平坦性の良い絶縁膜を形成することができる。その他、例えばポリイミドを絶縁樹脂として用いることも可能である。
次に、図３（ｆ）に示すように、フォトリソグラフィーにより、導体層１０上に開口部を設ける。開口部に対して、現像時の残渣除去を目的として、プラズマ処理を行ってもよい。 Next, the insulating resin layer C is formed as shown in FIG. 3 (e). The insulating resin layer C is formed so that the conductor layer 10 is embedded in the layer of the insulating resin layer C. In the present embodiment, for example, a photosensitive epoxy resin is formed as the insulating resin layer C by a spin coating method. The insulating resin layer C can be formed by the spin coating method using a photosensitive epoxy resin, or the insulating resin film can be formed by compression curing with a vacuum laminator. In this case, the insulating resin layer C is flat. A good insulating film can be formed. In addition, for example, polyimide can be used as the insulating resin.
Next, as shown in FIG. 3 (f), an opening is provided on the conductor layer 10 by photolithography. The openings may be subjected to plasma treatment for the purpose of removing residues during development.

次に、図４（ｇ）に示すように、開口部の表面上にシード層１２を設ける。シード層１２の構成については前述したシード層８と同様で、適宜構成、厚みを変更可能である。本発明の一実施形態ではＴｉ：５０ｎｍ、Ｃｕ：３００ｎｍをスパッタリング法で形成した。
次に、図４（ｈ）に示すように、シード層１２上にレジストパターン１３を形成し、その開口部に電解めっきにより導体層（配線層）１４を形成する。導体層１４は、インターポーザ３の内部の配線層となる。本発明の一実施形態では導体層１４として銅を形成した。その後、図４（ｉ）に示すようにレジストパターン１３を除去する。その後、不要なシード層１２をエッチング除去する。 Next, as shown in FIG. 4 (g), the seed layer 12 is provided on the surface of the opening. The structure of the seed layer 12 is the same as that of the seed layer 8 described above, and the structure and thickness can be changed as appropriate. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm were formed by a sputtering method.
Next, as shown in FIG. 4H, a resist pattern 13 is formed on the seed layer 12, and a conductor layer (wiring layer) 14 is formed in the opening thereof by electrolytic plating. The conductor layer 14 is a wiring layer inside the interposer 3. In one embodiment of the present invention, copper was formed as the conductor layer 14. After that, the resist pattern 13 is removed as shown in FIG. 4 (i). After that, the unnecessary seed layer 12 is removed by etching.

次に、図４（ｊ）に示すように絶縁樹脂層Ｂを形成する。絶縁樹脂層Ｂは導体層１４が絶縁樹脂層Ｃの層内に埋め込まれるように形成する。本実施形態では、絶縁樹脂層Ｂとして例えば、感光性のエポキシ系樹脂をスピンコート法により形成する。絶縁樹脂層Ｂとしては、感光性のエポキシ系樹脂を用いてスピンコート法により形成する他、絶縁樹脂フィルムを真空ラミネータで圧縮キュアを行って形成することも可能であり、この場合は平坦性の良い絶縁膜を形成することができる。その他、例えばポリイミドを絶縁樹脂として用いることも可能である。 Next, the insulating resin layer B is formed as shown in FIG. 4 (j). The insulating resin layer B is formed so that the conductor layer 14 is embedded in the layer of the insulating resin layer C. In the present embodiment, for example, a photosensitive epoxy resin is formed as the insulating resin layer B by a spin coating method. The insulating resin layer B can be formed by a spin coating method using a photosensitive epoxy resin, or the insulating resin film can be formed by compression curing with a vacuum laminator. In this case, the insulating resin layer B is flat. A good insulating film can be formed. In addition, for example, polyimide can be used as the insulating resin.

次に、図４（ｋ）に示すように、フォトリソグラフィーにより、導体層１４上に開口部を設ける。開口部に対して、現像時の残渣除去を目的として、プラズマ処理を行ってもよい。
次に、図４（ｌ）に示すように、開口部の表面上にシード層１５を設ける。シード層１５の構成については前述したシード層８と同様で、適宜構成、厚みを変更可能である。本発明の一実施形態ではＴｉ：５０ｎｍ、Ｃｕ：３００ｎｍをスパッタリング法で形成した。 Next, as shown in FIG. 4 (k), an opening is provided on the conductor layer 14 by photolithography. The openings may be subjected to plasma treatment for the purpose of removing residues during development.
Next, as shown in FIG. 4 (l), a seed layer 15 is provided on the surface of the opening. The structure of the seed layer 15 is the same as that of the seed layer 8 described above, and the structure and thickness can be changed as appropriate. In one embodiment of the present invention, Ti: 50 nm and Cu: 300 nm were formed by a sputtering method.

次に、図５（ｍ）に示すように、シード層１５上にレジストパターン１６を形成し、その開口部に電解めっきにより導体層（配線層）１７を形成する。導体層１７は、インターポーザ３の内部の配線層となる。本発明の一実施形態では導体層１７として銅を形成した。その後、図５（ｎ）に示すようにレジストパターン１６を除去する。その後、不要なシード層１２をエッチング除去する。
次に、図４（ｊ）から図５（ｎ）の工程を繰り返し、図５（ｏ）に示すような、導体層（配線層）１７が多層化された基板を得る。導体層１７の内、最表面に配置される導体層（第２電極）１８は、ＦＣ−ＢＧＡ用配線基板１との接合用の電極となる。 Next, as shown in FIG. 5 (m), a resist pattern 16 is formed on the seed layer 15, and a conductor layer (wiring layer) 17 is formed in the opening thereof by electrolytic plating. The conductor layer 17 is a wiring layer inside the interposer 3. In one embodiment of the present invention, copper was formed as the conductor layer 17. After that, the resist pattern 16 is removed as shown in FIG. 5 (n). After that, the unnecessary seed layer 12 is removed by etching.
Next, the steps of FIGS. 4 (j) to 5 (n) are repeated to obtain a substrate in which the conductor layer (wiring layer) 17 is multi-layered as shown in FIG. 5 (o). Of the conductor layers 17, the conductor layer (second electrode) 18 arranged on the outermost surface serves as an electrode for joining to the FC-BGA wiring board 1.

次に、図５（ｐ）に示すように、インターポーザ３に絶縁樹脂層Ａを形成する。絶縁樹脂層Ａは、絶縁樹脂層Ｂを覆うように、露光、現像により、導体層１７が露出するように開口部を備えるように形成する。本発明の実施形態では、絶縁樹脂層Ａとして感光性エポキシ樹脂を使用して絶縁樹脂層Ａを形成する。
次に、図５（ｑ）に示すように導体層１７の表面の酸化防止とはんだバンプの濡れ性をよくするため、表面処理層２４を設ける。本発明の実施形態では、表面処理層２４として無電解Ｎｉ／Ｐｄ／Ａｕめっきを成膜する。なお、表面処理層２４には、ＯＳＰ（Ｏｒｇａｎｉｃ Ｓｏｉｄｅｒａｂｉｌｉｔｙ Ｐｒｅｓｅｒｖａｔｉｖｅ 水溶性プレフラックスによる表面処理）膜を形成してもよい。また、無電解スズめっき、無電解Ｎｉ／Ａｕめっきなどから適宜用途に応じて選択しても良い。 Next, as shown in FIG. 5 (p), the insulating resin layer A is formed on the interposer 3. The insulating resin layer A is formed so as to cover the insulating resin layer B and to have an opening so that the conductor layer 17 is exposed by exposure and development. In the embodiment of the present invention, the insulating resin layer A is formed by using a photosensitive epoxy resin as the insulating resin layer A.
Next, as shown in FIG. 5 (q), a surface treatment layer 24 is provided in order to prevent oxidation of the surface of the conductor layer 17 and improve the wettability of the solder bumps. In the embodiment of the present invention, electroless Ni / Pd / Au plating is formed as the surface treatment layer 24. An OSP (Organic Soiderability Preservative surface treatment with a water-soluble preservative) film may be formed on the surface treatment layer 24. Further, electroless tin plating, electroless Ni / Au plating and the like may be appropriately selected depending on the intended use.

次に、図５（ｒ）に示すように、表面処理層２４上に、半田材料を搭載した後、一度溶融冷却して固着させることで、半田バンプからなるインターポーザ３側のＦＣ−ＢＧＡ用配線基板１とインターポーザ３との接合部１９ａを得る。これにより、支持体５上に形成されたインターポーザ（第２配線基板）３が完成する。 Next, as shown in FIG. 5 (r), the solder material is mounted on the surface treatment layer 24, and then melt-cooled and fixed once to fix the solder bumps for FC-BGA wiring on the interposer 3 side. A joint portion 19a between the substrate 1 and the interposer 3 is obtained. As a result, the interposer (second wiring board) 3 formed on the support 5 is completed.

続けて、図６Ａから図６Ｆを用いて、支持体５上に形成されたインターポーザ（第２配線基板）３とＦＣ−ＢＧＡ用配線基板（第１配線基板）１の本発明の一実施形態に係る接合工程の一例を説明する。
図６Ａに示すように、支持体５上に形成されたインターポーザ３の接合部１９ａに合わせてＦＣ−ＢＧＡ用配線基板１の接合部１９ｂを設計、製造したＦＣ−ＢＧＡ用配線基板１に対して支持体５上に形成されたインターポーザ３を配置する。 Subsequently, using FIGS. 6A to 6F, the interposer (second wiring board) 3 and the FC-BGA wiring board (first wiring board) 1 formed on the support 5 are set to one embodiment of the present invention. An example of such a joining process will be described.
As shown in FIG. 6A, with respect to the FC-BGA wiring board 1 in which the FC-BGA wiring board 1 joint 19b is designed and manufactured in accordance with the interposer 3 joint 19a formed on the support 5. The interposer 3 formed on the support 5 is arranged.

次に図６Ｂに示すように、支持体５上に形成されたインターポーザ３とＦＣ−ＢＧＡ用配線基板１を接合し、インターポーザ‐ＦＣ−ＢＧＡ接合部１９を形成する。接合部１９を形成する方式としては、例えば、リフロー炉を用いた一括リフロー（マスリフロー）方式が可能である。
次に図６Ｃに示すように、支持体５を剥離する。剥離層６は、ＵＶ光をレーザ光２３で照射して剥離する。支持体５の背面より、すなわち、支持体５のＦＣ−ＢＧＡ用配線基板１とは逆側の面からレーザ光２３を支持体５との界面に形成された剥離層６に照射し剥離可能な状態とすることで、図６Ｄに示すように支持体５を取り外すことが可能となる。 Next, as shown in FIG. 6B, the interposer 3 formed on the support 5 and the FC-BGA wiring board 1 are joined to form an interposer-FC-BGA joint portion 19. As a method for forming the joint portion 19, for example, a batch reflow (mass reflow) method using a reflow furnace is possible.
Next, as shown in FIG. 6C, the support 5 is peeled off. The peeling layer 6 is peeled by irradiating UV light with a laser beam 23. The peeling layer 6 formed at the interface with the support 5 can be peeled by irradiating the laser beam 23 from the back surface of the support 5, that is, from the surface of the support 5 opposite to the FC-BGA wiring board 1. In this state, the support 5 can be removed as shown in FIG. 6D.

次に図６Ｅに示すように、アンダーフィル２を形成しインターポーザ３とＦＣ−ＢＧＡ用配線基板１の固定、及び、接合部１９を封止する。アンダーフィル２の形成方式としては、毛細管現象を利用して接合後に液状の樹脂を充填させるキャピラリーフロー方式が可能である。
次に、シード層８を除去し、図６Ｆに示すような基板を得る。本発明の実施形態では、シード層８は、チタンと銅を用いており、それぞれアルカリ系のエッチング剤と、酸系のエッチング剤にて溶解除去することができる。このようにして、インターポーザ（第２配線基板）３とＦＣ−ＢＧＡ用配線基板（第１配線基板）１が接合された配線基板４０を得る。 Next, as shown in FIG. 6E, the underfill 2 is formed, the interposer 3 and the FC-BGA wiring board 1 are fixed, and the joint portion 19 is sealed. As a method for forming the underfill 2, a capillary flow method in which a liquid resin is filled after joining by utilizing the capillary phenomenon is possible.
Next, the seed layer 8 is removed to obtain a substrate as shown in FIG. 6F. In the embodiment of the present invention, titanium and copper are used for the seed layer 8, which can be dissolved and removed by an alkaline etching agent and an acid etching agent, respectively. In this way, the wiring board 40 to which the interposer (second wiring board) 3 and the FC-BGA wiring board (first wiring board) 1 are joined is obtained.

このとき、図７に示すように、表面に露出した導体層１０は、絶縁樹脂層Ｃの表面と面一であり平坦な形状をしている。表面に露出した導体層１０上に、酸化防止と半田バンプの濡れ性をよくするため、無電解Ｎｉ／Ｐｄ／Ａｕめっき、ＯＳＰ、無電解スズめっき、無電解Ｎｉ／Ａｕめっきなどの表面処理を施してもよい。以上により配線基板４０が完成する。 At this time, as shown in FIG. 7, the conductor layer 10 exposed on the surface is flush with the surface of the insulating resin layer C and has a flat shape. Surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating are performed on the conductor layer 10 exposed on the surface in order to prevent oxidation and improve the wettability of solder bumps. May be applied. With the above, the wiring board 40 is completed.

さらに、図８Ａから図８Ｃおよび図１を用いて、配線基板４０のインターポーザ（第２配線基板）３と半導体素子４の本発明の一実施形態に係る接合工程の一例を説明する。
図８Ａに示すように、配線基板４０のインターポーザ３の接合部２０ｂに対して、半導体素子４の接合部２０ａを配置する。
次に図８Ｂに示すように、配線基板４０のインターポーザ３と半導体素子４を接合する。接合部２０を形成する方式としては、例えば、リフロー炉を用いた一括リフロー（マスリフロー）方式や、加熱加圧機能を有するフリップチップ実装機を用いたローカルリフロー方式が可能である。 Further, with reference to FIGS. 8A to 8C and FIG. 1, an example of the joining process according to the embodiment of the present invention of the interposer (second wiring board) 3 of the wiring board 40 and the semiconductor element 4 will be described.
As shown in FIG. 8A, the joint portion 20a of the semiconductor element 4 is arranged with respect to the joint portion 20b of the interposer 3 of the wiring board 40.
Next, as shown in FIG. 8B, the interposer 3 of the wiring board 40 and the semiconductor element 4 are joined. As a method for forming the joint portion 20, for example, a batch reflow (mass reflow) method using a reflow furnace and a local reflow method using a flip chip mounting machine having a heating and pressurizing function are possible.

次に図８Ｃに示すように、アンダーフィル２１を形成しインターポーザ３と半導体素子４の固定、及び、接合部２０を封止する。アンダーフィル２１の形成方式としては、毛細管現象を利用して接合後に液状の樹脂を充填させるキャピラリーフロー方式を用いる。
キャピラリーフロー方式でアンダーフィル２１を充填することで、低コストで半導体素子４を封止できる。
次いで、必要に応じて図８Ａから図８Ｃの工程を繰り返し、複数個の半導体素子４を配線基板４０のインターポーザ３に実装することによって、図１に示す半導体素子を実装した半導体パッケージが完成する。 Next, as shown in FIG. 8C, the underfill 21 is formed, the interposer 3 and the semiconductor element 4 are fixed, and the joint portion 20 is sealed. As a method for forming the underfill 21, a capillary flow method is used in which a liquid resin is filled after joining by utilizing the capillary phenomenon.
By filling the underfill 21 by the capillary flow method, the semiconductor element 4 can be sealed at low cost.
Then, the steps of FIGS. 8A to 8C are repeated as necessary, and the plurality of semiconductor elements 4 are mounted on the interposer 3 of the wiring board 40 to complete the semiconductor package on which the semiconductor elements shown in FIG. 1 are mounted.

＜作用効果＞
次に、上述したような配線基板４０の構成とその製造方法を用いた場合の作用効果について説明する。本発明の一態様によれば、ＦＣ−ＢＧＡ用配線基板１に搭載した後に支持体５を剥離する方式において、支持体５を剥離した後も変形せず、形状安定性に優れた微細な配線層を形成することができる。また、信頼性の観点ではクラックを抑制することができる。そのため、実装性、信頼性に優れた配線基板を提供することが可能となる。 <Effect>
Next, the configuration of the wiring board 40 as described above and the operation and effect when the manufacturing method thereof is used will be described. According to one aspect of the present invention, in a method in which the support 5 is peeled off after being mounted on the FC-BGA wiring board 1, the fine wiring that does not deform even after the support 5 is peeled off and has excellent shape stability. Layers can be formed. Further, from the viewpoint of reliability, cracks can be suppressed. Therefore, it is possible to provide a wiring board having excellent mountability and reliability.

インターポーザ３に微細配線形成用の絶縁樹脂に加え、貯蔵弾性率の高い絶縁樹脂を用いることによって、支持体５を剥離した後、インターポーザ３の端部が下がったり、インターポーザ３の表面がうねったりする変形を抑制できる。また、貯蔵弾性率の高い絶縁樹脂を半導体チップ４側、ＦＣ−ＢＧＡ用配線基板１側の両側に配置することで、半導体チップ４とインターポーザ３とのＣＴＥ差、インターポーザ３とＦＣ−ＢＧＡ用配線基板１のＣＴＥ差に起因したクラックを抑制することができる。また、３種類の異なる絶縁樹脂を用いることによって、加工性を確保した上で最も剛直なインターポーザ３が得られ、うねり、クラックを抑制することができ、実装性、信頼性に優れた配線基板を提供することができる。 By using an insulating resin having a high storage elastic modulus in addition to the insulating resin for forming fine wiring in the interposer 3, the end portion of the interposer 3 is lowered or the surface of the interposer 3 is undulated after the support 5 is peeled off. Deformation can be suppressed. Further, by arranging insulating resins having a high storage elastic modulus on both sides of the semiconductor chip 4 side and the FC-BGA wiring board 1 side, the CTE difference between the semiconductor chip 4 and the interposer 3 and the wiring between the interposer 3 and the FC-BGA Cracks caused by the CTE difference of the substrate 1 can be suppressed. Further, by using three different types of insulating resins, the most rigid interposer 3 can be obtained while ensuring workability, waviness and cracks can be suppressed, and a wiring board having excellent mountability and reliability can be obtained. Can be provided.

絶縁樹脂層Ａ、Ｂ、Ｃの貯蔵弾性率の大きさはＢ＜Ｃ＜Ａとなることが望ましい。前述した微細配線層を形成する場合は、その加工性から貯蔵弾性率の小さな材料を選択する場合があるが、その外側に貯蔵弾性率の高い絶縁樹脂を配置することで、うねりを抑制することができる。一方、一般的に微細配線形成性と変形しにくさ、割れにくさはトレードオフの関係性になる場合があるが、半導体チップ４側の電極形成に求められる樹脂加工性よりもＦＣ−ＢＧＡ用配線基板１側のパッド形成に求められる樹脂加工性の方が寛容であり、より広い範囲で貯蔵弾性率の異なる樹脂を選択できる。それぞれの層に適した樹脂を選択することで加工性を確保した上で最も剛直なインターポーザ３が得られ、うねり、クラックを抑制することができ、実装性、信頼性に優れた配線基板を提供することができる。さらにまた、インターポーザ３の半導体素子４と接合する導体層１０は、絶縁樹脂層Ｃの表面と面一である、平坦電極である。平坦電極は、高さのばらつきが少なく、半導体素子４を実装するときに位置ずれが起こりにくいため、半導体素子４を歩留まりよく実装することができる。 It is desirable that the magnitude of the storage elastic modulus of the insulating resin layers A, B, and C is B <C <A. When forming the above-mentioned fine wiring layer, a material having a small storage elastic modulus may be selected from its workability, but waviness can be suppressed by arranging an insulating resin having a high storage elastic modulus on the outside. Can be done. On the other hand, in general, fine wiring formability, deformation resistance, and crack resistance may have a trade-off relationship, but for FC-BGA rather than the resin workability required for electrode formation on the semiconductor chip 4 side. The resin processability required for pad formation on the wiring board 1 side is more forgiving, and resins having different storage elastic moduli can be selected in a wider range. By selecting a resin suitable for each layer, the most rigid interposer 3 can be obtained while ensuring workability, waviness and cracks can be suppressed, and a wiring board with excellent mountability and reliability is provided. can do. Furthermore, the conductor layer 10 bonded to the semiconductor element 4 of the interposer 3 is a flat electrode that is flush with the surface of the insulating resin layer C. Since the flat electrode has little variation in height and is less likely to be displaced when the semiconductor element 4 is mounted, the semiconductor element 4 can be mounted with a high yield.

＜第２の実施形態＞
次に、第２の実施形態に係る配線基板ついて説明する。
第２の実施形態に係る配線基板と、第１の実施形態に係る配線基板とは類似であるが、第２電極に関して異なることを特徴としている。そのため、図９（ａ）〜図９（ｃ）を参照して第２電極について説明し、その他については説明を省略する。 <Second embodiment>
Next, the wiring board according to the second embodiment will be described.
The wiring board according to the second embodiment is similar to the wiring board according to the first embodiment, but is characterized in that the second electrode is different. Therefore, the second electrode will be described with reference to FIGS. 9 (a) to 9 (c), and the description of the other electrodes will be omitted.

図９（ａ）に示すように、表面に露出した導体層１０および絶縁樹脂層Ｃの上にレジストパターン３０を形成する。次に、図９（ｂ）に示すように、電解めっきによりピラー３１を形成する。ピラー３１は半導体素子４と接合用の電極となる。電解めっき法は電解ニッケルめっき、電解銅めっき、電解クロムめっき、電解Ｐｄめっき、電解金めっき、電解ロジウムめっき、電解イリジウムめっき等が挙げられるが、電解銅めっきであることが簡便で安価で、電気伝導性が良好であることから望ましい。電解銅めっきの厚みは、接続信頼性、及び、製造コストの観点から、３μｍ以上２０μｍ以下であることが望ましい。その後、図９（ｃ）に示すようにレジストパターン３０を除去する。さらに、ピラー３１に、酸化防止と半田バンプの濡れ性をよくするため、無電解Ｎｉ／Ｐｄ／Ａｕめっき、ＯＳＰ、無電解スズめっき、無電解Ｎｉ／Ａｕめっきなどの表面処理を施してもよい。 As shown in FIG. 9A, a resist pattern 30 is formed on the conductor layer 10 and the insulating resin layer C exposed on the surface. Next, as shown in FIG. 9B, the pillar 31 is formed by electrolytic plating. The pillar 31 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 3 μm or more and 20 μm or less from the viewpoint of connection reliability and manufacturing cost. After that, the resist pattern 30 is removed as shown in FIG. 9 (c). Further, the pillar 31 may be subjected to surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating in order to prevent oxidation and improve the wettability of solder bumps. ..

また、ピラー３１は、図３（ｂ）の後、図１０（ａ）〜図１０（ｂ）に示した方法によって形成することもできる。図１０（ａ）に示すようにレジストパターン３２を形成し、電解めっきによりピラー３１を形成する。ピラー３１は半導体素子４と接合用の電極となる。電解めっき法は電解ニッケルめっき、電解銅めっき、電解クロムめっき、電解Ｐｄめっき、電解金めっき、電解ロジウムめっき、電解イリジウムめっき等が挙げられるが、電解銅めっきであることが簡便で安価で、電気伝導性が良好であることから望ましい。電解銅めっきの厚みは、回路の接続信頼性、及び、製造コストの観点から、３μｍ以上２０μｍ以下であることが望ましい。次に、図１０（ｂ）に示すように絶縁樹脂層（第２絶縁樹脂）Ｃを形成する。この後、図４（ｇ）以降に示した方法によって、インターポーザ３を製造する。支持体５を剥離した後に表面に露出するレジストパターン３２を除去することによって、図１１に示すように凸形状の電極を有するインターポーザ３が完成する。さらに、ピラー３１に、酸化防止と半田バンプの濡れ性をよくするため、無電解Ｎｉ／Ｐｄ／Ａｕめっき、ＯＳＰ、無電解スズめっき、無電解Ｎｉ／Ａｕめっきなどの表面処理を施してもよい。 Further, the pillar 31 can also be formed by the method shown in FIGS. 10 (a) to 10 (b) after FIG. 3 (b). As shown in FIG. 10A, the resist pattern 32 is formed, and the pillar 31 is formed by electrolytic plating. The pillar 31 serves as an electrode for bonding with the semiconductor element 4. Examples of the electrolytic plating method include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. However, electrolytic copper plating is simple, inexpensive, and electric. It is desirable because it has good conductivity. The thickness of the electrolytic copper plating is preferably 3 μm or more and 20 μm or less from the viewpoint of circuit connection reliability and manufacturing cost. Next, as shown in FIG. 10B, the insulating resin layer (second insulating resin) C is formed. After that, the interposer 3 is manufactured by the method shown in FIG. 4 (g) and thereafter. By removing the resist pattern 32 exposed on the surface after peeling off the support 5, the interposer 3 having a convex electrode is completed as shown in FIG. Further, the pillar 31 may be subjected to surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating in order to prevent oxidation and improve the wettability of solder bumps. ..

＜作用効果＞
ピラー３１を有する凸形状の電極によって、インターポーザ３と半導体素子４との間を広くすることができる。このため、液状のアンダーフィル２１が流れやすくなり、インターポーザ３と半導体素子４との間にボイド（空隙）が発生しにくくなる。つまり、キャピラリーフロー方式によるアンダーフィル２１の形成が容易となる。 <Effect>
The convex electrode having the pillar 31 can widen the space between the interposer 3 and the semiconductor element 4. Therefore, the liquid underfill 21 easily flows, and voids (voids) are less likely to be generated between the interposer 3 and the semiconductor element 4. That is, the underfill 21 can be easily formed by the capillary flow method.

＜第３の実施形態＞
次に、第３の実施形態に係る配線基板ついて説明する。
第３の実施形態に係る配線基板と、第１の実施形態に係る配線基板とは類似であるが、第２電極に関して異なることを特徴としている。そのため、図１２（ａ）〜図１２（ｂ）を参照して第２電極について説明し、その他については説明を省略する。
図１２（ａ）に示す表面に露出した導体層１０の表面を、エッチングすることによって、図１２（ｂ）に示すように凹み形状の電極を形成することができる。エッチング方法は、ウェット、ドライのいずれも可能である。さらに、酸化防止と半田バンプの濡れ性をよくするため、無電解Ｎｉ／Ｐｄ／Ａｕめっき、ＯＳＰ、無電解スズめっき、無電解Ｎｉ／Ａｕめっきなどの表面処理を施してもよい。 <Third embodiment>
Next, the wiring board according to the third embodiment will be described.
The wiring board according to the third embodiment is similar to the wiring board according to the first embodiment, but is characterized in that it differs with respect to the second electrode. Therefore, the second electrode will be described with reference to FIGS. 12 (a) to 12 (b), and the description of the other electrodes will be omitted.
By etching the surface of the conductor layer 10 exposed to the surface shown in FIG. 12 (a), a concave electrode can be formed as shown in FIG. 12 (b). The etching method can be either wet or dry. Further, in order to prevent oxidation and improve the wettability of the solder bumps, surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating may be performed.

＜作用効果＞
凹み形状の電極によって、半導体素子４を実装するとき、半導体素子４の接合部２０ａがインターポーザ３側に接触した後、絶縁樹脂Ｃの側面があることによってはんだが濡れ広がる領域は導体層１０上のみとなり、はんだが導体層１０の周囲に流れ出ることを抑制できる。導体層１０の形状が矩形、長円形など、円形ではない場合により効果的である。 <Effect>
When the semiconductor element 4 is mounted by the concave electrode, after the joint portion 20a of the semiconductor element 4 comes into contact with the interposer 3 side, the region where the solder wets and spreads due to the side surface of the insulating resin C is only on the conductor layer 10. Therefore, it is possible to prevent the solder from flowing out around the conductor layer 10. It is more effective when the shape of the conductor layer 10 is not circular, such as a rectangle or an oval.

＜第４の実施形態＞
次に、第４の実施形態に係る配線基板ついて説明する。
第４の実施形態に係る配線基板の製造方法と、第１の実施形態に係る配線基板の製造方法とは類似であるが、アンダーフィルの形成に関して異なることを特徴としている。そのため、図１３Ａ〜図１３Ｂを参照してアンダーフィルの形成について説明し、その他については説明を省略する。
図１３Ａに示すように、配線基板４０のインターポーザ３の接合部２０ｂに対して、半導体素子４の接合部２０ａを配置する。半導体素子４には、フィルム状接続材料（ＮＣＦ）３３が仮接着されている。
次に図１３Ｂに示すように、配線基板４０のインターポーザ３と半導体素子４を接合する。接合部２０を形成する方式としては、例えば、加熱加圧機能を有するフリップチップ実装機を用いたローカルリフロー方式が可能である。
次いで、必要に応じて図１３Ａ〜図１３Ｂの工程を繰り返し、複数個の半導体素子４を配線基板４０のインターポーザ３に実装することによって、図１に示す半導体素子を実装した半導体パッケージが完成する。 <Fourth Embodiment>
Next, the wiring board according to the fourth embodiment will be described.
The method for manufacturing the wiring board according to the fourth embodiment is similar to the method for manufacturing the wiring board according to the first embodiment, but is characterized in that the formation of the underfill is different. Therefore, the formation of the underfill will be described with reference to FIGS. 13A to 13B, and the description of the others will be omitted.
As shown in FIG. 13A, the joint portion 20a of the semiconductor element 4 is arranged with respect to the joint portion 20b of the interposer 3 of the wiring board 40. A film-like connecting material (NCF) 33 is temporarily adhered to the semiconductor element 4.
Next, as shown in FIG. 13B, the interposer 3 of the wiring board 40 and the semiconductor element 4 are joined. As a method for forming the joint portion 20, for example, a local reflow method using a flip-chip mounting machine having a heating and pressurizing function is possible.
Then, the steps of FIGS. 13A to 13B are repeated as necessary, and the plurality of semiconductor elements 4 are mounted on the interposer 3 of the wiring substrate 40 to complete the semiconductor package on which the semiconductor elements shown in FIG. 1 are mounted.

＜作用効果＞
膜厚が均一なフィルム状接続材料（ＮＣＦ）を用いることによって、半導体素子４を実装するときのギャップが均一に制御され、またボイドの抑制ができるため信頼性に優れた半導体パッケージが得られる。
上述の実施形態は一例であって、その他、具体的な細部構造などについては適宜に変更可能であることは勿論である。 <Effect>
By using a film-like connecting material (NCF) having a uniform film thickness, the gap when the semiconductor element 4 is mounted can be uniformly controlled, and voids can be suppressed, so that a highly reliable semiconductor package can be obtained.
The above-described embodiment is an example, and it goes without saying that the specific detailed structure and the like can be appropriately changed.

本発明は、主基板とＩＣチップとの間に介在するインターポーザ等を備えた配線基板を有する半導体装置に利用可能である。 The present invention can be used in a semiconductor device having a wiring board provided with an interposer or the like interposed between a main board and an IC chip.

１…ＦＣ−ＢＧＡ用配線基板（第１配線基板）
２、２１…アンダーフィル
３…インターポーザ（第２配線基板）
４…半導体素子（半導体チップ）
５…支持体
６…剥離層
８、１２、１５…シード層
９、１３、１６、３０、３２…レジストパターン
１０…導体層（第１電極）
Ａ…絶縁樹脂層（第１絶縁樹脂）
Ｂ…絶縁樹脂層（配線用絶縁樹脂）
Ｃ…絶縁樹脂層（第２絶縁樹脂）
１７…導体層（配線層）
１８…導体層（第２電極）
１９…ＦＣ−ＢＧＡ用配線基板‐インターポーザ接合部
１９ａ…インターポーザ側バンプ
１９ｂ…ＦＣ−ＢＧＡ用配線基板側バンプ
２０…半導体素子‐インターポーザ接合部
２０ａ…半導体素子側銅−はんだバンプ
２０ｂ…インターポーザ側パッド電極
２２…微細配線層
２３…レーザ光
２４…表面処理層
３１…ピラー
３３…フィルム状接続材料（ＮＣＦ）
４０…配線基板 1 ... Wiring board for FC-BGA (first wiring board)
2, 21 ... Underfill 3 ... Interposer (second wiring board)
4 ... Semiconductor element (semiconductor chip)
5 ... Support 6 ... Release layer 8, 12, 15 ... Seed layer 9, 13, 16, 30, 32 ... Resist pattern 10 ... Conductor layer (first electrode)
A ... Insulating resin layer (first insulating resin)
B ... Insulation resin layer (insulation resin for wiring)
C ... Insulating resin layer (second insulating resin)
17 ... Conductor layer (wiring layer)
18 ... Conductor layer (second electrode)
19 ... FC-BGA wiring board-interposer joint 19a ... Interposer side bump 19b ... FC-BGA wiring board side bump 20 ... Semiconductor element-interposer joint 20a ... Semiconductor element side copper-solder bump 20b ... Interposer side pad electrode 22 ... Fine wiring layer 23 ... Laser light 24 ... Surface treatment layer 31 ... Pillar 33 ... Film-like connecting material (NCF)
40 ... Wiring board

Claims (12)

第１配線基板と、
前記第１配線基板に接合され、前記第１配線基板より微細な配線が形成された第２配線基板を備え、
前記第１配線基板との接合面に対向する前記第２配線基板の対向面に半導体素子が実装される配線基板であって、
前記第２配線基板に用いる微細な配線を形成する為の配線用絶縁樹脂の表裏に、貯蔵弾性率が前記配線用絶縁樹脂よりも大きな絶縁樹脂が形成されていることを特徴とする配線基板。 With the first wiring board
A second wiring board which is joined to the first wiring board and has finer wiring than the first wiring board is provided.
A wiring board in which a semiconductor element is mounted on a surface facing the second wiring board facing the joint surface with the first wiring board.
A wiring board characterized in that an insulating resin having a storage elastic modulus larger than that of the wiring insulating resin is formed on the front and back surfaces of a wiring insulating resin for forming fine wiring used for the second wiring board. 前記配線用絶縁樹脂の表裏に形成する前記絶縁樹脂は、貯蔵弾性率の異なる第１絶縁樹脂と第２絶縁樹脂を含む請求項１に記載の配線基板。 The wiring substrate according to claim 1, wherein the insulating resin formed on the front and back surfaces of the wiring insulating resin includes a first insulating resin and a second insulating resin having different storage elastic moduli. 前記半導体素子の実装面側から見て前記第２絶縁樹脂、前記配線用絶縁樹脂、前記第１絶縁樹脂の順に積層されており、
前記第１絶縁樹脂の貯蔵弾性率をＡとし、前記配線用絶縁樹脂の貯蔵弾性率をＢとし、前記第２絶縁樹脂の貯蔵弾性率をＣとしたとき、Ｂ＜Ｃ＜Ａの関係である請求項２に記載の配線基板。 The second insulating resin, the wiring insulating resin, and the first insulating resin are laminated in this order when viewed from the mounting surface side of the semiconductor element.
When the storage elastic modulus of the first insulating resin is A, the storage elastic modulus of the wiring insulating resin is B, and the storage elastic modulus of the second insulating resin is C, the relationship is B <C <A. The wiring board according to claim 2. 前記配線用絶縁樹脂が感光性樹脂である請求項１から３のいずれか１項に記載の配線基板。 The wiring board according to any one of claims 1 to 3, wherein the wiring insulating resin is a photosensitive resin. 前記第１配線基板と前記第２配線基板との接続ピッチが前記半導体素子の接続ピッチよりも大きい請求項１から４のいずれか１項に記載の配線基板。 The wiring board according to any one of claims 1 to 4, wherein the connection pitch between the first wiring board and the second wiring board is larger than the connection pitch of the semiconductor element. 前記第２配線基板のＣｕ電極形状が、前記第１配線基板との接続側は凹み形状であり、前記半導体素子との接続側が平坦形状である請求項１から５のいずれか１項に記載の配線基板。 The method according to any one of claims 1 to 5, wherein the Cu electrode shape of the second wiring board has a concave shape on the connection side with the first wiring board and a flat shape on the connection side with the semiconductor element. Wiring board. 前記第２配線基板のＣｕ電極形状が、前記第１配線基板との接続側は凹み形状であり、前記半導体素子との接続側が凸形状である請求項１から５のいずれか１項に記載の配線基板。 The method according to any one of claims 1 to 5, wherein the Cu electrode shape of the second wiring board has a concave shape on the connection side with the first wiring board and a convex shape on the connection side with the semiconductor element. Wiring board. 前記第２配線基板のＣｕ電極形状が、前記第１配線基板との接続側、および前記半導体素子との接続側が共に凹み形状である請求項１から５のいずれか１項に記載の配線基板。 The wiring board according to any one of claims 1 to 5, wherein the Cu electrode shape of the second wiring board has a concave shape on both the connection side with the first wiring board and the connection side with the semiconductor element. 第１配線基板と、
前記第１配線基板と、前記第１配線基板に接合された前記第１配線基板より微細な配線が形成された第２配線基板とを備え、前記第２配線基板の前記第１配線基板との接合面の対向面に半導体素子が実装される配線基板の製造方法であって、
支持体の一面上に剥離層を形成する工程と、
前記剥離層の上部に前記半導体素子と接合する前記第２電極を形成する工程と、
第２絶縁樹脂を形成する工程と、
配線用絶縁樹脂と配線層からなる微細配線層を形成する工程と、
前記微細配線層の前記支持体と対向する側に前記第１配線基板と接合する前記第１電極を形成する工程と、第１絶縁樹脂を形成する工程を有する前記第２配線基板を形成する工程と、
前記第１配線基板の一方の面に前記第２配線基板と接合する第３電極を形成し、前記第２配線基板と前記第１配線基板を、前記第１電極と前記第３電極とで接合する工程と、
前記支持体を前記剥離層により前記第２配線基板から剥離し、前記第２電極と前記第２絶縁樹脂を表面に露出させる工程と、
前記第１配線基板と前記第２配線基板との間に第１封止樹脂を形成する工程と、
前記第１封止樹脂を硬化させる工程と、
前記第２配線基板と前記半導体素子を、前記第２電極と前記半導体素子の第４電極とで接合する工程と、
前記第２配線基板と前記半導体素子との間に第２封止樹脂を形成する工程と、
前記第２封止樹脂を硬化させる工程と、
を含むことを特徴とする配線基板の製造方法。 With the first wiring board
The first wiring board and the first wiring board of the second wiring board are provided with the first wiring board and the second wiring board in which finer wiring is formed than the first wiring board joined to the first wiring board. A method for manufacturing a wiring board in which a semiconductor element is mounted on a surface facing a joint surface.
The process of forming a release layer on one surface of the support and
A step of forming the second electrode to be bonded to the semiconductor element on the upper part of the release layer, and
The process of forming the second insulating resin and
The process of forming a fine wiring layer consisting of an insulating resin for wiring and a wiring layer,
A step of forming the second wiring board having a step of forming the first electrode to be joined to the first wiring board and a step of forming a first insulating resin on the side of the fine wiring layer facing the support. When,
A third electrode to be joined to the second wiring board is formed on one surface of the first wiring board, and the second wiring board and the first wiring board are joined by the first electrode and the third electrode. And the process to do
A step of peeling the support from the second wiring board by the peeling layer to expose the second electrode and the second insulating resin on the surface.
A step of forming a first sealing resin between the first wiring board and the second wiring board, and
The step of curing the first sealing resin and
A step of joining the second wiring board and the semiconductor element with the second electrode and the fourth electrode of the semiconductor element.
A step of forming a second sealing resin between the second wiring board and the semiconductor element, and
The step of curing the second sealing resin and
A method for manufacturing a wiring board, which comprises. 前記第２配線基板と前記第１配線基板とはマスリフロー方式で接合する請求項９に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 9, wherein the second wiring board and the first wiring board are joined by a mass reflow method. 前記第２配線基板と前記第１配線基板との接合部、半導体素子の接合部共にキャピラリーフローアンダーフィルで封止する請求項９に記載の配線基板の製造方法。 The method for manufacturing a wiring board according to claim 9, wherein both the joint portion between the second wiring board and the first wiring board and the joint portion of the semiconductor element are sealed with a capillary flow underfill. 前記第２配線基板と前記第１配線基板との接合部はキャピラリーフローアンダーフィルで封止され、
半導体素子の接合部はフィルム状接続材料（ＮＣＦ）で封止される請求項９に記載の配線基板の製造方法。 The joint between the second wiring board and the first wiring board is sealed with a capillary flow underfill.
The method for manufacturing a wiring board according to claim 9, wherein the joint portion of the semiconductor element is sealed with a film-like connecting material (NCF).
JP2020018134A 2020-02-05 2020-02-05 Wiring board and method for manufacturing wiring board Pending JP2021125565A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023047947A1 (en) * 2021-09-22 2023-03-30 凸版印刷株式会社 Wiring board unit and design method therefor
WO2023047946A1 (en) * 2021-09-22 2023-03-30 凸版印刷株式会社 Support-equipped substrate and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023047947A1 (en) * 2021-09-22 2023-03-30 凸版印刷株式会社 Wiring board unit and design method therefor
WO2023047946A1 (en) * 2021-09-22 2023-03-30 凸版印刷株式会社 Support-equipped substrate and semiconductor device

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