JP2021086506A - System and programmable sequencer - Google Patents

Abstract

To prevent increase in a circuit scale.SOLUTION: A system according to an aspect of the present invention comprises: a storage unit that stores an execution instruction group including a plurality of execution instructions; and a programmable sequencer that executes an operation responding to a read-out execution instruction. The programmable sequencer includes at least one of a polling execution unit that executes a polling operation in response to a polling execution instruction, and a repeated jump execution unit that executes a repeated jump operation in response to a repeated jump execution instruction.SELECTED DRAWING: Figure 1

Description

The present application relates to systems and programmable sequencers.

Conventionally, there is known a technique of executing a specific process by using a dedicated state machine or a sub CPU instead of the main CPU (Central Processing Unit).

However, in the method using a dedicated state machine, not only the development man-hours are large, but also the man-hours for dealing with specification changes may be large. Further, in the method using a sub CPU, when the required processing content is simple, the circuit scale may become unnecessarily large because the sub CPU is provided with excessive functions such as a numerical calculation unit, an interrupt processing unit, and a cache. .. Furthermore, since it is desirable to prepare a software development environment for the sub CPU, it may take man-hours to master and maintain the development environment.

On the other hand, in order to suppress an increase in the circuit scale, a sequencer replaces the CPU and ROM (Read Only Memory) configuration of a general-purpose microcomputer with a sequencer (see, for example, Patent Document 1). Further, in order to improve the efficiency of programming work, a technique for mutually converting a motion control programming language and a sequence control programming language is disclosed (see, for example, Patent Document 2).

However, in the configuration of Patent Document 1, since the configuration of the general-purpose microcomputer is inherited by the arithmetic unit and the register structure, the circuit scale may become unnecessarily large when the functions of the general-purpose microcomputer are excessive. Further, since the method of Patent Document 2 does not disclose the method of reducing the circuit scale, it is not possible to suppress the increase in the circuit scale.

An object of the present invention is to suppress an increase in the scale of a circuit.

A system according to one aspect of the present invention includes a storage unit that stores an execution instruction group including a plurality of execution instructions, and a programmable sequencer that executes an operation in response to the read execution instruction. It includes at least one of a polling execution unit that executes a polling operation in response to a polling execution instruction and a repetitive jump execution unit that executes a repetitive jump operation in response to a repetitive jump execution instruction.

According to the present invention, it is possible to suppress an increase in the circuit scale.

It is a block diagram which shows the structural example of the ASIC which concerns on embodiment. It is a block diagram which shows the structural example of the sequencer which concerns on embodiment. It is a figure explaining an example of a NOP instruction. It is a figure explaining an example of a GR operation instruction. It is a figure explaining an example of an output terminal control instruction. It is a figure explaining an example of a direct bus transfer instruction and a local bus transfer instruction. It is a figure explaining an example of a forced jump instruction. It is a figure explaining an example of a repeat jump instruction. It is a figure explaining an example of a GR branch jump instruction. It is a figure explaining an example of an input terminal branch jump instruction. It is a figure explaining an example of an input terminal polling instruction. It is a figure explaining an example of the address space polling instruction. It is a figure which shows the address space allocation example of the ASIC which concerns on embodiment. It is a flowchart which shows the operation example of the sequencer which concerns on embodiment. It is a figure explaining the ROM area for a sequencer in the operation example of FIG.

Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.

In the following, an ASIC (Application Specific Integrated Circuit) 1 that includes a sequencer 100, which is an example of a programmable sequencer, and integrates control functions of an analog front-end device for a facsimile modem and a legacy device 30 such as a dedicated image processing device, is referred to as "Application Specific Integrated Circuit" 1. An embodiment will be described as an example of the “system”.

[First Embodiment]
<Configuration example of ASIC1>
FIG. 1 is a block diagram showing an example of the configuration of ASIC1.

As shown in FIG. 1, the ASIC 1 includes a legacy device control unit 10, a main CPU (Central Processing Unit) 21, a sub CPU 22, a DDR (Double Data Rate) controller 23, and a general-purpose DMAC (Direct Memory Access Controller) 24. And a storage control unit 25. These are electrically connected to each other via a common bus 20.

The legacy device control unit 10 has a function of controlling the legacy device 30, and includes a diversion module 11, an I / F terminal 12, a sequencer 100, a ROM 14, a work area 15, and a FIFO (First In Firest Out) 16. And a control register 17.

Further, the legacy device control unit 10 can transmit and receive data to and from higher-level systems such as the main CPU 21 and the sub CPU 22 via the local bus 13 and the common bus 20.

The diversion module 11 executes the control of the legacy device 30, but the control of the diversion module 11 itself needs to be performed by another module. When the control of the diversion module 11 is performed by a higher-level system such as the main CPU 21 or the sub CPU 22, the control of the diversion module 11 becomes a system constraint depending on the specifications of the diversion module 11, and scheduling with other processes becomes difficult. In some cases.

The specifications of the diversion module 11 that are restrictions on the system include bus occupancy time, data transfer protocol, interrupt processing, and the like. Since the bus occupancy time is long, there may be a restriction that it takes time for one access. Further, since the data transfer protocol is complicated, it is preferable that the main CPU 21 and the sub CPU 22 directly control the data, which cannot be controlled by a simple DMAC, or interrupt processing is required for each small amount of data transfer. May occur.

On the other hand, the sequencer 100 executes the control of the diversion module 11 instead of the main CPU 21 and the sub CPU 22 which are higher-level systems. The main CPU 21 and the sub CPU 22 do not directly control the diversion module 11, but control it via the sequencer 100, so that restrictions due to the specifications of the diversion module 11 can be avoided.

For example, when transmitting data to the legacy device 30, the main CPU 21 and the sub CPU 22 store the collected data in the FIFA 16, and the sequencer 100 transmits the data stored in the FIFA 16 according to a complicated protocol for the diversion module 11. As a result, it is possible to avoid executing complicated control for the diversion module 11 from the main CPU 21 and the sub CPU 22 side.

When receiving data from the legacy device 30, the sequencer 100 simply receives the data according to the complicated protocol of the diversion module 11 and then stores the data in the FIFA 16, and the main CPU 21 and the sub CPU 22 simply read the data stored in the FIFA 16. , Data from the legacy device 30 can be received.

The sequencer 100 includes a local bus master port 1061 that accesses various slave devices via the local bus 13, and a direct bus master port 1051 that can be directly accessed.

The accessible range of the sequencer 100 can be set for all slave devices connected to the local bus 13 and slave devices such as the DDR controller 23 connected to the common bus 20. However, in order to access the slave device connected to the common bus 20, it is necessary to correspond to the same address space as the main CPU 21 and the sub CPU 22. Therefore, as a result of the execution instruction group of the sequencer 100 corresponding to the same address space, the size per instruction becomes large, so that the circuit scale and the program size also become large.

On the other hand, if the access range of the sequencer 100 is limited to slave devices directly connected to the local bus, the address space that needs to be supported can be narrowed, so the size per instruction in the execution instruction group of the sequencer 100 can be set. Can be made smaller.

Therefore, in the present embodiment, the sequencer 100 is configured to be able to access only some slave devices connected to the local bus 13 and not to the devices connected to the common bus 20.

The ROM 14 stores an operation program for the sequencer 100. The operation program is described using the execution instruction group for the sequencer 100. The ROM 14 minimizes the read delay of the ROM 14 by directly connecting to the direct bus master port 1051 of the sequencer 100 without going through the local bus 13. As a result, the execution speed of the program is improved, and the execution timing can be guaranteed regardless of the degree of congestion of the local bus 13. Here, ROM 14 is an example of a “storage unit”.

The control register 17 is used by the main CPU 21 and the sub CPU 22 to operate the sequencer 100. For example, it is used to set (write) the operation start timing of the sequencer 100, and to confirm (read) the operation completion flag and the status.

The control register 17 includes a local bus slave port 172 accessed from the main CPU 21 and the sub CPU 22, and a direct bus slave port 171 accessed from the sequencer 100.

Here, in the present embodiment, the access from the sequencer 100 to the control register 17 is limited to only via the direct bus slave port 171 and cannot be accessed via the local bus 13. This facilitates the design of the local bus 13.

Further, by limiting the access from the sequencer 100 to the slave port 171 for the direct bus to read only and making it impossible to write, it is not necessary to consider access conflicts from a plurality of masters of the control register 17, and the design of the control register 17 is improved. It's getting easier.

Further, when the sequencer 100 wants to change the contents of the control register 17 such as the completion flag and the status, the general-purpose output port of the sequencer 100 can be read as a register value. As a result, the main CPU 21 and the sub CPU 22 can share the state of the sequencer 100.

The work area 15 is composed of a RAM (Random Access Memory) or a register, and is used for storing temporary data during operation of the sequencer 100. Further, the main CPU 21 and the sub CPU 22 are used as an area for writing the operation program of the sequencer 100.

If a boot device selection bit (bit) at the time of starting the sequencer 100 is provided in a part of the control register 17 so that the boot device can be selected to either the ROM 14 or the work area 15, even after the development of the ASIC 1. It is suitable because it can respond to changes in the operating specifications of the sequencer 100.

The work area 15 includes a direct bus slave port 151 for connecting to the direct bus master port 1051 of the sequencer 100, and a slave port 152 for connecting to the local bus 13. The sequencer 100 simplifies the structure of the sequencer 100 and the local bus 13 by providing a restriction that the program code is stored only in the slave device connected by the direct path.

The FIFA 16 as an example of the "first-in first-out unit" is used for data transfer between the main CPU 21, the sub CPU 22, and the sequencer 100. The FIFO 16 includes a write slave port 161 and a read slave port 162.

When data is transmitted from the main CPU 21 and the sub CPU 22 to the legacy device 30, the main CPU 21 and the sub CPU 22 write to the write slave port 161. The sequencer 100 transmits the data read from the read slave port 162 via the diversion module 11 to the legacy device 30.

When the main CPU 21 and the sub CPU 22 acquire the data of the legacy device 30, the sequencer 100 writes the acquired data via the diversion module 11 to the write slave port 161. Then, the main CPU 21 and the sub CPU 22 read from the read slave port 162.

The data storage state (full or empty) of the FIFA 16 can be read from the control register 17, and the main CPU 21, the sub CPU 22, and the sequencer 100 read and / or write after confirming the data storage state of the FIFA 16. Can be executed.

At this time, the sequencer 100 also executes processing according to the protocol required by the diversion module 11 before and after the access to the FIFA 16. A program for storing in the ROM 14 or the work area 15 has been created so as to satisfy the transfer protocol.

The local bus 13 arbitrates the master access executed by the main CPU 21 and the sub CPU 22 via the common bus 20 and the master access executed by the sequencer 100, and each master accesses the slave device inside the legacy device control unit 10. Relay.

The common bus 20 arbitrates and relays access to slaves such as the DDR controller 23 or the legacy device control unit 10 by each master such as the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, or the storage control unit 25.

The main CPU 21 operates at several hundred MHz to several GHz and executes the main processing of the system. Further, the sub CPU 22 operates at several tens of MHz to several hundreds of MHz, and executes sub-processing of ASIC1 such as processing at the time of energy saving. Here, each of the main CPU 21 and the sub CPU 22 is an example of a “processor”.

The DDR controller 23 executes read and / or write of the DDR memory 50 in accordance with a request from each master such as the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, or the storage control unit 25.

The DDR memory 50 is the main memory of the ASIC 1, and is used as an area for developing a program executed by the main CPU 21 and the sub CPU 22, a storage area for temporary data, and the like. This DDR memory 50 is an example of "memory".

The operation programs of the main CPU 21 and the sub CPU 22 are stored in the external storage 40, and the operation programs to be executed are transferred from the external storage 40 to the DDR memory 50 each time.

The storage control unit 25 controls access to the external storage 40. When writing to the external storage 40, the built-in DMAC251 is used to acquire the data of the DDR memory 50 and execute the data transmission to the external storage 40.

When reading from the external storage 40, the data received from the external storage 40 is written to the DDR memory 50 using the built-in DMAC251. As the external storage 40, for example, any one of HDD (Hard Disk Drive), SSD (Solid State Drive), eMMC (Embedded Multi Media Card) and the like can be connected.

<Configuration example of sequencer 100>
Next, the configuration of the sequencer 100 will be described with reference to FIG. FIG. 2 is a block diagram showing an example of the configuration of the sequencer 100.

As shown in FIG. 2, the sequencer 100 includes a PC 102, an IR (Instruction Register) lower 1031, an IR upper 1032, a direct bus access control unit 105, a local bus access control unit 106, and an input terminal state detection unit 107. The main state machine 101 and the instruction execution unit 1100 are provided.

The PC (Program Couter) 102 is a program counter that stores an address (storage position) in which an instruction to be executed most recently is stored. In the present embodiment, the bit width of the program counter is 12 bits. Here, this PC 102 is an example of a “storage position storage unit”.

There are two types of state machine instruction sizes in this embodiment, 2Byte (bytes) and 4Bytes, and 1Byte data is stored per address. Therefore, after the 2Byte instruction is executed, 2 is added to the value of PC102, and after the 4Byte instruction is executed, 4 is added to the value of PC102.

The IR lower 1031 is a 16-bit wide instruction register, and is used for storing a 2-byte instruction and a lower 16-bit instruction of a 4-bit instruction.

The IR upper 1032 is an instruction register having a width of 16 bits, and is used for storing the upper 16 bits of a 4-byte instruction.

Here, each of the IR lower 1031 and the IR upper 1032 is an example of the "command storage unit".

The GR 104 is an 8-bit wide general-purpose register, which is updated and / or referred to when various instructions are executed. This GR 104 is an example of an “execution storage unit”.

The direct bus access control unit 105 executes read and / or write of the ROM 14 or the control register 17 according to an instruction from the main state machine 101 or the instruction execution unit 1100 (including the designation of the target address and the operation start timing). .. In this embodiment, 16-bit data can be read and / or written with one instruction.
The local bus access control unit 106 executes read and / or write of a slave device such as a diversion module 11, a work area 15, or a FIFA 16 connected to the local bus 13 in accordance with an instruction from the instruction execution unit 1100. In this embodiment, 8-bit data can be read and / or written with one instruction.

The input terminal state detection unit 107 detects the level of the signal input to the sequencer 100. In this embodiment, eight signal levels can be detected. The input terminal state detection unit 107 outputs 8-bit data. Each 1 bit corresponds to the signal level of each input signal, and is an example of an "input terminal".

The main state machine 101 repeatedly transitions between the fetch execution state and the instruction execution state. In the fetch execution state, the instruction to be executed is acquired. Specifically, an instruction to read the address indicated by the PC 102 is issued to the direct bus access control unit 105, and the read result returned from the direct bus access control unit 105 is stored in the lower IR 1031 and then set to the value of the PC 102. Add 2 to update. Here, the main state machine 101 is an example of a "state control unit".

If the acquired instruction is a 2-byte instruction, the fetch execution state is completed and the instruction execution state is entered. If the acquired instruction is a 4-byte instruction, the instruction to read the address indicated by the PC 102 is issued to the direct bus access control unit 105 again, and the read result returned from the direct bus access control unit 105 is sent to the IR upper 1032. After storage, 2 is added to the value of PPC102 to update. After that, the fetch execution state is completed and the instruction execution state is entered.

In the instruction execution state, an instruction execution instruction corresponding to the instruction acquired in the fetch execution state is issued to the instruction execution unit 1100, and an instruction completion notification from the instruction execution unit 1100 is awaited.

When the instruction completion notification is received, the instruction execution state is completed and the state transitions to the fetch execution state. In the present embodiment, the "instruction execution instruction" and the "instruction completion notification" are prepared as one signal for each instruction type. Further, in the present embodiment, since there are 13 types of instructions, there are 13 "instruction execution instructions" and 13 "instruction completion notifications".

The instruction execution unit 1100 executes 13 types of instructions corresponding to the sequencer 100. By combining these 13 types of instructions, the sequencer 100 can be operated as intended.

<Example of each instruction>
Next, the details of each instruction executed by the instruction execution unit 1100 will be described with reference to FIGS. 3 to 12.

(NOP instruction)
FIG. 3 is a diagram illustrating an example of a NOP (No Operation) instruction. The NOP instruction is a 2Bite size instruction.

A code 4'b0000 indicating a NOP instruction is set in bit [15:12]. Here, the notation of bit [15:12] represents the range of 4 bits from the 15th bit to the 12th bit in the instruction of 2Bite size. Further, the notation of 4'b0000 indicates that the 4-bit code is "0000" in binary. In the NOP instruction, the 4-bit code "0000" is set in the range of 4 bits from the 15th bit to the 12th bit.

This code 4'b0000 is an example of "identification information for identifying the type of execution instruction". When the code 4'b0000 is set, it is identified that the execution instruction is a NOP instruction. In the following, the same notation as above may be used, but the meaning of the notation is the same as that described above.

bit [11: 0] is unused and is ignored when the instruction is executed. When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b0000, an instruction execution signal is issued to the NOP instruction execution unit 1151. After receiving the instruction execution signal, the NOP instruction execution unit 1151 issues an instruction completion notification.

(GR operation command)
FIG. 4 is a diagram illustrating an example of a GR (General Register) operation command. The GR operation instruction is a 2Bite size instruction.

A code 4'b0001 indicating a GR operation instruction is set in bit [15:12]. The operation type is set in bit [11: 8]. The GR operation command execution unit 1101 executes a logical operation or a substitution process of the operation data [7: 0] and the current GR 104 data [7: 0] according to the setting of the operation type, and updates the value of the GR 104. For example, the GR operation command execution unit 1101 executes the following operations for each value of the operation type setting [3: 0].

When the operation type setting [3: 0] = 4'h0, the GR operation command execution unit 1101 rewrites the value of GR104 to the value of the action data [7: 0].

Further, when the operation type setting [3: 0] = 4'h2, the GR operation command execution unit 1101 rewrites the value of GR 104 to the value obtained by logically inverting the current GR 104. For example, h55 is rewritten to hAA.

Further, when the operation type setting [3: 0] = 4'h3, the GR operation command execution unit 1101 rewrites the value of GR 104 to the output value of the input terminal state detection unit 107.

Further, when the operation type setting [3: 0] = 4'hA, the GR operation command execution unit 1101 rewrites the GR104 value to the logical product of the current GR104 value and the action data [7: 0].

Further, when the operation type setting [3: 0] = 4'hB, the GR operation command execution unit 1101 rewrites the GR104 value to the logical sum of the current GR1044 value and the action data [7: 0].

Further, when the operation type setting [3: 0] = 4'hC, the GR operation command execution unit 1101 rewrites the GR104 value to the exclusive OR of the current GR104 value and the action data [7: 0]. ..

Further, when the main state machine 101 transitions to the instruction execution state, the GR operation instruction execution unit 1101 refers to the GR operation instruction execution unit 1101 if the bit [15:12] of the IR lower 1031 is 4'b0001. , An instruction execution signal is issued.

The GR operation command execution unit 1101 issues a command completion notification after the rewriting of the GR 104 is completed.

In the above example, as a variation of the operation type setting [3: 0], the setting for executing the numerical calculation is not provided. However, for example, when the operation type setting [3: 0] = 4'hF, the value of GR104 is set. It is also possible to add a variation that can be rewritten by the addition result of the current GR104 value and the action data [7: 0]. As a result, the sequencer 100 can easily perform an operation of continuously accessing a specific memory area while increasing the access address by a constant value like the general-purpose DMAC 24.

(Output terminal control command)
FIG. 5 is a diagram illustrating an example of an output terminal control command. The output terminal control instruction is a 2Bite size instruction.

A code 4'b1000 indicating an output terminal control command is set in bit [15:12]. The operation type is set in bit [11: 8].

The output terminal control command execution unit 1141 executes a logical operation or a substitution process of the action data [7: 0] and the current output terminal data [7: 0] according to the operation type setting, and outputs the output terminal data [7: 0]. Update the value of.

Each 1 bit of the output terminal data [7: 0] corresponds to one output signal terminal of the sequencer 100. For example, the output terminal control command execution unit 1141 executes the following operations for each value of the operation type setting [3: 0].

When the operation type setting [3: 0] = 4'h0, the output terminal control command execution unit 1141 rewrites the value of the output terminal data to the value of the action data [7: 0].

Further, when the operation type setting [3: 0] = 4'hA, the output terminal control command execution unit 1141 logically sets the value of the output terminal data to the value of the current output terminal data and the action data [7: 0]. Rewrite as a product.

Further, when the operation type setting [3: 0] = 4'hB, the output terminal control command execution unit 1141 logically sets the value of the output terminal data to the value of the current output terminal data and the action data [7: 0]. Rewrite to sum.

Further, when the operation type setting [3: 0] = 4'hD, the output terminal control command execution unit 1141 rewrites the value of the output terminal data to the logical product of the current value of the output terminal data and the value of GR104.

Further, when the operation type setting [3: 0] = 4'hD, the output terminal control command execution unit 1141 rewrites the value of the output terminal data to the logical sum of the value of the current output terminal data and the value of GR104.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1000, an instruction execution signal is issued to the output terminal control instruction execution unit 1141. The output terminal control command execution unit 1141 issues an instruction completion notification after the rewriting of the output terminal data is completed.

(Direct bus transfer command)
Next, FIG. 6 is a diagram illustrating an example of a direct bus transfer instruction and a local bus transfer instruction. Each of the direct bus transfer instruction and the local bus transfer instruction is a 2-byte size instruction.

When writing to a direct bus connection device, the code 4'b0110 is set in bit [15:12]. When reading from a direct bus connection device, code 4'b0111 is set in bit [15:12].

When writing to a local bus connection device, the code 4'b0100 is set in bit [15:12]. When reading from a direct bus connection device, code 4'b0101 is set in bit [15:12]. An address to be accessed is set in bit [11: 0]. At the time of executing each instruction, data transfer is executed between the area specified by the target address [11: 0] and GR104.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b0110, an instruction execution signal is issued to the direct bus write instruction execution unit 1131.

The direct bus write instruction execution unit 1131 issues a write instruction and a write target address to the direct bus access control unit 105. At this time, the value of GR104 is issued as the write data. After the write operation of the direct bus access control unit 105 is completed, the direct bus write instruction execution unit 1131 issues an instruction completion notification.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b0111, an instruction execution signal is issued to the direct bus read instruction execution unit 1132.

The direct bus read instruction execution unit 1132 issues a read instruction and a read target address to the direct bus access control unit 105. When the direct bus read instruction execution unit 1132 receives the read data from the direct bus access control unit 105, the direct bus read instruction execution unit 1132 stores the received read data in the GR 104 and issues an instruction completion notification.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b0100, an instruction execution signal is issued to the local bus write instruction execution unit 1133.

The local bus write instruction execution unit 1133 issues a write instruction and a write target address to the local bus access control unit 106. At this time, the value of GR104 is issued as the write data. After the write operation of the local bus access control unit 106 is completed, the local bus write instruction execution unit 1133 issues an instruction completion notification.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b0111, an instruction execution signal is issued to the local bus read instruction execution unit 1134.

The local bus read instruction execution unit 1134 issues a read instruction and a read target address to the local bus access control unit 106. When the local bus read instruction execution unit 1134 receives the read data from the local bus access control unit 106, the local bus read instruction execution unit 1134 stores the received read data in the GR 104 and issues an instruction completion notification.

(Forced jump command)
FIG. 7 is a diagram illustrating an example of a forced jump instruction. The forced jump instruction is a 2Bite size instruction. Code 4'b1100 is set in bit [15:12]. The jump destination address is set in bit [11: 0].

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1100, an instruction execution signal is issued to the forced jump instruction execution unit 1121.

The forced jump instruction execution unit 1121 issues an instruction completion notification after rewriting the value of the PC 102 to the jump destination address.

(Repeat jump command)
FIG. 8 is a diagram illustrating an example of a repetitive jump instruction. The repeat jump instruction is a 4-byte size instruction. Code 4'b1101 is set in the lower bit [15:12]. The lower bit [11: 8] is used to specify whether the value to be loaded as the initial value of the repetition counter is the value of the lower bit [7: 0] of this instruction or GR104. This lower bit [11: 8] is an example of the “acquisition destination designation unit”.

The number of repetitions is set in the lower bit [7: 0]. When the value of GR104 is used as the number of repetitions, this bit is ignored. The address of the jump destination is set in the upper bit [11: 0]. This lower bit [7: 0] is an example of the "number of times designation unit".

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1101, an instruction execution signal is issued to the repetitive jump instruction execution unit 1122.

When the value of the load destination selection bit [3: 0] is 4'b0000 when the instruction execution signal is received for the first time, the repeat jump instruction execution unit 1122 sets the lower bit of the repeat jump instruction as the initial value of the repeat count counter [3: 0]. When the value of 7: 0] is set and the value of the load destination selection bit [3: 0] is 4'b0001, the value of GR104 is set as the initial value of the repetition count counter. Here, the repeat jump instruction execution unit 1122 is an example of the “repetition jump execution unit”.

After setting the initial value of the counter, the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this instruction. After rewriting the PC 102, the counter value is subtracted by 1 and the instruction completion notification is issued.

The repetitive jump instruction execution unit 1122 determines the repetitive counter value at the time of receiving the second and subsequent instruction execution signals, and if the repetitive counter value is not zero, sets the value of the PC 102 at the upper level [11: 0] of this instruction. Rewrite to the jump destination address to be performed. After rewriting the PC 102, the counter value is subtracted by 1 to issue an instruction completion notification. If the repeat counter value is zero, an instruction completion notification is issued without executing anything. Further, the value of PC102 is rewritten by adding 4 which is a value corresponding to the data size of the repeatedly jump execution instruction to the value of PC102.

(GR branch jump instruction)
FIG. 9 is a diagram illustrating an example of a GR branch jump instruction. The GR branch jump instruction is a 4-byte size instruction. Code 4'b1110 is set in the lower bit [15:12]. A branch condition is set in the lower bit [11: 8]. The jump destination address is set in the high-order bit [11: 0]. In the lower bit [7: 0], data for selecting (designating) the bit to be determined from the GR 104 is set at the time of jump determination.

Of each bit of the GR determination target bit selection [7: 0], the bit of GR 104 corresponding to the bit position set to "1" is the determination target. For example, if the value of the GR determination target bit selection [7: 0] is 8'b10101010, the jump determination is executed using the 4 bits of bits [7] [5] 3] [1] of GR104.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1110, an instruction execution signal is issued to the GR branch jump instruction execution unit 1123. The GR branch jump instruction execution unit 1123 changes the determination operation as follows depending on the value of the branch condition setting of the lower bit [11: 8] of this instruction.

When the value of the branch condition setting is 4'b1000, it is determined that the branch condition is satisfied when the GR determination target bit selection [7: 0] and the value of GR104 completely match, and the value of PC102 is higher than this instruction [7: 0]. It is rewritten to the jump destination address set at 11: 0]. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0100, it is determined that the branch condition is satisfied when all the target bits of the GR 104 bits set as the judgment target by the GR judgment target bit selection [7: 0] are "1". Then, the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0101, the branch condition is satisfied when at least one or more bits of the GR 104 bits set as the judgment target by the GR judgment target bit selection [7: 0] are "1". Is determined, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0110, it is determined that the branch condition is satisfied when all the target bits of the GR 104 bits set as the judgment target by the GR judgment target bit selection [7: 0] are "0". , The value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0111, the branch condition is satisfied when at least one or more bits of the GR 104 bits set as the judgment target by the GR judgment target bit selection [7: 0] are "0". Is determined, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b1001, it is determined that the branch condition is satisfied when the GR determination target bit selection [7: 0] and the value of GR104 do not match, and the value of PC102 is the higher rank [11] of this instruction. : 0] is rewritten to the jump destination address set. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without doing anything.

(Input terminal branch jump instruction)
FIG. 10 is a diagram illustrating an example of an input terminal branch jump instruction. The input terminal branch jump instruction is a 4-byte size instruction. Code 4'b1111 is set in the lower bit [15:12]. A branch condition is set in the lower bit [11: 8]. The jump destination address is set in the high-order bit [11: 0]. In the lower bit [7: 0], data for selecting (designating) the bit to be determined from the outputs of the input terminal state detection unit 107 at the time of jump determination is set. Of each bit of the input terminal determination target bit selection [7: 0], the output bit of the input terminal state detection unit 107 corresponding to the bit position set to “1” is the determination target.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1111, an instruction execution signal is issued to the input terminal branch jump instruction execution unit 1124. .. The determination operation of the input terminal branch jump instruction execution unit 1124 changes as follows depending on the value of the branch condition setting of the lower bit [11: 8] of this instruction.

When the value of the branch condition setting is 4'b1000, it is determined that the branch condition is satisfied when the input terminal determination target bit selection [7: 0] and the output of the input terminal state detection unit 107 completely match, and the value of the PC 102. Is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0100, when all the target bits of the output bits of the input terminal state detection unit 107 set as the judgment target by the input terminal determination target bit selection [7: 0] are "1". It is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0101, at least one or more of the output bits of the input terminal state detection unit 107 set as the determination target by the input terminal determination target bit selection [7: 0] is "1". In the case of ", it is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this instruction. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0110, when all the target bits of the output bits of the input terminal state detection unit 107 set as the judgment target by the input terminal determination target bit selection [7: 0] are "0". It is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b0111, at least one or more of the output bits of the input terminal state detection unit 107 set as the determination target by the input terminal determination target bit selection [7: 0] is "0". In the case of "", it is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

When the value of the branch condition setting is 4'b1001, it is determined that the branch condition is satisfied when the input terminal determination target bit selection [7: 0] and the output of the input terminal state detection unit 107 do not match, and the value of the PC 102 is set. It is rewritten to the jump destination address set at the upper level [11: 0] of this command. After rewriting the PC 102, an instruction completion notification is issued. If the branch condition is not satisfied, the instruction completion notification is issued without executing anything.

(Input terminal polling command)
FIG. 11 is a diagram illustrating an example of an input terminal polling instruction. The input terminal polling instruction is a 2-byte size instruction. Code 4'b1010 is set in bit [15:12]. A polling end condition is set in bit [11: 8]. This bit [11: 8] is an example of the polling end condition designation unit, and the data set in the bit [11: 8] is an example of "logical operation designation data".

In bit [7: 0], data for selecting (designating) a bit to be determined from the outputs of the input terminal state detection unit 107 at the time of polling end determination is set. Of each bit of the input terminal determination target bit selection [7: 0], the output bit of the input terminal state detection unit 107 corresponding to the bit position set to “1” is the determination target. Here, the data set in this bit [7: 0] is an example of "instruction-attached data".

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1010, an instruction execution signal is issued to the input terminal polling instruction execution unit 1111. The input terminal polling instruction execution unit 1111 changes the determination operation as follows depending on the value of the end condition setting of bit [11: 8] of this instruction. Here, the input terminal polling instruction execution unit 1111 is an example of the “polling execution unit”.

When the value of the end condition setting is 4'b1000, it is determined that the polling end condition is satisfied when the value of the input terminal determination target bit selection [7: 0] and the output bit of the input terminal state detection unit 107 completely match. Is executed, and an instruction completion notification is issued without executing anything.

If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0100, when all the target bits of the output bits of the input terminal state detection unit 107 set as the judgment target by the input terminal determination target bit selection [7: 0] are "1". It is judged that the end condition is satisfied, and the instruction completion notification is issued without executing anything.

If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0101, at least one or more of the output bits of the input terminal state detection unit 107 set as the determination target by the input terminal determination target bit selection [7: 0] is "1". In the case of "", it is determined that the end condition is satisfied, and the instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0101, all of the output bits of the input terminal state detection unit 107 set as the judgment target by the input terminal judgment target bit selection [7: 0] are "0". It is judged that the end condition is satisfied, and the instruction completion notification is issued without executing anything.

If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0111, at least one or more of the output bits of the input terminal state detection unit 107 set as the determination target by the input terminal determination target bit selection [7: 0] is "0". In the case of "", it is determined that the end condition is satisfied, and the instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b1001, it is determined that the end condition is satisfied when the input terminal determination target bit selection [7: 0] and the output of the input terminal state detection unit 107 do not match, and nothing is executed. An order completion notification is issued without any notice. If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

(Address space polling instruction)
FIG. 12 is a diagram illustrating an example of an address space polling instruction. The address space polling instruction is a 4-byte size instruction. Code 4'b1011 is set in the lower bit [15:12]. The end condition is set in the lower bit [11: 8]. The read target address to be polled is set in the upper bit [11: 0]. In the lower bit [7: 0], data for selecting (designating) the bit to be determined from the read results of the polling target address at the time of polling end determination is set. Of each bit of the read result determination target bit selection [7: 0], the read result bit corresponding to the bit position set to "1" is the determination target.

When the main state machine 101 transitions to the instruction execution state, if the bit [15:12] of the IR lower 1031 is 4'b1011, an instruction execution signal is issued to the address space polling instruction execution unit 1112.

Upon receiving the instruction execution signal, the address space polling instruction execution unit 1112 issues a read instruction and a read target address to the local bus access control unit 106. When the address space polling instruction execution unit 1112 receives the read data from the local bus access control unit 106, the address space polling instruction execution unit 1112 stores the received read data in the dedicated polling result register [7: 0]. The end and / or continuation of the polling operation is determined using the value of the polling result register and the value of the end condition setting. Here, the address space polling instruction execution unit 1112 is an example of the “polling execution unit”.

The address space polling instruction execution unit 1112 changes the determination operation as follows depending on the value of the end condition setting of the lower bit [11: 8] of this instruction.

When the value of the end condition setting is 4'b1000, it is determined that the polling end condition is satisfied when the read result determination target bit selection [7: 0] and the value of the polling result register [7: 0] completely match. , An instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, the value of PC102 is subtracted from "4" and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0100, all the target bits of the polling result register [7: 0] set as the judgment target by the read result judgment target bit selection [7: 0] are "1". In the case of, it is determined that the polling end condition is satisfied, and an instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "4" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0101, at least one or more bits of each bit of the polling result register [7: 0] set as the judgment target by the read result judgment target bit selection [7: 0] are selected. If it is "1", it is determined that the polling end condition is satisfied, and an instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "4" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0110, all the target bits of the polling result register [7: 0] set as the judgment target by the read result judgment target bit selection [7: 0] are "0". In the case of, it is determined that the polling end condition is satisfied, and an instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "4" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b0111, at least one or more bits of each bit of the polling result register [7: 0] set as the judgment target by the read result judgment target bit selection [7: 0] are selected. If it is "0", it is determined that the polling end condition is satisfied, and an instruction completion notification is issued without executing anything. If the polling end condition is not satisfied, "4" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

When the value of the end condition setting is 4'b1001, it is judged that the end condition is satisfied and nothing is executed when the values of the read result judgment target bit selection [7: 0] and the polling result register [7: 0] do not match. The order completion notification is issued without being issued. If the polling end condition is not satisfied, "4" is subtracted from the value of PC102 and returned, and then the instruction completion notification is issued, so that this instruction is executed again.

<Example of address space allocation>
Next, FIG. 13 is a diagram showing an example of the address space allocation of ASIC1 according to the present embodiment.

Registers for various settings and / or controls of the main CPU 21 are assigned to the main CPU control register area 210, and are accessible from the main CPU 21 and the sub CPU 22, but not accessible from the sequencer 100.

Further, the sub CPU control register area 220 is assigned various setting and / or control registers of the sub CPU 22, and can be accessed from the main CPU 21 and the sub CPU 22, but cannot be accessed from the sequencer 100.

Further, the DDR controller control register area 230 is assigned various setting and / or control registers of the DDR controller 23, and can be accessed from the main CPU 21 and the sub CPU 22, but cannot be accessed from the sequencer 100.

Further, the general-purpose DMAC control register area 240 is assigned various setting and / or control registers of the general-purpose DMAC 24, and can be accessed from the main CPU 21 and the sub CPU 22, but cannot be accessed from the sequencer 100.

Further, the storage control register area 250 is assigned various setting and / or control registers of the storage control unit 25, and can be accessed from the main CPU 21 and the sub CPU 22, but cannot be accessed from the sequencer 100.

Further, the DDR memory area 500 is assigned an address for reading and / or writing to the DDR memory 50, and can be accessed from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the storage control unit 25, but from the sequencer 100. Is inaccessible.

Further, the legacy device control register area 900 is assigned various setting and / or control registers of the legacy device control unit 10, and is basically accessible from the main CPU 21, the sub CPU 22, and the sequencer 100. There is also an area that cannot be accessed from the main CPU 21 and the sub CPU 22, such as the ROM area 914.

Further, the general-purpose DMAC 24 can access the FIFO write area 9161 and the FIFO read area 9162.

Further, the diversion module control register area 911 is assigned various setting and / or control registers of the diversion module 11, and can be accessed from the main CPU 21, the sub CPU 22, and the sequencer 100.

Further, the sequencer control register area 917 is assigned a control register 17 for various settings and / or controls of the sequencer 100, and can be accessed from the main CPU 21, the sub CPU 22, and the sequencer 100.

The ROM area 914 for the sequencer is allocated the ROM 14 for storing the operation program of the sequencer 100, and can be accessed only from the sequencer 100.

After the reset is released, the sequencer 100 starts the fetch operation from the address 0x2000, which is the start address of the ROM 14. However, by providing the boot device selection bit of the sequencer 100 in a part of the registers of the sequencer control register area 917, the first fetch address after the reset is released becomes the address 0x3000 which is the start address of the work area for the sequencer. It is also possible to configure the hardware in.

Specifically, the reset signal for the sequencer 100 and the reset signal in the sequencer control register area are separated, and the initial value of the PC 102 after the reset release of the sequencer 100 is set to either 0x200 or 0x300 depending on the value of the boot device selection bit. Make it selectable.

The operation of the sequencer 100 can be defined by arranging the various instructions described with reference to FIGS. 3 to 12 in the ROM area 914 for the sequencer and the work area 915 for the sequencer. Further, a jump instruction to the sequencer work area 915 is arranged in a part of the sequencer ROM area 914, and the main CPU 21, the sub CPU 22, or the general-purpose DMAC 24 is set in the sequencer work area before the reset release of the sequencer 100 is released. By describing the sequencer operation program in 915, the operation of the sequencer 100 can be dynamically changed to some extent.

The program described in the work area 915 for the sequencer is stored in the non-volatile external storage 40, expanded in the DDR memory area 500 by the storage control unit 25, and then the work for the sequencer is used by the main CPU 21, the sub CPU 22, or the general-purpose DMAC 24. Transferred to region 915.

The work area 915 for the sequencer is an area for storing the operation program and data of the sequencer 100, and can be accessed from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the sequencer 100.

The FIFO write area 9161 is allocated from 0x900 to 0x9FF as the address space, but when there is a write in this range, the data to the FIFO 16 is assigned in order from the earliest in time regardless of the address. The stuffing is performed. The FIFO write area 9161 is accessible from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the sequencer 100.

The FIFO read area 9162 is allocated from 0xA00 to 0xAFF as the address space, but when there is a read in this range, the FIFO 16 is ordered from the data stored earlier in time regardless of the address. Data is read from. The FIFO read area 9162 can be accessed from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the sequencer 100.

By executing data transfer between the main CPU 21, the sub CPU 22, or the general-purpose DMAC 24 and the sequencer 100 via the FIFA 16, the sequencer 100 can omit the calculation of the memory access address.

<Operation example of sequencer 100>
Next, the operation of the sequencer 100 will be described with reference to FIG. FIG. 14 is a flowchart showing an example of the operation of the sequencer 100.

First, in step S141, the sequencer 100 detects the sequencer execution signal assertion in response to the input terminal polling instruction “16'hA401”. The input terminal polling instruction is stored at the address 0x500 in the ROM area 914 for the sequencer.

When "1" is written to the sequencer execution start bit in which the main CPU 21 or the sub CPU 22 is mounted as one of the control registers 17, the sequencer execution signal becomes "1". The sequencer execution signal is output from the control register 17 and is input to the terminal corresponding to bit0 of the input terminal state detection unit 107 of the sequencer 100. The input terminal polling instruction "16'hA401" is an instruction to execute polling until bit0 of the input terminal state detection unit 107 becomes "1".

If the sequencer execution signal assertion is detected in step S141 (step S141, Yes), the operation proceeds to step S142, and if it is not detected (step S141, No), the operation of step S141 is repeated.

Subsequently, in step S142, the sequencer 100 executes 32 times of repetitive processing execution in response to the repetitive jump instruction "32'h0600_D020". The repeat jump instruction is stored at the address 0x502 in the ROM area 914 for the sequencer.

When the repeat jump instruction is executed for the first time, the value 8'h20 of the instruction bit [7: 0] is loaded as the number of repetitions, and when the repeat jump instruction is executed for the second time or later, 8'h20 to "1" is executed each time. Is subtracted.

If the number of repetitions is not zero, the value of PC102 is rewritten at address 0x600, and if the number of repetitions is zero, the value of PC102 is rewritten to address 0x506 (add "4" to the storage address 0x5022 of the repeat jump instruction). ..

Subsequently, in step S143, the sequencer 100 determines whether or not it is the final round of repetition.

If it is determined in step S143 that it is not the final round of repetition (step S143, No), in step S145, the sequencer 100 responds to the address space polling instruction "32'h0020_B480" to prepare for data transfer of 1 BYTE. Detect completion.

The address space polling instruction is stored at the address 0x600 in the ROM area 914 for the sequencer. In the address space polling instruction, the polling operation is continued until the bit [7] of the address 0x020 in the diversion module control register area 911 becomes "1".

The bit [7] at the address 0x020 indicates that the data transmitted by the legacy device 30 can be received and the data can be retrieved from the diversion module 11. When the bit [7] of the address 0x200 becomes "1", "4" is added to the value of PC102, and the polling operation ends.

If the completion of the data transfer preparation of 1Byte is not detected in step S145 (step S145, No), the operation of step S145 is repeated, and if it is detected (step S145, Yes), the operation proceeds to step S146.

Subsequently, in step S146, the sequencer 100 executes the reading of the transmission register of the diversion module 11 in response to the local bus read instruction "16'h5040". The local bus read instruction is stored at the address 0x604 in the ROM area 914 for the sequencer. By this instruction, the data at the address 0x040 in the diversion module control register area 911 is stored in the GR 104.

Subsequently, in step S147, the sequencer 100 executes the write of the read result to the FIFA 16 in response to the local bus write instruction "16'h4900". The local bus write instruction is stored at the address 0x606 in the ROM area 914 for the sequencer. The data stored in the GR 104 is written to the FIFO write area 9161 by the local bus write instruction.

Subsequently, in step S148, the sequencer 100 executes a jump to the storage address in response to the repetitive jump instruction "16'hC502". The repeat jump instruction is stored at the address 0x608 in the ROM area 914 for the sequencer. The value of PC102 is rewritten to 0x502 by the repeated jump instruction.

On the other hand, if it is determined in step S143 that it is the final round of repetition (step S143, Yes), in step S144, the sequencer 100 responds to the output terminal control instruction "16'h8B01" and outputs a completion signal. Perform an assert. The output terminal control instruction is stored at the address 0x506 in the ROM area 914 for the sequencer.

The output terminal control command sets the level of the signal line corresponding to bit [0] of the output terminal control command execution unit 1141 to "1". This signal line is connected to bit [0] of a register indicating the completion of the sequencer 100 in the control register 17, and the level of the signal line can be detected from the main CPU 21 and the sub CPU 22 by reading the register. Further, by using the completion signal as an interrupt factor of the main CPU 21 or the sub CPU 22, it is possible to notify the completion of the sequencer 100.

In this way, the sequencer 100 can operate.

Here, FIG. 15 is a diagram illustrating an example of the ROM area 914 for the sequencer in the operation example of FIG. The operation shown in FIG. 14 can be realized if the capacity of the ROM area 914 for the sequencer is 18 bytes. Not limited to the example of FIG. 14, the operation of the sequencer 100 can be defined by the contents described in the ROM area 914 for the sequencer.

<Action and effect of sequencer 100>
Conventionally, there is known a technique of executing a specific process by using a dedicated state machine or a sub CPU instead of the main CPU. In recent years, there is a tendency to reduce costs by realizing a function realized by a plurality of chips as a SoC (System on Chip) on a single chip.

In this case, it is desirable that the circuit used in the existing chip such as a legacy device can be used as it is in the new SoC, but the I / F (Interface) of the existing chip has a long bus occupancy time and one access. When the control of the existing chip part becomes a constraint on the system due to the complexity of the software of the main CPU, etc. because it takes time or the protocol is complicated to save the circuit even a little. There is.

It is conceivable to solve this constraint by using a dedicated sub CPU or a dedicated state machine that controls the existing chip, but the method using the dedicated state machine requires a large amount of development man-hours. In some cases, the man-hours required to deal with changes in specifications may increase.

Further, in the method using the sub CPU, when the required processing content is simple, the sub CPU is provided with excessive functions such as a numerical calculation unit, an interrupt processing unit, and a cache, so that the circuit scale is unnecessarily increased. There is. Further, since it is necessary to prepare a software development environment for the sub CPU, the man-hours may be less than those for developing a dedicated state machine, but it may take more man-hours to master and maintain the development environment.

On the other hand, in order to suppress an increase in the circuit scale, a sequencer replaces the CPU and ROM configurations of a general-purpose microcomputer with a sequencer. Further, in order to improve the efficiency of programming work, a method of mutual conversion between a programming language for motion control and a programming language for sequence control is disclosed.

However, in a configuration in which the CPU and ROM configurations of a general-purpose microcomputer are replaced with a sequencer, the configuration of the general-purpose microcomputer is inherited by the arithmetic unit and register structure, so that the circuit scale may become unnecessarily large when the functions of the general-purpose microcomputer are excessive. .. Further, in the method of mutually converting the motion control programming language and the sequence control programming language, since the method of reducing the circuit scale is not disclosed, it is not possible to suppress the increase in the circuit scale.

On the other hand, in the present embodiment, the ASIC 1 includes a ROM 14 that stores an execution instruction group including a plurality of execution instructions, and a sequencer 100 that executes an operation in response to the read execution instruction. The sequencer 100 is an input terminal. It includes a polling instruction execution unit 1111, an address space polling instruction execution unit 1112, and a repeat jump instruction execution unit 1122.

By providing the sequencer 100 that executes the sequence control, it is not necessary to mount the numerical calculation circuit and the interrupt processing circuit on the ASIC1, and it is possible to suppress the increase in the circuit scale of the ASIC1 by that amount.

Further, the polling performed by the input terminal poll command execution unit 1111 and the address space poll command execution unit 1112 and the repeated jump performed by the repeat jump command execution unit 1122 are performed by an analog front-end device for a facsimile modem or a dedicated image processing device. This is an operation that frequently occurs in the control of the legacy device 30 such as.

In the present embodiment, these operations can be performed in response to one polling execution instruction or one repetitive jump instruction, and a complicated execution instruction by a program or the like is not required. As a result, software can be efficiently developed in assembler language without using a development environment such as a compiler.

Further, in the present embodiment, the polling execution instruction includes identification information for identifying the type of the execution instruction and a polling end condition specifying unit for specifying the end condition of the polling operation, and the ASIC1 inputs the information acquired in the polling operation. It is equipped with an input terminal. This enables polling at the input terminal level, and the sequencer 100 can be controlled by using a signal directly connected to the sequencer 100.

Further, in the present embodiment, the polling execution instruction performs a logical calculation on the identification information for identifying the type of the execution instruction, the polling end condition specification unit for specifying the end condition of the polling operation, and the polling target data indicating the polling target. The input terminal polling instruction execution unit 1111 and the address space polling instruction execution unit 1112, including the instruction attachment data for the purpose, lead and poll the address space included in the ASIC1. As a result, even when the diversion module 11 does not have an interrupt signal, the operation equivalent to the interrupt function can be realized by polling the interrupt flag register.

Further, in the present embodiment, the polling end condition designation unit includes the logical operation designation data for designating one of the plurality of logical operation types. This makes it possible to flexibly set the polling end condition.

Further, in the present embodiment, the polling end condition specification unit corresponds to the fact that all the bits of the polling target and the instruction-attached data match, that at least one bit of the polling target and the instruction-attached data are different, and that the instruction-attached data is 1. All bits of the poll target data at the bit position are 1, that at least 1 bit of the poll target data at the bit position corresponding to 1 of the instruction attached data is 1, and it corresponds to 1 of the instruction attached data. It is specified that all the bits of the data to be polled at the bit position are 0, or at least 1 bit 0 of the data to be polled at the bit position corresponding to 1 of the instruction attached data. This makes it possible to flexibly set the polling end condition.

Further, in the present embodiment, the repeat jump execution instruction includes identification information for identifying the type of execution instruction, a jump destination address in the PC 102, and a number designation unit for designating the number of repeat jumps, and the repeat jump instruction execution unit 1122 After executing the repeated jumps for the number of repeated jumps, the value corresponding to the data size of the repeated jump execution instruction is added to the PC 102. Thereby, the number of repetitions can be set by the same instruction.

Further, in the present embodiment, the repetitive jump execution instruction includes identification information for identifying the type of the execution instruction and the jump destination address in the PC 102, and the repetitive jump instruction execution unit 1122 jumps for the number of repetitive jumps acquired from the GR 104. After the execution of is completed, the value corresponding to the data size of the repeated jump execution instruction is added to the PC 102. As a result, the number of repetitions can be set by the value read from other registers.

Further, in the present embodiment, the repeat jump execution instruction specifies identification information for identifying the type of execution instruction, a jump destination address in the PC 102, a number designation unit for specifying the number of repeat jumps, and an acquisition destination for the number of repeat jumps. The repeat jump command execution unit 1122, including the acquisition destination designation unit, acquires the number of repeated jumps from the acquisition destination of the number of repeated jumps. This makes it possible to flexibly set the number of repetitions.

Further, in the present embodiment, the main CPU 21, the sub CPU 22, and the DDR memory 50 are provided, and the accessible address range of the sequencer 100 in the DDR memory 50 is the accessible address range of the main CPU 21 and the sub CPU 22 in the DDR memory 50. Narrower than. As a result, the circuit scale of the sequencer 100 can be reduced.

Further, in the present embodiment, a FIFA 16 for data transfer between the sequencer 100 and the main CPU 21 and the sub CPU 22 is provided. As a result, even if the sequencer 100 does not have an address calculation function, a large amount of data can be transferred, and the circuit scale of the sequencer 100 can be reduced by the amount of the calculation function.

[Other Embodiments]
In the first embodiment, the ASIC1 including the sequencer 100 has been described as an example of the system, but the system is not limited to the ASIC1. The system may be a device including the sequencer 100 or ASIC1. This device includes MFPs (Multifunction Peripheral Product Printers), PJs (Projectors), IWBs (Interactive White Boards), output devices such as digital signage, and HUDs (HUDs). Head Up Display) devices, industrial machines, imaging devices, sound collectors, medical devices, network home appliances, automobiles (Connected Cars), notebook PCs (Personal Computers), mobile phones, smartphones, tablet terminals, game machines, PDA (Personal Digital) Assistant), digital cameras, wearable PCs, desktop PCs, etc.

Although the embodiments have been described above, the present invention is not limited to the above-described embodiments specifically disclosed, and various modifications and changes can be made without departing from the scope of claims. ..

1 ASIC (example of system)
14 ROM (an example of storage unit)
16 FIFO (an example of first-in first-out section)
21 Main CPU (example of processor)
22 Sub CPU (example of processor)
100 sequencer (an example of programmable sequencer)
101 Main state machine (example of state control unit)
102 PC (an example of storage position storage unit)
104 GR (Example of execution storage unit)
1031 IR lower level (example of command storage unit)
1032 IR upper level (an example of instruction storage unit)
1100 Instruction execution unit 1111 Input terminal Polling instruction execution unit (an example of polling execution unit)
1112 Address space polling instruction execution unit (example of polling execution unit)
1122 Repeated jump instruction execution unit (example of repeated jump execution unit)

Japanese Unexamined Patent Publication No. 2007-23390 JP-A-2002-073120

Claims (14)

A storage unit that stores a group of execution instructions including multiple execution instructions,
A programmable sequencer that executes an operation in response to the read execution instruction is provided.
The programmable sequencer is a system including at least one of a polling execution unit that executes a polling operation in response to a polling execution instruction and a repetitive jump execution unit that executes a repetitive jump operation in response to a repetitive jump execution instruction. The system according to claim 1, wherein the polling execution unit executes the polling operation in response to one polling execution instruction. The system according to claim 1 or 2, wherein the repetitive jump execution unit executes the repetitive jump operation in response to one repetitive jump execution command. The polling execution instruction includes identification information for identifying the type of the execution instruction and a polling end condition specifying unit for designating the end condition of the polling operation.
The system according to any one of claims 1 to 3, further comprising an input terminal for inputting information acquired by the polling operation. The polling execution instruction is an instruction for performing a logical operation on the identification information that identifies the type of the execution instruction, the polling end condition specification unit that specifies the end condition of the polling operation, and the polling target data indicating the polling target. Including attached data,
The system according to any one of claims 1 to 4, wherein the polling execution unit leads and polls the address space included in the system. The system according to claim 4 or 5, wherein the polling end condition designation unit includes logical operation designation data for designating one of a plurality of logical operation types. The polling end condition designation unit is
That all the bits of the polling target and the data attached to the instruction match.
At least one bit of the polling target and the data attached to the instruction are different.
All bits of the polling target data at the bit position corresponding to 1 of the instruction attached data are 1.
At least one bit of the polling target data at the bit position corresponding to 1 of the instruction attached data is 1.
All bits of the polling target data at the bit position corresponding to 1 of the instruction attached data are 0.
The system according to claim 6, wherein at least one of the polling target data is at least 1 bit 0 at a bit position corresponding to 1 of the instruction attachment data. The programmable sequencer is
A storage position storage unit that stores the storage position of the execution instruction to be executed most recently from the storage unit in the storage unit, and a storage position storage unit.
A state control unit that reads the execution instruction from the storage unit and updates the storage position stored in the storage position storage unit based on the storage position.
An instruction storage unit that stores the execution instruction read by the state control unit,
An instruction execution unit that executes an operation in response to the execution instruction stored in the instruction storage unit,
The system according to any one of claims 1 to 7, further comprising an execution storage unit that is written or read when the operation of the instruction execution unit is executed. The repetitive jump execution instruction includes identification information for identifying the type of the execution instruction, a jump destination address in the storage position storage unit, and a number of times designation unit for designating the number of repetitive jumps.
The system according to claim 8, wherein the repetitive jump execution unit executes the repetitive jump for the number of repetitive jumps, and then adds a value corresponding to the data size of the repetitive jump execution instruction to the storage position storage unit. .. The repetitive jump execution instruction includes identification information for identifying the type of the execution instruction and a jump destination address in the storage position storage unit.
The claim that the repetitive jump execution unit adds a value corresponding to the data size of the repetitive jump execution instruction to the storage position storage unit after the execution of the jump for the number of repetitive jumps acquired from the execution storage unit is completed. 8. Or 9, the system according to 9. The repeat jump execution instruction specifies identification information for identifying the type of the execution instruction, a jump destination address in the storage position storage unit, a number designation unit for specifying the number of repeat jumps, and an acquisition destination for the repeat jump count. Including the acquisition destination designation part and
The system according to any one of claims 8 to 10, wherein the repeated jump execution unit acquires the number of repeated jumps from the acquisition destination of the number of repeated jumps. With the processor
With memory,
The system according to any one of claims 1 to 11, wherein the accessible address range of the programmable sequencer in the memory is narrower than the accessible address range of the processor in the memory. 12. The system of claim 12, further comprising a first-in, first-out section for data transfer between the programmable sequencer and the processor. A storage position storage unit that stores the storage position of the execution instruction to be executed most recently from the storage unit that stores the execution instruction group including a plurality of execution instructions in the storage unit.
A state control unit that reads the execution instruction from the storage unit and updates the storage position stored in the storage position storage unit based on the storage position.
An instruction storage unit that stores the execution instruction read by the state control unit,
An instruction execution unit that executes an operation in response to the execution instruction stored in the instruction storage unit,
A pluggable sequencer including an execution storage unit that is written or read when the operation of the instruction execution unit is executed.

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