JP2021080505A - Production method of circuit board, and circuit board - Google Patents

Abstract

To provide a production method of a circuit board in which a bottom-up deposition can be achieved even when a large-area opening portion, where a bottom-up deposition cannot be achieved, is included in an insulation resin layer, and to provide a production method of a circuit board in which a dissimilar metal is arranged as a stopper layer in order to avoid a dishing where an electrolytic plating layer is recessed more than its surrounding insulation resin layer due to a CMP process with reference to a large-area land portion, via portion, trench circuit, etc.SOLUTION: An electrolytic copper plating is performed by covering part of the recess portion, which can be a via portion 3 etc., using a plating resist 5. After that, by peeling the plating resist, a bottom-up deposition can be achieved by having the recess portion be an area composed of a small-area recess portion, and thus the thickness of the copper plating to be deposited on the surface can be suppressed. Furthermore, a dishing in CMP can be suppressed by plating the recess portion with a dissimilar metal as a stopper layer having an appropriate thickness.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for manufacturing a wiring board.

Generally, a wiring board is configured by laminating a plurality of metal wiring layers formed on an insulating layer, thereby realizing high-density wiring in a limited area. As a method of electrically connecting the wiring layers formed in these different layers, a method of making a hole (via) in the insulating layer between the wiring layers of the upper layer and the lower layer, filling the insulation layer with a conductor, and connecting the wiring layers. Has been taken.

As a method of filling the conductor, there are a method of coating the conductor only on the side wall of the via (conformal method) and a method of filling the inside of the via with a conductor (filling method). In both methods, the method of filling the conductor includes a plating method and a method of printing a conductor paste, but a plating method is generally used and is formed at the same time as wiring.

The advantage of the conformal method is that the plating can be completed in a short time because it is not necessary to fill the inside of the via. On the other hand, the disadvantage is that it is necessary to embed an insulating resin in the cavity to ensure reliability.
The merit of the filling method is that there are no cavities because the inside of the via is completely filled by plating, which is advantageous in terms of reliability. The disadvantage is that there is a tendency for the plating film thickness to differ between the via and the part without vias. Therefore, unevenness is likely to occur on the surface, and there is a concern in terms of reliability when the wiring layer is multi-layered.

Due to these characteristics, it is customary to use the conformal method in the part where the via is large and it takes time to plate, and to perform the filling method in the part where the via is small. However, in the part where the via is small, the wiring is often fine, and unevenness is formed due to the large difference in plating film thickness between the via part and the surface layer part. There is a concern that reliability such as defects will decrease.

Therefore, in order to suppress the variation in film thickness due to the filling method, for example, as disclosed in Patent Document 1 and Patent Document 2, plating precipitation of the via portion is promoted (bottom-up), and the surface of the wiring board is surfaced. Additives for electrolytic copper plating (also called filling plating) for via filling that suppresses plating precipitation have been developed and used.

The filling plating additive exerts its effect mainly by the liquid flow, and exerts a promoting effect in the via part where the chemical liquid tends to stagnate. That is, the plating deposition on the surface is suppressed by exerting the suppressing effect on the surface of the wiring board having a strong liquid flow. On the other hand, in the via portion, the plating is thickly deposited. Therefore, while the via portion is filled with plating, the plating on the surface of the wiring board becomes thin, so that the finish becomes flat.

However, when the opening area of the via (part) becomes large, a liquid flow difference is less likely to occur between the inside of the via and the surface, and the above-mentioned bottom-up effect is reduced.
FIG. 5 shows a cross section of the via portion 3 when electrolytic copper plating is performed on the via portion 3 having a via diameter of 10 micrometer for 20 minutes in an electrolytic copper plating bath using an electrolytic copper plating additive for via filling. It is a photograph. It can be confirmed that the via portion 3 has copper, which is the electrolytic plating layer 30, deposited bottom-up by plating, the via portion 3 is filled with plating, and the surface 8 is relatively flat.

On the other hand, in FIG. 6, in the electrolytic copper plating bath using the same electrolytic copper plating additive for via filling as in FIG. 5, the via portion 3'with a via diameter of 20 micrometer is plated under the same conditions as in FIG. It is a cross-sectional photograph of the via portion 3 at the time of plating. In the electrolytic plating layer 30', bottom-up precipitation at the via portion 3'cannot be confirmed, and the plating thickness of the bottom of the surface 8 and the via portion 3'is almost the same. Therefore, plating having almost the same thickness is deposited following the shape of the via portion 3', and a large dent is formed on the plating surface of the via portion 3'.

FIG. 4 is an explanatory view schematically showing a cross section of the electrolytic plating layer 30'shown in FIG. 6 without bottom-up precipitation. Although it cannot be confirmed in FIG. 6, as shown in FIG. 4, the seed layer 4 is formed on the base of the electrolytic plating layer 30'.

On the other hand, there is a damascene method as one of the methods for forming fine wiring. In the damascene method, by removing the part where the wiring of the insulating resin layer is provided by laser or photolithography, recesses such as vias, lands, and trench wiring are provided, and the area including the recesses is plated to metal. After filling with, unnecessary metal is removed from the plated surface by polishing the electrolytic plating layer on the surface and via (or recess) by CMP (Chemical Mechanical Polishing), and the recess (or via) is removed. ) Is a method of forming a wiring layer or the like from the electrolytic plating layer remaining in), and is mainly used in the semiconductor field.

In this CMP step, the thinner the plating metal deposited on the insulating resin layer, the more time and cost required for the CMP step can be reduced. Therefore, as much as possible, the plating metal deposited on the surface 8 of the substrate (see FIG. 5) can be reduced. It is important to make it thinner.

By using the above-mentioned electrolytic copper plating additive for via filling, the plating precipitation inside the trench wiring and vias is prioritized, and the plating precipitation on the surface of the substrate is suppressed to reduce the load of the CMP process. It becomes possible to lower it.

However, as described above, if there is even one large opening in the via portion, land portion, or trench wiring, the plating does not deposit from the bottom up in that portion. Therefore, in order to fill the via portion with plating, plating is performed. Will be deposited thick enough. As a result, the plating is thickly deposited on the surface of the substrate (see FIG. 4), and it is necessary to polish a large amount of copper in the CMP process, which increases the time required for manufacturing and thus increases the cost load. There is a problem that it ends up.

JP-A-2019-52374 Japanese Unexamined Patent Publication No. 2010-255088

In order to solve the above problems, the present invention provides a method for manufacturing a wiring board capable of bottom-up deposition even when the insulating resin layer contains a large-area opening that does not deposit bottom-up. Make it an issue.

Further, a method for manufacturing a wiring board capable of avoiding dishing in which the plating layer in the opening forming a via portion having a large area that does not deposit from the bottom up becomes lower than the surface of the surrounding insulating resin layer due to the CMP process and is dented. The challenge is to provide.

In order to solve the above problems, in the plating method of the present invention, a land portion or a via portion having a large area that does not deposit bottom-up or a part of a trench wiring is shielded by a plating resist to create a region having a small plating area. By enabling bottom-up precipitation and suppressing the thickness of the copper plating deposited on the surface of the substrate, it is possible to suppress the load of the CMP process.

The invention according to claim 1 of the present invention is a method for manufacturing a wiring board having one or more wiring layers.
The process of forming one wiring layer is
The process of forming an insulating resin layer on the substrate and
A process of providing a first opening for forming a wiring pattern in the insulating resin layer, and
A step of forming a seed layer on the surface of the insulating resin layer provided with the opening and the bottom surface of the first opening, and
A step of providing a plating resist layer on the seed layer in the first opening, and
A process of providing a second opening for forming a wiring pattern in the plating resist layer, and
The process of forming the first electrolytic plating layer on the seed layer and
The process of removing the plating resist layer and
The process of forming the second electrolytic plating layer on the seed layer and the first electrolytic plating layer, and
A step of exposing the insulating resin layer by means of flattening the second electrolytic plating layer while removing it from the surface and making the upper surface of the insulating resin layer and the remaining upper surface of the second electrolytic plating layer flush with each other is provided. And
The minimum opening dimension of the first opening is 20 micrometers, and the distance A between the inner surface of the first opening and the second opening and the distance B between the second openings are less than 20 micrometers.
The depth of the second opening is shallower than the distance A and the distance B, which is a method for manufacturing a wiring board.

The wiring board according to claim 1, wherein the means for flattening the second plating layer while removing it from the surface is chemical mechanical polishing. It is a manufacturing method of.

The invention according to claim 3 of the present invention is the invention according to claim 1 or 2, wherein the electroplating is performed at least once using different electroplating bath compositions or different plating conditions. This is a method for manufacturing a wiring board.

The invention according to claim 4 of the present invention is a wiring board in which one or more wiring layers in which a wiring pattern is arranged at an opening of an insulating resin layer are laminated on the substrate.
The wiring pattern of the wiring layer is that of the opening formed in the insulating resin layer.
Inside, a seed layer, a first conductive layer formed on the seed layer, and a second conductive layer formed on the seed layer and the first conductive layer are provided.
It has an insulating resin layer on the outside.
The upper surface of the insulating resin layer and the upper surface of the second conductive layer are provided flush with each other.
The minimum opening size of the opening is 20 micrometers
The minimum dimension of the inner surface of the opening and the area surrounded by the first conductive layer is less than 20 micrometers.
The height of the first conductive layer is lower than the minimum dimension of the region, which is a wiring board.

Further, in the invention according to claim 5 of the present invention, the first conductive layer is either copper or a copper alloy or nickel or a nickel alloy, and the second conductive layer is copper or a copper alloy. The wiring board according to claim 4, which is a feature.

According to the method for manufacturing a wiring board of the present invention, the plating thickness of the substrate surface layer is suppressed even in a substrate having a large area trench wiring where bottom-up precipitation cannot be performed or a recess having a wiring pattern such as a via portion or a land portion. This makes it possible to realize bottom-up precipitation of plating.

Further, according to the wiring board of the present invention, a recess having a large area of trench wiring or a via or land portion where bottom-up precipitation cannot be performed and a recess having a small area wiring pattern capable of bottom-up deposition can be obtained. And, even if they are mixed, bottom-up precipitation is performed in all the recesses, and the upper surface of the electrolytic plating layer inside the recesses and the upper surface of the insulating resin layer outside the recesses are flush with each other. Is possible.

The cross-sectional explanatory view explaining an example of the manufacturing method of the wiring board of this invention. The cross-sectional explanatory view explaining an example of the wiring board of this invention. The cross-sectional explanatory view which shows the manufacturing method of the wiring board in the Example of this invention. A cross-sectional explanatory view of electrolytic plating without bottom-up precipitation. A cross-sectional photograph of bottom-up deposited electrolytic plating in a via portion having a diameter of 10 micrometers. A cross-sectional photograph of electrolytic plating with no bottom-up precipitation in a via portion with a diameter of 20 micrometers.

<Manufacturing method of wiring board>
Hereinafter, embodiments of the method for manufacturing a wiring board of the present invention will be described.
The method for manufacturing a wiring board of the present invention is a method for manufacturing a wiring board having one or more wiring layers, and the step of forming one layer of the wiring board includes the following steps.
(1) Step of Forming an Insulating Resin Layer on a Substrate Here, the substrate may be a substrate made of an insulating resin or a wiring layer made of a conductor formed on the insulating resin layer. ..
(2) Step of Providing First Opening for Forming Wiring Pattern in Insulating Resin Layer The first opening is a recess for forming a via portion, a land portion, a trench wiring, and the like.
(3) Step of forming a seed layer on the surface of the insulating resin layer provided with the opening and the bottom surface of the first opening The seed layer is a thin film layer formed on the surface of the substrate or the insulating resin layer to impart conductivity. is there. For example, a metal thin film such as copper formed by using a sputtering method or a vacuum vapor deposition method, a chemical copper plating film, or the like.
(4) Step of Providing a Plating Resist Layer on the Seed Layer in the First Opening The plating resist layer is for forming a plating mask pattern to be performed before electrolytic plating is performed on the seed layer. In the case of a non-photosensitive plating resist layer, there are a method of forming a plating mask pattern by screen printing and a method of forming a plating mask pattern by removing a desired portion by irradiating a laser beam. In the case of a photosensitive plating resist layer, a plating mask pattern is formed through exposure and development steps. The material of the plating resist layer is not particularly limited as long as it can withstand the electrolytic plating bath. For example, when the electrolytic plating bath is a copper sulfate plating bath, it is acidic, so any acid-resistant material may be used, and ordinary dry film resists and various liquid resists can be used.
(5) Step of providing a second opening for forming a wiring pattern in the plating resist layer Here, the wiring pattern refers to a via portion, a land portion, a trench wiring, and the like. A second opening is provided as a recess in the insulating resin layer for forming the components of these wirings.
(6) Step of Forming First Electroplating Layer on Seed Layer An electrolytic plating layer is formed over the entire surface of the seed layer, such as above the insulating resin layer and at the bottom of the second opening. As the first electrolytic plating layer, in addition to copper plating, a plating layer that is harder than copper plating and difficult to polish may be used. For example, nickel plating can be preferably used.
(7) Step of Removing the Plating Resist Layer The plating resist layer can be peeled off by using a stripping solution dedicated to the plating resist to be used or a stripping solution having a function equivalent thereto.
(8) Step of Forming Second Electrolytic Plating Layer on Seed Layer and First Electroplating Layer As the second electrolytic plating layer, an electrolytic copper plating layer having high conductivity can be preferably used.
(9) A step of exposing the insulating resin layer by a means for flattening the second electrolytic plating layer while removing it from the surface so that the upper surface of the insulating resin layer and the remaining upper surface of the second electrolytic plating layer are flush with each other. 2 As a means for uniformly removing the electrolytic plating layer from the surface, CMP (Chemical Mechanical Polishing, chemical mechanical polishing) can be preferably used. In CMP, in addition to the mechanical polishing action of the abrasive grains, the surface chemical action of the abrasive grains or the action of the chemical components contained in the slurry enhances the mechanical polishing action, resulting in high-speed and smooth polishing. It is possible to do. It may be mechanical polishing using abrasive grains instead of CMP.

In the method for manufacturing a wiring substrate of the present invention, the minimum opening dimension of the first opening is 20 micrometers, the distance A between the inner surface of the first opening and the second opening, and the second opening. The distance B between the parts is less than 20 micrometers, and the depth of the second opening is shallower than the distance A and the distance B.

When the minimum opening dimension of the first opening exceeds 20 micrometers, bottom-up precipitation does not occur even in an electrolytic plating bath using an electrolytic copper plating additive for via filling. Even with such a large opening, a structure by plating is formed inside the first opening by the first electrolytic plating, and the structure is as if the minimum opening size is less than 20 micrometers. As a result, bottom-up precipitation is possible in the second electrolytic plating.

Further, even under the above conditions, if the depth of the first opening is too deep, the first opening cannot be filled with electrolytic plating due to bottom-up precipitation. Therefore, flattening is possible by making the depth of the second opening shallower than the distance A and the distance B.

As described above, one wiring layer was obtained on the substrate 1. Further, by repeating the same process from the formation of the insulating resin layer, a wiring board provided with the multilayer wiring can be manufactured.

Hereinafter, the method for manufacturing the wiring board of the present invention will be described in more detail with reference to FIG.
FIG. 1A schematically shows a cross section of the via portion 3 before performing electrolytic plating.
First, the insulating resin layer 2 is formed on the substrate 1.
Next, a state is shown in which a first opening 6 that becomes a via 3 is provided by removing a part of the portion, and then a seed layer 4 that enables electrolytic plating is formed on the surface. Here, the via portion 3 has a minimum opening size of 20 micrometers or more, and is large enough to prevent bottom-up precipitation of electrolytic plating. Further, the via portion 3 may be a land portion or a trench wiring. A case where the via portion is used as a typical example will be described.

FIG. 1B is formed by forming a plating resist 5 on the seed layer 4 of FIG. 1A and then removing a part of the plating resist 5 inside the first opening 6. It shows a state in which the second opening 7 and the shielding portion 91 in which the plating resist 5 remains are formed. The shielding portion 91 formed in the central portion of the first opening 6 is a region that also serves as a narrow region 92. Further, the plating resist 5 in the shielding portion 91 sandwiched between the first opening 6 and the peripheral edge of the first opening 6 is also a region forming the narrow region 92.

FIG. 1 (c) shows a state in which the plating resist 5 is removed after electrolytic plating is performed in the state of FIG. 1 (b).
A first electrolytic plating layer 31 is formed in the second opening 7. An opening is formed between the two first electrolytic plating layers 31 and between the first electrolytic plating layer 31 and the inner side surface of the first opening 6 after the plating resist 5 is removed. This opening will be referred to as a narrow region 92. By setting the minimum value of the opening size of these narrow regions 92 to less than 20 micrometers, it becomes a region where bottom-up precipitation of electrolytic plating is possible.

When the shielding portion 91 is formed by the plating resist 5 in order to provide the narrow region 92 (see FIG. 1 (b)), the shape may be various, such as a striped shape, a lattice shape, a round shape, and a concentric circle shape. , The via portion, the land portion, and the trench wiring can be selected according to the shape, but it is important that the minimum value of the opening dimension of the opening of the narrow region 92 is less than 20 micrometers. By doing so, bottom-up precipitation becomes possible when performing electrolytic plating.

FIG. 1 (d) shows a state in which the second electrolytic plating layer 32 is formed by performing electrolytic plating in the state of FIG. 1 (c). At the time of electrolytic plating in the second electrolytic plating layer 32, electrolytic plating is performed on the seed layer 4 outside the first opening 6, that is, in the surface layer portion of the wiring board 100. Further, inside the first opening 6, electrolytic plating is performed on the surface of the first electrolytic plating layer 31 and the surface of the seed layer 4. At that time, since bottom-up precipitation occurs in the narrow region 92 of FIG. 1C, the height of the electrolytic plating deposited in the narrow region 92 and the electrolytic plating deposited on the crown of the first electrolytic plating layer 31 are included. The height is the same as the height, which is flattened, and the filled via plating in the via 3 is performed.

Further, the plating process is not limited to one side of the substrate 1 (see FIG. 1A), but both sides can be processed at the same time. Further, the substrate 1 is provided with vias on the substrate itself, and when filling the vias, the substrate 1 can be plated. It is also possible to apply the plating method of the present invention.

Further, the first plating (plating forming the first electrolytic plating layer 31) and the second plating (plating forming the second electrolytic plating layer 32) can have different chemical composition and plating conditions. For example, by forming the first electrolytic plating layer 31 with electrolytic nickel plating and the second electrolytic plating layer 32 with electrolytic copper plating, when the CMP process is performed thereafter, the electrolytic nickel plating is more difficult to polish, so excessive polishing is performed. Can be suppressed and dishing can be avoided.

It is also possible to change the size of the metal crystal and change the stress applied to the substrate by changing the current density under the first plating condition and the second plating condition.

<Wiring board>
Next, the wiring board of the present invention will be described with reference to FIG.
The wiring board 100 of the present invention is a wiring board in which one or more wiring layers in which a wiring pattern is arranged in an opening 3 of an insulating resin layer 2 formed on the substrate 1 are laminated. FIG. 2 is an explanatory cross-sectional view illustrating by enlarging the opening 3 of the wiring board 100 in which only one wiring layer is formed. here,
The wiring pattern includes all wiring components such as a via portion, a land portion, and a trench wiring, and they are formed in the opening 3.

The wiring pattern of the wiring layer is formed on the seed layer 4, the first conductive layer 10 formed on the seed layer 4, and the first conductive layer 10 inside the opening 3 formed in the insulating resin layer 2. The formed second conductive layer 20 and the like are provided.

Further, an insulating resin layer 4 is provided on the outside of the opening 3 formed in the insulating resin layer 4. The insulating resin layer 4 is removed by a removing means such as CMP that flattens the seed layer 4 and the second electrolytic plating layer 32 (see FIG. 1D) formed on the seed layer 4 while removing the seed layer 4 from the surface thereof. It is exposed by this. A wiring pattern can be formed by removing up to the seed layer 4.

Further, the upper surface of the insulating resin layer 4 and the upper surface of the second conductive layer 20 are provided flush with each other.
By removing the second electrolytic plating layer 32 from the state of FIG. 1D by using a means for flattening the second electrolytic plating layer 32 while removing it from the surface thereof, the state of the wiring board 100 of FIG. 2, that is, the outside of the opening 3. The upper surface of the insulating resin layer 4 and the upper surface of the second conductive layer 20 obtained by polishing the second electrolytic plating layer 32 inside the opening 3 are provided flush with each other.

The minimum opening dimension of the opening 3 is 20 micrometers. That is, the method of the present invention is applied to a large opening in which the opening size of the opening 3 is 20 micrometers or more and the electrolytic plating does not deposit bottom-up.

Further, the minimum dimension of the narrow region 92 surrounded by the inner surface of the opening 3 and the first conductive layer 10 is less than 20 micrometers. By satisfying this condition, bottom-up precipitation occurs during plating of the second electrolytic plating layer 32.

Further, the height of the first conductive layer 10 is made lower than the minimum dimension of the narrow region 92. This does not mean that bottom-up precipitation can be realized simply by setting the minimum dimension of the narrow region 92 to less than 20 macrometers. For example, when the opening 3 is a through hole, when the aspect ratio of the through hole (length of the through hole / diameter of the hole) becomes large, the electrolytic plating becomes thin at the central portion in the length direction of the through hole. Similar to this phenomenon, even if the minimum opening dimension of the opening 3 is 10 micrometers, if the opening is very deep, electroplating itself cannot be performed. In the present invention, the depth of the narrow region 92 where normal electroplating can be performed is defined as the height of the first electroplating 31 (see FIG. 1C), that is, the height of the first conductive layer 10 (FIG. 2). (See) needs to be lower than the minimum dimension of the narrow region 92.

By doing so, as shown in FIG. 1D, it is possible to form the second electrolytic plating layer 32 having substantially the same thickness on the inside and the side of the opening 3. Further, the second electrolytic plating layer 32 is polished from the surface to the seed layer 4 by polishing with CMP or the like to further flatten the surface, while exposing the underlying insulating resin layer 2 on the outside of the opening 3. Inside the opening 3, the second conductive layer 20 is flush with the upper surface of the insulating resin layer 2, and the wiring board 100 of the present invention can be obtained.

<Example 1>
Hereinafter, examples will be described with reference to FIG. In FIG. 3, the case where the opening 3 is the via portion 3 will be described.
First, a silicon substrate was prepared and used as the substrate 1. Photosensitive polyimide to be the insulating resin layer 2 is applied to this so as to have a thickness of 6 micrometers, and a via portion 3 having a square opening with a side of 1 mm is formed by photolithography, and the via portion is formed on the insulating resin layer 2 and the via portion. A seed layer 4 of a copper thin film was formed on the side wall and the bottom of No. 3 by a sputtering method.
Next, the plating resist 5 was applied to the via portion 3 to form a narrow region 92 by photolithography (FIG. 3 (a)).

FIG. 3 (b) shows a top view of FIG. 3 (a). The narrow region 92 was formed so as to have a shape having a length of 1 mm and a width of 10 micrometers in the longitudinal direction.

Next, the first electrolytic plating layer 31 was formed by plating with electrolytic copper plating until the plating thickness became 4 micrometers. After that, the plating resist 5 was peeled off (FIG. 3 (c)).

Next, the second electrolytic plating layer 32 was formed again by electrolytic copper plating so that the surface thickness was 2 micrometers. At this time, the portion covered with the plating resist 5 (see FIG. 3A) became a narrow region 92, so that the plating could be deposited bottom-up. As a result, it was possible to fill the inside of the via 3 with a depth of 6 micrometers by plating while suppressing the plating thickness on the substrate surface to 2 micrometers (FIG. 3 (d)). By performing CMP after this, unnecessary copper on the surface of the substrate could be removed, and a wiring board having a via portion 3 having an opening of 1 mm on a side as a filled via could be formed (see FIG. 2).

<Comparative example 1>
A silicon substrate was prepared and used as the substrate 1. Photosensitive polyimide to be the insulating resin layer 2 is applied to this so as to have a thickness of 6 micrometers, and a via portion 3 having a square opening with a side of 1 mm is formed by photolithography, and then the thickness is obtained by one plating. An electrolytic copper plating layer of 6 micrometers was formed, and the via portion 3 was filled. Since the via portion 3 is a large region of 1 mm square that does not cause bottom-up precipitation, it is necessary to perform thickness plating of the insulating resin layer (here, 6 micrometers). Therefore, the filling was completed by depositing a plating of 6 micrometers on the via portion 3, but the plating thickness of the surface other than the via portion 3 was as thick as 6 micrometers, and the tact time was long in the CMP process.

1 ... Substrate 2 ... Insulating resin layer 3, 3'... (becomes via part or land part or trench wiring) Opening 4 ... Seed layer 5 ... Plating resist 6 ... 1 Opening 7 ... Second opening 8 ... Surface 10 (of the wiring board) ... First conductive layer 20 ... Second conductive layer 30, 30'... Electroplating layer 31 ... First electrolytic plating layer 32 ... Second electrolytic plating layer 91 ... Shielding portion 92 ... Narrow area 100, 100'... Wiring board

Claims (5)

A method for manufacturing a wiring board having one or more wiring layers.
The process of forming one wiring layer is
The process of forming an insulating resin layer on the substrate and
A process of providing a first opening for forming a wiring pattern in the insulating resin layer, and
A step of forming a seed layer on the surface of the insulating resin layer provided with the opening and the bottom surface of the first opening, and
A step of providing a plating resist layer on the seed layer in the first opening, and
A process of providing a second opening for forming a wiring pattern in the plating resist layer, and
The process of forming the first electrolytic plating layer on the seed layer and
The process of removing the plating resist layer and
The process of forming the second electrolytic plating layer on the seed layer and the first electrolytic plating layer, and
A step of exposing the insulating resin layer by means of flattening the second electrolytic plating layer while removing it from the surface and making the upper surface of the insulating resin layer and the remaining upper surface of the second electrolytic plating layer flush with each other is provided. And
The minimum opening dimension of the first opening is 20 micrometers, and the distance A between the inner surface of the first opening and the second opening and the distance B between the second openings are less than 20 micrometers.
A method for manufacturing a wiring board, wherein the depth of the second opening is shallower than the distance A and the distance B. The method for manufacturing a wiring board according to claim 1, wherein the means for uniformly removing the second plating layer from the surface is chemical mechanical polishing. The method for manufacturing a wiring board according to claim 1 or 2, wherein the electroplating is performed at least once using different electroplating bath compositions or different plating conditions. A wiring board in which one or more wiring layers in which a wiring pattern is arranged at an opening of an insulating resin layer are laminated on the substrate.
The wiring pattern of the wiring layer is that of the opening formed in the insulating resin layer.
Inside, a seed layer, a first conductive layer formed on the seed layer, and a second conductive layer formed on the seed layer and the first conductive layer are provided.
It has an insulating resin layer on the outside.
The upper surface of the insulating resin layer and the upper surface of the second conductive layer are provided flush with each other.
The minimum opening size of the opening is 20 micrometers
The minimum dimension of the inner surface of the opening and the area surrounded by the first conductive layer is less than 20 micrometers.
A wiring board characterized in that the height of the first conductive layer is lower than the minimum dimension of the region. The wiring substrate according to claim 4, wherein the first conductive layer is either copper or a copper alloy or nickel or a nickel alloy, and the second conductive layer is copper or a copper alloy.

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