JP2023181069A - wiring board - Google Patents

Abstract

To provide a wiring board which is less likely to cause breakage of a wire.SOLUTION: The wiring board of the present invention includes an insulation layer 101, and a conductor layer 102 including a wire EW formed on the insulation layer 101. The wire EW includes a first region WA1 and a second region WA2 with different wire thicknesses. A wire width in the second region WA2 is smaller than that in the first region WA1. A wire thickness in the second region WA2 is smaller than that in the first region WA1.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board.

In the method for manufacturing a wiring board disclosed in Patent Document 1, the upper surface of an electrolytic copper plating layer constituting a wiring conductor is polished to make the thickness of the wiring conductor uniform.

JP2003-258410A

In the wiring board manufactured by the manufacturing method disclosed in Patent Document 1, the thickness of the wiring conductor is made constant by polishing regardless of the density or pattern width of the wiring conductor. When the width of the wiring is relatively small, it is considered that the risk of wire breakage increases as the thickness of the wiring decreases.

The wiring board of the present invention includes an insulating layer and a conductor layer including wiring formed on the insulating layer. The wiring includes a first region and a second region having different wiring thicknesses, the wiring width in the second region is smaller than the wiring width in the first region, and the wiring width in the second region is smaller than the wiring width in the first region. The wiring thickness in the region is greater than the wiring thickness in the first region.

According to an embodiment of the present invention, in a region (second region) where the wiring width is relatively small in the same wiring, the wiring thickness is smaller than in a region (first region) where the wiring width is relatively large. big. It is thought that the risk of wire breakage in a region where the wiring width is relatively small can be reduced.

FIG. 1 is a plan view showing an example of a wiring board according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 2 is a sectional view taken along line BB in FIG. 1. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment. FIG. 1 is a diagram showing an example of a method for manufacturing a wiring board according to an embodiment.

A wiring board according to an embodiment of the present invention will be explained with reference to the drawings. The drawings referred to hereinafter are not intended to show exact proportions of each component, but are drawn so that the features of the present embodiment can be easily understood.

FIG. 1 shows a plan view of a wiring board that is an example of a wiring board according to an embodiment. 2A shows a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B shows a cross-sectional view taken along line BB in FIG. Note that the plan view shown in FIG. 1 and the cross-sectional views shown in FIGS. 2A and 2B represent arbitrary layers that the wiring board of the embodiment should have among the plurality of insulating layers and conductor layers that the wiring board of the embodiment may have. A portion of one conductor layer 102 and insulating layer 101 is shown. An additional insulating layer may be laminated on the opposite side of the conductor layer 102 from the insulating layer 101. Further, an additional conductor layer may be formed on the side of the insulating layer 101 opposite to the conductor layer 102.

Note that in the description of the wiring board of this embodiment, the side on which the conductor layer 102 is formed in the thickness direction of the insulating layer 101 is referred to as "upper" or "upper side", and the side on which the conductor layer 102 is formed is referred to as "upper" or "upper side". The opposite side is referred to as the "bottom" or "lower side."

The insulating layer 101 is, for example, an arbitrary insulating layer among a plurality of insulating layers that can constitute a wiring board in the form of a so-called build-up wiring board, and may be formed using, for example, epoxy resin. The insulating layer 101 may be formed using an insulating resin such as bismaleimide triazine resin (BT resin) or phenol resin, for example. The insulating layer 101 may contain a reinforcing material (core material) such as glass fiber and/or an inorganic filler such as silica or alumina.

The conductor layer 102 formed on the insulating layer 101 may be formed using any metal such as copper or nickel. The conductor layer 102 may be made of, for example, a metal foil such as a copper foil, and/or a metal film formed by plating, sputtering, or the like. In the illustrated example, the conductor layer 102 formed on the surface of the insulating layer 101 includes an electroless plated film layer 102n (preferably an electroless copper plating film) and an electrolytic plated film layer 102e (preferably an electrolytic copper plating film). ) has a two-layer structure. However, the structure of the conductor layer 102 is not limited to the two-layer structure of the electroless plated film layer 102n and the electrolytic plated film layer 102e. The conductor layer 102 may have a layer structure of three or more layers including a metal foil layer, an electroless plated film layer, and an electroplated film layer.

The conductor layer 102 included in the wiring board of the embodiment is patterned to have wiring EW as its conductor pattern. The three wires EW illustrated each have a plurality of regions with different wire widths in the length direction of the wire EW. Specifically, the wiring EW includes a first area WA1 having a relatively large wiring width and a second area WA2 having a smaller wiring width than the first area WA1. The wiring width A1 in the first area WA1 is larger than the wiring width A2 in the second area WA2. Further, in the illustrated example, each of the plurality of wirings EW is adjacent to a so-called solid pattern BP included in the conductor layer 102 and extending in the planar direction (extending direction of the surface of the insulating layer 101).

2A shows a cross section along the wiring width direction of a portion of the wiring EW corresponding to the first area WA1, and FIG. 2B shows a cross section of the wiring EW corresponding to the second area WA2 in the wiring width direction. A cross section along is shown. As understood from the comparison between FIG. 2A and FIG. 2B, regarding the thickness of the wiring EW, the wiring thickness T2 in the second area WA2 is larger than the wiring thickness T1 in the first area WA1. That is, the wiring EW has a first area WA1 with a relatively large wiring width and a relatively small wiring thickness, and a second area WA2 with a relatively small wiring width and a relatively large wiring thickness. It has

The wiring width A2 of the second area WA2 is smaller than the wiring width A1 of the first area WA1, and the wiring thickness T2 of the second area WA2 is larger than the wiring thickness T1 of the first area WA1. In this way, by making the wiring thickness relatively large in the second area WA2 where the wiring width is relatively small, the possibility of disconnection of the wiring EW, especially in the second area WA2, is reduced. There may be cases where

For example, specifically, in the first region WA1 of the wiring EW, the wiring width may be formed to be approximately 12 μm to 95 μm, and the wiring thickness may be approximately 8 μm to 15 μm. On the other hand, in the second region WA2 of the wiring EW, the wiring width may be formed to be approximately 7 μm to 90 μm, and the wiring thickness may be approximately 12 μm to 18 μm.

By making the wiring thickness relatively large in the second area WA2 where the wiring width of the wiring EW is relatively small, it may be possible to suppress the degree of variation in resistance value within the same wiring EW to a small level. . That is, the degree of variation in the cross-sectional area (cross-sectional area) perpendicular to the length direction of the wire along the wire width direction within the same wire EW may be suppressed.

Specifically, the area of the cross section of the wiring EW perpendicular to the length direction of the wiring in the first area WA1 where the wiring width is relatively large, and the length of the wiring in the second area WA2 where the wiring width is relatively small. The difference with the area of the cross section perpendicular to the direction can be suppressed by adjusting the wiring thickness in each region. For example, when the wiring width A1 of the wiring EW in the first area WA1 is about 30 μm and the wiring width A2 of the second area WA2 is about 20 μm, the wiring thickness T1 of the wiring EW in the first area WA1 is may be approximately 10 μm, and the wiring thickness T2 in the second area WA2 may be approximately 15 μm.

Preferably, the area of a cross section along the wiring width direction in the first area WA1 and perpendicular to the wiring length direction and the area of the cross section perpendicular to the wiring length direction along the wiring width direction in the second area WA2. The cross-sectional area may be approximately constant. In other words, the electrical resistance value per unit length in the wiring length direction in the first area WA1 of the wiring EW and the electrical resistance value per unit length in the wiring length direction in the second area WA2 of the wiring EW. and may have approximately equal values. As described above, the relationship between the wiring width A1 and the wiring thickness T1 in the first area WA1 and the wiring width A2 and the wiring thickness T2 in the second area WA2 is adjusted, thereby reducing the risk of disconnection. It is possible to provide a wiring EW in which resistance value is reduced and variation in resistance value is suppressed.

Note that the degree of difference in conductor thickness within the conductor layer 102 is determined from the viewpoint of adhesion between a further insulating layer that may be coated on the conductor layer 102 and the insulating layer 101 exposed between the conductor layer 102 and the patterns of the conductor layer 102. Therefore, a smaller value may be desirable. Therefore, in the wiring EW, it may be desirable that the difference between the wiring thickness in the first area WA1 and the wiring thickness in the second area WA2 is 15 μm or less. Furthermore, the difference in wiring width within the same wiring EW (the difference between the wiring width in the first area WA1 and the wiring width in the second area WA2) can be adjusted while suppressing the change in resistance value within the same wiring. From the viewpoint of suppressing differences in wiring thickness, the thickness is preferably 30 μm or less, and more preferably 10 μm or less.

As will be described later in the description of the wiring board manufacturing method, in forming the conductor layer 102, the thickness of the wiring EW can be adjusted with relatively high precision by adjusting the amount of conductor to be formed around the wiring EW. It may be realized. Therefore, in the formed conductor layer 102, the amount of conductor present around the first region WA1 of the wiring EW may differ from the amount of conductor present around the second region WA2.

As shown in FIG. 1, a region is formed between the first region WA1 and the second region WA2, where the wiring width gradually decreases from the first region WA1 to the second region WA2. has been done. The region interposed between the first region WA1 and the second region WA2 and in which the wiring width gradually changes is referred to as a third region WA3. In the third area WA3, where the wiring width gradually decreases from the first area WA1 to the second area WA2, the wiring thickness decreases from the first area WA1 to the second area WA2. It is gradually increasing.

As described above, the area of the cross section perpendicular to the length direction of the wiring in the first region WA1 and the area of the cross section perpendicular to the length direction of the wire in the second region WA2 are approximately constant. Furthermore, the area of the cross section perpendicular to the length direction of the wiring in the third region WA3 can also be made substantially constant with the cross-sectional areas of the first region WA1 and the second region WA2.

In this case, in the third region WA3, as the wiring width gradually changes, the wiring thickness may gradually change so that the cross-sectional area becomes constant. Specifically, in the third area WA3, as the wiring width gradually decreases from the first area WA1 to the second area WA2, the wiring width decreases from the first area WA1 to the second area WA1. The interconnect thickness may gradually increase toward the region WA2 so that the cross-sectional area becomes constant. As a result, the electrical resistance value per unit length in the same wiring EW may be approximately constant.

The wiring board of the embodiment may be manufactured by any general wiring board manufacturing method. With reference to FIGS. 3A to 3H, a method for manufacturing a wiring board will be described using as an example the case where the conductor layer 102 on the insulating layer 101 of the wiring board shown in FIG. 1 is manufactured. Note that in the manufacturing method described below with reference to FIGS. 3A to 3H, a cross-sectional view of a portion of the wiring board corresponding to the insulating layer 101 and the conductive layer 102 is shown similarly to FIGS. 2A and 2B. In particular, the fabrication of the conductor layer 102 will be described.

First, as shown in FIG. 3A, a laminate in which the insulating layer 101 has been laminated is prepared. As the insulating layer 101, for example, a resin film containing an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenol resin may be used. A metal film layer 102n is formed entirely on one surface of the insulating layer 101. For example, the metal film layer 102n, which is an electroless copper plating film layer, is formed by electroless plating. The metal film layer 102n may be formed, for example, by sputtering using a target containing copper.

Next, as shown in FIG. 3B, a plating resist 102r for electrolytic plating is formed on the metal film layer 102n. For example, a plating resist 102r containing, for example, photosensitive polyhydroxy ether resin, epoxy resin, phenol resin, or polyimide resin is applied, for example, by spray coating or by applying a film, so as to cover the entire area on the metal film layer 102n. It is formed over the entire area by attaching, etc.

Next, as shown in FIGS. 3C and 3D, an opening is formed in the plating resist 102r. An opening is formed in the plating resist 102r in accordance with a conductor pattern (see FIG. 1) having the wiring EW and the solid pattern BP that the conductor layer 102 should have. Note that FIG. 3C and FIGS. 3E and 3G, which will be referred to later, show a portion corresponding to the cross section of the first area WA1 shown in FIG. 2A, which is referred to in the description of the wiring board of the embodiment. FIG. 3D and FIGS. 3F and 3H, which will be referred to later, show a portion corresponding to the cross section of the second area WA2 shown in FIG. 2B.

The openings in the plating resist 102r can be formed, for example, by exposure and development using a mask having an appropriate opening pattern. Specifically, an opening WO according to the pattern of the wiring EW to be formed and an opening PO according to the solid pattern BP to be formed are formed in the plating resist 102r.

As can be understood from a comparison between FIG. 3C and FIG. 3D, the opening width of the opening WO in the portion corresponding to the second area WA2 of the wiring EW to be formed is the same as that of the opening in the portion corresponding to the first area WA1. It is formed smaller than the opening width of the WO. The opening width of the opening WO in the portion corresponding to the second region WA2 of the wiring EW to be formed is approximately 7 μm to 90 μm, and the opening WO in the portion corresponding to the first region WA1 of the wiring EW to be formed is approximately 7 μm to 90 μm. The opening width can be formed to be about 12 μm to 95 μm.

The opening PO formed adjacent to the opening WO is determined by the ratio of the area of the openings WO and PO to the area of the area surrounding the opening WO in the portion corresponding to the first area WA1, and the second area. The openings WO and PO may be formed to have different ratios of area to the area of the area surrounding the opening WO in the portion corresponding to the area WA2.

The ratio of the area occupied by the openings WO and PO in the area around the opening WO corresponding to the second area WA2 is the ratio of the area occupied by the openings WO and PO in the area around the opening WO corresponding to the first area WA1. By forming the opening PO to be smaller than the above, the subsequent formation of the electrolytic plating layer 102e described with reference to FIGS. 3E and 3F can be successfully realized. Filling of the electrolytic plated layers 102e with different thicknesses into the openings WO as shown in FIGS. 3E and 3F may be achieved satisfactorily.

Next, as shown in FIGS. 3E and 3F, the openings WO and PO are filled with a conductor by electrolytic plating to form an electroplated layer 102e. By electrolytic plating using the metal film layer 102n as a seed layer, the inside of the opening WO of the plating resist 102r is filled with a conductor to form the electroplated layer 102e that constitutes the wiring EW, and the inside of the opening PO is filled with the conductor. Then, an electroplated layer 102e forming a solid pattern around the wiring EW is formed.

In forming the electrolytic plated layer 102e, as shown in FIGS. 3E and 3F, the electrolytic plated layer 102e in the portion corresponding to the second area WA2 of the wiring EW to be formed shown in FIG. The electrolytic plated layer 102e is formed to be thicker than the electroplated layer 102e in the portion corresponding to the first region WA1 of the wiring EW to be formed, as shown in FIG. As described above, when the ratio of the area occupied by the opening PO in the area around the opening WO is different, the thickness of the electroplated layer 102e formed in the opening WO and PO may be different. Specifically, by appropriately adjusting the electrolytic plating conditions (temperature, plating time, etc.) according to the current density distribution related to the arrangement of the openings WO and PO, the proportion occupied by the openings PO in the area around the openings WO can be reduced. An electroplated layer 102e having different thicknesses in different regions may be formed relatively well.

The wiring thickness (the thickness of the metal film layer 102n and the electrolytic plating layer 102e) of the wiring EW shown in FIG. 3E, which corresponds to the first area WA1, is such that the width of the opening WO (wiring width) is 12 μm to 95 μm. In some cases, it may be formed to have a thickness of 8 μm to 15 μm. In contrast, when the width of the opening WO is 7 μm to 90 μm, the wiring thickness of the wire EW shown in FIG. 3F corresponding to the second area WA2 is 12 μm to 18 μm. can be formed. In this way, since the wiring thickness relative to the wiring width can be adjusted, the cross-sectional areas of the wiring in the first region WA1 and the second region WA2 of the wiring EW to be formed may be adjusted to be approximately equal. .

Next, as shown in FIGS. 3G and 3H, the plating resist 102r is removed, and the metal film layer 102n exposed by the removal of the plating resist 102r is removed by etching. Formation of the conductor layer 102 including the wiring EW is completed. In manufacturing wiring boards, after the formation of conductor layer 102 is completed, optional additional insulating and conductor layers may be laminated on conductor layer 102.

The wiring board of the embodiment is not limited to one in which the conductor layer 102 of the wiring board has the illustrated structure and the structure, shape, and material exemplified in this specification. The wiring EW included in the conductor layer 102 has at least a first area WA1 with a relatively large wiring width and a relatively small wiring thickness, and a second area WA1 with a smaller wiring width and a larger wiring thickness than the first area WA1. It is sufficient if the area WA2 is included. The wiring EW may also include a fourth region having a wiring width and wiring thickness different from the first region WA1 and the second region WA2. Further, a via conductor connecting the conductor layer 102 and a conductor layer that may be formed on the opposite side to the conductor layer 102 may be formed in the insulating layer 101 included in the wiring board.

101 Insulating layer 102 Conductor layer 102n Metal film layer 102e Electrolytic plating layer 102r Plating resist EW Wiring BP Solid pattern WO, PO Opening WA1 First area WA2 Second area

Claims (6)

A wiring board comprising an insulating layer and a conductor layer including wiring formed on the insulating layer,
The wiring includes a first region and a second region having mutually different wiring thicknesses,
The wiring width in the second region is smaller than the wiring width in the first region,
The wiring thickness in the second region is greater than the wiring thickness in the first region. 2. The wiring board according to claim 1, wherein an area of a cross section perpendicular to the length direction of the wire in the first region, and an area of a cross section perpendicular to the length direction of the wire in the second region. are approximately equal. 2. The wiring board according to claim 1, wherein the wiring width in the second region is 90 μm or less, and the wiring thickness is 18 μm or more. The wiring board according to claim 1,
The wiring further includes a third region interposed between the first region and the second region,
The wiring width in the third region gradually decreases from the first region to the second region,
The wiring thickness in the third region gradually increases from the first region to the second region. 5. The wiring board according to claim 4, wherein: an area of a cross section along the wiring width direction in the first region, an area of a cross section along the wiring width direction in the second region, and the third region. The area of the cross section along the wiring width direction is approximately equal. The wiring board according to claim 1,
The difference between the wiring width in the first region and the wiring width in the second region is 10 μm or less,
The difference between the wiring thickness in the first region and the wiring thickness in the second region is 15 μm or less.

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