JP2021052159A - Semiconductor device and amplifier module - Google Patents

Abstract

To provide a semiconductor device that can suppress the increase in parasitic inductance of a collector wire connected to a plurality of transistor cells.SOLUTION: A semiconductor device includes a collector region, a base region, and an emitter region, each provided to a substrate, and two cell lines including a plurality of transistor cells that are arranged in parallel to each other. A plurality of collector extraction wires are connected to the collector region of the plurality of transistor cells and are extracted in a direction intersecting with the direction where the plurality of transistor cells are arranged. A collector bundling wire connects the plurality of collector extraction wires to each other. A collector intermediate bundling wire disposed between the two cell lines in a plan view connects the plurality of collector extraction wires respectively extracted from the plurality of transistor cells belonging to one of the two cell lines.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices and amplifier modules.

Heterojunction bipolar transistors (HBTs) are used in high frequency power amplifier circuits. In order to obtain high output, a plurality of transistor cells connected in parallel to the final stage amplifier circuit are used (for example, Patent Document 1 below). Each of the plurality of transistor cells of the amplifier circuit disclosed in Patent Document 1 has an emitter region that is long in one direction in a plan view. A plurality of transistor cells are arranged in the width direction of the emitter region to form a cell row. The amplifier circuit includes four cell rows arranged parallel to each other.

A collector wiring is arranged between two adjacent cell rows among the four cell rows, and the collector wiring is connected to the collectors of a plurality of transistor cells in the cell rows on both sides. A pad for connecting the collector to the module board or the like is arranged near one end of the four cell rows.

JP-A-2018-142688

In order to improve the performance of the amplifier circuit, it is preferable to suppress the increase in the parasitic inductance of the collector wiring. When a plurality of transistor cells are arranged in four rows and a collector pad is arranged near one end of the four cell rows, the collector wiring to the transistor cell arranged at the end far from the pad is arranged. The parasitic inductance increases.

An object of the present invention is to provide a semiconductor device capable of suppressing an increase in parasitic inductance of collector wiring connected to a plurality of transistor cells. Yet another object of the present invention is to provide an amplifier module including this semiconductor device.

According to one aspect of the invention
With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings connected to the collector regions of the plurality of transistor cells and drawn out in a direction intersecting the arrangement direction of the plurality of transistor cells.
The collector collective wiring that connects the plurality of collector lead wiring to each other, and
The plurality of collector lead wires arranged between the two cell rows in a plan view and drawn from the plurality of transistor cells belonging to one of the two cell rows are connected to each other. A semiconductor device having a collector intermediate bundle wiring is provided.

According to another aspect of the invention
It includes a semiconductor device and a module substrate on which the semiconductor device is mounted.
The semiconductor device is
With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings connected to the collector regions of the plurality of transistor cells and drawn out in a direction intersecting the arrangement direction of the plurality of transistor cells.
The collector collective wiring that connects the plurality of collector lead wiring to each other, and
A collector intermediate that is arranged between the two cell rows in a plan view and connects the plurality of collector lead wires drawn from a plurality of transistor cells belonging to one of the two cell rows to each other. Summary wiring and
It has at least one emitter bump for each of the two cell rows.
The module board is
A ground conductor connected to the emitter bump of the semiconductor device,
Provided is an amplifier module having a via conductor extending from the ground conductor in the thickness direction and reaching a surface opposite to the surface on which the ground conductor is provided.

According to yet another aspect of the invention.
With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings that are connected to the collector regions of the plurality of transistor cells and are drawn out to the outside of one of the two cell rows in a direction orthogonal to the arrangement direction of the plurality of transistor cells. When,
The two cell rows are connected to the base regions of the plurality of transistor cells, respectively, orthogonal to the arrangement direction of the plurality of transistor cells, and in the direction opposite to the direction in which the plurality of collector extraction wires are drawn out. Multiple base lead-out wires pulled out to the outside of the other cell row,
It has a plurality of base lead-out wirings and an emitter wiring arranged in a wiring layer above the plurality of collector-leading wirings and connected to the emitter region.
Of the base lead-out wiring and collector lead-out wiring adjacent to each other in the arrangement direction of the plurality of transistor cells, the portion arranged at the same position in the direction orthogonal to the arrangement direction of the plurality of transistor cells is the emitter wiring in a plan view. The semiconductor device included in the above is provided.

By arranging the collector intermediate group wiring, the parasitic inductance of the collector wiring can be reduced. Further, by arranging the emitter wiring on the portion where the collector lead wiring and the base lead wiring run in parallel, the parasitic inductance can be reduced.

FIG. 1 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the first embodiment. FIG. 2A is an enlarged plan view of one transistor cell, and FIG. 2B is a cross-sectional view taken along the alternate long and short dash line 2B-2B of FIG. 2A. FIG. 3 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. FIG. 4A is a diagram showing a planar positional relationship between a transistor cell, a collector lead wiring, a collector collective wiring, a collector intermediate collective wiring, a collector bump, and an input capacitance element of the semiconductor device according to the first embodiment, and is a diagram of FIG. 4B. 4C and 4D are diagrams showing a planar positional relationship between a transistor cell, a collector lead wiring, a collector collective wiring, a collector bump, and an input capacitance element of a semiconductor device according to a comparative example. FIG. 5 is a graph showing the calculation results of the parasitic inductance at the evaluation points A1 to A6 of the semiconductor device from FIGS. 4A to 4D. 6A and 6B show the transistor cell, collector lead wiring, collector collective wiring, and input capacitance element of the semiconductor device according to the first embodiment and the comparative example, which are the targets for simulating the temperature rise while mounted on the module substrate, respectively. It is a figure which shows the planar positional relationship of an emitter bump, a collector bump and the like. FIG. 7A is a diagram showing the positional relationship between the conductor pattern and via conductor of the module substrate on which the semiconductor device is mounted according to the first embodiment and the emitter bump of the semiconductor device, and FIGS. 7B and 7C are the first embodiments, respectively. It is a figure which shows the simulation result of the temperature rise of the semiconductor device (FIG. 1A) by example, and the semiconductor device (FIG. 6A) by comparative example. FIG. 8 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the second embodiment. FIG. 9 is an equivalent circuit diagram of the semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the third embodiment. FIG. 11 is an equivalent circuit diagram of the semiconductor device according to the third embodiment. FIG. 12 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the fourth embodiment. FIG. 13 is an equivalent circuit diagram of the semiconductor device according to the fourth embodiment. FIG. 14 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the fifth embodiment. FIG. 15 is an equivalent circuit diagram of the semiconductor device according to the fifth embodiment. FIG. 16 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the sixth embodiment. FIG. 17 is an equivalent circuit diagram of the semiconductor device according to the sixth embodiment. FIG. 18 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the seventh embodiment. FIG. 19 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eighth embodiment. FIG. 20 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the ninth embodiment. FIG. 21 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the tenth embodiment. FIG. 22 is a cross-sectional view of one transistor cell of the semiconductor device according to the tenth embodiment. FIG. 23 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eleventh embodiment. FIG. 24 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the twelfth embodiment. FIG. 25A is a block diagram of the amplifier module according to the thirteenth embodiment, and FIG. 25B is a diagram showing a circuit layout of the semiconductor device mounted on the module board of the amplifier module according to the thirteenth embodiment. FIG. 26 is a cross-sectional view of the module substrate of the amplifier module and the semiconductor device according to the thirteenth embodiment. FIG. 27 is a block diagram of the amplifier module according to the 14th embodiment. FIG. 28A is an equivalent circuit diagram of the semiconductor device according to the fifteenth embodiment, and FIG. 28B is a plurality of transistor cells, an input capacitance element, a base ballast resistance element, an emitter bump, a collector bump, and a transistor Q3 of an output stage bias circuit (FIG. 28B). It is a figure which shows the planar positional relationship of FIG. 28A). 29A and 29B are equivalent circuit diagrams of the semiconductor device according to the modified example of the fifteenth embodiment. FIG. 30 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the sixteenth embodiment. 31A, 31B, and 31C are diagrams showing the relative positional relationship between the collector electrode, the base electrode, and the emitter electrode in one transistor cell of the three prepared samples. FIG. 32 is a graph showing the measurement results of the transition voltage at the SOA boundary and the voltage at the fracture boundary of Sample A (FIG. 31A), Sample B (FIG. 31B), and Sample C (FIG. 31C). FIG. 33 is a diagram showing a planar arrangement of four transistor cells of the semiconductor device according to the seventeenth embodiment. FIG. 34 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eighteenth embodiment. 35A is a cross-sectional view taken along the alternate long and short dash line 35A-35A of FIG. 34, and FIG. 35B is a schematic cross-sectional view taken along the alternate long and short dash line 35B-35B of FIG. 34. FIG. 36 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to a modification of the 18th embodiment. FIG. 37 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to another modification of the 18th embodiment. FIG. 38 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the nineteenth embodiment. FIG. 39 is a schematic view showing a cross section of the alternate long and short dash line 39-39 of FIG. 38. FIG. 40 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to a modified example of the 19th embodiment. FIG. 41 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to another modification of the 19th embodiment. FIG. 42 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to still another modification of the 19th embodiment. FIG. 43 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the twentieth embodiment. FIG. 44 is a schematic view showing a cross section of the alternate long and short dash line 44-44 of FIG. 43. FIG. 45 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to a modified example of the twentieth embodiment. FIG. 46 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to another modification of the 20th embodiment. FIG. 47 is a diagram showing a planar arrangement of a plurality of transistor cells, an input capacitance element, a base ballast resistance element, wiring, bumps, etc. constituting an amplifier circuit of a semiconductor device according to still another modification of the twentieth embodiment.

[First Example]
The semiconductor device according to the first embodiment will be described with reference to the drawings of FIGS. 1 to 5.
FIG. 1 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the first embodiment. A plurality of transistor cells 30 connected in parallel to each other are arranged on a substrate made of a semiconductor.

FIG. 2A is an enlarged plan view of one transistor cell 30. FIG. 2B is a cross-sectional view taken along the alternate long and short dash line 2B-2B of FIG. 2A. A sub-collector layer 51 made of n-type GaAs is arranged on a substrate 50 made of a semi-insulating semiconductor such as GaAs. The surface of the substrate 50 is the (100) plane of GaAs. The sub-collector layer 51 is surrounded by an element separation region (not shown) that is insulated by implanting ions into a part of the n-type GaAs layer grown on the entire surface of the substrate 50.

A collector region 30C made of an n-type GaAs layer is arranged on a part of the sub-collector layer 51, and a base region 30B made of a p-type GaAs layer is arranged on the collector region 30C. An emitter region 30E made of n-type InGaP or the like is arranged on a part of the base region 30B. The collector region 30C, the base region 30B, and the emitter region 30E constitute a transistor cell 30 which is a heterojunction bipolar transistor (HBT).

The emitter region 30E has a long planar shape in the [011] direction (longitudinal direction in FIG. 2A) of the substrate 50. The plurality of transistor cells 30 (FIG. 1) are arranged in the [01-1] direction (width direction of the emitter region 30E) of the substrate 50. The direction in which the plurality of transistor cells 30 are arranged is simply referred to as the "arrangement direction".

A pair of collector electrodes 40C are arranged on the sub-collector layer 51 so as to sandwich the collector region 30C in the arrangement direction. The collector electrode 40C is electrically connected to the collector region 30C via the sub-collector layer 51. Unless otherwise noted herein, "connection" means electrical connection. Further, "connection" means both a form of direct contact and a form of being electrically connected via another conductive member.

The base electrode 40B is arranged on the base region 30B so as to sandwich the emitter region 30E in the arrangement direction. The base electrode 40B is ohmically connected to the base region 30B. The emitter electrode 40E is arranged on the emitter region 30E. The emitter electrode 40E is ohmically connected to the emitter region 30E. The base electrode 40B surrounds the emitter region 30E and the emitter electrode 40E in a U shape from three directions in a plan view.

The n-type InGaP layer may be arranged over the entire upper surface of the base region 30B, and the emitter mesa layer may be arranged on a part of the region. The emitter mesa layer includes, for example, an n-type GaAs layer and an n-type InGaAs layer arranged on the n-type GaAs layer. Of the n-type InGaP layer covering the entire upper surface of the base region 30B, the region not covered by the emitter mesa layer is depleted and is called a ledge layer. In this configuration, the emitter mesa layer and the n-type InGaP layer immediately below the emitter mesa layer function as the emitter region 30E.

An insulating film (not shown) is arranged so as to cover the sub-collector layer 51, the transistor cell 30, the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E. A collector lead wiring 41C, a base lead wire 41B (FIG. 2A), and an emitter wiring 41E are arranged on the insulating film. The collector lead-out wiring 41C, the base lead-out wiring 41B, and the emitter wiring 41E are connected to the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E through openings 34, 35, and 36 provided in the insulating film, respectively. In FIGS. 1 and 2A, the collector lead wiring 41C, the base lead wiring 41B, and the emitter wiring 41E arranged in the first wiring layer are hatched so that the planar arrangement can be easily understood.

The base lead-out wiring 41B is drawn out from the connection point with the base electrode 40B in a direction orthogonal to the arrangement direction. The collector lead-out wiring 41C is drawn out from the connection point with the collector electrode 40C in the direction opposite to that of the base lead-out wiring 41B.

A second layer of insulating film (not shown) is arranged so as to cover the collector lead wiring 41C, the base lead wiring 41B, and the emitter wiring 41E. The second layer emitter wiring 42E (FIGS. 1 and 2B) is arranged on the second layer insulating film. The second-layer emitter wiring 42E is connected to the first-layer emitter wiring 41E through an opening 44 provided in the second-layer insulating film. The second layer emitter wiring 42E is covered with a protective film (not shown). The protective film is provided with an opening for exposing a part of the emitter wiring 42E. The emitter bump 43E is arranged on the emitter wiring 42E exposed in this opening.

Returning to FIG. 1, the planar arrangement of the plurality of transistor cells 30 and the like will be described. In FIG. 1, the openings provided in the insulating film between the first wiring layer and the second wiring layer are shown by broken lines, and the openings provided in the other insulating films and protective films are complicated. The illustration is omitted to avoid this. The opening 44 (FIG. 2B) is provided in the insulating film between the first wiring layer and the second wiring layer, but is not shown in FIG.

The semiconductor device according to the first embodiment includes two cell rows 33 composed of a plurality of transistor cells 30 arranged in parallel with each other. Each of the plurality of transistor cells 30 in the cell row 33 is arranged in the width direction ([01-1] direction) of the emitter electrode 40E. The number of transistor cells 30 constituting the two cell rows 33 is the same. The plurality of transistor cells 30 in one cell row 33 and the plurality of transistor cells 30 in the other cell row 33 are arranged alternately in the arrangement direction. The transistor cells 30 of the other cell row 33 are not arranged between the two transistor cells 30 located in the center of one cell row 33, and the regularity of the alternate arrangement is broken. At this point, the regularity of alternating arrangement is maintained. Arrangement of a plurality of transistor cells 30 on one side and a plurality of transistors on the other side with respect to a straight line (hereinafter referred to as a symmetry axis) located at a place where the regularity of the alternating arrangement is broken and orthogonal to the arrangement direction. The arrangement of the cells 30 has a mirror-symmetrical relationship.

One collector group wiring 41CI extending in the arrangement direction is arranged on the side opposite to the other cell row when viewed from one cell row 33 (lower cell row 33 in FIG. 1). For example, the collector collective wiring 41CI is connected to all of the collector extraction wirings 41C drawn from the plurality of transistor cells 30 connected in parallel to each other. The collector group wiring 41CI is arranged in the same first layer as the collector lead wiring 41C. Multiple Transistors in Cell Row 33 Far from Collector Collective Wiring 41CI The plurality of Collector Lead Wiring 41Cs drawn from cell 30 cross the region between the two cell rows 33 and the transistors in the other cell row 33. It passes between the cells 30 or outside the transistor cells 30 at both ends to reach the collector collective wiring 41CI.

The collector lead wiring 41C overlaps with the collector electrode 40C and is connected to the collector electrode 40C at a portion passing between the transistor cells 30 of the cell row 33 closer to the collector collective wiring 41CI. As described above, the collector lead wiring 41C drawn from the transistor cell 30 of the cell row 33 farther from the collector collective wiring 41CI is the collector lead wiring 41C of the transistor cell 30 of the cell row 33 closer to the collector collective wiring 41CI. Shared.

The second-layer emitter wiring 42E is provided for each cell row 33 and is arranged so as to overlap the transistor cell 30. The second-layer emitter wiring 42E is connected to the first-layer emitter wiring 41E through an opening 44 (FIG. 2B) provided in an insulating film covering the first-layer emitter wiring 41E. Further, the second layer emitter wiring 42E is separated into two in the arrangement direction at the position of the axis of symmetry. That is, a total of four emitter wirings 42E are arranged. Four emitter bumps 43E are arranged so as to overlap the four emitter wirings 42E. Therefore, the emitter bumps 43E corresponding to each of the two cell rows 33 are also separated into two in the arrangement direction. The emitter bump 43E is connected to the corresponding emitter wiring 42E through an opening provided in the protective film covering the emitter wiring 42E.

A collector intermediate group wiring 42CH extending in the arrangement direction is arranged between the two cell rows 33. The collector intermediate wiring 42CH is arranged in the same second wiring layer as the emitter wiring 42E. The collector intermediate group wiring 42CH is connected to a plurality of collector extraction wirings 41C through an opening 45 provided in an insulating film arranged between the first layer wiring layer and the second layer wiring layer. .. That is, the plurality of collector lead-out wirings 41C are connected to each other by the collector intermediate group wiring 42CH. For example, the collector intermediate wiring 42CH connects a plurality of collector extraction wirings 41C drawn from a part of a plurality of transistor cells 30 connected in parallel to each other between the transistor cells 30 and the collector wiring 41CI. Is connected to.

The second layer collector wiring 42C is arranged so as to partially overlap the collector collective wiring 41CI. The second layer collector wiring 42C is connected to the collector wiring 41CI through an opening 46 provided in the insulating film covering the collector wiring 41CI. The second layer collector wiring 42C has a portion protruding in a direction away from the cell row 33. A collector bump 43C is arranged in this overhanging portion. The collector bump 43C is connected to the collector wiring 42C through an opening provided in the protective film covering the collector wiring 42C.

A plurality of input capacitance elements 31 are arranged on the side opposite to the collector collective wiring 41CI when viewed from the two cell rows 33. The input capacitance element 31 is provided for each transistor cell 30. The plurality of input capacitance elements 31 are composed of a base lead-out wiring 41B drawn from the plurality of transistor cells 30 and a high-frequency input wiring 42RF arranged on the base lead-out wiring 41B via an insulating film. The high-frequency input wiring 42RF has a long planar shape in the arrangement direction and is shared by a plurality of input capacitance elements 31. The base lead-out wiring 41B is widened in a region overlapping the high-frequency input wiring 42RF, and a required capacity is secured.

The base control wiring 41BC extending in the arrangement direction is arranged at a position far from the area where the input capacitance elements 31 are arranged when viewed from the cell row 33. The base lead-out wiring 41B drawn from the plurality of transistor cells 30 is connected to the base control wiring 41BC via the base ballast resistance element 32 at the tip of the intersection with the high-frequency input wiring 42RF. The base control wiring 41BC and the base ballast resistance element 32 are arranged in the same first wiring layer as the base lead wiring 41B.

FIG. 3 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. Eight transistor cells 30 are included in each of the two cell rows 33. The collector lead wiring 41C drawn from the collectors of the plurality of transistor cells 30 is connected to one collector collective wiring 41CI. A plurality of collector drawing wires 41C drawn from the collectors of the plurality of transistor cells 30 in the cell row 33 farther from the collector collecting wiring 41CI are connected to each other by the collector intermediate collecting wiring 42CH.

For every four transistor cells 30, the emitter of the transistor cell 30 is connected to the emitter wiring 42E. Each of the four emitter wires 42E is connected to an emitter bump 43E that is dropped to the ground.

The bases of the plurality of transistor cells 30 are connected to one high-frequency input wiring 42RF via the base extraction wiring 41B and the input capacitance element 31, respectively. Further, the bases of the plurality of transistor cells 30 are connected to one base control wiring 41BC via the base lead-out wiring 41B and the base ballast resistance element 32, respectively.

A base bias voltage and a current are supplied from the base control terminal 61 to the bases of the plurality of transistor cells 30 via the base control wiring 41BC and the plurality of base ballast resistance elements 32, respectively. High-frequency signals are input from the high-frequency input terminal 62 to the bases of the plurality of transistor cells 30 via the plurality of input capacitance elements 31. The collector bump 43C functions as a terminal for applying a DC voltage to the collectors of the plurality of transistor cells 30 and a terminal for outputting an amplified high-frequency signal. Here, the "terminal" includes not only bumps for connecting to an external circuit but also connection points for connecting to other circuits in the substrate 50 (FIG. 2B).

Next, the excellent effect of the first embodiment will be described.
In the first embodiment, the collector lead-out wiring 41C is pulled out in a direction orthogonal to the arrangement direction of the plurality of transistor cells 30, and a plurality of collector lead-out wires 41C are mutually connected by the collector intermediate group wiring 42CH between the two cell rows 33. Is connected to. With this configuration, the parasitic inductance from the collector bump 43C to the transistor cell 30 can be reduced. Hereinafter, the evaluation results confirmed that the parasitic inductance reduction effect can be obtained will be described with reference to the drawings from FIGS. 4A to 5.

FIG. 4A is a diagram showing a planar positional relationship between the transistor cell 30, the collector lead wiring 41C, the collector collective wiring 41CI, the collector intermediate collective wiring 42CH, the collector bump 43C, and the input capacitance element 31 of the semiconductor device according to the first embodiment. is there. One cell row 33 includes 18 transistor cells 30. 4B, 4C, and 4D are diagrams showing the planar positional relationship of the transistor cell 30, the collector lead wiring 41C, the collector collective wiring 41CI, the collector bump 43C, and the input capacitance element 31 of the semiconductor device according to a comparative example. ..

In the comparative example shown in FIG. 4B, the collector intermediate group wiring 42CH (FIG. 4A) is not arranged. Other configurations are the same as those of the first embodiment (FIG. 4A).

In the comparative example shown in FIG. 4C, 36 transistor cells 30 are arranged in a row. The collector group wiring 41CI is arranged on one side of one cell row, and a plurality of input capacitance elements 31 are arranged on the opposite side. In a plan view, the collector bump 43C is included in the collector collective wiring 41CI.

In the comparative example shown in FIG. 4D, four cell rows, each containing nine transistor cells 30, are arranged in the vertical direction. A collector group wiring 41CI is arranged between the two cell rows on the right side and between the two cell rows on the left side, respectively, and one end of the two collector group wiring 41CIs is connected to each other. A collector bump 43C is arranged at this connecting portion.

In both the first embodiment and the comparative example from FIGS. 4A to 4D, the pitch of the transistor cells 30 was made the same. The parasitic inductance of the collector wiring from the collector bump 43C of the semiconductor device according to the first embodiment and the comparative example from FIGS. 4A to 4D to the evaluation points A1, A2, A3, A4, A5, and A6 was obtained by simulation.

FIG. 5 is a graph showing the calculation results of the parasitic inductance at the evaluation points A1 to A6. The horizontal axis represents 6 evaluation points, and the vertical axis represents the normalized inductance with the maximum parasitic inductance as 1. The circles, squares, pentagons, and triangles in the graph of FIG. 5 indicate the normalized parasitic inductances in the semiconductor devices of FIGS. 4A, 4B, 4C, and 4D, respectively.

In either case, it can be seen that the closer the evaluation point is to the collector bump 43C, the smaller the parasitic inductance. In the one-row semiconductor device shown in FIG. 4C, the parasitic inductance at the evaluation point A1 located at the end of the cell row is large. Further, in the semiconductor device having a four-row configuration shown in FIG. 4D, the parasitic inductance at the two evaluation points A3 and A6 farthest from the collector bump 43C is large. As a whole, it can be seen that the parasitic inductance is small in the two-row semiconductor device shown in FIGS. 4A and 4B.

Further, it can be seen that the parasitic inductance in the semiconductor device according to the first embodiment shown in FIG. 4A is smaller than the parasitic inductance in the semiconductor device according to the comparative example shown in FIG. 4B. This is an effect of connecting a plurality of collector lead wiring 41Cs to each other by the collector intermediate collective wiring 42CH. In this way, by connecting a plurality of collector lead wiring 41Cs to each other between the two cell rows 33, the parasitic inductance from the collector bump 43C to the transistor cell 30 can be reduced.

Next, the excellent effect on the chip area will be described.
Comparing the semiconductor device according to the first embodiment shown in FIG. 4A with the semiconductor device according to the comparative example shown in FIGS. 4C and 4D, the arrangement pitches of the input capacitance elements 31 of the semiconductor device according to the first embodiment are compared. It can be seen that it is narrower than the arrangement pitch of the input capacitance elements 31 of the semiconductor device according to the example. This is because the transistor cells 30 are arranged in two rows in the first embodiment, but the input capacitance elements 31 are arranged in one row. Therefore, when a plurality of transistor cells 30 are arranged at the same pitch, the area occupied by the amplifier circuit on the substrate can be reduced in the first embodiment as compared with the comparative example.

In the first embodiment, the emitter bumps 43E (FIG. 1) are arranged in a direction orthogonal to the arrangement direction. The same potential (ground potential) is given to the two emitter bumps 43E arranged in the direction orthogonal to the arrangement direction. According to the design rule, the distance between the two emitter bumps 43E to which the same potential is given can be made narrower than the distance between the emitter bump 43E and the collector bump 43C to which different potentials are given. Therefore, even if the emitter bumps 43E are arranged in the direction orthogonal to the arrangement direction, the influence of the increase in the dimensions in the direction orthogonal to the arrangement direction is reduced.

Next, the excellent thermal effect will be described with reference to the drawings from FIGS. 6A to 7C. The temperature rise of the semiconductor device when the semiconductor devices according to the first embodiment and the comparative examples were mounted on the module substrate and operated under the same conditions was obtained by simulation.

6A and 6B show the transistor cell 30, collector lead wiring 41C, collector collective wiring 41CI, input capacitance element 31, emitter bump 43E, and collector bump 43C of the semiconductor device according to the first embodiment and the comparative example to be simulated, respectively. It is a figure which shows the planar positional relationship such as. The semiconductor device according to the first embodiment shown in FIG. 6A is the same as that shown in FIG. 4A, and 36 transistor cells 30 are provided. Emitter bumps 43E are arranged for each cell row 33 and are separated in the longitudinal direction on the axis of symmetry.

The semiconductor device according to the comparative example shown in FIG. 6B includes one cell row 33 in which 36 transistor cells 30 are arranged. The pitch of the transistor cells 30 is half the pitch of the transistor cells 30 constituting one cell row 33 of the semiconductor device according to the first embodiment shown in FIG. 6A. One emitter bump 43E is arranged corresponding to one cell row 33. The length of one cell row 33 of the semiconductor device according to the comparative example is substantially equal to the length of each of the two cell rows 33 (FIG. 6A) of the semiconductor device according to the first embodiment.

FIG. 7A is a diagram showing a positional relationship between the conductor pattern and via conductor of the module substrate on which the semiconductor device is mounted according to the first embodiment and the emitter bump 43E of the semiconductor device. The conductor pattern 70 of the module substrate includes four emitter bumps 43E in a plan view. Three via conductors 71, which are long in the same direction as the longitudinal direction of the emitter bumps 43E, are provided on the module substrate with respect to the two emitter bumps 43E arranged in the arrangement direction of the plurality of transistor cells 30. In a plan view, the three via conductors 71 and the two emitter bumps 43E substantially overlap each other in the width direction orthogonal to the arrangement direction. The conductor pattern 72 of the module substrate includes the collector bump 43C.

In the simulation of the semiconductor device (FIG. 6B) according to the comparative example, the same module substrate as the module substrate on which the semiconductor device (FIG. 6A) according to the first embodiment is mounted was used. In the semiconductor device according to the comparative example (FIG. 6B), the pattern is designed so that one emitter bump 43E overlaps with the three via conductors 71 closer to the conductor pattern 72 of the module substrate in the width direction of the emitter bump 43E. A simulation was performed.

7B and 7C are diagrams showing simulation results of temperature rise of the semiconductor device (FIG. 6A) according to the first embodiment and the semiconductor device (FIG. 6B) according to the comparative example, respectively. The number of transistor cells 30 of the semiconductor device to be simulated is different from the number of transistor cells 30 of the semiconductor device shown in FIGS. 1A, 6A and 6B. The color depth shown in FIGS. 7B and 7C corresponds to the high temperature. The relatively hot region is represented relatively darkly. It can be seen that the temperature of the transistor cell 30 of the semiconductor device according to the comparative example (FIG. 7C) is higher than the temperature of the transistor cell 30 of the semiconductor device according to the first embodiment (FIG. 7B).

In the simulation results, the maximum temperature of the semiconductor device according to the first embodiment was 53.47 ° C., whereas the maximum temperature of the semiconductor device according to the comparative example was 61.78 ° C. The thermal resistance of the heat dissipation path of the semiconductor device and the module substrate according to the first embodiment is 14.2 ° C./W, whereas the thermal resistance of the heat dissipation path of the semiconductor device and the module substrate according to the comparative example is 18.4 ° C./W. Is. As described above, by adopting the configuration of the first embodiment, the thermal resistance of the heat dissipation path from the transistor cell 30 can be reduced by about 23% as compared with the comparative example. This is because the arrangement pitch of the transistor cells 30 is doubled by using two cell rows as in the first embodiment.

In the first embodiment, the maximum output of the amplifier circuit can be improved by reducing the thermal resistance of the heat dissipation path from the transistor cell 30.

Next, an excellent effect on the flatness of the emitter bump 43E will be described. In the first embodiment, two cell rows 33 are provided. Therefore, the length of each of the cell rows 33 is shorter than that of the configuration in which the number and pitch of the transistor cells 30 are the same and arranged in one row. Therefore, the length of the emitter bump 43E arranged corresponding to the cell row 33 is also shortened. Further, in the first embodiment, since the emitter bumps 43E corresponding to the cell row 33 are separated into two in the arrangement direction, the emitter bumps 43E are further shortened. As a result, the surface flatness of the emitter bump 43E can be improved. As a result, it is possible to suppress a decrease in yield in the process of mounting the semiconductor device on the module substrate.

Next, a modified example of the first embodiment will be described.
In the first embodiment, eight transistor cells 30 form one cell row 33, but the number of transistor cells 30 forming one cell row 33 may be other than eight. For example, as shown in FIG. 4A, 18 transistor cells 30 may form one cell row 33. Further, in the first embodiment, the arrangement of the plurality of transistor cells 30 constituting the two cell rows 33 is mirror-symmetrical with respect to the axis of symmetry located at the center in the arrangement direction. That is, the rule of alternating arrangement of the plurality of transistor cells 30 is broken at the position of the axis of symmetry. The arrangement of the plurality of transistor cells 30 constituting the two cell rows 33 does not necessarily have to be mirror-symmetrical, and the plurality of transistor cells 30 in one cell row 33 and the plurality of transistor cells in the other cell row 33 are arranged. The rules of alternating arrangement with 30 may be maintained from one end to the other.

In the first embodiment, GaAs is used for the collector and the base, and InGaP is used for the emitter, but other compound semiconductors may be used. Further, a normal bipolar transistor may be used as the transistor cell 30.

In the first embodiment, the base lead-out wiring 41B and the collector lead-out wiring 41C are arranged in the first-layer conductor layer, but the base lead-out wiring 41B is arranged in the first-layer conductor layer and the collector lead-out wiring 41C is arranged in 2. It may be arranged in the conductor layer of the layer. When the base lead-out wiring 41B and the collector lead-out wiring 41C are arranged in parallel with each other, the input signal and the output signal interfere with each other due to their coupling. By making the conductor layer in which the base lead-out wiring 41B is arranged different from the conductor layer in which the collector lead-out wiring 41C is arranged, the coupling between the two can be weakened and mutual interference between the input signal and the output signal can be suppressed. ..

[Second Example]
Next, the semiconductor device according to the second embodiment will be described with reference to FIGS. 8 and 9. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 8 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the second embodiment. In the first embodiment, the second layer emitter wiring 42E is arranged corresponding to each of the two cell rows 33, and is separated into one side and the other side of the axis of symmetry. That is, the second layer emitter wiring 42E is separated into four conductor patterns. On the other hand, in the second embodiment, the second layer emitter wiring 42E is composed of one conductor pattern.

Specifically, the emitter wiring 42E includes two in-cell row connecting portions 42E1 and two cell row-to-cell row connecting portions 42E2. Each of the two cell row connecting portions 42E1 has a long planar shape in the arrangement direction and is arranged corresponding to the two cell rows 33, and is an emitter of a plurality of transistor cells 30 of the corresponding cell row 33. It is connected to region 30E (FIG. 2B). For example, the connection portion 42E1 in the cell row connects the emitter regions 30E of a plurality of transistor cells 30 included in one cell row 33 to each other. The connection portion 42E2 between the two cell rows connects the corresponding ends of the connection portion 42E1 within the two cell rows. The second-layer emitter wiring 42E has a closed annular shape in a plan view. The collector intermediate group wiring 42CH is arranged in the region surrounded by the annular emitter wiring 42E.

FIG. 9 is an equivalent circuit diagram of the semiconductor device according to the second embodiment. The emitters of each of the eight transistor cells 30 in the cell row 33 are connected to each other by the connection portion 42E1 in the cell row. The two cell row connection portions 42E1 are connected to each other by the two cell row connection portions 42E2.

Next, the excellent effect of the second embodiment will be described.
In the second embodiment, since the emitters of all the transistor cells 30 of the two cell rows 33 are connected to each other by the emitter wiring 42E of the second layer, the wiring connected to the emitter of the transistor cell 30 Parasitic resistance, parasitic inductance, etc. become smaller. As a result, an excellent effect of improving the performance of the amplifier circuit can be obtained.

Next, a modified example of the second embodiment will be described.
In the second embodiment, the second layer emitter wiring 42E has a closed annular planar shape, but it may have an open planar shape at one place. For example, one end of the two cell row connection portions 42E1 may be connected to each other by the cell row connection portion 42E2, and the other end portions may not be connected to each other. Further, one of the connection portions 42E1 in the cell row may be separated into two at the center (position of the axis of symmetry). Also in this case, since the emitter wiring 42E of the second layer is composed of one conductor pattern, the same excellent effect as that of the second embodiment can be obtained. Further, when the lift-off method is used to form the emitter wiring 42E of the second layer, the effect that the emitter wiring 42E can be formed with good reproducibility can be obtained.

[Third Example]
Next, the semiconductor device according to the third embodiment will be described with reference to FIGS. 10 and 11. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 10 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the third embodiment. In the first embodiment, one input capacitance element 31 is connected to one transistor cell 30. On the other hand, in the third embodiment, the input capacitance element 31 includes one transistor cell 30 in one cell row 33 of the two cell rows 33 and one transistor cell 30 in the other cell row 33. It is provided for each row-to-row pair 37. Further, the base ballast resistance element 32 is also provided for each row-to-row pair 37. When a serial number is assigned to a plurality of transistor cells 30 in one cell row 33 from one end, and a serial number is assigned to a plurality of transistor cells 30 in the other cell row 33 from the same end, they are the same. One row-to-row pair 37 is composed of two transistor cells 30 having serial numbers.

The two base lead-out wires 41B drawn out from the two transistor cells 30 forming the inter-row pair 37 are widened, and the widened portions are integrated with each other. This widened and integrated portion overlaps with the high frequency input wiring 42RF to form the input capacitance element 31.

FIG. 11 is an equivalent circuit diagram of the semiconductor device according to the third embodiment. One transistor cell 30 in one cell row 33 and one transistor cell 30 in the other cell row 33 form an inter-row pair 37. The bases of the two transistor cells 30 forming one row-to-row pair 37 are connected to the same input capacitance element 31. Further, the bases of the two transistor cells 30 forming one row-to-row pair 37 are connected to the same base ballast resistance element 32.

ここで、βはトランジスタの電流増幅率であり、Ｉ_ＣＭＡＸは回路設計最大コレクタ電流であり、φはベースエミッタ間電圧Ｖ_ＢＥの温度計数であり、Ｒ_ｔｈは熱抵抗であり、Ｖ_ＣＥはコレクタエミッタ間電圧であり、ｋはボルツマン定数であり、Ｔ_０は雰囲気温度であり、ｑは電荷素量である。熱抵抗Ｒｔｈが小さくなると、数式（１）の右辺が小さくなり、ベースバラスト抵抗素子３２の抵抗値Ｒ_ＢＬを小さくすることができる。 Next, the excellent effect of the third embodiment will be described.
_{The resistance value R BL} of the base ballast resistance element 32 is preferably set so as to satisfy the following inequality.

Here, β is the current amplification factor of the transistor, _ICMAX is the circuit design maximum collector current, φ is the temperature count of the _{base-emitter voltage V BE , R th} is the thermal resistance, and V _CE is the collector. It is the voltage between emitters, k is the Boltzmann constant, T ₀ is the ambient temperature, and q is the amount of charge element. When the thermal resistance Rth becomes small, the right side of the equation (1) becomes small, and the resistance value R _BL of the base ballast resistance element 32 can be made small.

In the third embodiment, the two transistor cells 30 of the row-to-row pair 37 connected to one base ballast resistance element 32 are arranged so as to straddle the two cell rows 33. In the one-row array comparative example shown in FIG. 6B, the distance between the two transistor cells 30 of the inter-row pair 37 is wider than the distance between the two adjacent transistor cells 30. _{As described with reference to FIGS. 7A, 7B, and 7C, the thermal resistance Rth} corresponding to the two transistor cells 30 constituting the inter-row pair 37 is the transistor cells 30 arranged in one row (FIG. 6B). _{) Is} smaller than the thermal resistance Rth. Therefore, in the third embodiment, the resistance value R _BL of the base ballast resistance element 32 can be reduced. As a result, the performance of the amplifier circuit can be improved.

[Fourth Example]
Next, the semiconductor device according to the fourth embodiment will be described with reference to FIGS. 12 and 13. Hereinafter, the description of the configuration common to the semiconductor devices (FIGS. 10 and 11) according to the third embodiment will be omitted.

FIG. 12 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the fourth embodiment. In the third embodiment, one input capacitance element 31 is provided for each of the two transistor cells 30 forming the inter-row pair 37 (FIGS. 10 and 11). On the other hand, in the fourth embodiment, one input capacitance element 31 is provided for all the transistor cells 30 in the two cell rows 33. Similarly, one base ballast resistance element 32 is provided for all the transistor cells 30 in the two cell rows 33.

FIG. 13 is an equivalent circuit diagram of the semiconductor device according to the fourth embodiment. The bases of all the transistor cells 30 of the two cell rows 33 are connected to one input capacitance element 31. Further, the bases of all the transistor cells 30 of the two cell rows 33 are connected to one base ballast resistance element 32.

Next, the excellent effect of the fourth embodiment will be described. In the fourth embodiment, since one input capacitance element 31 is provided for all the transistor cells 30, the layout efficiency of the input capacitance element 31 is improved. As a result, the chip size can be reduced and the cost can be reduced.

[Fifth Example]
Next, the semiconductor device according to the fifth embodiment will be described with reference to FIGS. 14 and 15. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 14 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the fifth embodiment. In the first embodiment, the second layer emitter wiring 42E and the emitter bump 43E arranged corresponding to each of the cell rows 33 are separated into two at the position of the axis of symmetry. On the other hand, in the fifth embodiment, one emitter wiring 42E and one emitter bump 43E are arranged for each of the cell rows 33.

FIG. 15 is an equivalent circuit diagram of the semiconductor device according to the fifth embodiment. The emitters of each of the plurality of transistor cells 30 in the cell row 33 are connected to one emitter wiring 42E. One emitter bump 43E is connected to one emitter wiring 42E.

Next, the excellent effect of the fifth embodiment will be described. In the fifth embodiment as well, as in the first embodiment, since the collector intermediate group wiring 42CH is arranged, the parasitic inductance of the collector wiring can be reduced. Further, in the fifth embodiment, the path cross section of the emitter bump 43E serving as the heat dissipation path is larger than that in the first embodiment. Therefore, the thermal resistance can be further reduced.

Comparing FIG. 4A and FIG. 4C, it can be seen that the length of each of the cell rows 33 is shorter than that of the semiconductor device arranged in one row in which the number and pitch of the transistor cells 30 are the same. Therefore, the length of each of the cell rows 33 is shorter than that of the semiconductor device arranged in a single row. Since the length of the emitter bump 43E provided corresponding to the cell row 33 is also short, the surface flatness of the emitter bump 43E can be improved as compared with the one-row arrangement configuration.

[Sixth Example]
Next, the semiconductor device according to the sixth embodiment will be described with reference to FIGS. 16 and 17. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 16 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the sixth embodiment. Also in the first embodiment and the sixth embodiment, the arrangement of the plurality of transistor cells 30 in the two cell rows 33 is mirror-symmetrical with respect to the axis of symmetry. Therefore, the lengths of the two cell rows 33 are different.

In the first embodiment, the second layer emitter wiring 42E arranged for each of the two cell rows 33 is composed of a conductor pattern separated into two at the position of the axis of symmetry. On the other hand, in the sixth embodiment, the second layer emitter wiring 42E arranged corresponding to the longer cell row 33 is composed of two conductor patterns separated into two at the position of the axis of symmetry. However, the second layer emitter wiring 42E arranged corresponding to the shorter cell row 33 is composed of one conductor pattern connected from one end to the other end of the cell row 33. Emitter bumps 43E are also arranged for each conductor pattern of the second layer emitter wiring 42E. As described above, the longer cell row 33 corresponds to a plurality of emitter bumps 43E separated in the arrangement direction, and the shorter cell row 33 corresponds to one unseparated emitter bump 43E. There is.

FIG. 17 is an equivalent circuit diagram of the semiconductor device according to the sixth embodiment. The eight transistor cells 30 of the longer cell row 33 are divided into four sets at the position of the axis of symmetry, and the emitters of the four transistor cells 30 belonging to one set are one emitter wiring 42E. It is connected to the. The emitters of the eight transistor cells 30 in the shorter cell row 33 are connected to one emitter wire 42E.

Next, the excellent effect of the sixth embodiment will be described. In the sixth embodiment as well, as in the first embodiment, since the collector intermediate group wiring 42CH is arranged, the parasitic inductance of the collector wiring can be reduced.

Further, in the fifth embodiment described above, the second layer emitter wiring 42E and the emitter bump 43E corresponding to the shorter cell row 33 have the length of the second layer emitter wiring corresponding to the longer cell row 33. It is the same as the length of 42E and the emitter bump 43E. That is, the second layer emitter wiring 42E and the emitter bump 43E corresponding to the shorter cell row 33 are extended to the outside from the positions of the transistor cells 30 at both ends. On the other hand, in the sixth embodiment, the second layer emitter wiring 42E and the emitter bump 43E corresponding to the shorter cell row 33 are not affected by the length of the longer cell row 33, and the cell row 33 It is said that the length corresponds to the length of. Therefore, the surface flatness of the emitter bump 43E corresponding to the shorter cell row 33 can be improved.

Further, since the emitter bump 43E corresponding to the longer cell row 33 is separated into two parts at the position of the axis of symmetry, the length of each part of the emitter bump 43E after separation is the length of the cell row 33. Shorter than that. Therefore, the surface flatness of the emitter bump 43E corresponding to the longer cell row 33 can be improved.

[7th Example]
Next, the semiconductor device according to the seventh embodiment will be described with reference to FIG. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 18 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the seventh embodiment. In the first embodiment, the plurality of transistor cells 30 in one cell row 33 and the plurality of transistor cells 30 in the other cell row 33 are arranged alternately in the arrangement direction. On the other hand, in the seventh embodiment, two transistor cells 30 adjacent to each other in the same cell row 33 are basic units, and a plurality of basic units of one cell row 33 and a plurality of basic units of the other cell row 33 are used. Units and units are arranged alternately in the arrangement direction. Also in the seventh embodiment, the plurality of basic units of the two cell rows 33 are arranged mirror-symmetrically with respect to the axis of symmetry, and the regularity of the alternating arrangement is broken at the position of the axis of symmetry.

The input capacitance element 31 is provided for each basic unit including the two transistor cells 30. The arrangement of the emitter wiring 42E and the emitter bump 43E of the second layer is the same as in the case of the first embodiment.

Next, the excellent effect of the seventh embodiment will be described. In the seventh embodiment as well, as in the first embodiment, since the collector intermediate group wiring 42CH is arranged, the parasitic inductance of the collector wiring can be reduced.

Next, a modified example of the seventh embodiment will be described. In the seventh embodiment, two transistor cells 30 adjacent to each other in the same cell row 33 are used as the basic unit of the alternate arrangement. In addition, three or more consecutive transistor cells 30 in the same cell row 33 may be used as the basic unit for alternating arrangement.

[8th Example]
Next, the semiconductor device according to the eighth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 18) according to the seventh embodiment will be omitted.

FIG. 19 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eighth embodiment. In the seventh embodiment, the second layer emitter wiring 42E and the emitter bump 43E corresponding to the longer cell row 33 and the second layer emitter wiring 42E and the emitter bump 43E corresponding to the shorter cell row 33 are , Are arranged at the same position with respect to the arrangement direction. On the other hand, in the eighth embodiment, the second layer emitter wiring 42E and the emitter bump 43E corresponding to the longer cell row 33 and the second layer emitter wiring 42E and the emitter corresponding to the shorter cell row 33 The bump 43E is displaced in the arrangement direction.

Specifically, one emitter bump 43E is arranged so as to belong to the same cell row 33 and include a plurality of basic units continuous in the arrangement direction in a plan view. The number of basic units included in one emitter bump 43E is the same for the longer cell row 33 and the shorter cell row 33. Both ends of the emitter bump 43E correspond to the positions of the basic units of both ends included in the emitter bump 43E. Since the plurality of basic units of the longer cell row 33 and the plurality of basic units of the shorter cell row 33 are alternately arranged in the arrangement direction, the emitter bump 43E corresponding to the longer cell row 33 and the emitter bump 43E The emitter bump 43E corresponding to the shorter cell row 33 is arranged so as to be displaced in the arrangement direction. This amount of deviation is approximately equal to the arrangement pitch of the basic units alternately arranged in the arrangement direction.

For example, the number of transistor cells 30 to which one emitter bump 43E corresponding to one cell row of the two cell rows 33 is connected and one emitter bump 43E corresponding to the other cell row 33 are connected. The number of transistor cells 30 to be formed is the same. One emitter bump 43E and the other emitter bump 43E include overlapping portions in the arrangement direction, and one emitter bump 43E and the other emitter bump 43E are extended in opposite directions from the overlapping portions. ing.

Next, the excellent effect of the eighth embodiment will be described.
In the eighth embodiment, since both ends of the emitter bump 43E correspond to the positions of the basic units of both ends included in the emitter bump 43E, the emitter bump 43E is shorter than that in the case of the seventh embodiment. Therefore, the surface flatness of the emitter bump 43E can be improved.

[9th Example]
Next, the semiconductor device according to the ninth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 18) according to the seventh embodiment will be omitted.

FIG. 20 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the ninth embodiment. In the seventh embodiment (FIG. 18), the base lead-out wiring 41B is drawn out from the two transistor cells 30 belonging to one basic unit in the direction orthogonal to the arrangement direction, and reaches one input capacitance element 31. On the other hand, in the ninth embodiment, the base lead-out wires 41B drawn from the two transistor cells 30 belonging to the basic unit are connected to each other in the vicinity of the transistor cells 30 and then bundled into one base lead-out wire 41B. It extends to the input capacitance element 31.

Next, the excellent effect of the ninth embodiment will be described. In the seventh embodiment (FIG. 18), the base lead-out wiring 41B drawn upward from the lower transistor cell 30 in FIG. 18 and the collector lead-out wiring 41C drawn downward from the upper transistor cell 30 Because they are close to each other, they are easy to combine. On the other hand, in the ninth embodiment, the base lead-out wiring 41B drawn from the two transistor cells 30 is bundled into one, so that the distance between the base lead-out wiring 41B and the collector lead-out wiring 41C is widened. As a result, the bond between the two is weakened. As a result, mutual interference between the input signal transmitted through the base lead-out wiring 41B and the output signal transmitted through the collector lead-out wiring 41C can be suppressed.

[10th Example]
Next, the semiconductor device according to the tenth embodiment will be described with reference to FIGS. 21 and 22. Hereinafter, the description of the common configuration with the semiconductor device (FIGS. 1, FIG. 2A, FIG. 2B, FIG. 3) according to the first embodiment will be omitted.

FIG. 21 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the tenth embodiment. FIG. 22 is a cross-sectional view of one transistor cell 30 of the semiconductor device according to the tenth embodiment.

In the first embodiment, the plurality of transistor cells 30 in one cell row 33 and the plurality of transistor cells 30 in the other cell row 33 are arranged alternately in the arrangement direction. On the other hand, in the tenth embodiment, the plurality of transistor cells 30 in one cell row 33 and the plurality of transistor cells 30 in the other cell row 33 are arranged at the same positions in the arrangement direction. Further, in the first embodiment, a pair of collector electrodes 40C (FIGS. 2A and 2B) are arranged so as to sandwich the emitter electrode 40E and the base electrode 40B (FIGS. 2A and 2B) in the arrangement direction. On the other hand, in the tenth embodiment, the collector electrode 40C is arranged only on one side in the arrangement direction when viewed from the emitter electrode 40E and the base electrode 40B. In the first embodiment, the arrangement direction is parallel to the [01-1] direction of the substrate 50 made of GaAs, but in the tenth embodiment, the arrangement direction is parallel to the [011] direction of the substrate 50 made of GaAs. Is. The longitudinal direction of the emitter region 30E and the emitter electrode 40E is parallel to the [01-1] direction.

The collector lead wiring 41C of the first layer is drawn out from the collector electrodes 40C of the plurality of transistor cells 30 in a direction orthogonal to the arrangement direction. One collector lead wiring 41C is shared by two transistor cells 30 arranged at the same position in the arrangement direction.

The base lead-out wiring 41B is drawn out from the base electrodes 40B of the plurality of transistor cells 30 in the arrangement direction on the side opposite to the side where the collector lead-out wiring 41C is arranged. The base lead-out wiring 41B is drawn out from the base electrode 40B in the arrangement direction, then moves away from the collector collective wiring 41CI and extends in a direction orthogonal to the arrangement direction. The portion of the base lead-out wiring 41B extending in the direction orthogonal to the arrangement direction is shared by the two transistor cells 30 arranged at the same position with respect to the arrangement direction. One input capacitance element 31 is arranged for two transistor cells 30 sharing the base lead-out wiring 41B.

The base lead-out wiring 41B is drawn out from the base electrode 40B and crosses the step corresponding to the edge of the collector region 30C and the base region 30B (FIG. 22). The edges of the collector region 30C and the base region 30B (FIG. 22) that the base lead-out wiring 41B crosses are parallel to the [01-1] direction of the substrate 50 made of GaAs. The step extending in this direction is composed of a slope having an inclination angle of less than 90 ° with respect to the surface of the substrate 50. Therefore, the base lead-out wiring 41B is unlikely to be disconnected.

Regarding the plurality of transistor cells 30 arranged on one side with the central axis of symmetry in the arrangement direction as a boundary, the positional relationship between the transistor cell 30, the collector lead wiring 41C, and the base lead wiring 41B with respect to the arrangement direction is the same. Further, the positional relationship between the transistor cell 30, the collector lead-out wiring 41C, and the base lead-out wiring 41B with respect to the arrangement direction is mirror-symmetrical on both sides of the axis of symmetry.

Next, the excellent effect of the tenth embodiment will be described.
Also in the tenth embodiment, by providing the collector intermediate collective wiring 42CH, the parasitic inductance of the collector wiring can be reduced as in the first embodiment.

[11th Example]
Next, the semiconductor device according to the eleventh embodiment will be described with reference to FIG. 23. Hereinafter, the description of the configuration common to the semiconductor devices (FIGS. 21 and 22) according to the tenth embodiment will be omitted.

FIG. 23 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eleventh embodiment. In the tenth embodiment, the plurality of transistor cells 30 arranged on one side with the center of the arrangement direction as a boundary have the same positional relationship with respect to the arrangement direction of the transistor cell 30, the collector lead wiring 41C, and the base lead wiring 41B. Is. On the other hand, in the eleventh embodiment, with respect to the two transistor cells 30 adjacent to each other in the arrangement direction, the positional relationship between the transistor cell 30, the collector lead wiring 41C, and the base drawer wiring 41B with respect to the arrangement direction is mirror-symmetrical. One collector lead wiring 41C is shared by the transistor cells 30 on both sides thereof. Further, one collector lead wiring 41C is also shared by two transistor cells 30 arranged at the same position in the arrangement direction as in the case of the tenth embodiment. Therefore, one collector lead wiring 41C is shared by a total of four transistor cells 30.

Next, the excellent effect of the eleventh embodiment will be described.
In the eleventh embodiment, since one collector lead wiring 41C is shared by the two transistor cells 30 on both sides, the length of the cell row 33 can be shortened.

[12th Example]
Next, the semiconductor device according to the twelfth embodiment will be described with reference to FIG. 24. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 23) according to the eleventh embodiment will be omitted.

FIG. 24 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the twelfth embodiment. In the eleventh embodiment, one collector lead wiring 41C is shared by the two transistor cells 30 on both sides. On the other hand, in the twelfth embodiment, the portion of the base lead-out wiring 41B orthogonal to the arrangement direction is shared by the two transistor cells 30 on both sides. Further, the portion of the base lead-out wiring 41B orthogonal to the arrangement direction is also shared by the two transistor cells 30 arranged at the same position with respect to the arrangement direction as in the eleventh embodiment. Therefore, the portion of the base lead-out wiring 41B orthogonal to the arrangement direction is shared by a total of four transistor cells 30.

As a result, one input capacitance element 31 is provided for each of the four transistor cells 30 that share the base lead-out wiring 41B.

Next, the excellent effect of the twelfth embodiment will be described.
In the twelfth embodiment, since the portion of the base lead-out wiring 41B orthogonal to the arrangement direction is shared by the two transistor cells 30 on both sides, the length of the cell row 33 can be shortened.

Next, a modified example of the twelfth embodiment will be described.
In the twelfth embodiment, one collector lead wiring 41C is shared by two transistor cells 30 arranged at the same position in the arrangement direction, but further, two transistor cells 30 adjacent to each other in the arrangement direction share the same. It may be shared. In this case, one collector lead wiring 41C is shared by a total of four transistor cells 30.

[13th Example]
Next, the amplifier module according to the thirteenth embodiment will be described with reference to FIGS. 25A, 25B, and 26.

FIG. 25A is a block diagram of the amplifier module according to the thirteenth embodiment. The amplifier module according to the thirteenth embodiment includes a module board 80 and a semiconductor device 81 mounted on the module board 80.

The semiconductor device 81 includes a first stage amplifier circuit 82, an interstage matching circuit 85, an output stage amplifier circuit 83, a first stage bias circuit 87, and an output stage bias circuit 88. An input matching circuit 84, an output matching circuit 86, and inductors L1 and L2 are mounted on the module board 80. As the output stage amplifier circuit 83, the amplifier circuit of the semiconductor device according to any one of the first to twelfth embodiments is used.

The high-frequency signal input from the high-frequency signal input terminal RFin1 of the module substrate 80 is input to the high-frequency signal input terminal RFin of the semiconductor device 81 via the input matching circuit 84. The high-frequency signal input to the high-frequency signal input terminal RFin is amplified by the first-stage amplifier circuit 82 and input to the high-frequency input terminal 62 (FIG. 3) of the output stage amplifier circuit 83 via the interstage matching circuit 85. The high-frequency signal amplified by the output stage amplifier circuit 83 is output from the high-frequency signal output terminal RFout (corresponding to the collector bump 43C (FIG. 3)). The high-frequency signal output from the high-frequency signal output terminal RFout is output from the high-frequency signal output terminal RFout1 of the module board 80 via the output matching circuit 86 mounted on the module board 80.

A bias voltage is applied from the bias voltage terminal Vbatt to the first stage bias circuit 87 and the output stage bias circuit 88. The first-stage bias circuit 87 supplies the vise voltage and current to the first-stage amplifier circuit 82 based on the control signal input from the bias control terminal Vbias1. Based on the control signal input from the bias control terminal Vbias2, the output stage bias circuit 88 supplies the bias voltage and current to the base control terminal 61 (FIG. 3) of the output stage amplifier circuit 83.

A DC power supply voltage is applied to the power supply terminal Vcc1 of the first-stage amplifier circuit 82 via the inductor L1. A DC power supply voltage is applied to the power supply terminal Vcc2 (corresponding to the collector bump 43C (FIG. 3)) of the output stage amplifier circuit 83 via the inductor L2.

FIG. 25B is a diagram showing a circuit layout of the semiconductor device 81 mounted on the module board 80 (FIG. 25A) of the amplifier module according to the thirteenth embodiment. A plurality of bumps are arranged on the surface of the semiconductor device 81 facing the module substrate 80. The emitter bump 43E (FIGS. 1 and 3) of the output stage amplifier circuit 83 is connected to the ground of the module substrate 80. The collector bump 43C (FIG. 1) of the output stage amplifier circuit 83 corresponds to the power supply terminal Vcc2 and the high frequency signal output terminal RFout in FIG. 25A. In addition, bumps such as a bias voltage terminal Vbatt, a bias control terminal Vbias1, Vbias2, a power supply terminal Vcc1, a high frequency signal input terminal RFin, and a ground GND are provided.

FIG. 26 is a cross-sectional view of the module substrate 80 and the semiconductor device 81. The emitter bump 43E provided on the semiconductor device 81 is connected to the ground conductor 90 on the first surface of the module substrate 80 by solder 94. In addition to the semiconductor device 81, a plurality of surface mount elements 93 are mounted on the first surface of the module substrate 80. A plurality of via conductors 91 extend from the ground conductor 90 on the first surface in the thickness direction and reach the ground conductor 92 provided on the second surface opposite to the first surface. The emitter bump 43E and the plurality of via conductors 91 partially overlap each other in a plan view. The ground conductor 92 on the second surface is connected to a ground such as a motherboard. The ground of the motherboard or the like also functions as a heat sink.

Next, the excellent effect of the thirteenth embodiment will be described.
The emitter bump 43E, the solder 94, the ground conductor 90, the plurality of via conductors 91, and the ground conductor 92 serve as a heat dissipation path for conducting the heat generated in the plurality of transistor cells 30 of the output stage amplifier circuit 83 to the ground of the motherboard or the like. .. Since the emitter bump 43E and the plurality of via conductors 91 are arranged so as to overlap each other in a plan view, the thermal resistance of the heat dissipation path is lowered. As a result, the temperature rise of the transistor cell 30 can be suppressed.

Further, since the amplifier circuit of the semiconductor device according to any one of the first to twelfth embodiments is used for the output stage amplifier circuit 83, any of the first to twelfth embodiments. The same effect as the excellent effect obtained in the above embodiment can be obtained.

[14th Example]
Next, the amplifier module according to the 14th embodiment will be described with reference to FIG. 27. Hereinafter, the description of the configuration common to the amplifier modules (FIGS. 25A, 25B, 26) according to the thirteenth embodiment will be omitted.

FIG. 27 is a block diagram of the amplifier module according to the 14th embodiment. The amplifier module according to the thirteenth embodiment includes a module board 80 and a semiconductor device 81 mounted on the module board 80. In the thirteenth embodiment, the output stage amplifier circuit 83 is composed of a plurality of transistor cells 30 in which the output stage amplifier circuits 83 are connected in parallel to each other. However, in the fourteenth embodiment, the output stage amplifier circuit 83 is stacked in the first amplifier circuit. It is composed of 83A and a second amplifier circuit 83B. In the first amplifier circuit 83A and the second amplifier circuit 83B, the amplifier circuit of the semiconductor device according to any one of the first to twelfth embodiments is used.

The transistor of the first amplifier circuit 83A and the transistor of the second amplifier circuit 83B are cascode-connected via the capacitor C. The capacitor C connects the emitter of the transistor of the first amplifier circuit 83A and the collector of the transistor of the second amplifier circuit 83B in an alternating current manner, and disconnects them in a direct current manner.

The high frequency signal amplified by the first stage amplifier circuit 82 is input to the second amplifier circuit 83B via the interstage matching circuit 85. The output stage bias circuit 89 supplies the bias voltage and current to the transistor of the second amplifier circuit 83B based on the control signal input from the bias control terminal Vbias3. A DC power supply voltage is applied to the power supply terminal Vc (corresponding to the collector of the transistor) of the second amplifier circuit 83B via the inductor L4.

A DC power supply voltage is applied to the power supply terminal Vcc2 (corresponding to the collector of the transistor) of the first amplifier circuit 83A via the inductor L2. The ground terminal Ve (corresponding to the emitter bump 43E (FIG. 3)) of the first amplifier circuit 83A is connected to the ground via the inductor L3. The output stage bias circuit 88 supplies the bias voltage and the current to the transistor of the first amplifier circuit 83A based on the control signal input from the bias control terminal Vbias2.

The high-frequency signal amplified by the first amplifier circuit 83A and the second amplifier circuit 83B is output from the high-frequency signal output terminal RFout (collector terminal of the transistor of the first amplifier circuit 83A). The high-frequency signal output from the high-frequency signal output terminal RFout is output from the high-frequency signal output terminal RFout1 of the module board 80 via the output matching circuit 86 mounted on the module board 80.

Next, the excellent effect of the 14th embodiment will be described.
In the 14th embodiment, the maximum output power can be increased by cascode-connecting the transistors. Further, since the amplifier circuit of the semiconductor device according to any one of the first to twelfth embodiments is used for the first amplifier circuit 83A and the second amplifier circuit 83B, the first to twelfth embodiments are used. The same excellent effect as that obtained in any of the above examples can be obtained.

[15th Example]
Next, the semiconductor device according to the fifteenth embodiment will be described with reference to FIGS. 28A and 28B. Hereinafter, the description of the configuration common to the semiconductor device according to the first embodiment will be omitted.

FIG. 28A is an equivalent circuit diagram of the semiconductor device according to the fifteenth embodiment. A plurality of transistor cells 30 are connected to each other in parallel. Each collector and emitter of the plurality of transistor cells 30 is connected to the collector bump 43C and the emitter bump 43E, respectively. The bases of the plurality of transistor cells 30 are connected to the high frequency input wiring 42RF via the input capacitance element 31, respectively. Further, the bases of the plurality of transistor cells 30 are connected to the output stage bias circuit 88 via the base ballast resistance element 32, respectively.

The output stage bias circuit 88 includes a transistor Q2 that operates as an emitter follower transistor that applies a base bias voltage and a current to the transistor cell 30. For the transistor Q2, for example, an HBT is used. The emitter of the transistor Q2 is connected to the base ballast resistance element 32 via the resistance element R2. The collector of the transistor Q2 is connected to the bias voltage terminal Vbatt.

The transistor Q3 and the transistor Q4 are connected in series to form the temperature characteristic compensation circuit S1. For the transistors Q3 and Q4, for example, HBTs are used. Each of the transistors Q3 and Q4 is diode-connected and functions as a diode. Specifically, in each of the transistors Q3 and Q4, the collector and the base are short-circuited. The base of the transistor Q4 and the base of the transistor Q2 are connected to form a current mirror.

The bias control terminal Vbias2 is connected to the ground via the resistance element R7 and the temperature characteristic compensation circuit S1. The voltage applied to the bias control terminal Vbias2 is divided by the resistance element R7 and the temperature characteristic compensation circuit S1 and applied to the base of the transistor Q2. The base of the transistor Q2 is connected to the ground via the bypass capacitance element C1.

FIG. 28B is a diagram showing a planar positional relationship between a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, an emitter bump 43E, a collector bump 43C, and a transistor Q3 of the output stage bias circuit 88. The transistor Q3 is arranged in a cell row 33 composed of a plurality of transistor cells 30 in a region near the end portion 95 on an extension line extending from the end portion in the arrangement direction or an internal region 96 of the cell row 33.

Next, the operation of the output stage bias circuit 88 will be described. Since the transistor Q3 is arranged in the region near the end of the cell row 33 or the internal region 96, the transistor Q3 is thermally affected by the transistor cell 30. When the temperature of the transistor cell 30 rises, the temperature of the transistor Q3 also rises. As a result, the bias voltage applied to the base of the transistor Q2 decreases. When the bias voltage applied to the base of the transistor Q2 decreases, the bias voltage and current supplied to the base of the transistor cell 30 also decrease.

As described above, when the temperature of the transistor cell 30 rises, the temperature characteristic compensation circuit S1 lowers the bias voltage and the current supplied to the base of the transistor cell 30. As a result, the collector current of the transistor cell 30 decreases. Therefore, when the collector current increases as the temperature of the transistor cell 30 rises, the temperature characteristic compensation circuit S1 suppresses the increase in the collector current.

Next, the excellent effect of the fifteenth embodiment will be described.
In the fifteenth embodiment, since the transistor Q3 of the temperature characteristic compensation circuit S1 is arranged in the region near the end of the cell row 33 of the plurality of transistor cells 30 or the internal region 96, the transistor Q3 is the temperature of the transistor cell 30. Susceptible to rise. As a result, fluctuations in transistor characteristics when the temperature of the transistor cell 30 rises can be sufficiently compensated.

When the transistor Q3 is arranged in the end vicinity region 95 on the extension line of the cell row 33 or the internal region 96 of the cell row 33, the dimensions of the output stage amplifier circuit 83 in the direction orthogonal to the arrangement direction are hardly increased. When the transistor Q3 is arranged in the region near the end portion 95, it is preferable to arrange the transistor Q3 on the extension line of the shorter cell row 33. With this arrangement, it is possible to suppress an increase in the size of the region including the output stage amplifier circuit 83 and the transistor Q3 in the arrangement direction.

In order to enhance the temperature compensation effect, it is preferable that the center-to-center distance from the transistor Q3 to the nearest transistor cell 30 is set to be equal to or less than the pitch of the plurality of transistor cells 30.

Next, a modified example of the fifteenth embodiment will be described.
In the fifteenth embodiment, the transistor Q3 is arranged in the end vicinity region 95 or the internal region 96 of the cell row 33, but instead of the transistor Q3, the transistor Q4 is arranged in the end vicinity region 95 or the internal region 96. May be good. Further, both the transistor Q3 and the transistor Q4 may be arranged in the end vicinity region 95 or the internal region 96.

Next, another modification of the fifteenth embodiment will be described with reference to FIGS. 29A and 29B.
29A and 29B are equivalent circuit diagrams of the semiconductor device according to the modified example of the fifteenth embodiment. In these modifications, the configuration of the output stage bias circuit 88 is different from the configuration of the output stage bias circuit 88 of the semiconductor device according to the fifteenth embodiment. Also in the modification shown in FIG. 29A, the series connection circuit of the transistor Q3 and the transistor Q4 functions as the temperature characteristic compensation circuit S1. In the modified example shown in FIG. 29B, the transistor Q3 functions as the temperature characteristic compensation circuit S1.

In the modification shown in FIG. 29A, at least one of the transistor Q3 and the transistor Q4 is arranged in the end vicinity region 95 or the internal region 96 (FIG. 28B) of the cell row 33. In the modified example shown in FIG. 29B, the cells are arranged in the end vicinity region 95 or the internal region 96 (FIG. 28B) of the cell row 33. In these modified examples, the same excellent effects as those in the 15th embodiment can be obtained.

[16th Example]
Next, the semiconductor device according to the sixteenth embodiment will be described with reference to FIGS. 30 to 32. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 23) according to the eleventh embodiment will be omitted.

FIG. 30 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the sixteenth embodiment. Focusing on one transistor cell 30, in the eleventh embodiment, the base electrodes 40B are arranged on both sides of the emitter electrode 40E (FIG. 23) with respect to the arrangement direction of the transistor cell 30. On the other hand, in the 16th embodiment, focusing on one transistor cell 30, the base electrode 40B is arranged only on one side of the emitter electrode 40E in the arrangement direction.

In one transistor cell 30, the collector electrode 40C, the emitter electrode 40E, and the base electrode 40B are arranged in this order or in the reverse order in the arrangement direction. Further, two transistor cells 30 are arranged in one sub-collector layer 51.

In one transistor cell 30 and the other transistor cell 30 of the two transistor cells 30 adjacent to each other in the arrangement direction, the arrangement order of the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E is reversed. In the two transistor cells 30 arranged in one sub-collector layer 51, a pair of base electrodes 40B are arranged on the outermost side in the arrangement direction, a pair of emitter electrodes 40E are arranged on the inner side thereof, and one emitter electrode 40E is arranged on the inner side thereof. The collector electrode 40C is arranged. The collector electrode 40C is shared by the two transistor cells 30.

In the eleventh embodiment, the base electrodes 40B of the two transistor cells 30 (FIG. 23) arranged in the direction orthogonal to the arrangement direction are connected to one input capacitance element 31 and the base ballast resistance element 32. On the other hand, in the 16th embodiment, the input capacitance element 31 and the base ballast resistance element 32 are connected to each transistor cell 30.

Next, the excellent effect of the 16th embodiment will be described with reference to FIGS. 31A to 32. Three types of samples having different relative positional relationships between the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E were prepared, and the transition voltage at the SOA boundary and the voltage at the fracture boundary of these samples were measured. Here, SOA means a range of collector voltage and collector current in which a transistor can perform stable operation without self-damage. The transition voltage is defined as the collector voltage when the SOA line, which is the boundary of the SOA, drops sharply when the collector voltage is increased in the graph showing the relationship between the collector voltage and the collector current. The break boundary means the boundary of the collector voltage and collector current ranges in which the transistor does not break (short-circuit or open state).

31A, 31B, and 31C are diagrams showing the relative positional relationship between the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E in the transistor cell 30 of one of the three prepared samples.

In the sample shown in FIG. 31A (hereinafter referred to as sample A), the base electrodes 40B are arranged on both sides of the emitter electrode 40E in the arrangement direction, and the collector electrodes 40C are arranged on both sides thereof. This arrangement is, for example, the same as the arrangement in the semiconductor device (FIG. 1) according to the first embodiment. In the sample shown in FIG. 31B (hereinafter referred to as sample B), emitter electrodes 40E are arranged on both sides of the base electrode 40B in the arrangement direction, and collector electrodes 40C are arranged on both sides thereof. In the sample shown in FIG. 31C (hereinafter referred to as sample C), the collector electrode 40C, the emitter electrode 40E, and the base electrode 40B are arranged in this order in the arrangement direction.

FIG. 32 is a graph showing the measurement results of the transition voltage at the SOA boundary and the voltage at the fracture boundary of Sample A, Sample B, and Sample C. The horizontal axis represents the transition voltage at the SOA boundary in the unit "V", and the vertical axis represents the voltage at the fracture boundary in the unit "V".

Both the transition voltage at the SOA boundary and the voltage at the fracture boundary are higher in sample C than in sample A and sample B. The reason for this will be described below. In the sample A and the sample B, the operating current from the collector electrode 40C to the emitter electrode 40E flows in both the right direction and the left direction in the figure. In particular, in sample B, a current from the collector electrode 40C on the left side toward the emitter electrode 40E on the right side and a current from the collector electrode 40C on the right side toward the emitter electrode 40E on the left side are superimposed between the two emitter electrodes 40E. To. When the balance between the right-pointing operating current and the left-pointing operating current is lost, the left-right balance of the calorific value is lost. When the calorific value is out of balance and a temperature difference occurs, the operating current is concentrated more and more in the relatively high temperature region.

In the sample C, since only the operating current flowing to the right in FIG. 31C flows, it is not necessary to maintain the balance of the operating currents flowing in both directions, and the balance of the operating currents does not become unbalanced. Therefore, the left-right balance of the calorific value is not lost. As a result, it is considered that the SOA of the sample C is expanded and the breakdown pressure resistance is higher than that of the sample A and the sample B.

Further, in the sample A, the base electrodes 40B are arranged on both sides of the emitter electrode 40E, whereas in the sample B and the sample C, the base electrodes 40B are arranged only on one side of the emitter electrode 40E. From the results shown in FIG. 32, it can be seen that the voltage at the fracture boundary is higher in the sample B and the sample C than in the sample A. Therefore, in order to increase the voltage at the fracture boundary, it is preferable to adopt a configuration in which the base electrode 40B is arranged on only one side of the emitter electrode 40E.

In the 16th embodiment, since the base electrode 40B is arranged only on one side of the emitter electrode 40E, the SOA is expanded and the fracture withstand voltage is high as compared with the configurations of the sample A and the sample B as in the sample C. An excellent effect can be obtained.

Further, in the 16th embodiment, since one collector electrode 40C is shared by the two transistor cells 30, the chip size can be reduced as compared with the configuration in which the collector electrodes 40C are arranged for each transistor cell 30. ..

Next, a modified example of the 16th embodiment will be described.
In the 16th embodiment, the collector electrode 40C, the emitter electrode 40E, and the base electrode 40B are arranged in this order in the arrangement direction or in the reverse order. That is, the emitter electrode 40E is arranged between the collector electrode 40C and the base electrode 40B. In addition, the collector electrode 40C, the base electrode 40B, and the emitter electrode 40E may be arranged in this order in the arrangement direction or in the reverse order. That is, the base electrode 40B may be arranged between the collector electrode 40C and the emitter electrode 40E.

Further, in the 16th embodiment, the input capacitance element 31 and the base ballast resistance element 32 are connected to each transistor cell 30, but they are arranged in a direction orthogonal to the arrangement direction as in the 11th embodiment (FIG. 23). One input capacitance element 31 and a base ballast resistance element 32 may be connected to two transistor cells 30.

[17th Example]
Next, the semiconductor device according to the 17th embodiment will be described with reference to FIG. 33. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 30) according to the 16th embodiment will be omitted.

FIG. 33 is a diagram showing a planar arrangement of four transistor cells of the semiconductor device according to the seventeenth embodiment. Similar to the case of the 16th embodiment, in each of the transistor cells 30, the collector electrode 40C, the emitter electrode 40E, and the base electrode 40B are arranged in this order or in the reverse order in the arrangement direction. Two transistor cells 30 are arranged in one sub-collector layer 51. The two transistor cells 30 share one collector electrode 40C arranged in the center in the arrangement direction.

The collector lead-out wiring 41C is drawn out from the collector electrode 40C in a direction orthogonal to the arrangement direction. The base lead-out wiring 41B is drawn out from the base electrode 40B in a direction orthogonal to the arrangement direction. The emitter wiring 41E of the first layer is arranged so as to substantially overlap the emitter electrode 40E in a plan view. In FIG. 33, the collector electrode 40C, the emitter electrode 40E, and the base electrode 40B are hatched with relatively high density upward to the right, and are relative to the collector lead wiring 41C, the base lead wiring 41B, and the emitter wiring 41E. Has a low-density downward-sloping hatch.

The distance LE1 between the two emitter electrodes 40E arranged in one sub-collector layer 51 and the distance LE2 between the emitter electrodes 40E arranged in the two adjacent sub-collector layers 51 in the arrangement direction are equal to each other. In other words, the emitter electrodes 40E are arranged at equal intervals in the arrangement direction. The interval LE1 and the interval LE2 are, for example, 10 μm or more and 25 μm or less.

For example, since the collector electrode 40C is not arranged between the two emitter electrodes 40E arranged in the adjacent sub-collector layers 51, the interval LE2 can be made narrower than the interval LE1. In the 17th embodiment, the interval LE2 is not narrowed and is substantially equal to the interval LE1.

Next, the excellent effect of the 17th embodiment will be described.
During the operation of the transistor cell 30, heat is generated mainly in the region where the emitter electrode 40E is arranged in a plan view. In the 17th embodiment, since the emitter electrodes 40E are arranged at equal intervals in the arrangement direction, the temperature difference between the transistor cells 30 can be reduced as compared with the configuration in which the heat generating region is localized at a specific location. it can. Further, as compared with the configuration in which the interval LE2 is narrower than the interval LE1, the distribution density of the heat generation region is lower as a whole, so that the temperature rise of the transistor cell 30 can be suppressed. As a result, it is possible to suppress a decrease in gain due to an increase in temperature.

Next, a modified example of the 17th embodiment will be described.
In the 17th embodiment, the interval LE2 is made substantially equal to the interval LE1, but even if the two are different, if the difference is small, almost the same effect as when the two are equal can be obtained. For example, the smaller of the interval LE1 and the interval LE2 may be halved or more of the larger one.

[18th Example]
Next, the semiconductor device according to the 18th embodiment will be described with reference to FIGS. 34, 35A, and 5B. Hereinafter, the description of the configuration common to the semiconductor device according to the first embodiment shown in the drawings of FIGS. 1 to 3 will be omitted.

FIG. 34 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the eighteenth embodiment. FIG. 35A is a cross-sectional view taken along the alternate long and short dash line 35A-35A of FIG. 34. In the first embodiment (FIG. 2B), the emitter bump 43E is directly arranged on the emitter wiring 42E of the second layer. On the other hand, in the eighteenth embodiment, as shown in FIG. 35A, the third layer emitter wiring 47E is arranged between the second layer emitter wiring 42E and the emitter bump 43E.

As shown in FIG. 34, the emitter wiring 47E of the third layer has the emitter region 30E to the other end of the transistor cell 30 at one end of the cell row 33 with respect to the arrangement direction of the transistor cells 30 (horizontal direction in FIG. 34). It is arranged over the range up to the emitter region 30E of the transistor cell 30 of the above. Further, with respect to the direction orthogonal to the arrangement direction of the transistor cells 30 (vertical direction in FIG. 34), from the emitter region 30E of the transistor cell 30 of one cell row 33 to the emitter region 30E of the transistor cell 30 of the other cell row 33. It is arranged over a range.

Two emitter bumps 43E are arranged for each cell row 33, as in the first embodiment (FIG. 1). Each emitter region 30E of the plurality of transistor cells 30 is included in any of the emitter bumps 43E in a plan view.

Similar to the first embodiment (FIG. 1), the plurality of collector lead wiring 41Cs are included in the two cell rows 33 in the direction orthogonal to the arrangement direction (vertical direction in FIG. 34) from the plurality of transistor cells 30. It is pulled out from one cell row 33 (lower cell row 33 in FIG. 34) to the outside. Two cells in a direction (upward in FIG. 34) in which the plurality of base lead-out wires 41B are orthogonal to the arrangement direction from the plurality of transistor cells 30 and the direction in which the plurality of collector lead-out wires 41C are drawn out. It is pulled out from the other cell row 33 (upper cell row 33 in FIG. 34) of the row 33.

Collector lead-out wiring 41C is provided on both sides or one side of the base lead-out wiring 41B drawn from one cell row 33 (lower cell row 33 in FIG. 34) toward the other cell row 33 (upper cell row 33). Have been placed. A part of each of the base lead-out wiring 41B and the collector lead-out wiring 41C adjacent to each other in the arrangement direction of the plurality of transistor cells 30 is arranged at the same position in the direction orthogonal to the arrangement direction, and both run in parallel. The portion in which both run in parallel is referred to as a parallel running portion 100. The parallel running portion 100 of the base lead-out wiring 41B and the collector lead-out wiring 41C is included in the emitter wiring 47E of the third layer in a plan view.

Next, the excellent effect of the 18th embodiment will be described. In the 18th embodiment as well, as in the 1st embodiment, the effect of reducing the parasitic inductance from the collector bump 43C to the transistor cell 30, the effect of reducing the area occupied by the amplifier circuit on the substrate, and the effect of reducing the area occupied by the amplifier circuit, and the transistor cell 30 The effect of reducing the thermal resistance of the heat dissipation path of the above can be obtained.

Next, with reference to FIG. 35B, other excellent effects of the 18th embodiment will be described.
FIG. 35B is a schematic cross-sectional view taken along the alternate long and short dash line 35B-35B of FIG. 34. The base lead-out wiring 41B and the collector lead-out wiring 41C are arranged between the substrate 50 and the emitter wiring 47E of the third layer. The third layer emitter wiring 47E is connected to the ground.

The third layer emitter wiring 47E arranged in the vicinity of the base lead-out wiring 41B and the collector lead-out wiring 41C has a function of shielding the magnetic field generated by the high-frequency current flowing through the base lead-out wiring 41B and the collector lead-out wiring 41C. Therefore, it is possible to reduce the magnetic interaction that may occur between the base lead-out wiring 41B and the collector lead-out wiring 41C. Further, the magnetic field shielding effect can reduce the parasitic inductance of each of the base lead-out wiring 41B and the collector lead-out wiring 41C.

Next, a modification of the 18th embodiment will be described with reference to FIGS. 36 and 37.
36 and 37 are views showing the planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the modified example of the 18th embodiment. Is.

In the eighteenth embodiment (FIG. 34), two emitter bumps 43E are arranged for each cell row 33, and a total of four emitter bumps 43E are arranged for the two cell rows 33. On the other hand, in the modified example shown in FIG. 36, two emitter bumps 43E are arranged in the arrangement direction of the transistor cells 30, and each of the emitter bumps 43E is a plurality of transistor cells 30 in one cell row 33. It is continuously arranged over the range from the emitter region 30E to the emitter region 30E of the plurality of transistor cells 30 in the other cell row 33. In the modified example shown in FIG. 37, one emitter bump 43E is arranged for two cell rows 33. In each modification, each emitter electrode 40E of the plurality of transistor cells 30 is included in any of the emitter bumps 43E in a plan view.

As in the modified examples shown in FIGS. 36 and 37, the number and arrangement of the emitter bumps 43E may be changed with respect to the 18th embodiment (FIG. 34).

[19th Example]
Next, the semiconductor device according to the 19th embodiment will be described with reference to FIGS. 38 and 39. Hereinafter, the description of the configuration common to the semiconductor device (FIGS. 34 and 35A) according to the 18th embodiment will be omitted.

FIG. 38 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the 19th embodiment. In the 18th embodiment (FIG. 34), the collector intermediate grouping wiring 42CH is arranged as in the first embodiment (FIG. 1), but in the 19th embodiment, the collector intermediate grouping wiring is not arranged.

In the 19th embodiment, the second layer emitter wiring 42E is arranged in the region where the collector intermediate group wiring 42CH is arranged in the first embodiment and the 18th embodiment. More specifically, the second layer emitter wiring 42E is continuously arranged over the range from one cell row 33 to the other cell row 33. A third layer emitter wiring 47E is arranged between the emitter bump 43E and the second layer emitter wiring 42E as in the eighteenth embodiment (FIG. 35A).

Next, the excellent effect of the 19th embodiment will be described.
In the 19th embodiment, since the collector intermediate group wiring 42CH (FIGS. 1 and 34) is not arranged, the effect obtained by arranging the collector intermediate group wiring 42CH, that is, the parasitism from the collector bump 43C to the transistor cell 30 The effect of reducing the inductance cannot be obtained. However, in the 19th embodiment as well, as in the 1st embodiment, the effect of reducing the area occupied by the amplifier circuit on the substrate and the effect of reducing the thermal resistance of the heat dissipation path from the transistor cell 30 can be obtained.

Next, with reference to FIG. 39, other excellent effects of the 19th embodiment will be described.
FIG. 39 is a schematic view showing a cross section of the alternate long and short dash line 39-39 of FIG. 38. In the eighteenth embodiment (FIG. 35B), the third layer emitter wiring 47E is arranged on the base lead-out wiring 41B and the collector lead-out wiring 41C. On the other hand, in the 19th embodiment, as shown in FIG. 39, both the second layer emitter wiring 42E and the third layer emitter wiring 47E are arranged on the base leader wiring 41B and the collector leader wiring 41C. ing.

Therefore, the distance from the base lead-out wiring 41B and the collector lead-out wiring 41C to the ground conductor (emitter wiring 42E of the second layer) is shorter in the 19th embodiment than in the 18th embodiment (FIG. 35B). .. As a result, the effect of shielding the magnetic field by the ground conductor appears more strongly. As a result, the effect of reducing the magnetic interaction that may occur between the base lead-out wiring 41B and the collector lead-out wiring 41C, and the effect of reducing the parasitic inductance of the base lead-out wiring 41B and the collector lead-out wiring 41C are achieved. It will be larger than the examples.

Next, a modified example of the 19th embodiment will be described with reference to FIGS. 40, 41 and 42.
40, 41, and 42 show a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. that constitute an amplifier circuit of a semiconductor device according to a modification of the 19th embodiment. It is a figure which shows.

In the 19th embodiment (FIG. 38), two emitter bumps 43E are arranged for each cell row 33, and a total of four emitter bumps 43E are arranged for the two cell rows 33. On the other hand, in the modified example shown in FIG. 40, two emitter bumps 43E are arranged in the arrangement direction of the transistor cells 30, and each of the emitter bumps 43E is a plurality of transistor cells 30 in one cell row 33. It is continuously arranged over the range from the emitter region 30E to the emitter region 30E of the plurality of transistor cells 30 in the other cell row 33. In the modified example shown in FIG. 41, one emitter bump 43E is arranged for two cell rows 33. In each modification, each emitter region 30E of the plurality of transistor cells 30 is included in any of the emitter bumps 43E in a plan view.

In the 19th embodiment, it is necessary to secure the minimum distance based on the process rule between the two emitter bumps 43E in the direction orthogonal to the arrangement direction of the transistor cells 30. Since the spacing of the cell rows 33 is set according to the spacing of the emitter bumps 43E, the minimum spacing of the cell rows 33 is also constrained by the minimum spacing based on the process rules of the process of forming the emitter bumps 43E.

On the other hand, in the modified examples shown in FIGS. 40 and 41, since the plurality of emitter bumps 43E are not arranged in the direction orthogonal to the arrangement direction of the transistor cells 30, 2 compared to the 19th embodiment (FIG. 38). The spacing between the cell rows 33 of the book can be narrowed. When the distance between the two cell rows 33 is narrowed, the parallel running portion 100 of the base lead-out wiring 41B and the collector lead-out wiring 41C becomes shorter. Therefore, the effect of reducing the magnetic interaction that may occur between the base lead-out wiring 41B and the collector lead-out wiring 41C and the effect of reducing the parasitic inductance of the base lead-out wiring 41B and the collector lead-out wiring 41C are the eighteenth. It will be larger than the examples.

In the modified example shown in FIG. 42, in a plan view, a part of each of the emitter regions 30E of the plurality of transistor cells 30 protrudes to the outside of the emitter bump 43E. By adopting this positional relationship, it is possible to obtain the effect that the influence of the stress generated on the emitter bump 43E when flip-chip bonding the semiconductor device to the module substrate or the like is less likely to reach the transistor cell 30.

In the modified example shown in FIG. 42, the cross-sectional area of the heat dissipation path of the heat generated in the transistor cell 30 is smaller than that in the modified examples of FIGS. 41 and 42. Therefore, from the viewpoint of reducing the thermal resistance, the modified example shown in FIGS. 40 and 41 is more advantageous than the modified example shown in FIG. 42.

[20th Example]
Next, the semiconductor device according to the twentieth embodiment will be described with reference to FIGS. 43 and 44. Hereinafter, the description of the configuration common to the semiconductor device (FIG. 38) according to the 19th embodiment will be omitted.

FIG. 43 is a diagram showing a planar arrangement of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, etc. constituting the amplifier circuit of the semiconductor device according to the twentieth embodiment. In the 19th embodiment (FIG. 38), as in the 18th embodiment (FIG. 35A), the third layer emitter wiring 47E is arranged between the second layer emitter wiring 42E and the emitter bump 43E. .. On the other hand, in the 20th embodiment, as in the 1st embodiment (FIG. 2B), the emitter wiring of the third layer is not arranged, and the emitter bump 43E directly contacts the emitter wiring 42E of the second layer. ing.

FIG. 44 is a schematic view showing a cross section of the alternate long and short dash line 44-44 of FIG. 43. In the 20th embodiment as well, the second layer emitter wiring 42E is arranged on the base lead-out wiring 41B and the collector lead-out wiring 41C as in the 19th embodiment (FIG. 39). The third layer emitter wiring 47E (FIG. 39) is not arranged.

Next, the excellent effect of the twentieth embodiment will be described.
In the 20th embodiment as well, as in the 19th embodiment, the effect of reducing the area occupied by the amplifier circuit on the substrate and the effect of reducing the thermal resistance of the heat dissipation path from the transistor cell 30 can be obtained. Further, as shown in FIG. 44, since the second layer emitter wiring 42E is arranged on the base lead-out wiring 41B and the collector lead-out wiring 41C, the base drawer is similarly formed in the 19th embodiment (FIG. 39). The effect of reducing the magnetic interaction that may occur between the wiring 41B and the collector lead wiring 41C and the effect of reducing the parasitic inductance of the base lead wiring 41B and the collector lead wiring 41C are compared with those of the 18th embodiment. growing.

Next, a modified example of the twentieth embodiment will be described with reference to FIGS. 45, 46, and 47.
45, 46, and 47 show planar arrangements of a plurality of transistor cells 30, an input capacitance element 31, a base ballast resistance element 32, wiring, bumps, and the like that constitute an amplifier circuit of a semiconductor device according to a modified example of the twentieth embodiment. It is a figure which shows.

In the modified examples shown in FIGS. 45, 46, and 47, the arrangement of the emitter bumps 43E is the emitter bump 43E of the semiconductor device according to the modified example of the 19th embodiment shown in FIGS. 40, 41, and 42, respectively. Is the same as the arrangement of. In the modified examples shown in FIGS. 45, 46, and 47, the distance between the two cell rows 33 is narrower than that in the 20th embodiment (FIG. 43). Therefore, the effect of reducing the magnetic interaction that may occur between the base lead-out wiring 41B and the collector lead-out wiring 41C is similar to the modification of the 19th embodiment shown in FIGS. 40, 41, and 42. The effect of reducing the parasitic inductance of the base lead-out wiring 41B and the collector lead-out wiring 41C is greater than that of the 20th embodiment.

Further, from the viewpoint of the stress applied to the transistor cell 30, the modified example shown in FIG. 47 is advantageous, and from the viewpoint of heat dissipation, the modified example shown in FIGS. 45 and 46 is advantageous.

It goes without saying that each of the above embodiments is exemplary and the configurations shown in different examples can be partially replaced or combined. Similar effects and effects due to the same configuration of a plurality of examples will not be mentioned sequentially for each example. Furthermore, the present invention is not limited to the above-mentioned examples. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

30 Transistor cell 30B Base area 30C Collector area 30E Emitter area 31 Input capacitance element 32 Base ballast resistance element 33 Cell rows 34, 35, 36 Opening 37 Row-to-row pair 40B Base electrode 40C Collector electrode 40E Emitter electrode 41B Base lead wiring 41BC Base control Wiring 41C Collector lead wiring 41CI Collector collective wiring 41E 1st layer emitter wiring 42C 2nd layer collector wiring 42CH Collector intermediate collective wiring 42E 2nd layer emitter wiring 42E1 Cell row connection part 42E2 Cell row connection part 42RF High frequency input Wiring 43C Collector bump 43E Emitter bump 44, 45, 46 Opening 47E Third layer emitter wiring 50 Board 51 Sub-collector layer 61 Base control terminal 62 High frequency input terminal 70 Module board conductor pattern 71 Module board via conductor 72 Module board Conductor pattern 80 Module board 81 Semiconductor device 82 First stage amplifier circuit 83 Output stage amplifier circuit 83A First stage amplifier circuit 83B Second amplification circuit 84 Input matching circuit 85 Interstage matching circuit 86 Output matching circuit 87 First stage bias circuit 88, 89 Output stage Bias circuit 90 Ground conductor 91 Via conductor 92 Ground conductor 93 Surface mount element 94 Solder 95 Area near the end of the cell row 96 Internal area of the cell row 100 Parallel running area

Claims (26)

With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings connected to the collector regions of the plurality of transistor cells and drawn out in a direction intersecting the arrangement direction of the plurality of transistor cells.
The collector collective wiring that connects the plurality of collector lead wiring to each other, and
The plurality of collector lead wires arranged between the two cell rows in a plan view and drawn from the plurality of transistor cells belonging to one of the two cell rows are connected to each other. A semiconductor device having a collector intermediate wiring. It further has an emitter wiring arranged in the same layer as the layer in which the collector intermediate collective wiring is arranged.
The emitter wiring includes a cell row connecting portion arranged corresponding to each of the two cell rows and a cell row connecting portion connecting the cell row connecting portions to each other, and the cell row The semiconductor device according to claim 1, wherein the internal connection portion is connected to the emitter region of a plurality of transistor cells in the corresponding cell row. Further, each of the two cell rows has at least one emitter bump that partially overlaps with the plurality of transistor cells in the corresponding cell row in plan view, and the at least one emitter bump. The semiconductor device according to claim 1 or 2, wherein is connected to the emitter region of the plurality of transistor cells in the corresponding cell row. The semiconductor device according to claim 3, wherein at least one emitter bump corresponding to at least one of the two cell rows is composed of a plurality of emitter bumps separated in the arrangement direction. The number of transistor cells to which one emitter bump corresponding to one of the two cell rows is connected and the number of transistor cells to which one emitter bump corresponding to the other cell row is connected. One emitter bump and the other emitter bump include overlapping portions in the arrangement direction, and one emitter bump and the other emitter bump are oriented in opposite directions from the overlapping portion. The semiconductor device according to claim 3 or 4, which is stretched to. The two cell rows have different lengths, and a plurality of emitter bumps separated in the arrangement direction are arranged corresponding to the longer cell row, and correspond to the shorter cell row. The semiconductor device according to claim 4, wherein one emitter bump that is not separated is arranged. The collector group wiring is arranged on the side opposite to the other cell row when viewed from one of the two cell rows in a plan view.
The plurality of collector extraction wires drawn from the plurality of transistor cells in the cell row farther from the collector group wiring among the two cell rows cross the region between the two cell rows. The semiconductor device according to any one of claims 1 to 6, which is connected to the collector collective wiring and is connected to each other by the collector intermediate collective wiring. The semiconductor according to claim 7, further comprising at least one input capacitance element arranged on the side opposite to the collector collective wiring when viewed from the two cell rows and connected to the base region of the plurality of transistor cells. apparatus. The semiconductor device according to claim 8, wherein the input capacitance elements are provided corresponding to each of the plurality of transistor cells and are arranged in a row in the arrangement direction. The input capacitance element is provided for each row-to-row pair consisting of one transistor cell in one cell row of the two cell rows and one transistor cell in the other cell row, and is provided in the arrangement direction. The semiconductor device according to claim 8, which is arranged in one row. The semiconductor device according to claim 8, wherein the input capacitance element is provided once for all the transistor cells in the two cell rows. At least a part of the plurality of transistor cells in one of the two cell rows and at least a part of the plurality of transistor cells in the other cell row are the plurality of transistors in the same cell row. Each basic unit consisting of cells is arranged alternately in the above-mentioned arrangement direction.
The semiconductor device according to claim 8, wherein the input capacitance elements are arranged for each of the basic units, and the plurality of input capacitance elements are arranged in a row in the arrangement direction. At least a part of the plurality of transistor cells in one of the two cell rows and at least a part of the plurality of transistor cells in the other cell row are said to be one or the same cell row. Each basic unit consisting of a plurality of transistor cells is alternately arranged in the above-mentioned arrangement direction.
The plurality of collector extraction wires drawn from the plurality of transistor cells in the cell row farther from the collector bundle wiring are between the transistor cells in the cell row closer to the collector bundle wiring or from the transistor cells at both ends. The semiconductor device according to claim 7 or 8, which is connected to the collector collective wiring through the outside. The plurality of transistor cells in one of the two cell rows are arranged at the same positions as the plurality of transistor cells in the other cell row of the two cell rows in the arrangement direction. Ori,
The semiconductor device according to claim 7, wherein each of the plurality of collector lead wires is shared by two transistor cells arranged at the same position with respect to the arrangement direction. The semiconductor device according to claim 14, wherein each of the plurality of collector lead wires is arranged between two transistor cells adjacent to each other in the arrangement direction and shared by the transistor cells on both sides. Further, a base lead-out wiring that is connected to the base region of the plurality of transistor cells, is drawn out from the transistor cell to the side opposite to the side on which the collector lead-out wiring is arranged, and then extends in a direction orthogonal to the arrangement direction. Have and
The semiconductor device according to claim 14 or 15, wherein a portion of the base lead-out wiring extending in a direction orthogonal to the arrangement direction is shared by transistor cells arranged at the same position with respect to the arrangement direction. In the two transistor cells adjacent to each other in the arrangement direction, the positional relationship between the transistor cell, the corresponding collector lead wiring, and the corresponding base lead out wiring in the arrangement direction is mirror-symmetrical.
The semiconductor device according to claim 16, wherein a portion of the base lead-out wiring extending in a direction orthogonal to the arrangement direction is shared by transistor cells on both sides. Further, a collector electrode, a base electrode, and an emitter electrode connected to each of the collector region, the base region, and the emitter region of the plurality of transistor cells are provided.
In each of the plurality of transistor cells, the collector electrode, the base electrode, and the emitter electrode are arranged in the order of the collector electrode, the base electrode, the emitter electrode, or the collector electrode, the emitter electrode, and the base electrode in the arrangement direction. And
The semiconductor device according to any one of claims 1 to 17, wherein the collector electrodes of the plurality of transistor cells are connected to the collector lead wiring. In the two transistor cells adjacent to each other in the arrangement direction, the arrangement order of the collector electrode, the base electrode, and the emitter electrode is reversed, and the collector electrode of the two transistor cells adjacent to each other in the arrangement direction is the emitter electrode and the base. The semiconductor device according to claim 18, wherein a collector electrode is shared by two transistor cells located inside the electrodes. In the two transistor cells adjacent to each other in the arrangement direction, the smaller of the distance between the two emitter electrodes having the collector electrode arranged between them and the distance between the two emitter electrodes having no collector electrode arranged between them is the smaller one. The semiconductor device according to claim 19, which is ½ or more of the larger one. The semiconductor device according to claim 19, wherein the emitter electrodes of the plurality of transistor cells are arranged at equal intervals in the arrangement direction. It includes a semiconductor device and a module substrate on which the semiconductor device is mounted.
The semiconductor device is
With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings connected to the collector regions of the plurality of transistor cells and drawn out in a direction intersecting the arrangement direction of the plurality of transistor cells.
The collector collective wiring that connects the plurality of collector lead wiring to each other, and
A collector intermediate that is arranged between the two cell rows in a plan view and connects the plurality of collector lead wires drawn from a plurality of transistor cells belonging to one of the two cell rows to each other. Summary wiring and
It has at least one emitter bump for each of the two cell rows.
The module board is
A ground conductor connected to the emitter bump of the semiconductor device,
An amplifier module having a via conductor extending from the ground conductor in the thickness direction and reaching a surface opposite to the surface on which the ground conductor is provided. With the board
Two cell rows, each containing a collector region, a base region, and an emitter region provided on the substrate, each consisting of a plurality of transistor cells arranged in parallel with each other.
A plurality of collector lead wirings that are connected to the collector regions of the plurality of transistor cells and are drawn out to the outside of one of the two cell rows in a direction orthogonal to the arrangement direction of the plurality of transistor cells. When,
The two cell rows are connected to the base regions of the plurality of transistor cells, respectively, orthogonal to the arrangement direction of the plurality of transistor cells, and in the direction opposite to the direction in which the plurality of collector extraction wires are drawn out. Multiple base lead-out wires pulled out to the outside of the other cell row,
It has a plurality of base lead-out wirings and an emitter wiring arranged in a wiring layer above the plurality of collector-leading wirings and connected to the emitter region.
Of the base lead-out wiring and collector lead-out wiring adjacent to each other in the arrangement direction of the plurality of transistor cells, the portion arranged at the same position in the direction orthogonal to the arrangement direction of the plurality of transistor cells is the emitter wiring in a plan view. Semiconductor devices included in. The semiconductor device according to claim 23, wherein the emitter regions of the plurality of transistor cells are included in the emitter wiring in a plan view. Further, it has at least one emitter bump arranged on the emitter wiring.
The emitter bumps are arranged over a range from the emitter region of the transistor cells in one cell row to the emitter region of the transistor cells in the other cell row with respect to the direction orthogonal to the arrangement direction of the plurality of transistor cells. The semiconductor device according to claim 23 or 24. Further, it is arranged between the two cell rows in a plan view, is drawn from the plurality of transistor cells in one of the two cell rows, and passes between the two cell rows. It has a collector intermediate group wiring that connects a plurality of the collector lead wirings to each other.
The semiconductor device according to any one of claims 23 to 25, wherein the emitter wiring is arranged in a wiring layer above the collector intermediate group wiring.

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