JP2019220669A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of alleviating a thermal stress generated in a transistor portion, suppressing an increase in an element dimension, and suppressing a decrease in heat dissipation.SOLUTION: A first wiring is arranged above operation regions of a plurality of unit transistors formed on a substrate, and a second wiring is arranged above the substrate. An insulation film is arranged on the first wiring and the second wiring. In a plan view, the insulation film is provided with a first opening whose whole area overlaps the first wiring and a second opening overlapping the second wiring. A first bump arranged on the insulation film is connected to the first wiring through the first opening, and a second bump is connected to the second wiring through the second opening. In the plan view, at least one operation region among a plurality of operation regions is arranged inside the first bump, and at least one region among a plurality of operation regions arranged inside the first bump is arranged outside the first opening. A planar shape of the first opening is equal to a planar shape of the second opening.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art A heterojunction bipolar transistor (HBT) is used in a power amplifier module of a portable terminal or the like. Patent Document 1 listed below discloses a semiconductor device in which bumps are arranged immediately above an HBT. The bump is electrically connected to the HBT through an opening provided in an insulating film disposed between the HBT and the bump. The entire HBT is arranged inside the opening provided in the insulating film below the bump. With such a configuration, the distance from the HBT to the bump is reduced, and as a result, the thermal resistance of the heat flow path from the HBT to the bump can be reduced.

  With this configuration, thermal stress due to the difference between the coefficient of thermal expansion of the emitter layer of the HBT and the like and the coefficient of thermal expansion of the bump is likely to be generated in the emitter layer and the like. This thermal stress reduces the reliability of the HBT.

  Patent Literature 2 below discloses a semiconductor device capable of relaxing thermal stress. In this semiconductor device, the emitter layer of the HBT has a substantially rectangular planar shape, and an opening provided in the insulating film below the bump is arranged at a position shifted from the emitter layer of the HBT in the longitudinal direction. I have. By employing this configuration, the thermal stress generated in the emitter layer and the like is reduced as compared with the case where the entire area of the emitter layer is arranged inside the opening.

JP 2003-77930 A Japanese Patent No. 5967317

  In the semiconductor device disclosed in Patent Document 2, the opening is shifted from the emitter layer in the longitudinal direction of the emitter layer, and a part of the emitter layer extends to the outside of the bump. If the amount of displacement between the emitter layer and the opening is increased to reduce thermal stress, the heat dissipation will be reduced. In addition, the size of the element increases in the longitudinal direction of the emitter layer, which leads to an increase in manufacturing cost.

  An object of the present invention is to provide a semiconductor device capable of relaxing thermal stress generated in a transistor portion of a semiconductor device, suppressing an increase in element size, and suppressing a decrease in heat dissipation.

According to one aspect of the invention,
A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A first wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
A second wiring disposed above the substrate;
An insulating film disposed on the first wiring and the second wiring, wherein at least one first opening that overlaps the first wiring and a second opening that overlaps the second wiring in an entire area in plan view. Said insulating film provided;
A first bump disposed on the insulating film and electrically connected to the first wiring through the first opening;
A second bump disposed on the insulating film and electrically connected to the second wiring through the second opening;
In a plan view, at least one of the plurality of operation regions is arranged inside the first bump, and at least one of the operation regions arranged inside the first bump is operated. At least a part of the region is disposed outside the first opening,
A semiconductor device is provided in which the planar shape of the first opening is equal to the planar shape of the second opening.

  By arranging the insulating film, thermal stress generated in the operation region can be reduced. Furthermore, by arranging the operation area inside the first bump in plan view, it is possible to suppress an increase in the size of the element. Heat can be conducted from the operation region to the first bump through the first opening, and heat radiation can be ensured. Further, since the planar shapes of the first opening and the second opening are equal, when the first bump and the second bump are formed by the plating method, the filling in the first opening and the second opening is made uniform. As a result, the manufacturing yield is improved, and the manufacturing cost can be reduced.

FIG. 1A is a diagram illustrating a planar layout of components of the semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along a dashed line 1B-1B in FIG. 1A. FIG. 2 is a diagram showing a planar layout of components of the semiconductor device according to the second embodiment. FIG. 3 is a sectional view taken along dashed line 3-3 in FIG. FIG. 4 is a sectional view taken along dashed line 4-4 in FIG. FIG. 5A and FIG. 5B are plan views illustrating the positional relationship between the operation region, the opening, and the pillar bump of the semiconductor devices according to the comparative example and the example, respectively. FIG. 6A is a graph showing the relationship between the shift amounts Dx and Dy and the amount of thermal stress generated in the emitter region, and FIG. 6B is a graph showing the relationship between the shift amounts Dx and Dy and the increase amount of the thermal resistance. It is a graph. FIG. 7 is a diagram showing a planar layout of components of the semiconductor device according to the third embodiment. FIG. 8 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fourth embodiment. FIG. 9 is an equivalent circuit diagram of the transistor Q2 and its peripheral circuits. FIG. 10 is a diagram showing a layout of each element of a semiconductor chip constituting a semiconductor device according to the fourth embodiment. FIG. 11A is a diagram showing a pillar bump, an operating region of a plurality of unit transistors connected thereto, and a positional relationship of a plurality of openings, and FIG. 11B is a diagram showing a circular pillar bump and an opening of an opening arranged thereunder. It is a figure showing a positional relationship. FIG. 12 is a sectional view of a semiconductor device according to the fourth embodiment. FIG. 13 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fifth embodiment. FIG. 14 is a diagram showing a layout of each element of a semiconductor chip constituting a semiconductor device according to the fifth embodiment. FIG. 15 is a diagram showing a positional relationship between pillar bumps, operation regions of unit transistors, and openings. FIGS. 16A, 16B, 16C, and 16D are views showing the positional relationship between the operation region and the opening of the unit transistor of the semiconductor device according to the sixth embodiment and its modification. FIGS. 17A, 17B, 17C, and 17D are diagrams each showing a positional relationship between an operation region of a unit transistor and an opening of a semiconductor device according to a modification of the sixth embodiment. FIG. 18 is a sectional view of the semiconductor device according to the seventh embodiment. FIG. 19 is a sectional view of a semiconductor device according to the eighth embodiment. FIG. 20 is a sectional view of the semiconductor device according to the ninth embodiment. FIG. 21 is a diagram showing a planar layout of components of the semiconductor device according to the ninth embodiment. FIG. 22 is a diagram showing a planar layout of four unit transistors arranged in one row of the semiconductor device according to the ninth embodiment. FIG. 23 is a sectional view of the semiconductor device according to the tenth embodiment. FIG. 24 is a diagram showing a planar layout of components of the semiconductor device according to the tenth embodiment. FIG. 25A is a cross-sectional view of a semiconductor device to be simulated according to the eleventh embodiment, and FIG. is there. 26A, 26B, and 26C are diagrams illustrating the positional relationship between pillar bumps, openings, and operation regions of a semiconductor device according to the twelfth embodiment and its modification. FIGS. 27A and 27B are diagrams showing a positional relationship among pillar bumps, openings, and operation regions of a semiconductor device according to a modification of the twelfth embodiment.

[First embodiment]
A semiconductor device according to a first embodiment will be described with reference to FIGS. 1A and 1B.
FIG. 1A is a diagram illustrating a planar layout of components of the semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along a dashed line 1B-1B in FIG. 1A.

  A plurality, for example, six unit transistors 60 are formed on the substrate 30 (FIG. 1B). Each of unit transistors 60 includes an operation region 61 through which an operation current flows. For example, the unit transistor 60 includes a collector layer, a base layer, and an emitter layer that are sequentially stacked, and a region where an emitter current and a collector current substantially flow can be referred to as an operation region 61.

  An insulating film 54 is disposed on the substrate 30 so as to cover the unit transistor 60. A wiring 87 (first wiring) is arranged above the operation region 61 via the insulating film 54. Here, “above” refers to a space that is not directly in contact with the operation area 61 but is located above the operation area 61. The wiring 87 is connected to the unit transistor 60 through an opening provided in the insulating film 54, and serves as a path for a current flowing through the unit transistor 60. On the insulating film 54, in addition to the wiring 87, another wiring 88 (second wiring) is arranged. The wiring 88 is connected to other transistors than the unit transistor 60 formed on the substrate 30.

  Another insulating film 52 is disposed on the insulating film 54 and the wirings 87 and 88. The insulating film 52 has at least one opening 45 (first opening) and at least one other opening 46 (second opening). The whole area of at least one opening 45 overlaps with wiring 87 in plan view. Further, the entire area of at least one opening 46 overlaps with the wiring 88. In plan view, one opening 45 does not overlap with the wiring 88, and the other opening 46 does not overlap with the wiring 87.

  On the insulating film 52, a pillar bump 82 (first bump) having a substantially rectangular planar shape and a pillar bump 84 (second bump) having a substantially circular planar shape are arranged. One pillar bump 82 is electrically connected to the wiring 87 through the opening 45, and the other pillar bump 84 is electrically connected to the wiring 88 through the opening 46. In a plan view, the opening 45 is arranged inside the rectangular pillar bump 82, and the opening 46 is arranged inside the circular pillar bump 84.

  In plan view, at least one of the plurality of operation regions 61 is arranged inside the pillar bump 82. In the first embodiment shown in FIG. 1A, all the operation areas 61 are arranged inside the pillar bumps 82 in plan view. At least a part of at least one operation area 61 among the operation areas 61 arranged inside the pillar bump 82 is arranged outside the opening 45. In the first embodiment shown in FIG. 1A, a part of each of the third and fourth operation regions 61 from the left is arranged outside the opening 45. The entire second and fifth operation regions 61 from the left are arranged inside the opening 45. The entire operating region 61 at both ends is arranged outside the opening 45.

  Next, excellent effects obtained by adopting the configuration of the semiconductor device according to the first embodiment will be described.

  In the first embodiment, by disposing the insulating film 52, the thermal stress generated in the operation region 61 due to the difference between the coefficient of thermal expansion of the pillar bump 82 and the coefficient of thermal expansion of the substrate 30 or the unit transistor 60 is reduced. be able to. Further, by arranging the operation region 61 inside the pillar bump 82 in a plan view, it is possible to suppress an increase in the size of the element as compared with a configuration in which the operation region 61 is arranged to protrude from the pillar bump 82.

  Heat can be conducted from the operation region 61 to the pillar bumps 82 through the openings 45 to ensure heat dissipation. Furthermore, since the opening 45 and the opening 46 have the same planar shape, when the pillar bump 82 and the pillar bump 84 are formed by plating, the filling in the opening 45 and the opening 46 is uniform. As a result, the manufacturing yield is improved, and the manufacturing cost can be reduced.

[Second embodiment]
A semiconductor device according to a second embodiment will be described with reference to FIGS. 2 to 6B.
FIG. 2 is a diagram showing a planar layout of components of the semiconductor device according to the second embodiment. FIG. 3 is a cross-sectional view taken along a dashed line 3-3 in FIG. 2, and FIG. 4 is a cross-sectional view taken along a dashed line 4-4 in FIG. The semiconductor device is configured by stacking a plurality of components. In FIG. 2, in order to easily distinguish the components of the semiconductor device, lower components hidden by upper components are indicated by broken lines. May be. Further, the outer periphery of the component may be indicated by a broken line, or the component may be hatched with a different density.

  An xyz orthogonal coordinate system is defined in which the horizontal direction in the plan view shown in FIG. 2 is the x-axis direction, the vertical direction is the y-axis direction, and the direction perpendicular to the plane of FIG. 2 is the z-axis direction. A plurality of unit transistors 60 are arranged side by side in the x-axis direction. In the second embodiment shown in FIG. 2, four unit transistors 60 are arranged side by side. The plurality of unit transistors 60 are connected to each other in parallel by an upper layer wiring.

  Each of the unit transistors 60 includes a collector layer 32, a base layer 33, an emitter layer 34, a collector electrode C0, a base electrode B0, and two emitter electrodes E0. A region of the emitter layer 34 that contributes to the operation of the HBT (a region where an emitter current flows substantially) is referred to as an emitter region 34A. The two emitter electrodes E0 are respectively arranged inside the emitter region 34A. Each of the two emitter regions 34A has a rectangular planar shape elongated in the y-axis direction, and the two emitter regions 34A are arranged at intervals in the x-axis direction. The main part of base electrode B0 is arranged between two emitter regions 34A. As will be described later with reference to FIG. 3, an operating current flows through the emitter region 34A in the thickness direction (z-axis direction). The region inside the emitter region 34A in plan view becomes the operation region 61 of the unit transistor 60, and the operation region 61 mainly becomes a heat source. In FIG. 2, the operation area 61 is indicated by dark hatching downward to the right.

  The emitter region 34A and the base electrode B0 are disposed inside the base layer 33. The base electrode B0 has a portion (connection portion) extending from one end of the main portion (the end on the positive side of the y-axis in FIG. 2) to both sides in parallel with the x-axis direction. The first-layer base wiring B1 is connected to this connection portion. The first-layer base wiring B1 intersects with the second-layer wiring M2, and a capacitor 55 is formed in a crossing region. Further, the first-layer base wiring B1 is connected to the ballast resistor 56.

  Collector electrodes C0 are arranged on both sides of the base layer 33 in the x-axis direction. Two adjacent unit transistors 60 share a collector electrode C0 disposed between the base layers 33 of the unit transistors 60.

  Above the emitter layer 34, a second-layer emitter wiring E2 is arranged. The emitter wiring E2 of the second layer includes four unit transistors 60 inside when viewed in plan, and functions as a wiring through which an operating current flows to the unit transistors 60. The second-layer emitter wiring E2 is electrically connected to the emitter electrode E0 via the first-layer emitter wiring E1 (FIGS. 3 and 4).

  A pillar bump (metal member) 40 is arranged so as to overlap the emitter wiring E2 of the second layer in plan view. The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via a plurality of openings 45 provided in the insulating film immediately below the pillar bump 40. In FIG. 2, the opening 45 is provided with thin hatching that rises to the right.

  For example, the dimension (width) in the x-axis direction of each of the emitter regions 34A is 2 μm or more and 8 μm or less, and the dimension (length) in the y-axis direction is 10 μm or more and 40 μm or less. The dimension of the pillar bump 40 in the x-axis direction is 70 μm or more and 500 μm or less, and the dimension in the y-axis direction is 60 μm or more and 100 μm or less. The dimension of the opening 45 in the x-axis direction is not less than 10 μm and not more than 60 μm.

  As shown in FIG. 3, a subcollector layer 31 made of high-concentration n-type GaAs is formed on a substrate 30 made of semi-insulating GaAs. The thickness of the sub-collector layer 31 is, for example, 0.5 μm.

  A plurality of mesas in which a collector layer 32, a base layer 33, and an emitter layer 34 are stacked are arranged on the sub-collector layer 31. One mesa corresponds to one unit transistor 60 (FIG. 2). On the emitter layer 34, two emitter mesa layers 35 are arranged apart from each other in the x-axis direction. The emitter layer 34 immediately below the emitter mesa layer 35 operates as an emitter region 34A through which an operation current flows in the thickness direction. In the emitter layer 34, a region where the emitter mesa layer 35 is not disposed is depleted and is called a ledge layer 34B. The ledge layer 34B functions as a protective layer that suppresses carrier recombination on the surface of the base layer 33.

  The collector layer 32 is formed of, for example, n-type GaAs, and has a thickness of 1 μm. The base layer 33 is formed of, for example, p-type GaAs, and has a thickness of 100 nm. The emitter layer 34 is formed of, for example, n-type InGaP, and has a thickness of 30 nm or more and 40 nm or less. The interface between the emitter layer 34 and the base layer 33 forms a hetero junction. The emitter mesa layer 35 has a two-layer structure of, for example, a 100-nm-thick layer made of high-concentration n-type GaAs and a 100-nm-thick layer made of high-concentration n-type InGaAs.

  An emitter electrode E0 is arranged on the emitter mesa layer 35. As the emitter electrode E0, for example, a Ti film having a thickness of 50 nm is used. The emitter electrode E0 is ohmically connected to the emitter mesa layer 35.

  An opening is provided in the ledge layer 34B in a region between the two emitter mesa layers 35, and the base electrode B0 is disposed in the opening. The base electrode B0 is ohmically connected to the base layer 33. The base electrode B0 is formed, for example, by laminating a Ti film, a Pt film, and an Au film in this order.

  A collector electrode C0 is disposed on the sub-collector layer 31 between two mesas, each of which is composed of three layers of a collector layer 32, a base layer 33, and an emitter layer. The collector electrode C0 is formed, for example, by laminating an AuGe film, a Ni film, and an Au film in this order. Collector electrode C0 is ohmically connected to subcollector layer 31. The collector electrode C0 is shared by the two unit transistors 60 on both sides thereof. Subcollector layer 31 functions as a current path connecting collector electrode C0 and collector layer 32.

  An insulating film 50 is formed so as to cover the mesa including the collector layer 32 to the emitter layer 34, the emitter mesa layer 35, the emitter electrode E0, the base electrode B0, and the collector electrode C0. As the insulating film 50, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used.

  On the insulating film 50, a first-layer emitter wiring E1 and a first-layer collector wiring C1 are arranged. The first-layer emitter wiring E1 is electrically connected to the emitter electrode E0 through an opening provided in the insulating film 50. The first-layer collector wiring C1 is electrically connected to the collector electrode C0 through an opening provided in the insulating film 50. The first-layer emitter wiring E1 and the first-layer collector wiring C1 have a stacked structure in which, for example, a 50-nm-thick Ti film and a 1-μm-thick Au film are stacked in this order.

  A second insulating film 51 is formed on the insulating film 50 so as to cover the first emitter wiring E1 and the collector wiring C1. As the second insulating film 51, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used. On the second insulating film 51, a second emitter wiring E2 is arranged. The second-layer emitter wiring E2 includes, for example, a 50-nm-thick Ti film and a 4-μm-thick Au film disposed thereon. The second-layer emitter wiring E2 is connected to the first-layer emitter wiring E1 through an opening provided in the insulating film 51. The first-layer emitter wiring E1 arranged for each unit transistor 60 is connected to each other via the second-layer emitter wiring E2.

  A third-layer insulating film 52 is arranged so as to cover the second-layer emitter wiring E2. As the third insulating film 52, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used. A plurality of openings 45 (only one opening 45 is shown in FIG. 3) are formed in the third insulating film 52. As shown in FIG. 2, the plurality of openings 45 are arranged inside the second-layer emitter wiring E2 in plan view, and the second-layer emitter wiring E2 is exposed at the bottom thereof.

  The pillar bump (metal member) 40 is arranged on the third insulating film 52. The pillar bump 40 includes a lowermost under bump metal layer 41, a metal post 42 thereon, and an uppermost solder layer 43. The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 through the opening 45.

  As the under bump metal layer 41, for example, a Ti film having a thickness of 100 nm can be used. The under bump metal layer 41 has a function of improving the adhesiveness to the underlying insulating film 52. For the metal post 42, for example, a metal material containing copper as a main component can be used. For example, a Cu film having a thickness of about 20 μm or more and about 50 μm or less can be used as the metal post 42. As the solder layer 43, for example, a Sn film having a thickness of 30 μm can be used. Note that a barrier metal layer for preventing mutual diffusion may be arranged between the metal post 42 and the solder layer 43. For example, Ni can be used for the barrier metal layer.

  In each of the unit transistors 60, a large amount of electrons are injected from the emitter region 34A into the base layer 33. Most of the electrons injected into the base layer 33 are mainly transported through the collector layer 32 in the thickness direction and reach the sub-collector layer 31. At this time, Joule heat is generated due to a voltage drop in the base layer 33 and the collector layer 32. For this reason, the emitter layer 34, the base layer 33, and the collector layer 32 immediately below the emitter mesa layer 35 become an operation region 61, and heat is generated in the operation region 61. In plan view, the outer peripheral line of the operation region 61 coincides with the outer peripheral line of the emitter mesa layer 35.

  Next, a configuration not shown in the cross-sectional view of FIG. 3 will be described with reference to FIG. The isolation region 31A is formed by increasing the resistance of a part of the sub-collector layer 31. In this specification, the sub-collector layer 31 indicates a region other than the isolation region 31A. The mesa including the collector layer 32, the base layer 33, and the emitter layer 34 is disposed on the sub-collector layer 31 surrounded by the isolation region 31A.

  The first-layer base wiring B1 is arranged on the first-layer insulating film 50. The first-layer base wiring B1 is electrically connected to the base electrode B0 through an opening provided in the insulating film 50.

  Next, the positional relationship between the pillar bump 40, the opening 45, and the operation area 61 will be described. The geometric center PA (FIG. 2) of the operation region 61 is defined for each unit transistor 60. The geometric center PA corresponds to the position of the center of gravity of the two operation regions 61 included in the unit transistor 60. That is, when focusing on one unit transistor 60, the area of the operation region 61 on the positive side of the x-axis from the geometric center PA is equal to the area of the operation region 61 on the negative side. Further, the area of the operation area 61 on the positive side of the y-axis from the geometric center PA is equal to the area of the operation area 61 on the negative side. In this specification, the geometric center of the two operation regions 61 included in one unit transistor 60 as a whole is simply referred to as the geometric center PA of the operation region 61.

  Furthermore, the geometric center PO of each of the openings 45 is defined. The geometric center PO corresponds to the position of the center of gravity of each of the openings 45. For example, when the plane shape of the opening 45 is a rectangle, the geometric center PO coincides with the intersection of two diagonal lines of the rectangle.

  A plurality of unit transistors 60 are arranged in the x-axis direction (a direction orthogonal to the longitudinal direction of the operation region 61), and the plurality of openings 45 are also arranged in the x-axis direction. The geometric center PO of each of the two openings 45 is shifted from the geometric center PA of the operation area 61 in the x-axis direction.

  The shift amounts between the geometric center PA of the operation region 61 of the unit transistor 60 located at the left end and the right end in the x-axis direction and the geometric center PO of the opening 45 closest thereto are represented by Dx1 and Dx4, respectively. The amounts of shift between the geometric center PO of the operation region 61 of the second and third unit transistors 60 from the left and the geometric center PO of the opening 45 closest thereto are represented by Dx2 and Dx3, respectively. At this time, the shift amounts Dx1 and Dx4 are larger than the shift amounts Dx2 and Dx3.

  Further, the geometric center PO of the opening 45 is also shifted in the y-axis direction with respect to the geometric center PA of the operation area 61.

Next, the excellent effects obtained by the configuration of the semiconductor device according to the second embodiment will be described.
In the second embodiment, as shown in FIG. 2, the operation region 61 of the unit transistor 60 is arranged inside the pillar bump 40 in plan view. As shown in FIGS. 3 and 4, in the cross-sectional views, the pillar bumps 40 are arranged directly above the operation regions 61 of the unit transistors 60. For this reason, the distance from the operation region 61 to the pillar bump 40 is shorter than in a structure in which the pillar bump 40 is arranged at a position shifted from directly above the operation region 61.

  The pillar bump 40 functions as a heat path for radiating heat generated in the operation region 61 to the outside. By reducing the distance from the operation region 61 to the pillar bump 40, heat dissipation can be improved.

  Furthermore, since the entire region of the operation region 61 is arranged so as to overlap the pillar bump 40 in a plan view, the chip area of the semiconductor device can be reduced as compared with a configuration in which the operation region 61 protrudes from the pillar bump 40. This makes it possible to reduce costs.

  Further, by employing the configuration of the semiconductor device according to the second embodiment, an effect is obtained that thermal stress generated in the unit transistor 60 can be reduced. Hereinafter, this effect will be described.

  The thermal stress is generated due to a difference between a coefficient of thermal expansion of a semiconductor layer such as the emitter layer 34 (FIG. 3) and a coefficient of thermal expansion of the pillar bump 40. The metal constituting the pillar bumps 40 has a larger coefficient of thermal expansion than the coefficient of thermal expansion of GaAs (about 6 ppm / ° C.). For example, the thermal expansion coefficient of Cu is 17 ppm / ° C., and the thermal expansion coefficient of Sn solder is 22 ppm / ° C. Further, the coefficient of thermal expansion (15 ppm / ° C. or more and 20 ppm / ° C. or less) of the printed circuit board on which the semiconductor device is mounted is larger than the coefficient of thermal expansion of GaAs.

  When the geometric center PO of the opening 45 is separated from the geometric center PA of the operation region 61, the insulating film 52 exists between the emitter layer 34 and the pillar bump 40. For example, the insulating film 52 is arranged between the unit transistor 60 on the left side and the pillar bump 40 shown in FIG. Since the insulating film 52 functions as a stress relaxation material, thermal stress generated in the semiconductor layer of the unit transistor 60 is reduced. When crystal defects occur due to thermal stress, the current amplification rate decreases in a short time. In the second embodiment, since the thermal stress is reduced, a decrease in reliability due to operation at a high temperature can be suppressed. When a plurality of unit transistors 60 are arranged, the magnitude of the thermal stress generated in the unit transistors 60 varies depending on the relative positional relationship between the pillar bumps 40 and the unit transistors 60. Regarding the unit transistor 60 where heat stress is unlikely to be generated, the emitter layer 34 may be arranged inside the opening 45 in plan view.

  The coefficient of thermal expansion of the material used for the insulating film 52 is often smaller than the coefficient of thermal expansion of the material of the pillar bumps 40 or a semiconductor material such as GaAs. For example, the thermal expansion coefficient of SiN used for the insulating film 52 is 2 ppm / ° C. or more and 3 ppm / ° C. or less. By using a material having a smaller coefficient of thermal expansion than the coefficient of thermal expansion of the semiconductor material forming the operation region 61 of the unit transistor 60 for the insulating film 52, a remarkable effect of reducing thermal stress can be obtained.

  In particular, the thermal stress generated in the semiconductor layers such as the emitter layers 34 of the two unit transistors 60 disposed at both ends in the x-axis direction tends to be larger than the thermal stress generated in the semiconductor layers of the other unit transistors 60. . In the second embodiment, the shift amounts Dx1 and Dx4 between the geometric center PA of the operation region 61 of the unit transistors 60 at both ends and the geometric center PO of the opening 45 are larger than the shift amounts Dx2 and Dx3 in the other operation regions 61. Therefore, the effect of reducing the thermal stress generated in the semiconductor layers of the unit transistors 60 at both ends is particularly enhanced. As a result, thermal stress generated in the semiconductor layers of the plurality of unit transistors 60 can be leveled. As a result, a decrease in the reliability of the entire semiconductor device can be suppressed.

  Further, by applying the configuration of the semiconductor device according to the second embodiment, it is possible to obtain an effect that the heat radiation characteristics of the plurality of unit transistors 60 from the operation region 61 can be controlled for each unit transistor 60. Hereinafter, this effect will be described.

  The heat generated in the operation region 61 (FIG. 3) is mainly radiated to the outside via the emitter electrode E0, the first-layer emitter wiring E1, the second-layer emitter wiring E2, and the pillar bump 40. When the geometric center PO of the opening 45 is separated from the geometric center PA of each operation region 61 of the unit transistor 60, the insulating film 52 exists between the first-layer emitter wiring E1 and the pillar bump 40. For example, the insulating film 52 is not disposed between most of the first-layer emitter wiring E1 connected to the unit transistor 60 on the right side of FIG. On the other hand, an insulating film 52 is disposed between the pillar bump 40 and the entire first-layer emitter wiring E1 connected to the unit transistor 60 on the left side of FIG.

  The thermal conductivity of SiN or resin used for the insulating film 52 is lower than the thermal conductivity of metal used for wiring and pillar bumps. Therefore, the thermal resistance from the operating region 61 of the left unit transistor 60 to the pillar bump 40 is higher than the thermal resistance from the operating region 61 of the right unit transistor 60 to the pillar bump 40. As a result, the heat radiation characteristics of the left unit transistor 60 from the operation region 61 are worse than the heat radiation characteristics of the right unit transistor 60 from the operation region 61. In general, the larger the amount of deviation from the geometric center PA of the operation region 61 of each unit transistor 60 to the geometric center PO of the nearest opening 45, the worse the heat radiation characteristics from the operation region 61 are. it can.

  In the unit transistors 60 other than the unit transistors 60 at both ends shown in FIG. 2, the other unit transistors 60 are adjacent on both sides in the x-axis direction. For this reason, the operating region 61 of the unit transistor 60 on the inner side tends to be higher in temperature than the operating region 61 of the unit transistor 60 on both ends.

  In the second embodiment, the shift amounts Dx2 and Dx3 shown in FIG. 2 are smaller than the shift amounts Dx1 and Dx4. Therefore, the heat radiation characteristics of the two inner unit transistors 60 from the operation region 61 are higher than the heat radiation characteristics of the two unit transistors 60 at both ends from the operation region 61. Since the heat radiation characteristics from the operation region 61 where the temperature tends to be relatively high are relatively high, it is possible to suppress the temperature variation in the operation region 61 of the plurality of unit transistors 60. By performing a simulation or an evaluation experiment using various combinations of the shift amounts Dx1, Dx2, Dx3, and Dx4, an appropriate shift amount for leveling the temperatures of the plurality of operation regions 61 can be determined. By leveling the temperatures of the plurality of operation regions 61, it is possible to suppress a decrease in high-frequency characteristics.

  Further, when a plurality of unit transistors 60 are connected and operated in parallel, the life of the unit transistors 60 whose temperature is high is relatively shortened. Therefore, the life of the semiconductor device including the plurality of unit transistors 60 is shortened. By leveling the temperatures of the operation regions 61 of the plurality of unit transistors 60, it is possible to suppress a decrease in the lifetime of the semiconductor device as a whole.

  In the second embodiment, the opening 45 is not disposed outside the geometric center of the operation region 61 of the two unit transistors 60 disposed at both ends in the x-axis direction. By arranging the openings 45 in this manner, the heat radiation characteristics of the unit transistors 60 disposed inside from the operation region 61 can be higher than the heat radiation characteristics of the unit transistors 60 at both ends from the operation region 61.

  The effect of employing a configuration in which the geometric center PO of the opening 45 is shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60 has been confirmed by simulation. Hereinafter, this simulation will be described with reference to FIGS. 5A to 6B. The simulation target has a configuration in which one unit transistor 60 includes one operation region 61.

  FIG. 5A is a plan view illustrating a positional relationship among an operation region 61, an opening 45, and a pillar bump 40 of a semiconductor device according to a comparative example to be simulated. The planar shape of the pillar bump 40 is a race track shape in which a semicircle having a diameter of 75 μm is connected to both ends in the length direction of a rectangle having a length of 240 μm in the x-axis direction and a width of 75 μm in the y-axis direction. The dimension of the operation area 61 in the x-axis direction was 4 μm, and the dimension in the y-axis direction was 30 μm. The size of the opening 45 in the x-axis direction was 240 μm, and the size in the y-axis direction was 51 μm. The positions of the geometric center PA of the operation area 61 and the geometric center PO of the opening 45 in the x-axis direction were matched, and the positions in the y-axis direction were shifted. The absolute value of the shift amount in the y-axis direction is represented by Dy.

  FIG. 5B is a plan view illustrating a positional relationship between the operation region 61, the opening 45, and the pillar bump 40 of the semiconductor device according to the embodiment. The shapes and dimensions of the pillar bumps 40 and the operation regions 61 are the same as those of the semiconductor device shown in FIG. 5A. The size of the opening 45 in the x-axis direction was 20 μm, and the size in the y-axis direction was 50 μm. The position of the geometric center PA of the operation area 61 and the position of the geometric center PO of the opening 45 in the y-axis direction were matched, and the position in the x-axis direction was shifted. The absolute value of the shift amount in the x-axis direction is represented by Dx.

  In the simulation, the thermal stress generated in the emitter region 34A (FIGS. 3 and 4) when the temperature of the semiconductor device is 150 ° C. was obtained. Further, the thermal resistance from the emitter region 34A to the pillar bump 40 was determined.

  FIG. 6A is a graph showing the relationship between the shift amounts Dx and Dy and the reduction amount of the thermal stress generated in the emitter region 34A. The horizontal axis of the graph of FIG. 6A represents the shift amounts Dx and Dy in units of “μm”, and the vertical axis represents the reduction amount of the thermal stress in units of “%”. Circles and triangles in the graph of FIG. 6A indicate calculation results of the amount of reduction in thermal stress in the semiconductor device according to the comparative example (FIG. 5A) and the semiconductor device according to the example (FIG. 5B). The amount of reduction of the thermal stress is based on the value of the thermal stress when the shift amount Dy of the semiconductor device (FIG. 5A) according to the comparative example is 0, and the amount of reduction from the reference value is expressed as a ratio to the reference value. .

  It can be seen that in the semiconductor device of the comparative example (FIG. 5A), the thermal stress decreases as the shift amount Dy increases. In the semiconductor device of the example (FIG. 5B), it was confirmed that the thermal stress tended to decrease more gradually than the comparative example, but the thermal stress decreased as the shift amount Dx increased.

  FIG. 6B is a graph illustrating a relationship between the shift amounts Dx and Dy and the increase amount of the thermal resistance. The horizontal axis of the graph in FIG. 6B represents the shift amounts Dx and Dy in units of “μm”, and the vertical axis represents the increase in the thermal resistance in units of “%”. The circle symbol and the triangle symbol in the graph of FIG. 6B indicate calculation results of the increase in thermal resistance in the semiconductor device according to the comparative example (FIG. 5A) and the semiconductor device according to the example (FIG. 5B). The amount of increase in the thermal resistance is based on the value of the thermal resistance of the semiconductor device according to the comparative example (FIG. 5A) when the deviation amount Dy = 0, and represents the amount of increase from the reference value as a ratio to the reference value. . It can be seen that the thermal resistance increases as the shift amounts Dx and Dy increase. From this simulation result, it was confirmed that the thermal resistance can be controlled by changing the shift amount of the opening 45 in the x-axis direction or the y-axis direction with respect to the operation region 61.

  Next, a modification of the second embodiment will be described. In the second embodiment, the emitter electrode E0 is arranged between the emitter mesa layer 35 (FIG. 3) and the first-layer emitter wiring E1 (FIG. 3). As another configuration, a configuration in which the first-layer emitter wiring E1 is in direct contact with the emitter mesa layer 35 may be employed. In this case, the emitter electrode E0 is omitted, and the first-layer emitter wiring E1 also serves as the emitter electrode.

  In the second embodiment, in FIG. 2, the geometric centers PO of all the openings 45 are shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60. May be shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60. Here, shifting the geometric center PO in the x-axis direction with respect to the geometric center PA means that a vector starting from the geometric center PA and ending at the geometric center PO has an x component.

  In the second embodiment, two openings 45 are arranged for connection to the pillar bumps 40 and the second-layer emitter wiring E2, but at least one opening 45 may be arranged.

  In the second embodiment, the pillar bumps 40 are used as bumps for external connection, but other bumps, such as solder bumps and stud bumps, may be used. Further, in the second embodiment, the planar shape of the emitter layer 34 and the emitter mesa layer 35 (FIGS. 2, 3, and 4) is rectangular, but may be other shapes. For example, the planar shape may be circular, elliptical, hexagonal, octagonal, or the like.

  In the second embodiment, InGaP is used for the emitter layer 34 and GaAs is used for the base layer 33. However, another compound semiconductor may be used. For example, as a combination of the material of the emitter layer 34 and the material of the base layer 33, AlGaAs / GaAs, InP / InGaAs, InGaP / GaAsSb, InGaP / InGaAsN, Si / SiGe, AlGaN / GaN, or the like may be applied. In any combination, the emitter-base interface becomes a heterojunction.

  Although the semiconductor device according to the second embodiment includes four unit transistors 60 as shown in FIG. 2, the number of unit transistors 60 is not limited to four. It is preferable that the semiconductor device include a plurality of unit transistors 60.

[Third embodiment]
Next, a semiconductor device according to a third embodiment will be described with reference to FIG. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted.

  FIG. 7 is a diagram showing a planar layout of the semiconductor device according to the third embodiment. In the third embodiment of FIG. 7, an example is shown in which three unit transistors 60 are arranged in the x-axis direction. However, the number of unit transistors 60 is not limited to three, and may be four in the same manner as in the first embodiment. The number may be two, five, or more. In the second embodiment, one unit transistor 60 includes two emitter regions 34A (FIGS. 2 and 3). In the third embodiment, one unit transistor 60 includes one emitter region 34A. Each of unit transistors 60 includes an operation region 61. The operation region 61 is defined for each unit transistor 60 by an outer peripheral line of the emitter region 34A. In FIG. 7, the operation area 61 is indicated by dark hatching downward to the right.

  The planar shape of the emitter region 34A is a rectangle long in the y-axis direction, as in the case of the second embodiment. The main part of the base electrode B0 is arranged beside the emitter region 34A in the x-axis direction. In the second embodiment, the planar shape of the base electrode B0 is T-shaped, but in the third embodiment, the planar shape of the base electrode B0 is L-shaped.

  In the second embodiment, the geometric center PA of the operation region 61 of the unit transistor 60 is located between the two operation regions 61. In the third embodiment, since one unit transistor 60 includes one operation region 61, the geometric center PA of the operation region 61 is located at the center of gravity of the one operation region 61. That is, the geometric center PA of the operation area 61 is located at the intersection of two diagonal lines of the rectangular operation area 61. One opening 45 is arranged inside the pillar bump 40. In FIG. 7, the opening 45 is provided with thin hatching that rises to the right. Also in the third embodiment, the geometric center PO of the opening 45 is arranged at a position shifted from the geometric center PA of the operation area 61 in the x-axis direction.

  Also in the third embodiment, since the positional relationship between the operation region 61 and the opening 45 is the same as that of the semiconductor device according to the second embodiment, the same effects as in the second embodiment can be obtained.

[Fourth embodiment]
Next, a semiconductor device according to a fourth embodiment will be described with reference to FIGS. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted. The semiconductor device according to the fourth embodiment is a power amplifier module using a plurality of unit transistors 60 (FIG. 2) according to the second embodiment as an amplifier circuit.

  FIG. 8 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fourth embodiment. The power amplification circuit according to the fourth embodiment amplifies and outputs an input signal in a radio frequency band. The frequency of the input signal is, for example, in the range of several hundred MHz (for example, 600 MHz) or more and several tens of GHz (for example, 60 GHz).

  The power amplifier circuit realized by the semiconductor device according to the fourth embodiment includes transistors Q1, Q2, matching circuits MN1, MN2, MN3, filter circuits 71, 72, bias circuits 75, 76, and inductors L1, L2. The transistor Q1 forms a power amplifier circuit of a first stage (drive stage), and the transistor Q2 forms a power amplifier circuit of a subsequent stage (power stage). The transistors Q1 and Q2 have a configuration in which a plurality of unit transistors 60 are connected in parallel, for example, as in the semiconductor device according to the second embodiment or the third embodiment.

  The power supply voltage Vcc is supplied to the collectors of the transistors Q1 and Q2 via the inductors L1 and L2, respectively. The emitters of the transistors Q1 and Q2 are grounded. A bias current or a bias voltage is supplied to the bases of the transistors Q1 and Q2 from the bias circuits 75 and 76, respectively.

  The input signal RFin is supplied to the base of the transistor Q1 via the matching circuit MN1. The transistor Q1 amplifies the input signal RFin and outputs an amplified signal RFout1 from the collector. The amplified signal RFout1 is supplied to the base of the transistor Q2 via the matching circuit MN2. The transistor Q2 further amplifies the amplified signal RFout1, and outputs an amplified signal RFout2 from the collector. The amplified signal RFout2 is supplied to an external circuit via the matching circuit MN3.

  Filter circuits 71 and 72 are connected between the transmission line connecting the collector of the transistor Q2 and the matching circuit MN3 and the ground. The filter circuit 71 is a series resonance circuit in which a capacitor C1a and an inductor L3a are connected in series, and the filter circuit 72 is a series resonance circuit in which a capacitor C1b and an inductor L3b are connected in series. The filter circuits 71 and 72 function as harmonic termination circuits that attenuate the frequency components in the harmonic band included in the amplified signal RFout2. For example, the harmonic termination circuit adjusts the impedance so that a desired harmonic impedance (for example, an impedance with respect to a second harmonic or a third harmonic) becomes short-circuited or open as compared with the fundamental wave impedance. As described above, by setting (impedance adjustment) each harmonic impedance independently of the fundamental wave impedance, the harmonic components are attenuated. The circuit constants of the capacitors C1a and C1b of the filter circuits 71 and 72 and the inductors L3a and L3b are set so that the resonance frequency substantially matches the frequency of the harmonic of the amplified signal RFout2, for example, the frequency of the second or third harmonic. Selected.

  For example, the transistors Q1 and Q2, the matching circuits MN1 and MN2, the bias circuits 75 and 76, the capacitors C1a and C1b of the filter circuits 71 and 72, and a part of the matching circuit MN3 are formed in one semiconductor chip 70. The inductors L1 and L2, the inductors L3a and L3b of the filter circuits 71 and 72, and the remaining portion of the matching circuit MN3 are formed or mounted on a mounting board on which the semiconductor chip 70 is mounted. The inductors L3a and L3b of the filter circuits 71 and 72 are realized by, for example, wiring having an inductance component formed on a mounting board.

  FIG. 9 is an equivalent circuit diagram of the transistor Q2 and its peripheral circuits. The transistor Q2 is composed of a plurality of unit transistors 60 connected in parallel, similarly to the semiconductor device according to the second or third embodiment. A capacitor 55 and a ballast resistor 56 are connected to the bases of the plurality of unit transistors 60, respectively. The capacitor 55 and the ballast resistor 56 correspond to the capacitor 55 and the ballast resistor 56 shown in FIG. 2, respectively.

  The high-frequency signal that has passed through the matching circuit MN2 is supplied to each base of the unit transistor 60 via the capacitor 55. A bias current or a bias voltage is supplied from the bias circuit 76 to each base of the unit transistor 60 via the ballast resistor 56. Each collector of unit transistor 60 is DC-connected to power supply voltage Vcc. Each emitter of the unit transistor 60 is grounded.

  FIG. 10 is a diagram showing a layout of each element of a semiconductor chip 70 constituting the semiconductor device according to the fourth embodiment. The planar shape of the semiconductor chip 70 is a rectangle having sides parallel to the x-axis direction and the y-axis direction. The semiconductor chip 70 is provided with pillar bumps 81, 82, 83 that are long in the x-axis direction.

  The pillar bump 81 is connected to the emitters of the four unit transistors 60 forming the transistor Q1 (FIG. 8). The transistor Q2 includes two unit transistor groups each including ten unit transistors 60 connected in parallel. The emitters of ten unit transistors 60 included in one unit transistor group are connected to pillar bumps 82, and the emitters of ten unit transistors 60 included in the other unit transistor group are connected to pillar bumps 83.

  The pillar bumps 82 and 83 have the same planar shape and the same dimensions, and are arranged at intervals in the y-axis direction. The pillar bump 81 is shorter than the other two pillar bumps 82 and 83. This is because the number of unit transistors 60 connected to the pillar bumps 81 is smaller than the number of unit transistors 60 connected to each of the pillar bumps 82 and 83.

  On the semiconductor chip 70, capacitors C1a and C1b constituting filter circuits 71 and 72 (FIG. 8) are arranged. On-chip capacitors formed on the semiconductor chip 70 are used for the capacitors C1a and C1b. One capacitor C1a is arranged closer to the unit transistor 60 at the other end (left end) than the unit transistor 60 at one end (right end). The other capacitor C1b is arranged at a position near the unit transistor 60 at an end opposite to the end near the capacitor C1a.

  For this reason, the capacitors C1a and C1b are connected to the pillar bumps 82 and 83, respectively, and are arranged in the vicinity of the unit transistor 60 located at the opposite end of the plurality of unit transistors 60 arranged in the x-axis direction. become. For example, the capacitors C1a and C1b are arranged at positions that are line-symmetric with respect to the center line of the semiconductor chip 70 in the x-axis direction.

  The capacitor C1a is connected to a circular pillar bump 84 via a wiring formed on the semiconductor chip 70. When the semiconductor chip 70 is mounted on the mounting board, the capacitor C1a is electrically connected to the inductor L3a on the mounting board via the pillar bump 84. Similarly, the capacitor C1b is electrically connected to the inductor L3b on the mounting board via the pillar bump 85.

  Other circular pillar bumps 86 are connected to the collectors of the transistors Q1 and Q2 (FIG. 8), the matching circuits MN1 and MN3 (FIG. 8), and the like.

  FIG. 11A is a diagram illustrating a positional relationship between the pillar bumps 82, the operation regions 61 of the plurality (ten) of unit transistors 60 connected thereto, and the plurality of openings 45. Ten operation areas 61 are arranged in the x-axis direction, and eight openings 45 are arranged. FIG. 11A shows an example in which each of the unit transistors 60 includes one operation region 61 (FIG. 7), but may have a configuration in which each of the unit transistors 60 includes two operation regions 61 (FIG. 2).

  The displacement amount in the x-axis direction between each geometric center PA of the operation area 61 and the geometric center PO of the opening 45 closest thereto (hereinafter, referred to as “displacement amount of the closest opening”) is represented by Dx. The shift amount Dx of the closest opening is defined for each unit transistor 60. The geometric center PO of any of the openings 45 is arranged at a position shifted from the geometric center PA of the operation area 61 in the x-axis direction. That is, the shift amount Dx of the closest opening is not 0. Further, all the openings 45 are arranged inside the geometric center PA of the operation region 61 of the unit transistor 60 located at both ends, and the openings 45 are not arranged outside.

  The shift amount Dx of the closest openings corresponding to the unit transistors 60 at both ends is larger than the shift amount Dx of the closest openings corresponding to the eight inner unit transistors 60. Further, the shift amount Dx of the closest opening increases from the center to the end of the arrangement of the plurality of unit transistors 60.

  Regarding the other pillar bumps 81 and 83 (FIG. 10), the positional relationship between the pillar bumps 81 and 83, the operating regions 61 of the plurality of unit transistors 60 connected thereto, and the plurality of openings 45 is similar to that of the pillar bump 81. It is. The shape and size of the openings 45 arranged inside the pillar bumps 81, 82, 83 are all the same.

  FIG. 11B is a plan view of the circular pillar bump 84 and the opening 46 disposed thereunder. The pillar bump 84 is electrically connected to a wiring below the opening via the inside of the opening 46. One opening 46 is provided corresponding to one pillar bump 84. Similar openings are provided for other circular pillar bumps 85 and 86 (FIG. 10).

  The shape and size of the openings 46 and the like provided corresponding to the circular pillar bumps 84, 85, 86 (FIG. 10) are provided corresponding to the pillar bumps 81, 82, 83 (FIG. 10) which are long in the x-axis direction. The shape and size of each of the openings 45 are the same.

  FIG. 12 is a sectional view of a semiconductor device according to the fourth embodiment. The semiconductor chip 70 is soldered to the mounting board 90 via pillar bumps 81, 82, 83, 86 and the like. As the mounting board 90, for example, a printed board made of alumina, ceramic, epoxy, or the like is used. In addition to the semiconductor chip 70, inductors L3a and L3b (FIG. 10) and other surface-mounted elements 91 are mounted on the mounting substrate 90. The semiconductor chip 70, the inductors L3a and L3b, and the surface-mounted element 91 are sealed with a sealing resin 93.

Next, excellent effects obtained by employing the configuration of the semiconductor device according to the fourth embodiment will be described.
In the fourth embodiment, as shown in FIG. 11A, the pillar bump 82, the operating region 61 of the plurality of unit transistors 60 connected thereto, and the plurality of openings 45 are different from those of the second embodiment or the third embodiment. Has the same positional relationship as. Therefore, the same effects as those of the semiconductor device according to the second or third embodiment can be obtained.

  In the fourth embodiment, the capacitors C1a and C1b of the filter circuits 71 and 72 are connected near the unit transistors 60 at both ends of the plurality of unit transistors 60 arranged in the x-axis direction. As a result, the characteristics of the filter circuits 71 and 72 as a high-frequency terminal circuit are improved, and as a result, the performance of the power amplifier is improved.

  Further, in the fourth embodiment, the plurality of openings 45 (FIG. 11A) corresponding to the pillar bumps 81, 82, 83 (FIG. 10) and the openings 46 (FIG. 10) corresponding to the circular pillar bumps 84, 85, 86 (FIG. 10). The shape and size of FIG. 11B) were the same. Thereby, when the pillar bumps 81 and the like are formed by the plating method, the filling in the openings is made uniform, so that the production yield can be improved.

  In order to make the embedding uniform, a plurality of openings 45 (FIG. 11A) corresponding to the pillar bumps 81, 82, 83 (FIG. 10) are preferably arranged at equal intervals. Further, it is preferable to make the intervals of the plurality of openings 45 and the like provided corresponding to each of the pillar bumps 81, 82, 83 (FIG. 10) the same.

  Next, a modification of the fourth embodiment will be described. In the fourth embodiment, the power amplifier circuit has a two-stage configuration, but may have a single-stage configuration or a configuration having three or more stages.

[Fifth embodiment]
Next, a semiconductor device according to a fifth embodiment will be described with reference to FIG. 13, FIG. 14, and FIG. Hereinafter, the description of the same configuration as the semiconductor device according to the fourth embodiment (the drawings from FIG. 8 to FIG. 12) will be omitted.

  FIG. 13 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fifth embodiment. In the fourth embodiment, two filter circuits 71 and 72 are connected in parallel between the ground and the transmission line from the collector of the transistor Q2 to the matching circuit MN3. In the fifth embodiment, one filter circuit 71 is connected. As in the case of the fourth embodiment, the filter circuit 71 is configured by a series resonance circuit in which a capacitor C1a and an inductor L3a are connected in series.

  The configuration of the transistor Q1 is the same as the configuration of the transistor Q1 (FIG. 8) of the semiconductor device according to the fourth embodiment. The transistor Q2 is composed of two unit transistor groups, similarly to the transistor Q2 (FIG. 8) of the semiconductor device according to the fourth embodiment. In the fourth embodiment, each of the two unit transistor groups forming the transistor Q2 includes ten unit transistors 60 (FIG. 2, FIG. 11A, etc.). On the other hand, in the fifth embodiment, each of the unit transistor groups includes eight unit transistors 60.

  FIG. 14 is a diagram showing a layout of each element of the semiconductor chip 70 constituting the semiconductor device according to the fifth embodiment. Eight unit transistors 60 are connected to each of the pillar bumps 82 and 83. Since the number of unit transistors 60 connected to each of the pillar bumps 82 and 83 is smaller in the fifth embodiment than in the fourth embodiment, the pillar bumps 82 and 83 of the semiconductor device according to the fifth embodiment are It is shorter than the pillar bumps 82 and 83 (FIG. 10) of the semiconductor device according to the embodiment. One pillar bump 83 is arranged on an extension of the other pillar bump 82 extending in the x-axis direction.

  In the fifth embodiment, the capacitor C1b (FIG. 10) of the semiconductor device according to the fourth embodiment is not provided, and only the capacitor C1a is provided. Correspondingly, in the fifth embodiment, the circular pillar bump 85 (FIG. 10) is not provided. The capacitor C1a is disposed near one end of the pillar bump 82 near the unit transistor 60.

  FIG. 15 is a diagram illustrating a positional relationship between the pillar bump 82, the operation region 61 of the unit transistor 60, and the opening 45. The operating regions 61 of the eight unit transistors 60 are arranged side by side in the x-axis direction inside pillar pillars 82 having a long planar shape in the x-axis direction. Further, the eight openings 45 are also arranged inside the pillar bumps 82 in the x-axis direction.

  The shift amount Dx of the closest opening corresponding to the unit transistor 60 arranged at one end (right end) is the shift amount Dx of the closest opening corresponding to the unit transistor 60 arranged at the other end (left end). Greater than. Further, the shift amount Dx of the closest opening corresponding to the unit transistor 60 increases from one end (left end) to the other end (right end). The capacitor C1a (FIG. 14) of the filter circuit 71 is arranged near the left end of the pillar bump.

  Next, excellent effects obtained by adopting the configuration of the semiconductor device according to the fifth embodiment will be described.

  When the filter circuit 71 (FIG. 14) operating as a harmonic termination circuit is connected to the collector of the transistor Q2 (FIG. 13), the inventors of the present application generate heat at the plurality of unit transistors 60 during high-frequency operation. It has been found that a phenomenon of non-uniformity occurs. For example, in the example shown in FIG. 15, it has been found that the amount of heat generated tends to gradually decrease from the leftmost unit transistor 60 toward the rightmost unit transistor 60.

  In the fifth embodiment, the heat radiation characteristic of the unit transistor 60 from the operating region 61 is adjusted so as to cancel out the variation in the amount of heat generated for each unit transistor 60. Specifically, by increasing the shift amount Dx of the closest opening corresponding to the unit transistor 60 from the left end to the right end, the heat radiation characteristic of the unit transistor 60 from the operation region 61 is increased from the left end to the right end. It is gradually decreasing. With such a configuration, the temperatures during operation of the plurality of unit transistors 60 can be equalized.

  Further, the average value of the heat value of the plurality of unit transistors 60 connected to one pillar bump 82 (FIG. 14) and the average value of the heat value of the plurality of unit transistors 60 connected to the other pillar bump 83 (FIG. 14). May not be equal to In the example shown in FIG. 14, the average value of the calorific value of the unit transistor 60 connected to the pillar bump 82 closer to the capacitor C1a of the filter circuit 71 is larger. In such a case, the average value of the shift amount Dx of the closest opening corresponding to the unit transistor 60 having the larger average value of the heat generation amount is determined by the unit of the smaller average value of the heat generation amount. It is preferable that the difference be smaller than the average value of the shift amount Dx of the closest opening corresponding to the transistor 60. Thus, the difference between the operating temperature of the plurality of unit transistors 60 connected to one pillar bump 82 and the operating temperature of the plurality of unit transistors 60 connected to the other pillar bump 83 can be reduced. .

  Depending on how to select the high frequency operation conditions of the semiconductor device, the distribution of the heat generation amount may be different from the above distribution. In such a case, the distribution of the shift amount Dx of the closest opening corresponding to the unit transistor 60 may be set so as to offset the variation in the heat generation amount.

  As in the semiconductor device according to the fourth embodiment (FIG. 8), even when two filter circuits 71 and 72 operating as a harmonic termination circuit are connected, the amount of heat generated between the plurality of unit transistors 60 is increased. May be uneven. In such a case, the distribution of the shift amount Dx of the nearest opening may be determined so as to offset the variation in the heat generation amount.

  Next, the reason why the heat generation amount varies for each unit transistor 60 will be described. The collectors of the plurality of unit transistors 60 are connected to a common collector wiring. When operating the plurality of unit transistors 60 at a high frequency, the inductance component of the collector wiring cannot be ignored. If the length of the collector wiring from the power supply terminal varies among the plurality of unit transistors 60, the inductance component of the collector wiring also varies. As a result, variations occur in output power and current consumption among the plurality of unit transistors 60.

Next, a semiconductor device according to a modification of the fifth embodiment will be described.
When a harmonic termination circuit is connected to the collector of the transistor Q2 (FIG. 13), the heat generation amount tends to vary among the unit transistors 60. If the variation in the amount of generated heat becomes extremely large, the filter circuit 71 (FIG. 13) functioning as a harmonic termination circuit may not be connected.

  In the fifth embodiment, a part of the matching circuit MN3 (FIG. 13) is formed on the semiconductor chip 70, and the remaining part is mounted on the mounting board 90 (FIG. 12). As a modification, all the matching circuits MN3 may be mounted on the mounting board 90.

  It is preferable to determine whether to adopt the configuration of the above-described modification in consideration of the optimum condition of the high-frequency characteristics and the ease of manufacturing.

[Sixth embodiment]
Next, a semiconductor device according to a sixth embodiment and its modification will be described with reference to FIGS. 16A to 17D. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted. The configuration of the unit transistor 60 of the semiconductor device according to the sixth embodiment is the same as the configuration of the unit transistor 60 (FIG. 2) of the semiconductor device according to the second embodiment or the unit transistor 60 (FIG. 7) of the semiconductor device according to the third embodiment. It is. In the sixth embodiment, the positional relationship between the operation region 61 of the unit transistor 60 and the opening 45 immediately below the pillar bump 40 is different from that in the second or third embodiment. 16A to 17D show an example in which one unit transistor 60 includes one operation region 61, but two operation regions 61 as in the semiconductor device according to the second embodiment (FIG. 2). May be included.

  FIG. 16A is a diagram showing a positional relationship between the operation region 61 of the unit transistor 60 and the opening 45 of the semiconductor device according to the sixth embodiment. A plurality of openings 45 are arranged inside the outer edge of the operation region 61 of the unit transistor 60 located at both ends in the x-axis direction. The opening 45 is not arranged outside the operation region 61 of the unit transistor 60 at both ends.

  The operation region 61 of the unit transistor 60 at one end (left end) partially overlaps with the opening 45, whereas the operation region 61 of the unit transistor 60 at the other end (right end) has the opening 45. Do not overlap.

  When priority is given to heat radiation from the operation region 61 of the unit transistor 60 located at the left end, an arrangement as shown in FIG. 16A may be used.

  In the example shown in FIG. 16B, the number of unit transistors 60 is odd, for example, five, and the number of openings 45 is also odd, for example, three. The geometric center PA of the operating region 61 of the central unit transistor 60 and the geometric center PO of the central opening 45 are arranged at the same position in the x-axis direction. The shift amount Dx of the closest opening corresponding to the unit transistor 60 increases from the central unit transistor 60 toward the unit transistors 60 at both ends. Therefore, the closer the unit transistor 60 is to both ends, the worse the heat radiation characteristic becomes.

  In this example, in a semiconductor device in which the calorific value of the central unit transistor 60 is relatively large and the calorific value tends to decrease toward both ends, the temperature during operation of the unit transistor 60 can be equalized.

  In the example shown in FIG. 16C, two unit transistors 60 and one opening 45 are arranged. Two unit transistors 60 are arranged at symmetric positions with respect to a virtual straight line passing through the geometric center PO of the opening 45 and parallel to the y-axis. Therefore, the shift amount Dx of the closest opening corresponding to one unit transistor 60 and the shift amount Dx of the closest opening corresponding to the other unit transistor 60 are equal. Therefore, heat radiation characteristics from the two unit transistors 60 can be made substantially equal. Further, the thermal stress generated in the emitter layer 34 and the like of the two unit transistors 60 can be reduced substantially uniformly.

  In the example shown in FIG. 16D, six unit transistors 60 and two openings 45 are arranged. The opening 45 is arranged only inside the operation region 61 of the unit transistor 60 at both ends. The operating regions 61 of the unit transistors 60 at both ends do not overlap with the openings 45. That is, the opening 45 is not disposed directly above the unit transistors 60 at both ends where the temperature tends to be relatively low.

  When the heat generation amount of the unit transistors 60 at both ends is smaller than the heat generation amount of the inner unit transistor 60, by employing this arrangement, the temperature of the junction of the plurality of unit transistors 60 can be equalized.

  In the example shown in FIG. 17A, the plurality of openings 45 are arranged in a matrix in the x-axis direction and the y-axis direction. This arrangement can be considered to be such that each of the plurality of openings 45 of the semiconductor device according to the second embodiment is divided into two in the y-axis direction.

  By dividing the opening 45 in the y-axis direction, the area of each of the openings 45 is reduced. As the flow path cross-sectional area of the heat path in the opening 45 decreases, the thermal resistance increases. Therefore, it becomes easy to control the heat radiation characteristics from the unit transistor 60. Furthermore, since the proportion of the insulating film 52 (FIGS. 3 and 4) where the opening 45 is not formed increases, the effect of relaxing thermal stress increases.

  High-frequency signals tend to pass only through the surface of the conductor due to the skin effect. When the opening 45 is divided, the surface area of the conductor in the opening 45 increases, so that the effect of reducing the resistance to a high-frequency signal can be obtained. Further, since the area of each of the openings 45 is reduced, when the pillar bumps 40 (FIGS. 3 and 4) are formed by plating or the like, the openings 45 are easily filled with a conductor, and the flatness of the upper surface of the pillar bumps 40 is improved. The effect is obtained.

  In FIG. 17A, two openings 45 are arranged in the y-axis direction, but three or more openings 45 may be arranged. When the number of openings 45 arranged in the y-axis direction is increased, the above-described effect is increased.

  In the example shown in FIG. 17B, the geometric center PO of the opening 45 is shifted in the x-axis direction and also shifted in the y-axis direction with respect to the geometric center PA of the operation region 61 of the unit transistor 60. The geometric center PA of the operation area 61 is also shifted in the y-axis direction with respect to the geometric center PP of the pillar bump 40. By displacing the geometric center PO of the opening 45 also in the y-axis direction with respect to the geometric center of the operation area 61, a structure in which the thermal resistance from the operation area 61 to the pillar bump 40 is easily increased can be obtained. As a result, an effect is obtained that the heat radiation characteristics of the unit transistor 60 can be easily adjusted. Further, the effect of relieving thermal stress is enhanced.

  In the example shown in FIG. 17C, the geometric centers PA of the operation regions 61 of the plurality of unit transistors 60 are arranged in a staggered arrangement. Specifically, among the plurality of unit transistors 60 arranged in the x-axis direction, the geometric center PA of the operation region 61 of the odd-numbered unit transistor 60 is arranged on a straight line parallel to the x-axis direction. Similarly, the geometric center PA of the operation region 61 of the even-numbered unit transistor 60 is also arranged on a straight line parallel to the x-axis direction. Further, the geometric center PA of the operation region 61 of the odd-numbered unit transistor 60 is shifted from the geometric center PA of the operation region 61 of the even-numbered unit transistor 60 at a different position in the y-axis direction.

  The geometric center PO of the opening 45 is shifted in the x-axis direction and the y-axis direction with respect to the geometric center PA of any of the operation areas 61. Therefore, an effect similar to that of the example shown in FIG. 17B is obtained.

  In the example shown in FIG. 17D, the amplitude of the staggered arrangement of the geometric center PA of the operation area 61 is larger than that in the example shown in FIG. 17C, and a part of the operation area 61 is outside the pillar bump 40 in plan view. Is jumping out. To avoid a significant increase in thermal resistance, a portion of each of the operating regions 61 is arranged to overlap the pillar bumps 40. The opening 45 is divided in the y-axis direction. The geometric center PO of the opening 45 is shifted in the x-axis direction and the y-axis direction with respect to the geometric center PA of any of the operation areas 61. Therefore, an effect similar to that of the example shown in FIG. 17B is obtained.

[Seventh embodiment]
Next, a semiconductor device according to a seventh embodiment will be described with reference to FIG. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment (FIGS. 2, 3, and 4) will be omitted.

  FIG. 18 is a sectional view of the semiconductor device according to the seventh embodiment. In the second embodiment, the pillar bumps 40 (FIGS. 3 and 4) are formed on the upper surface of the semiconductor chip on which the unit transistors 60 are formed. The semiconductor device according to the seventh embodiment is realized by a wafer level package including a semiconductor chip.

  On a package substrate 100, a semiconductor chip 110 is adhered and fixed. The semiconductor chip 110 has, for example, an element structure from the substrate 30 to the second-layer emitter wiring E2 of the semiconductor device (FIGS. 2, 3, and 4) according to the second embodiment, and insulation covering the second-layer emitter wiring E2. Including the membrane 52. The semiconductor chip 110 includes a plurality of unit transistors 60. On the package substrate 100, in addition to the semiconductor chip 110, other surface-mounted devices are adhered and fixed.

  A semiconductor chip 110 and a surface mount type device are embedded in an insulating film 105 made of resin. The upper surface of the semiconductor chip 110 is located at the same height as the upper surface of the insulating film 105. A plurality of first-layer rewirings 101 are arranged on the semiconductor chip 110 and the insulating film 105. Part of the first-layer rewiring 101 is electrically connected to the lower emitter wiring E2 through an opening 103 formed in the insulating film 52. A plurality of second-layer rewirings 102 are arranged on the first-layer rewiring 101. The second-layer rewiring 102 is electrically connected to a terminal 106 such as a bump disposed thereon. For the first layer rewiring 101 and the second layer rewiring 102, for example, Cu formed by plating is used.

  The planar positional relationship between the first-layer rewiring 101, the opening 103, and the operation region 61 of the unit transistor 60 depends on the pillar bump 40, the opening 45, and the operation region 61 of the unit transistor 60 of the semiconductor device according to the second embodiment. This is equivalent to a planar positional relationship.

  Next, excellent effects obtained by adopting the configuration of the semiconductor device according to the seventh embodiment will be described.

  In the seventh embodiment, the first-layer rewiring 101 has the same function as the pillar bumps 40 (FIGS. 2, 3, and 4) of the second embodiment. That is, the first-layer rewiring 101 functions as a heat path for radiating heat generated in the operation region 61 of the unit transistor 60 to the outside. The opening 103 connecting the first-layer rewiring 101 and the second-layer emitter wiring E2 has the same function as the opening 45 (FIGS. 2, 3, and 4) of the semiconductor device according to the second embodiment. Therefore, the same effect as that of the second embodiment can be obtained by setting the above-described positional relationship between the first-layer rewiring 101, the opening 103, and the operation region 61 of the unit transistor 60.

  The rewiring 101 of the first layer, the opening 103, and the operation region 61 of the unit transistor 60 may be equivalent to the positional relationship of any of the third to sixth embodiments. . In this case, the same effect as any one of the third to sixth embodiments can be obtained.

[Eighth embodiment]
Next, a semiconductor device according to an eighth embodiment will be described with reference to FIG. Hereinafter, the description of the same configuration as the semiconductor device according to the seventh embodiment (FIG. 18) will be omitted.

  FIG. 19 is a sectional view of a semiconductor device according to the eighth embodiment. In the seventh embodiment, as shown in FIG. 18, the semiconductor chip 110 was bonded to the package substrate 100, and the rewirings 101 and 102 were formed on the package substrate 100. In the eighth embodiment, a first layer rewiring 101 and a second layer rewiring 102 are formed on the uppermost insulating film 52 of the semiconductor chip 110. Terminals 106 for external connection are arranged on the second-layer rewiring 102. The first layer rewiring 101 is electrically connected to the second layer emitter wiring E2 via the inside of the opening 103 provided in the insulating film 52.

  Also in the eighth embodiment, the positional relationship between the rewiring 101 of the first layer, the opening 103, and the operation region 61 of the unit transistor 60 is made the same as the positional relationship in the semiconductor device according to the seventh embodiment. The same effects as in the seventh embodiment can be obtained.

[Ninth embodiment]
Next, a semiconductor device according to a ninth embodiment will be described with reference to FIGS. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted. The semiconductor device according to the ninth embodiment includes an HBT in which SiGe is used for a base layer.

  FIG. 20 is a sectional view of the semiconductor device according to the ninth embodiment. In the second embodiment, GaAs is used for the base layer 33, and InGaP is used for the emitter layer. On the other hand, in the ninth embodiment, SiGe is used for the base layer 33.

  A sub-collector layer 131 made of high-concentration n-type Si is arranged on a surface layer of a substrate 130 made of p-type Si, and a collector layer 132 made of n-type Si is arranged thereon. On the collector layer 132, a base layer 133 made of epitaxially grown SiGe is arranged.

  A plurality of active regions are defined by a shallow trench isolation structure extending from the upper surface of the base layer 133 to a position slightly deeper than the upper surface of the sub-collector layer 131, and the unit transistor 60 is arranged in each of the active regions. A plurality of unit transistors 60 are electrically isolated from surrounding circuits by a shallow trench isolation structure reaching the bottom surface of subcollector layer 131. FIG. 20 shows a cross section of two unit transistors 60.

  A p-type external base layer 134 is formed on the surface of a part of the active region. The external base layer 134 surrounds the base layer 133 made of p-type SiGe in plan view. Two base layers 133 are arranged in one active region.

  An insulating film 140 made of silicon oxide or the like is arranged on each of the base layers 133, and an emitter layer 135 made of n-type polysilicon or the like is arranged thereon. Emitter layer 135 contacts base layer 133 through an opening provided in insulating film 140. An operating current flows through the heterojunction interface between the emitter layer 135 and the base layer 133 in the thickness direction. In plan view, the outer peripheral line of the bonding interface defines the operation area 61. Each of unit transistors 60 includes two operation regions 61.

  A base electrode B0 is arranged on the surface of the external base layer 134. The base electrode B0 is formed of, for example, Ti silicide, Ni silicide, or the like. The base electrode B0 is arranged to lower the base resistance. If the base resistance becomes sufficiently low without disposing the base electrode B0, the base electrode B0 need not be disposed.

  An insulating film 141 made of silicon oxide or the like is arranged so as to cover the emitter layer 135, the external base layer 134, and the base electrode B0. On the insulating film 141, a first-layer emitter wiring E1 and a collector wiring C1 made of Al or the like are arranged. The first-layer emitter wiring E1 is electrically connected to the emitter layer 135 through an opening provided in the insulating film 141. The first-layer collector wiring C1 passes through an opening provided in the insulating film 141, and is electrically connected to the sub-collector layer 131 via a high-concentration n-type region 136 provided in a surface mounting portion of the substrate. . For the purpose of lowering the collector resistance, a collector electrode made of metal silicide may be arranged at the interface between the first-layer collector wiring C1 and the n-type region 136.

  The base electrode B0 is connected to the first-layer base wiring at a location not shown in the cross section of FIG.

  A second-layer insulating film 142 made of silicon oxide or silicon nitride is arranged on the insulating film 141 so as to cover the first-layer emitter wiring E1 and the collector wiring C1. A second-layer emitter wiring E2 is disposed on the insulating film 142. The second-layer emitter wiring E2 is electrically connected to the first-layer emitter wiring E1 through an opening provided in the insulating film 142, and mutually connects the emitter layers 135 of the plurality of unit transistors 60. .

  The third-layer insulating film 143, the third-layer wiring 150, the fourth-layer insulating film 144, the fourth-layer wiring 151, and the fifth-layer insulating film 145 are formed on the second-layer emitter wiring E2. They are arranged in order. The third-layer wiring 150 is electrically connected to the second-layer emitter wiring E2 through an opening 155 provided in the third-layer insulating film 143. The fourth-layer wiring 151 is electrically connected to the third-layer wiring 150 through an opening 156 provided in the fourth-layer insulating film 144. The bump 152 is arranged on the fifth insulating film 145. The bump 152 is electrically connected to the wiring 151 of the fourth layer through an opening 157 provided in the insulating film 145 of the fifth layer. The second-layer emitter wiring E2, the third-layer wiring 150, and the fourth-layer wiring 151 are formed of, for example, Al or Cu. The third insulating film 143, the fourth insulating film 144, and the fifth insulating film 145 are formed of, for example, silicon oxide or silicon nitride.

  The upper surfaces of the insulating films from the second insulating film 142 to the fifth insulating film 145 are flattened. Note that the upper surface of the first insulating film 141 may be planarized as necessary.

  FIG. 21 is a diagram showing a planar layout of components of the semiconductor device according to the ninth embodiment. A cross-sectional view taken along a dashed-dotted line 20-20 in FIG. 21 corresponds to FIG. Assuming that the x-axis direction is a row direction and the y-axis direction is a column direction, eight unit transistors 60 are arranged in a matrix of 2 rows and 4 columns. Each of unit transistors 60 includes two operation regions 61. Each of the operation regions 61 has a planar shape that is long in the y-axis direction, and two operation regions 61 are arranged side by side in the x-axis direction in one unit transistor 60.

  A second-layer emitter wiring E2 is arranged for each row of the eight unit transistors 60 arranged in a matrix. The emitter wiring E2 of the second layer includes the inside of the operation region 61 of the unit transistor 60 in the corresponding row in a plan view.

  The third-layer wiring 150, the fourth-layer wiring 151, and the bump 152 are arranged so as to overlap with all of the operation regions 61 of the eight unit transistors 60. Four openings 155 provided in the third insulating film 143 (FIG. 20) are arranged in a matrix of 2 rows and 2 columns. One row of the opening 155 corresponds to one row of the unit transistor 60.

  With respect to a virtual straight line passing through the center of the bump 152 and parallel to the x-axis, the operation region 61 of the unit transistor 60 in the first row and the operation region 61 of the unit transistor 60 in the second row are arranged at line-symmetric positions. . Similarly, with respect to this virtual straight line, the openings 155 in the first row and the openings 155 in the second row are arranged at line-symmetric positions.

  The geometric center PO of the opening 155 is arranged at a position shifted from the geometric center PA of the operation region 61 of one unit transistor 60 in the x-axis direction. Focusing on each row of the unit transistors 60, as in the case of the second embodiment (FIG. 2), the shift amount Dx of the closest opening to the unit transistors 60 at both ends is the shift amount of the closest opening to the inner unit transistor 60. Greater than Dx.

  The opening 156 provided in the fourth insulating film 144 (FIG. 20) and the opening 157 provided in the fifth insulating film 145 (FIG. 20) have the same shape and the same dimensions. Almost overlap in plan view. The openings 156 and 157 are arranged inside the operation regions 61 at both ends in the x-axis direction. In the y-axis direction, the openings 156 and 157 partially overlap with the operation region 61 of the unit transistor 60 in the first row, and partially overlap with the operation region 61 of the unit transistor 60 in the second row.

  FIG. 22 is a diagram showing a planar layout of four unit transistors 60 arranged in one row of the semiconductor device according to the ninth embodiment. Each of the unit transistors 60 includes two operation regions 61 arranged at an interval in the x-axis direction. The base electrode B0 has a comb-shaped planar shape having three comb-tooth portions. The three comb teeth portions of the base electrode B0 are arranged between the two operation regions 61 and outside. The operating region 61 and the base electrode B0 are arranged inside the outer peripheral line 137 of the region where the base layer 133 (FIG. 20) and the external base layer 134 (FIG. 20) are combined.

  The n-type regions 136 are arranged between the unit transistors 60 arranged in the x-axis direction and outside the unit transistors 60 at both ends. The second-layer emitter wiring E2 is arranged so as to include the unit transistor 60 and the n-type region 136 inside in plan view.

  Next, excellent effects obtained by employing the configuration of the semiconductor device according to the ninth embodiment will be described.

  The opening 155 connecting the second-layer emitter wiring E2 and the third-layer wiring 150 functions as a heat path for transmitting heat generated in the operation region 61 to the outside. The opening 155 corresponds to the opening 45 of the semiconductor device (FIG. 2) according to the second embodiment from the viewpoint of radiating the heat generated in the operation region 61.

  In the ninth embodiment, since the geometric center PO of the opening 155 is shifted in the x-axis direction with respect to the geometric center PA of the operation area 61, the same effect as in the second embodiment can be obtained.

[Tenth embodiment]
Next, a semiconductor device according to a tenth embodiment will be described with reference to FIGS. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted. In the second embodiment, the unit transistor 60 (FIGS. 2, 3, and 4) is a heterojunction bipolar transistor. In the tenth embodiment, the unit transistor 60 is a MOS field effect transistor (MOSFET).

  FIG. 23 is a sectional view of the semiconductor device according to the tenth embodiment. An active region 171 surrounded by a shallow trench isolation structure is formed in a surface layer portion of a substrate 170 made of silicon. In the active region 171, a plurality of unit transistors 60 are arranged side by side in the x-axis direction. In the tenth embodiment shown in FIG. 23, five unit transistors 60 are arranged. Each of the unit transistors 60 is a MOSFET, and includes a source region 175 and a drain region 176 spaced apart in the x-axis direction. A gate electrode G0 is arranged on a channel region between source region 175 and drain region 176. A source electrode S0 and a drain electrode D0 are electrically connected to the source region 175 and the drain region 176, respectively. The source region 175 and the drain region 176 other than both ends are shared by the unit transistors 60 on both sides. In the active region 171, an in-plane operation current flows in the operation region 61 directly below the gate electrode G <b> 0.

  A first-layer insulating film 190 is arranged so as to cover the unit transistor 60. On the first insulating film 190, a first layer source wiring S1 and a drain wiring D1 made of Al or the like are arranged. The source wiring S1 and the drain wiring D1 are each electrically connected to the source region 175 via the source electrode S0 through the opening provided in the first insulating film 190, and are connected to the drain region 176 via the drain electrode D0. It is electrically connected.

  A second-layer insulating film 191 is arranged so as to cover the first-layer source wiring S1 and the drain wiring D1. The second-layer source wiring S2 is disposed on the second-layer insulating film 191. The source wiring S2 is electrically connected to a plurality of first-layer source wirings S1 through openings provided in the second-layer insulating film 191.

  A third-layer insulating film 192 is arranged so as to cover the second-layer source wiring S2. A third-layer wiring 180 is arranged on the third-layer insulating film 192. The third-layer wiring 180 is electrically connected to the second-layer source wiring S2 through a plurality of openings 185 provided in the third-layer insulating film 192. A fourth-layer insulating film 193 is arranged so as to cover the third-layer wiring 180.

  The source wiring S2 of the second layer and the wiring 180 of the third layer are formed of, for example, Al or Cu. Each of the insulating films from the first insulating film 190 to the fourth insulating film 193 is formed of, for example, silicon oxide or silicon nitride.

  FIG. 24 is a diagram showing a planar layout of components of the semiconductor device according to the tenth embodiment. Each of the five gate electrodes G0 arranged in the x-axis direction crosses a rectangular active region 171 that is long in the x-axis direction. Each of gate electrodes G0 has a planar shape that is long in the y-axis direction, and extends from one edge of active region 171 that is long in the x-axis direction to the other edge. The region where the active region 171 overlaps the gate electrode G0 (the region hatched in FIG. 24) functions as the operation region 61.

  The third-layer wiring 180 is arranged so as to overlap with all the operation regions 61. Three openings 185 are arranged in the x-axis direction inside the third-layer wiring 180 in plan view. The geometric center PO of the opening 185 is arranged at a position different from the geometric center PA of the operation area 61 in the x-axis direction. In the x-axis direction, the shift amount Dx of the closest opening increases from the central operation area 61 to the operation areas 61 at both ends.

  By setting the positional relationship between the operation region 61 and the opening 185 as described above, the same effect as that of the second embodiment can be obtained. That is, the thermal stress generated in the semiconductor portion of the unit transistor 60 is reduced, and the temperatures during operation of the plurality of unit transistors 60 can be equalized. As a result, an effect is obtained that the high-frequency characteristics are improved as a whole of the transistor circuit in which the unit transistors 60 are connected in parallel.

  In the tenth embodiment, a silicon substrate is used as the substrate 170, but a substrate made of a compound semiconductor may be used. For example, a GaAs substrate may be used as the substrate 170, and the unit transistor 60 may be configured by a high electron mobility transistor (HEMT) having a channel made of InGaAs. Alternatively, the unit transistor 60 may be constituted by a HEMT on a GaN substrate.

[Eleventh embodiment]
Next, a semiconductor device according to an eleventh embodiment will be described with reference to FIGS. 25A and 25B. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted. In the eleventh embodiment, the amount of reduction in the stress generated in the operation region 61 was obtained by simulation by simplifying the structure of the semiconductor device, changing the material and thickness of the insulating film 52 (FIG. 3).

  The planar shape and positional relationship of the operation region 61, the pillar bump 40, and the opening 45 of the semiconductor device to be simulated according to the eleventh embodiment are the same as those of the semiconductor device shown in FIG. 5B. In this simulation, the displacement amount Dx was fixed at 20 μm.

  FIG. 25A is a sectional view of a semiconductor device to be simulated. An operation region 61 made of GaAs is formed on a partial region of the substrate 30 made of GaAs, and a first-layer emitter wiring E1 is arranged thereon. A second-layer emitter wiring E2 is arranged on the emitter wiring E1. The second-layer emitter wiring E2 extends in the in-plane direction.

  An insulating film 52 is disposed on the second-layer emitter wiring E2. An opening 45 is provided in the insulating film 52. The opening 45 is arranged at a position shifted laterally from the operation area 61. The pillar bumps 40 are arranged inside the openings 45 and on the insulating film 52. The material of the emitter wirings E1 and E2 is Au, and the material of the pillar bump 40 is Cu.

  Simulation was performed on four samples A, B, C, and D having different configurations of the insulating film 52. The insulating film 52 of the sample A is a 0.5 μm thick SiN film. The insulating film 52 of the sample B has a two-layer structure of a 0.5 μm thick SiN film and a 5 μm thick benzocyclobutene (BCB) film thereon. The insulating film 52 of the sample C is a 0.5 μm thick BCB film. The insulating film 52 of the sample D is a 5.5 μm thick BCB film.

  FIG. 25B is a graph showing a relationship between the maximum values of the thermal stresses generated in the operation regions 61 of the samples A, B, C, and D. The vertical axis of the graph in FIG. 25B represents the amount of reduction in thermal stress in units of “%”. The reduction amount of the thermal stress is based on the value of the thermal stress when the shift amount Dx (FIG. 5B) is 0, and represents the reduction amount from the reference value as a ratio to the reference value.

  From the simulation result of the sample A, it is understood that the effect of relaxing the stress generated in the operation region 61 can be obtained by using the SiN film for the insulating film 52. Hereinafter, the reason why the stress relaxation effect is obtained will be described.

  The metal such as Cu or Al used for the pillar bumps 40 and the rewiring 101 (FIGS. 18 and 19) has a thermal expansion coefficient of about 20 ppm / ° C. On the other hand, the thermal expansion coefficients of the semiconductor substrate 30 and the operation region 61 are about 6 ppm / ° C. in the case of GaAs, and about 2.6 ppm / ° C. in the case of Si. As described above, the thermal expansion coefficients of the pillar bumps 40 and the rewiring 101 are larger than the thermal expansion coefficients of the substrate 30 and the operation area 61. Thermal stress is generated due to the difference between the thermal expansion coefficients.

  By disposing an insulating film 52 having a coefficient of thermal expansion equal to or less than the coefficient of thermal expansion of the operating region 61 between the pillar bump 40 or the rewiring 101 and the operating region 61, the thermal stress generated in the operating region 61 can be reduced. Can be. Examples of the material having a thermal expansion coefficient equal to or less than the thermal expansion coefficient of the semiconductor substrate 30 or the operation region include SiO and other inorganic insulating materials in addition to SiN.

  From the simulation results of Sample C and Sample D, it is understood that the effect of relaxing the stress generated in the operation region 61 can be obtained by using the BCB film for the insulating film 52. Hereinafter, the reason why the stress relaxation effect is obtained will be described.

  When the pillar bumps 40 and the substrate 30 thermally expand, the strain generated due to the difference between the thermal expansion coefficients of the pillar bumps 40 and the substrate 30 concentrates on the insulating film 52 having a small Young's modulus. For example, the Young's modulus of the GaAs substrate 30 is about 83 GPa, and the Young's modulus of BCB is about 2.9 GPa. For this reason, strain concentrates on the insulating film 52, and strain and stress generated in the operation region 61 can be reduced. In order to obtain a stress relaxation effect, a material having a Young's modulus smaller than that of the substrate 30 may be used for the insulating film 52. In particular, in order to obtain a sufficient stress relaxation effect, it is preferable to use a material having a Young's modulus of 3 GPa or less as the material of the insulating film 52. Examples of such a material include polyimide and other resin-based insulating materials in addition to BCB. In particular, it can be seen that the thicker the BCB film, the higher the stress relaxation effect.

  From the simulation result of the sample B, it is found that the insulating film 52 is a multilayer including two layers: a film having a coefficient of thermal expansion equal to or less than the coefficient of thermal expansion of the semiconductor substrate 30 and a film having a Young's modulus smaller than that of the substrate 30. It can be seen that the use of the film enhances the stress relaxation effect.

[Twelfth embodiment]
Next, a semiconductor device according to a twelfth embodiment and a modification thereof will be described with reference to FIGS. 26A to 27B. Hereinafter, description of the configuration common to the semiconductor device according to the second embodiment will be omitted.

  FIG. 26A is a diagram illustrating a positional relationship between the pillar bump 40, the opening 45, and the operation region 61 of the semiconductor device according to the twelfth embodiment. The whole of the plurality of operation regions 61 is arranged inside the pillar bump 40. In addition, a part of each of the operation regions 61 is disposed inside the opening 45, and the other part is disposed outside the opening 45. The ratio of the area of the portion arranged outside the opening 45 in the operation region 61 is higher in the operation regions 61 at both ends in the x-axis direction than in the operation regions 61 other than both ends. In a portion disposed outside the opening 45, an insulating film 52 (FIG. 3) is disposed between the operation region 61 and the pillar bump 40. Therefore, the higher the ratio of the portion arranged outside the opening 45, the higher the stress relaxation effect is obtained.

  Due to the difference between the thermal expansion coefficients, the thermal stress generated in the operating regions 61 at both ends in the x-axis direction tends to be larger than the thermal stress generated in the inner operating region 61. In the twelfth embodiment shown in FIG. 26A, the ratio of the portion of the operation region 61 arranged outside the opening 45 is relatively high in the operation regions 61 at both ends. For this reason, a high stress relaxation effect can be obtained in the operating regions 61 at both ends where stress is likely to occur.

  In addition, the inside operation region 61 other than both ends is likely to become hot during operation compared to the operation regions 61 at both ends. In the twelfth embodiment, in the inner operation region 61, the ratio of the portion arranged inside the opening 45 is relatively increased, so that a sufficient heat radiation characteristic is ensured in a region where the temperature tends to be high.

  FIG. 26B is a diagram illustrating a positional relationship among pillar bumps 40, openings 45, and operation regions 61 of a semiconductor device according to a modification of the twelfth embodiment. In the present modification, the entire operation area 61 other than both ends in the x-axis direction is arranged inside the opening 45. In the operation regions 61 at both ends, a part is arranged inside the opening 45 and another part is arranged outside the opening 45.

  In the present modification, a stress relaxation effect can be obtained in the operation regions 61 at both ends, and higher heat radiation characteristics can be secured in the inner operation region 61.

  FIG. 26C is a diagram illustrating a positional relationship among pillar bumps 40, openings 45, and operation regions 61 of a semiconductor device according to another modification of the twelfth embodiment. In the present modification, a part of the plurality of operation regions 61 is entirely disposed inside the pillar bump 40, but the remaining operation region 61 is disposed outside the pillar bump 40. Alternatively, they are arranged so as to partially overlap with the pillar bumps 40. In this case, the operation regions 61 located at both ends of the operation region 61 in which the entire region is disposed inside the pillar bump 40 may be considered as the operation regions 61 at both ends shown in FIG. 26A or 26B.

  When attention is paid to a plurality of operation regions 61 in which the whole region is arranged inside the pillar bump 40, the positional relationship between the operation region 61 and the opening 45 is the same as the positional relationship shown in FIG. 26A or 26B. Note that there may be an operation area 61 that is arranged entirely inside the pillar bump 40 and outside the opening 45.

  FIG. 27A is a diagram illustrating a positional relationship among pillar bumps 40, openings 45, and operation regions 61 of a semiconductor device according to still another modification of the twelfth embodiment. In the present modification, a region 47 where the insulating film 52 (FIG. 3) is left is arranged in an island shape inside the outer peripheral line of the opening 45. The region 47 where the insulating film 52 is left is arranged corresponding to the operation region 61, and overlaps the region other than both ends of the corresponding operation region 61. In this modification, since the region 47 where the insulating film is left overlaps the central portion other than the both ends in the y-axis direction of the operating region 61, the stress particularly at the central portion of the operating region 61 can be reduced.

  FIG. 27B is a diagram showing a positional relationship among pillar bumps 40, openings 45, and operation regions 61 of a semiconductor device according to still another modification of the twelfth embodiment. In the present modification, a plurality of, for example, two openings 45 are provided, and each of the openings 45 extends from the operation region 61 at one end to the operation region 61 at the other end in the x-axis direction. Also in this modification, the stress generated in the operation region 61 can be reduced.

  As in the twelfth embodiment and its modification, the whole of at least a part of the plurality of operation regions 61 may be arranged inside the pillar bump 40 in plan view. Further, at least a part of at least one operation region 61 among the operation regions 61 whose entire area is arranged inside the pillar bump 40 may be arranged outside the opening 45.

  Each of the above-described embodiments is an exemplification, and it goes without saying that the configurations shown in the different embodiments can be partially replaced or combined. The same operation and effect of the same configuration of the plurality of embodiments will not be sequentially described for each embodiment. Furthermore, the invention is not limited to the embodiments described above. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

30 Substrate 31 Sub-collector layer 31A Isolation region 32 Collector layer 33 Base layer 34 Emitter layer 34A Emitter region 34B Ledge layer 35 Emitter mesa layer 40 Pillar bump (metal member)
41 Under bump metal layer 42 Metal post 43 Solder layer 45, 46 Opening 47 Regions 50, 51, 52 where insulating film is left Insulating film 55 Capacitor 56 Ballast resistor 60 Unit transistor 61 Operating region 70 Semiconductor chip 71, 72 Filter circuit 75 , 76 Bias circuits 81, 82, 83 Pillar bumps 84, 85, 86 Circular pillar bumps 87, 88 Wiring 90 Mounting substrate 91 Surface mount type device 93 Sealing resin 100 Package substrate 101 First layer rewiring 102 Second layer rewiring Wiring 103 Opening 105 Insulating film 106 Terminal 110 Semiconductor chip 130 Substrate 131 Sub-collector layer 132 Collector layer 133 Base layer 134 External base layer 135 Emitter layer 136 N-type region 137 Peripheral line of region where base layer and external base layer are combined 140, 141, 1 42, 143, 144, 145 Insulating film 150 Third layer wiring 151 Fourth layer wiring 152 Bump 155, 156, 157 Opening 170 Substrate 171 Active region 175 Source region 176 Drain region 180 Wiring 185 Openings 190, 191, 192, 193 insulating film B0 base electrode B1 first-layer base wiring C0 collector electrode C1 first-layer collector wiring C1a, C1b capacitor D0 drain electrode D1 first-layer drain wiring E0 emitter electrode E1 first-layer emitter wiring E2 two-layer Second emitter wiring G0 Gate electrodes L1, L2, L3a, L3b Inductor M2 Second wiring MN1, MN2, MN3 Matching circuit Q1, Q2 Transistor S0 Source electrode S1 First source wiring S2 Second wiring

In the fourth embodiment, the capacitors C1a and C1b of the filter circuits 71 and 72 are connected near the unit transistors 60 at both ends of the plurality of unit transistors 60 arranged in the x-axis direction. As a result, the characteristics of the filter circuits 71 and 72 as a harmonic termination circuit are improved, and as a result, the performance of the power amplifier is improved.

Claims (12)

A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A first wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
A second wiring disposed above the substrate;
An insulating film disposed on the first wiring and the second wiring, wherein at least one first opening that overlaps with the first wiring in an entire area in plan view and a second opening that overlaps with the second wiring are formed. Said insulating film provided;
A first bump disposed on the insulating film and electrically connected to the first wiring through the first opening;
A second bump disposed on the insulating film and electrically connected to the second wiring through the second opening;
In a plan view, at least one of the plurality of operation regions is arranged inside the first bump, and at least one of the operation regions arranged inside the first bump is operated. At least a part of the region is disposed outside the first opening,
A semiconductor device in which the planar shape of the first opening is equal to the planar shape of the second opening.   2. The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the insulating film is equal to or less than a thermal expansion coefficient of the substrate, or a Young's modulus of the insulating film is smaller than a Young's modulus of the substrate.   A plurality of the unit transistors are arranged side by side in one direction, and in a plan view, outside the first opening of the operation regions at both ends of the plurality of operation regions arranged inside the first bump. 3. The method according to claim 1, wherein the ratio of the area of the disposed portion is higher than the ratio of the area of the portion disposed outside the first opening in the operation region other than both ends in the operation regions at both ends. 13. The semiconductor device according to claim 1. A plurality of the first openings are arranged at equal intervals;
A plurality of the second openings are arranged at equal intervals,
4. The semiconductor device according to claim 1, wherein a distance between the plurality of first openings is equal to a distance between the plurality of second openings. 5.   The plurality of unit transistors are arranged side by side in one direction, and the operation region of the plurality of unit transistors has a planar shape that is long in a direction orthogonal to a direction in which the unit transistors are arranged. 5. The semiconductor device according to any one of 4.   The semiconductor device according to claim 1, wherein the first bump forms a pillar bump including a metal post containing copper as a main component.   The semiconductor device according to claim 1, wherein the insulating film includes at least one material of silicon oxide, silicon nitride, and resin.   Each of the plurality of unit transistors is a bipolar transistor including a collector layer, a base layer, and an emitter layer formed on the substrate, and the operation region is a region where an operation current flows in a thickness direction. Item 8. The semiconductor device according to any one of items 1 to 7.   The collector layer, the base layer, and the emitter layer of each of the unit transistors are sequentially stacked on the substrate, and the emitter layer is electrically connected to the first wiring; 9. The semiconductor device according to claim 8, wherein an interface between the base layer and the emitter layer is a hetero junction.   10. The semiconductor device according to claim 9, wherein said substrate is formed of GaAs, and said emitter layer is formed of InGaP.   10. The semiconductor device according to claim 9, wherein each of said unit transistors is a heterojunction bipolar transistor including said base layer made of SiGe.   Each of the plurality of unit transistors is a field-effect transistor including a source, a drain, and a gate formed on the substrate, and the operation region is a region where an operation current flows in an in-plane direction of a surface of the substrate. The semiconductor device according to claim 1, wherein:

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