JP2019220668A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing differences in temperature during operation of a plurality of unit transistors formed on the same substrate and eliciting performance of a whole transistor.SOLUTION: A wiring is arranged above an operation region of a plurality of unit transistors formed on a substrate, and an insulation film is arranged on the wiring. The insulation film is provided with an opening whose whole area overlaps the wiring in a plan view. A metal member electrically connected to the wiring through the opening is arranged on the insulation film. Unit transistors are arranged side by side on the substrate in a first direction. A geometric center of the opening is deviated in a first direction with respect to a geometric center of each operation region of the unit transistors. When an opening having a geometric center nearest to a geometric center of each operation region of the unit transistors is defined as a nearest opening, an amount of deviation in the first direction from the geometric center of the operation region to the geometric center of the nearest opening increases from the center of a sequence of the unit transistors toward an edge of the sequence.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art A heterojunction bipolar transistor (HBT) is used in a power amplifier module of a portable terminal or the like. Patent Document 1 listed below discloses a semiconductor device in which bumps are arranged immediately above an HBT. The bump is electrically connected to the HBT through an opening provided in an insulating film disposed between the HBT and the bump. The entire HBT is arranged inside the opening provided in the insulating film below the bump. With such a configuration, the distance from the HBT to the bump is reduced, and as a result, the thermal resistance of the heat flow path from the HBT to the bump can be reduced.

  With this configuration, thermal stress due to the difference between the coefficient of thermal expansion of the emitter layer of the HBT and the like and the coefficient of thermal expansion of the bump is likely to be generated in the emitter layer and the like. This thermal stress reduces the reliability of the HBT.

  Patent Literature 2 below discloses a semiconductor device capable of relaxing thermal stress. In this semiconductor device, the emitter layer of the HBT has a substantially rectangular planar shape, and an opening provided in the insulating film below the bump is arranged at a position shifted from the emitter layer of the HBT in the longitudinal direction. I have. By employing this configuration, the thermal stress generated in the emitter layer and the like is reduced as compared with the case where the entire area of the emitter layer is arranged inside the opening.

JP 2003-77930 A Japanese Patent No. 5967317

  Patent Document 2 discloses a semiconductor device including one hetero bipolar transistor. In practice, a configuration in which a plurality of unit transistors are formed on one substrate and connected in parallel is often adopted. When a plurality of unit transistors connected in parallel are operated, the temperature of the unit transistors may vary. A unit transistor that easily becomes high in temperature deteriorates faster than other unit transistors, and the life of the semiconductor device as a whole is shortened. Furthermore, if the temperature fluctuates during the operation, the high-frequency characteristics deteriorate.

  An object of the present invention is to provide a semiconductor device capable of reducing a temperature difference during operation of a plurality of unit transistors formed on a substrate and through which an operating current flows, and which can bring out performance of the entire transistor. is there.

According to one aspect of the invention,
A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the wiring, wherein the insulating film is provided with at least one opening, the entire area of which is overlapped with the wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the wiring through the opening;
A plurality of the unit transistors are arranged on the substrate in a first direction;
In a plan view, a geometric center of the opening is shifted in the first direction with respect to a geometric center of the operation region of each of the plurality of unit transistors;
When the opening having the geometric center closest to the geometric center of the operation region of each of the plurality of unit transistors is defined as the closest opening, the opening from the geometric center of the operation region to the geometric center of the closest opening is A semiconductor device is provided in which the amount of displacement in one direction increases from the center to the end of the arrangement of the plurality of unit transistors.

According to another aspect of the present invention,
A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the wiring, wherein the insulating film is provided with at least one opening, the entire area of which is overlapped with the wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the wiring through the opening;
A plurality of the unit transistors are arranged side by side in the first direction on the substrate;
In a plan view, a geometric center of the opening is shifted in the first direction with respect to a geometric center of the operation region of each of the plurality of unit transistors,
When the opening having the geometric center closest to the geometric center of the operation region of each of the plurality of unit transistors is defined as the closest opening, the unit transistor of the unit transistor arranged at one end with respect to the first direction is defined. The amount of shift in the first direction from the geometric center of the operation region to the geometric center of the closest opening is determined by the amount of shift from the geometric center of the operation region of the unit transistor disposed at the other end. A semiconductor device smaller than the shift amount in the first direction up to the geometric center of the semiconductor device.

According to yet another aspect of the invention,
A plurality of unit transistors formed on the substrate and including at least one operation region through which an operation current flows;
A wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the wiring, wherein the insulating film is provided with at least one opening, the entire area of which is overlapped with the wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the wiring through the opening;
A plurality of the unit transistors are arranged side by side in the first direction on the substrate;
In a plan view, a minimum rectangle including the operation region of each of the plurality of unit transistors is defined as an effective operation region, and passes through a midpoint of a line segment having both ends at the geometric centers of the adjacent effective operation regions. When defining a plurality of regions separated by a virtual straight line parallel to a second direction orthogonal to the first direction as an influence range corresponding to the effective operation region located inside the region, The area of the overlapping region, which is the region where the affected range and the opening overlap, is different depending on the effective operation region,
A semiconductor device is provided in which the area of the overlap region corresponding to the effective operation region located at both ends in the first direction is smaller than the area of the overlap region corresponding to the effective operation region other than both ends.

  Heat generated in the operation area or the effective operation area is conducted to the upper surface of the metal member through the metal member in the opening. If the opening is shifted with respect to the operation region, or if the area of the overlap region differs depending on the effective operation region, the heat radiation characteristics change depending on the operation region or the effective operation region. When the temperature of the operating area or the effective operating area tends to be non-uniform, the heat dissipation characteristics are made different for each operating area or effective operating area so as to reduce the non-uniformity of the temperature. The temperature difference can be reduced.

FIG. 1 is a diagram showing a planar layout of components of the semiconductor device according to the first embodiment. FIG. 2 is a sectional view taken along dashed line 2-2 in FIG. FIG. 3 is a sectional view taken along dashed line 3-3 in FIG. FIG. 4A and FIG. 4B are plan views illustrating the positional relationship between the operation region, the opening, and the pillar bump of the semiconductor device according to the comparative example and the example, respectively. FIG. 5A is a graph showing the relationship between the shift amounts Dx and Dy and the reduction amount of the thermal stress generated in the emitter region, and FIG. 5B is a graph showing the relationship between the shift amounts Dx and Dy and the thermal resistance increase amount. is there. FIG. 6 is a diagram showing a planar layout of components of the semiconductor device according to the second embodiment. FIG. 7 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the third embodiment. FIG. 8 is an equivalent circuit diagram of the transistor Q2 and its peripheral circuits. FIG. 9 is a diagram showing a layout of each element of a semiconductor chip constituting a semiconductor device according to the third embodiment. FIG. 10A is a diagram showing a pillar bump, an operating region of a plurality of unit transistors connected thereto, and a positional relationship between a plurality of openings, and FIG. 10B is a view showing a circular pillar bump and an opening arranged thereunder. It is a figure showing a positional relationship. FIG. 11 is a sectional view of a semiconductor device according to the third embodiment. FIG. 12 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fourth embodiment. FIG. 13 is a diagram showing a layout of each element of a semiconductor chip constituting the semiconductor device according to the fourth embodiment. FIG. 14 is a diagram showing a positional relationship between pillar bumps, operation regions of unit transistors, and openings. FIGS. 15A, 15B, 15C, and 15D are views showing the positional relationship between the operation region and the opening of the unit transistor of the semiconductor device according to the fifth embodiment and its modification. FIGS. 16A, 16B, 16C, and 16D are views showing the positional relationship between the operation region and the opening of the unit transistor of the semiconductor device according to the modification of the fifth embodiment. FIG. 17 is a sectional view of the semiconductor device according to the sixth embodiment. FIG. 18 is a sectional view of the semiconductor device according to the seventh embodiment. FIG. 19 is a sectional view of a semiconductor device according to the eighth embodiment. FIG. 20 is a diagram showing a planar layout of components of the semiconductor device according to the eighth embodiment. FIG. 21 is a diagram showing a planar layout of components of four unit transistors arranged in one row of the semiconductor device according to the eighth embodiment. FIG. 22 is a sectional view of the semiconductor device according to the ninth embodiment. FIG. 23 is a diagram showing a planar layout of components of the semiconductor device according to the ninth embodiment. FIG. 24A is a diagram showing a positional relationship between an operation region and an effective operation region. FIG. 24B is a diagram showing an arrangement of operation regions of the semiconductor device according to the tenth embodiment. 5 is a graph showing a temperature distribution in an operation region when there is a temperature distribution. FIG. 25A is a diagram showing a positional relationship between an operation region, an opening, and a pillar bump of a semiconductor device according to the tenth embodiment. FIGS. 25B and 25C are diagrams showing an operation region, an opening, and a semiconductor device according to a modification of the tenth embodiment. FIG. 3 is a diagram showing a positional relationship between the first and second pillar bumps. FIGS. 26A, 26B, and 26C are diagrams illustrating a positional relationship between an operation region, an opening, and a pillar bump of a semiconductor device according to a modification of the tenth embodiment. FIG. 27 is a diagram illustrating a positional relationship between an operation region, an opening, and a pillar bump of a semiconductor device according to a modification of the tenth embodiment. FIG. 28 is a diagram showing an arrangement of operation regions of the semiconductor device according to the eleventh embodiment, and a graph showing a temperature distribution in the operation region when the heat radiation characteristics from the operation region are constant. FIG. 29A is a diagram illustrating a positional relationship between an operation region, an opening, and a pillar bump of the semiconductor device according to the eleventh embodiment. FIGS. 29B and 29C are diagrams illustrating an operation region, an opening, and a semiconductor device according to a modification of the eleventh embodiment. FIG. 3 is a diagram showing a positional relationship between the first and second pillar bumps. FIGS. 30A, 30B, and 30C are diagrams showing a positional relationship between an operation region, an opening, and a pillar bump of a semiconductor device according to a modification of the eleventh embodiment. FIG. 31 is a diagram showing a positional relationship between an operation region, an opening, and a pillar bump of a semiconductor device according to a modification of the eleventh embodiment. FIGS. 32A and 32B are diagrams illustrating the positional relationship between the effective operation area, the openings, and the pillar bumps of the semiconductor device according to the twelfth embodiment and its modification.

[First embodiment]
A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 5B.
FIG. 1 is a diagram showing a planar layout of components of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along dashed line 2-2 in FIG. 1, and FIG. 3 is a cross-sectional view taken along dashed line 3-3 in FIG. A semiconductor device is configured by stacking a plurality of components. In FIG. 1, in order to make it easy to distinguish components of the semiconductor device, lower components hidden by upper components are indicated by broken lines. May be. Further, the outer periphery of the component may be indicated by a broken line, or the component may be hatched with a different density.

  An xyz orthogonal coordinate system is defined in which the horizontal direction in the plan view shown in FIG. 1 is the x-axis direction, the vertical direction is the y-axis direction, and the direction perpendicular to the plane of FIG. A plurality of unit transistors 60 are arranged side by side in the first direction (x-axis direction). In the first embodiment shown in FIG. 1, four unit transistors 60 are arranged side by side. The plurality of unit transistors 60 are connected to each other in parallel by an upper layer wiring.

  Each of the unit transistors 60 includes a collector layer 32, a base layer 33, an emitter layer 34, a collector electrode C0, a base electrode B0, and two emitter electrodes E0. A region of the emitter layer 34 that contributes to the operation of the HBT (a region where an emitter current flows substantially) is referred to as an emitter region 34A. The two emitter electrodes E0 are respectively arranged inside the emitter region 34A. Each of the two emitter regions 34A has a rectangular planar shape elongated in the y-axis direction, and the two emitter regions 34A are arranged at intervals in the x-axis direction. The main part of base electrode B0 is arranged between two emitter regions 34A. As will be described later with reference to FIG. 2, an operating current flows in the emitter region 34A in the thickness direction (z-axis direction). The region inside the emitter region 34A in plan view becomes the operation region 61 of the unit transistor 60, and the operation region 61 mainly becomes a heat source. In FIG. 1, the operation area 61 is hatched in a downward-sloping manner.

  The emitter region 34A and the base electrode B0 are disposed inside the base layer 33. The base electrode B0 has a portion (connection portion) extending from one end of the main portion (the end on the positive side of the y-axis in FIG. 1) toward both sides in parallel with the x-axis direction. The first-layer base wiring B1 is connected to this connection portion. The first-layer base wiring B1 intersects with the second-layer wiring M2, and a capacitor 55 is formed in a crossing region. Further, the first-layer base wiring B1 is connected to the ballast resistor 56.

  Collector electrodes C0 are arranged on both sides of the base layer 33 in the x-axis direction. Two adjacent unit transistors 60 share a collector electrode C0 disposed between the base layers 33 of the unit transistors 60.

  Above the emitter layer 34, a second-layer emitter wiring E2 is arranged. Here, “above” refers to a space that is not directly in contact with the emitter layer 34 but is located above the emitter layer 34. The second-layer emitter wiring E2 is arranged above the operation region 61. The emitter wiring E2 of the second layer includes four unit transistors 60 inside when viewed in plan, and functions as a wiring through which an operating current flows to the unit transistors 60. The second-layer emitter wiring E2 is electrically connected to the emitter electrode E0 via the first-layer emitter wiring E1 (FIGS. 2 and 3).

  A pillar bump (metal member) 40 is arranged so as to overlap the emitter wiring E2 of the second layer in plan view. The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via a plurality of openings 45 provided in the insulating film immediately below the pillar bump 40. In FIG. 1, the opening 45 is provided with a thin hatching that rises to the right.

  For example, the dimension (width) in the x-axis direction of each of the emitter regions 34A is 2 μm or more and 8 μm or less, and the dimension (length) in the y-axis direction is 10 μm or more and 40 μm or less. The dimension of the pillar bump 40 in the x-axis direction is 70 μm or more and 500 μm or less, and the dimension in the y-axis direction is 60 μm or more and 100 μm or less. The dimension of the opening 45 in the x-axis direction is not less than 10 μm and not more than 60 μm.

  As shown in FIG. 2, a subcollector layer 31 made of high-concentration n-type GaAs is formed on a substrate 30 made of semi-insulating GaAs. The thickness of the sub-collector layer 31 is, for example, 0.5 μm.

  A plurality of mesas in which a collector layer 32, a base layer 33, and an emitter layer 34 are stacked are arranged on the sub-collector layer 31. One mesa corresponds to one unit transistor 60 (FIG. 1). Alternatively, a transistor sharing one continuous base layer 33 can be referred to as a unit transistor 60. On the emitter layer 34, two emitter mesa layers 35 are arranged apart from each other in the x-axis direction. The emitter layer 34 immediately below the emitter mesa layer 35 operates as an emitter region 34A through which an operation current flows in the thickness direction. In the emitter layer 34, a region where the emitter mesa layer 35 is not disposed is depleted and is called a ledge layer 34B. The ledge layer 34B functions as a protective layer that suppresses carrier recombination on the surface of the base layer 33.

  The collector layer 32 is formed of, for example, n-type GaAs, and has a thickness of 1 μm. The base layer 33 is formed of, for example, p-type GaAs, and has a thickness of 100 nm. The emitter layer 34 is formed of, for example, n-type InGaP, and has a thickness of 30 nm or more and 40 nm or less. The interface between the emitter layer 34 and the base layer 33 forms a hetero junction. The emitter mesa layer 35 has a two-layer structure of, for example, a 100-nm-thick layer made of high-concentration n-type GaAs and a 100-nm-thick layer made of high-concentration n-type InGaAs.

  An emitter electrode E0 is arranged on the emitter mesa layer 35. As the emitter electrode E0, for example, a Ti film having a thickness of 50 nm is used. The emitter electrode E0 is ohmically connected to the emitter mesa layer 35.

  An opening is provided in the ledge layer 34B in a region between the two emitter mesa layers 35, and the base electrode B0 is disposed in the opening. The base electrode B0 is ohmically connected to the base layer 33. The base electrode B0 is formed, for example, by laminating a Ti film, a Pt film, and an Au film in this order.

  A collector electrode C0 is disposed on the sub-collector layer 31 between two mesas, each of which includes three layers, that is, a collector layer 32, a base layer 33, and an emitter layer. The collector electrode C0 is formed, for example, by laminating an AuGe film, a Ni film, and an Au film in this order. Collector electrode C0 is ohmically connected to subcollector layer 31. The collector electrode C0 is shared by the two unit transistors 60 on both sides thereof. Subcollector layer 31 functions as a current path connecting collector electrode C0 and collector layer 32.

  An insulating film 50 is formed so as to cover the mesa including the collector layer 32 to the emitter layer 34, the emitter mesa layer 35, the emitter electrode E0, the base electrode B0, and the collector electrode C0. As the insulating film 50, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used.

  On the insulating film 50, a first-layer emitter wiring E1 and a first-layer collector wiring C1 are arranged. The first-layer emitter wiring E1 is electrically connected to the emitter electrode E0 through an opening provided in the insulating film 50. The first-layer collector wiring C1 is electrically connected to the collector electrode C0 through an opening provided in the insulating film 50. The first-layer emitter wiring E1 and the first-layer collector wiring C1 have a stacked structure in which, for example, a 50-nm-thick Ti film and a 1-μm-thick Au film are stacked in this order.

  A second insulating film 51 is formed on the insulating film 50 so as to cover the first emitter wiring E1 and the collector wiring C1. As the second insulating film 51, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used. On the second insulating film 51, a second emitter wiring E2 is arranged. The second-layer emitter wiring E2 includes, for example, a 50-nm-thick Ti film and a 4-μm-thick Au film disposed thereon. The second-layer emitter wiring E2 is connected to the first-layer emitter wiring E1 through an opening provided in the insulating film 51. The first-layer emitter wiring E1 arranged for each unit transistor 60 is connected to each other via the second-layer emitter wiring E2.

  A third-layer insulating film 52 is arranged so as to cover the second-layer emitter wiring E2. As the third insulating film 52, for example, a SiN single layer film or a laminated film of a SiN film and a resin film is used. A plurality of openings 45 (only one opening 45 is shown in FIG. 2) are formed in the third insulating film 52. As shown in FIG. 1, the plurality of openings 45 are arranged inside the second-layer emitter wiring E2 in plan view, and the second-layer emitter wiring E2 is exposed at the bottom thereof.

  The pillar bump (metal member) 40 is arranged on the third insulating film 52. The pillar bump 40 includes a lowermost under bump metal layer 41, a metal post 42 thereon, and an uppermost solder layer 43. The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 through the opening 45.

  As the under bump metal layer 41, for example, a Ti film having a thickness of 100 nm can be used. The under bump metal layer 41 has a function of improving the adhesiveness to the underlying insulating film 52. For the metal post 42, for example, a metal material containing copper as a main component can be used. For example, a Cu film having a thickness of about 20 μm or more and about 50 μm or less can be used as the metal post 42. As the solder layer 43, for example, a Sn film having a thickness of 30 μm can be used. Note that a barrier metal layer for preventing mutual diffusion may be arranged between the metal post 42 and the solder layer 43. For example, Ni can be used for the barrier metal layer.

  In each of the unit transistors 60, a large amount of electrons are injected from the emitter region 34A into the base layer 33. Most of the electrons injected into the base layer 33 are mainly transported through the collector layer 32 in the thickness direction and reach the sub-collector layer 31. At this time, Joule heat is generated due to a voltage drop in the base layer 33 and the collector layer 32. For this reason, the emitter layer 34, the base layer 33, and the collector layer 32 immediately below the emitter mesa layer 35 become an operation region 61, and heat is generated in the operation region 61. In plan view, the outer peripheral line of the operation region 61 coincides with the outer peripheral line of the emitter mesa layer 35.

  Next, a configuration not shown in the cross-sectional view of FIG. 2 will be described with reference to FIG. The isolation region 31A is formed by increasing the resistance of a part of the sub-collector layer 31. In this specification, the sub-collector layer 31 indicates a region other than the isolation region 31A. The mesa including the collector layer 32, the base layer 33, and the emitter layer 34 is disposed on the sub-collector layer 31 surrounded by the isolation region 31A.

  The first-layer base wiring B1 is arranged on the first-layer insulating film 50. The first-layer base wiring B1 is electrically connected to the base electrode B0 through an opening provided in the insulating film 50.

  Next, the positional relationship between the pillar bump 40, the opening 45, and the operation area 61 will be described. The geometric center PA (FIG. 1) of the operation region 61 is defined for each unit transistor 60. The geometric center PA corresponds to the position of the center of gravity of the two operation regions 61 included in the unit transistor 60. That is, when focusing on one unit transistor 60, the area of the operation region 61 on the positive side of the x-axis from the geometric center PA is equal to the area of the operation region 61 on the negative side. Further, the area of the operation area 61 on the positive side of the y-axis from the geometric center PA is equal to the area of the operation area 61 on the negative side. In this specification, the geometric center of the two operation regions 61 included in one unit transistor 60 as a whole is simply referred to as the geometric center PA of the operation region 61.

  Furthermore, the geometric center PO of each of the openings 45 is defined. The geometric center PO corresponds to the position of the center of gravity of each of the openings 45. For example, when the plane shape of the opening 45 is a rectangle, the geometric center PO coincides with the intersection of two diagonal lines of the rectangle.

  A plurality of unit transistors 60 are arranged in the x-axis direction (a direction orthogonal to the longitudinal direction of the operation region 61), and the plurality of openings 45 are also arranged in the x-axis direction. The geometric center PO of each of the two openings 45 is shifted from the geometric center PA of the operation area 61 in the x-axis direction.

  The shift amounts between the geometric center PA of the operation region 61 of the unit transistor 60 located at the left end and the right end in the x-axis direction and the geometric center PO of the opening 45 closest thereto are represented by Dx1 and Dx4, respectively. The amounts of shift between the geometric center PO of the operation region 61 of the second and third unit transistors 60 from the left and the geometric center PO of the opening 45 closest thereto are represented by Dx2 and Dx3, respectively. At this time, the shift amounts Dx1 and Dx4 are larger than the shift amounts Dx2 and Dx3.

  Further, the geometric center PO of the opening 45 is also shifted in the y-axis direction with respect to the geometric center PA of the operation area 61.

Next, excellent effects obtained by the configuration of the semiconductor device according to the first embodiment will be described.
In the first embodiment, as shown in FIG. 1, the operating region 61 of the unit transistor 60 is arranged inside the pillar bump 40 in plan view. As shown in FIGS. 2 and 3, in the cross-sectional views, the pillar bumps 40 are arranged directly above the operation regions 61 of the unit transistors 60. For this reason, the distance from the operation region 61 to the pillar bump 40 is shorter than in a structure in which the pillar bump 40 is arranged at a position shifted from directly above the operation region 61.

  The pillar bump 40 functions as a heat path for radiating heat generated in the operation region 61 to the outside. By reducing the distance from the operation region 61 to the pillar bump 40, heat dissipation can be improved.

  Furthermore, since the entire region of the operation region 61 is arranged so as to overlap the pillar bump 40 in a plan view, the chip area of the semiconductor device can be reduced as compared with a configuration in which the operation region 61 protrudes from the pillar bump 40. This makes it possible to reduce costs.

  Furthermore, by employing the configuration of the semiconductor device according to the first embodiment, an effect is obtained that thermal stress generated in the unit transistor 60 can be reduced. Hereinafter, this effect will be described.

  The thermal stress occurs due to the difference between the coefficient of thermal expansion of the semiconductor layer such as the emitter layer 34 (FIG. 2) and the coefficient of thermal expansion of the pillar bump 40. The metal constituting the pillar bumps 40 has a larger coefficient of thermal expansion than the coefficient of thermal expansion of GaAs (about 6 ppm / ° C.). For example, the thermal expansion coefficient of Cu is 17 ppm / ° C., and the thermal expansion coefficient of Sn solder is 22 ppm / ° C. Further, the coefficient of thermal expansion (15 ppm / ° C. or more and 20 ppm / ° C. or less) of the printed circuit board on which the semiconductor device is mounted is larger than the coefficient of thermal expansion of GaAs.

  When the geometric center PO of the opening 45 is separated from the geometric center PA of the operation region 61, the insulating film 52 exists between the emitter layer 34 and the pillar bump 40. For example, the insulating film 52 is disposed between the unit transistor 60 on the left side and the pillar bump 40 shown in FIG. Since the insulating film 52 functions as a stress relaxation material, thermal stress generated in the semiconductor layer of the unit transistor 60 is reduced. When crystal defects occur due to thermal stress, the current amplification rate decreases in a short time. In the first embodiment, since the thermal stress is reduced, a decrease in reliability due to operation at a high temperature can be suppressed. When a plurality of unit transistors 60 are arranged, the magnitude of the thermal stress generated in the unit transistors 60 varies depending on the relative positional relationship between the pillar bumps 40 and the unit transistors 60. Regarding the unit transistor 60 where heat stress is unlikely to be generated, the emitter layer 34 may be arranged inside the opening 45 in plan view.

  The coefficient of thermal expansion of the material used for the insulating film 52 is often smaller than the coefficient of thermal expansion of the material of the pillar bumps 40 or a semiconductor material such as GaAs. For example, the thermal expansion coefficient of SiN used for the insulating film 52 is 2 ppm / ° C. or more and 3 ppm / ° C. or less. By using a material having a smaller coefficient of thermal expansion than the coefficient of thermal expansion of the semiconductor material forming the operation region 61 of the unit transistor 60 for the insulating film 52, a remarkable effect of reducing thermal stress can be obtained.

  In particular, the thermal stress generated in the semiconductor layers such as the emitter layers 34 of the two unit transistors 60 disposed at both ends in the x-axis direction tends to be larger than the thermal stress generated in the semiconductor layers of the other unit transistors 60. . In the first embodiment, the deviation amounts Dx1 and Dx4 between the geometric center PA of the operation region 61 of the unit transistors 60 at both ends and the geometric center PO of the opening 45 are larger than the deviation amounts Dx2 and Dx3 in the other operation regions 61. Therefore, the effect of reducing the thermal stress generated in the semiconductor layers of the unit transistors 60 at both ends is particularly enhanced. As a result, thermal stress generated in the semiconductor layers of the plurality of unit transistors 60 can be leveled. As a result, a decrease in the reliability of the entire semiconductor device can be suppressed.

  Further, by applying the configuration of the semiconductor device according to the first embodiment, it is possible to obtain an effect that the heat radiation characteristics of the plurality of unit transistors 60 from the operation region 61 can be controlled for each unit transistor 60. Hereinafter, this effect will be described.

  The heat generated in the operation region 61 (FIG. 2) is mainly radiated to the outside via the emitter electrode E0, the first-layer emitter wiring E1, the second-layer emitter wiring E2, and the pillar bump 40. When the geometric center PO of the opening 45 is separated from the geometric center PA of each operation region 61 of the unit transistor 60, the insulating film 52 exists between the first-layer emitter wiring E1 and the pillar bump 40. For example, the insulating film 52 is not disposed between most of the first-layer emitter wiring E1 connected to the unit transistor 60 on the right side of FIG. On the other hand, an insulating film 52 is arranged between the entire first-layer emitter wiring E1 connected to the unit transistor 60 on the left side of FIG.

  The thermal conductivity of SiN or resin used for the insulating film 52 is lower than the thermal conductivity of metal used for wiring and pillar bumps. Therefore, the thermal resistance from the operating region 61 of the left unit transistor 60 to the pillar bump 40 is higher than the thermal resistance from the operating region 61 of the right unit transistor 60 to the pillar bump 40. As a result, the heat radiation characteristics of the left unit transistor 60 from the operation region 61 are worse than the heat radiation characteristics of the right unit transistor 60 from the operation region 61. In general, the larger the amount of deviation from the geometric center PA of the operation region 61 of each unit transistor 60 to the geometric center PO of the nearest opening 45, the worse the heat radiation characteristics from the operation region 61 are. it can.

  In the unit transistors 60 other than the unit transistors 60 at both ends shown in FIG. 1, other unit transistors 60 are adjacent on both sides in the x-axis direction. For this reason, the operating region 61 of the unit transistor 60 on the inner side tends to be higher in temperature than the operating region 61 of the unit transistor 60 on both ends.

  In the first embodiment, the shift amounts Dx2 and Dx3 shown in FIG. 1 are smaller than the shift amounts Dx1 and Dx4. In other words, when the opening 45 having the geometric center closest to the geometric center of each of the operation regions 61 of the plurality of unit transistors 60 is defined as the closest opening, the closest to the geometric center of the operation region 61 of each of the unit transistors 60 is defined. The amount of displacement in the x-axis direction to the geometric center of the opening increases from the center of the arrangement of the plurality of unit transistors 60 to the end. Therefore, the heat radiation characteristics of the two inner unit transistors 60 from the operation region 61 are higher than the heat radiation characteristics of the two unit transistors 60 at both ends from the operation region 61. Since the heat radiation characteristics from the operation region 61 where the temperature tends to be relatively high are relatively high, it is possible to suppress the temperature variation in the operation region 61 of the plurality of unit transistors 60. By performing a simulation or an evaluation experiment using various combinations of the shift amounts Dx1, Dx2, Dx3, and Dx4, an appropriate shift amount for leveling the temperatures of the plurality of operation regions 61 can be determined. By leveling the temperatures of the plurality of operation regions 61, it is possible to suppress a decrease in high-frequency characteristics.

  Further, when a plurality of unit transistors 60 are connected and operated in parallel, the life of the unit transistors 60 whose temperature is high is relatively shortened. Therefore, the life of the semiconductor device including the plurality of unit transistors 60 is shortened. By leveling the temperatures of the operation regions 61 of the plurality of unit transistors 60, it is possible to suppress a decrease in the lifetime of the semiconductor device as a whole.

  In the first embodiment, the opening 45 is not disposed outside the geometric center of the operation region 61 of the two unit transistors 60 disposed at both ends in the x-axis direction. By arranging the openings 45 in this manner, the heat radiation characteristics of the unit transistors 60 disposed inside from the operation region 61 can be higher than the heat radiation characteristics of the unit transistors 60 at both ends from the operation region 61.

  The effect of employing a configuration in which the geometric center PO of the opening 45 is shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60 has been confirmed by simulation. Hereinafter, this simulation will be described with reference to FIGS. 4A to 5B. The simulation target has a configuration in which one unit transistor 60 includes one operation region 61.

  FIG. 4A is a plan view illustrating a positional relationship among an operation region 61, an opening 45, and a pillar bump 40 of a semiconductor device according to a comparative example to be simulated. The planar shape of the pillar bump 40 is a race track shape in which a semicircle having a diameter of 75 μm is connected to both ends in the length direction of a rectangle having a length of 240 μm in the x-axis direction and a width of 75 μm in the y-axis direction. The dimension of the operation area 61 in the x-axis direction was 4 μm, and the dimension in the y-axis direction was 30 μm. The size of the opening 45 in the x-axis direction was 240 μm, and the size in the y-axis direction was 51 μm. The positions of the geometric center PA of the operation area 61 and the geometric center PO of the opening 45 in the x-axis direction were matched, and the positions in the y-axis direction were shifted. The absolute value of the shift amount in the y-axis direction is represented by Dy.

  FIG. 4B is a plan view illustrating a positional relationship between the operation region 61, the opening 45, and the pillar bump 40 of the semiconductor device according to the embodiment. The shapes and dimensions of the pillar bumps 40 and the operation regions 61 are the same as those of the semiconductor device shown in FIG. 4A. The size of the opening 45 in the x-axis direction was 20 μm, and the size in the y-axis direction was 50 μm. The position of the geometric center PA of the operation area 61 and the position of the geometric center PO of the opening 45 in the y-axis direction were matched, and the position in the x-axis direction was shifted. The absolute value of the shift amount in the x-axis direction is represented by Dx.

  In the simulation, the thermal stress generated in the emitter region 34A (FIGS. 2 and 3) when the temperature of the semiconductor device was 150 ° C. was obtained. Further, the thermal resistance from the emitter region 34A to the pillar bump 40 was determined.

  FIG. 5A is a graph showing the relationship between the shift amounts Dx and Dy and the reduction amount of the thermal stress generated in the emitter region 34A. The horizontal axis of the graph of FIG. 5A represents the deviation amounts Dx and Dy in units of “μm”, and the vertical axis represents the reduction amount of thermal stress in units of “%”. The circle symbol and the triangle symbol in the graph of FIG. 5A indicate the calculation results of the reduction amount of the thermal stress in the semiconductor device according to the comparative example (FIG. 4A) and the semiconductor device according to the example (FIG. 4B). The amount of reduction in the thermal stress is based on the value of the thermal stress when the shift amount Dy of the semiconductor device (FIG. 4A) according to the comparative example is 0, and the amount of reduction from the reference value is expressed as a ratio to the reference value. .

  It can be seen that in the semiconductor device of the comparative example (FIG. 4A), the thermal stress decreases as the shift amount Dy increases. In the semiconductor device of the example (FIG. 4B), it was confirmed that the thermal stress tended to decrease more slowly than in the comparative example, but the thermal stress decreased as the shift amount Dx increased.

  FIG. 5B is a graph showing the relationship between the shift amounts Dx and Dy and the increase amount of the thermal resistance. The horizontal axis of the graph in FIG. 5B represents the deviation amounts Dx and Dy in units of “μm”, and the vertical axis represents the increase in the thermal resistance in units of “%”. A circle symbol and a triangle symbol in the graph of FIG. 5B indicate calculation results of the increase in thermal resistance of the semiconductor device according to the comparative example (FIG. 4A) and the semiconductor device according to the example (FIG. 4B). The amount of increase in the thermal resistance is based on the value of the thermal resistance of the semiconductor device according to the comparative example (FIG. 4A) when the deviation Dy = 0, and the amount of increase from the reference value is represented by a ratio to the reference value. . It can be seen that the thermal resistance increases as the shift amounts Dx and Dy increase. From this simulation result, it was confirmed that the thermal resistance can be controlled by changing the shift amount of the opening 45 in the x-axis direction or the y-axis direction with respect to the operation region 61.

  Next, a modification of the first embodiment will be described. In the first embodiment, the emitter electrode E0 is arranged between the emitter mesa layer 35 (FIG. 2) and the first-layer emitter wiring E1 (FIG. 2). As another configuration, a configuration in which the first-layer emitter wiring E1 is in direct contact with the emitter mesa layer 35 may be employed. In this case, the emitter electrode E0 is omitted, and the first-layer emitter wiring E1 also serves as the emitter electrode.

  In the first embodiment, in FIG. 1, the geometric centers PO of all the openings 45 are shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60. May be shifted in the x-axis direction with respect to the geometric center PA of each operation region 61 of the unit transistor 60. Here, "displace in the x-axis direction" means that the geometric center PO is shifted with respect to the geometric center PA so that a vector having the geometric center PA as a start point and the geometric center PO as an end point includes an x component. .

  In the first embodiment, two openings 45 are arranged to connect to the pillar bumps 40 and the emitter wiring E2 of the second layer, but at least one opening 45 may be arranged.

  In the first embodiment, the pillar bumps 40 are used as bumps for external connection, but other bumps, such as solder bumps and stud bumps, may be used. Further, in the first embodiment, the planar shape of the emitter layer 34 and the emitter mesa layer 35 (FIGS. 1, 2 and 3) is rectangular, but may be other shapes. For example, the planar shape may be circular, elliptical, hexagonal, octagonal, or the like.

  In the first embodiment, InGaP is used for the emitter layer 34 and GaAs is used for the base layer 33. However, other compound semiconductors may be used. For example, as a combination of the material of the emitter layer 34 and the material of the base layer 33, AlGaAs / GaAs, InP / InGaAs, InGaP / GaAsSb, InGaP / InGaAsN, Si / SiGe, AlGaN / GaN, or the like may be applied. In any combination, the emitter-base interface becomes a heterojunction.

  Although the semiconductor device according to the first embodiment includes four unit transistors 60 as shown in FIG. 1, the number of unit transistors 60 is not limited to four. It is preferable that the semiconductor device include a plurality of unit transistors 60.

[Second embodiment]
Next, a semiconductor device according to a second embodiment will be described with reference to FIG. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted.

  FIG. 6 is a diagram showing a planar layout of components of the semiconductor device according to the second embodiment. In the second embodiment shown in FIG. 6, an example is shown in which three unit transistors 60 are arranged in the x-axis direction. However, the number of unit transistors 60 is not limited to three. The number may be two, five, or more. In the first embodiment, one unit transistor 60 includes two emitter regions 34A (FIGS. 1 and 2). In the second embodiment, one unit transistor 60 includes one emitter region 34A. Each of unit transistors 60 includes an operation region 61. The operation region 61 is defined for each unit transistor 60 by an outer peripheral line of the emitter region 34A. In FIG. 6, the operation area 61 is indicated by dark hatching downward to the right.

  The planar shape of the emitter region 34A is a rectangle long in the y-axis direction, as in the first embodiment. The main part of the base electrode B0 is arranged beside the emitter region 34A in the x-axis direction. In the first embodiment, the planar shape of the base electrode B0 is T-shaped. In the second embodiment, the planar shape of the base electrode B0 is L-shaped.

  In the first embodiment, the geometric center PA of the operation region 61 of the unit transistor 60 is located between the two operation regions 61. In the second embodiment, since one unit transistor 60 includes one operation region 61, the geometric center PA of the operation region 61 is located at the center of gravity of the one operation region 61. That is, the geometric center PA of the operation area 61 is located at the intersection of two diagonal lines of the rectangular operation area 61. One opening 45 is arranged inside the pillar bump 40. In FIG. 6, the opening 45 is thinly hatched to the right. Also in the second embodiment, the geometric center PO of the opening 45 is arranged at a position shifted from the geometric center PA of the operation area 61 in the x-axis direction.

  Also in the second embodiment, since the positional relationship between the operation region 61 and the opening 45 is the same as that of the semiconductor device according to the first embodiment, the same effect as that of the first embodiment can be obtained.

[Third embodiment]
Next, a semiconductor device according to a third embodiment will be described with reference to FIGS. 7 to 11. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted. The semiconductor device according to the third embodiment is a power amplifier module using a plurality of unit transistors 60 (FIG. 1) according to the first embodiment as an amplifier circuit.

  FIG. 7 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the third embodiment. The power amplifier circuit according to the third embodiment amplifies and outputs an input signal in a radio frequency band. The frequency of the input signal is, for example, in the range of several hundred MHz (for example, 600 MHz) or more and several tens of GHz (for example, 60 GHz).

  The power amplifier circuit realized by the semiconductor device according to the third embodiment includes transistors Q1 and Q2, matching circuits MN1, MN2, MN3, filter circuits 71 and 72, bias circuits 75 and 76, and inductors L1 and L2. The transistor Q1 forms a power amplifier circuit of a first stage (drive stage), and the transistor Q2 forms a power amplifier circuit of a subsequent stage (power stage). The transistors Q1 and Q2 have a configuration in which a plurality of unit transistors 60 are connected in parallel, for example, as in the semiconductor device according to the first embodiment or the second embodiment.

  The power supply voltage Vcc is supplied to the collectors of the transistors Q1 and Q2 via the inductors L1 and L2, respectively. The emitters of the transistors Q1 and Q2 are grounded. A bias current or a bias voltage is supplied to the bases of the transistors Q1 and Q2 from the bias circuits 75 and 76, respectively.

  The input signal RFin is supplied to the base of the transistor Q1 via the matching circuit MN1. The transistor Q1 amplifies the input signal RFin and outputs an amplified signal RFout1 from the collector. The amplified signal RFout1 is supplied to the base of the transistor Q2 via the matching circuit MN2. The transistor Q2 further amplifies the amplified signal RFout1, and outputs an amplified signal RFout2 from the collector. The amplified signal RFout2 is supplied to an external circuit via the matching circuit MN3.

  Filter circuits 71 and 72 are connected between the transmission line connecting the collector of the transistor Q2 and the matching circuit MN3 and the ground. The filter circuit 71 is a series resonance circuit in which a capacitor C1a and an inductor L3a are connected in series, and the filter circuit 72 is a series resonance circuit in which a capacitor C1b and an inductor L3b are connected in series. The filter circuits 71 and 72 function as harmonic termination circuits that attenuate the frequency components in the harmonic band included in the amplified signal RFout2. For example, the harmonic termination circuit adjusts the impedance so that a desired harmonic impedance (for example, an impedance with respect to a second harmonic or a third harmonic) becomes short-circuited or open as compared with the fundamental wave impedance. As described above, by setting (impedance adjustment) each harmonic impedance independently of the fundamental wave impedance, the harmonic components are attenuated. The circuit constants of the capacitors C1a and C1b of the filter circuits 71 and 72 and the inductors L3a and L3b are set so that the resonance frequency substantially matches the frequency of the harmonic of the amplified signal RFout2, for example, the frequency of the second or third harmonic. Selected.

  For example, the transistors Q1 and Q2, the matching circuits MN1 and MN2, the bias circuits 75 and 76, the capacitors C1a and C1b of the filter circuits 71 and 72, and a part of the matching circuit MN3 are formed in one semiconductor chip 70. The inductors L1 and L2, the inductors L3a and L3b of the filter circuits 71 and 72, and the remaining portion of the matching circuit MN3 are formed or mounted on a mounting board on which the semiconductor chip 70 is mounted. The inductors L3a and L3b of the filter circuits 71 and 72 are realized by, for example, wiring having an inductance component formed on a mounting board.

  FIG. 8 is an equivalent circuit diagram of the transistor Q2 and its peripheral circuits. The transistor Q2 is composed of a plurality of unit transistors 60 connected in parallel, similarly to the semiconductor device according to the first embodiment or the second embodiment. A capacitor 55 and a ballast resistor 56 are connected to the bases of the plurality of unit transistors 60, respectively. The capacitor 55 and the ballast resistor 56 correspond to the capacitor 55 and the ballast resistor 56 shown in FIG. 1, respectively.

  The high-frequency signal that has passed through the matching circuit MN2 is supplied to each base of the unit transistor 60 via the capacitor 55. A bias current or a bias voltage is supplied from the bias circuit 76 to each base of the unit transistor 60 via the ballast resistor 56. Each collector of unit transistor 60 is DC-connected to power supply voltage Vcc. Each emitter of the unit transistor 60 is grounded.

  FIG. 9 is a diagram showing a layout of each element of the semiconductor chip 70 constituting the semiconductor device according to the third embodiment. The planar shape of the semiconductor chip 70 is a rectangle having sides parallel to the x-axis direction and the y-axis direction. The semiconductor chip 70 is provided with pillar bumps 81, 82, 83 that are long in the x-axis direction.

  The pillar bump 81 is connected to the emitters of the four unit transistors 60 constituting the transistor Q1 (FIG. 7). The transistor Q2 includes two unit transistor groups each including ten unit transistors 60 connected in parallel. The emitters of ten unit transistors 60 included in one unit transistor group are connected to pillar bumps 82, and the emitters of ten unit transistors 60 included in the other unit transistor group are connected to pillar bumps 83.

  The pillar bumps 82 and 83 have the same planar shape and the same dimensions, and are arranged at intervals in the y-axis direction. The pillar bump 81 is shorter than the other two pillar bumps 82 and 83. This is because the number of unit transistors 60 connected to the pillar bumps 81 is smaller than the number of unit transistors 60 connected to each of the pillar bumps 82 and 83.

  On the semiconductor chip 70, capacitors C1a and C1b constituting filter circuits 71 and 72 (FIG. 7) are arranged. On-chip capacitors formed on the semiconductor chip 70 are used for the capacitors C1a and C1b. One capacitor C1a is arranged closer to the unit transistor 60 at the other end (left end) than the unit transistor 60 at one end (right end). The other capacitor C1b is arranged at a position near the unit transistor 60 at an end opposite to the end near the capacitor C1a.

  For this reason, the capacitors C1a and C1b are connected to the pillar bumps 82 and 83, respectively, and are arranged in the vicinity of the unit transistor 60 located at the opposite end of the plurality of unit transistors 60 arranged in the x-axis direction. become. For example, the capacitors C1a and C1b are arranged at positions that are line-symmetric with respect to the center line of the semiconductor chip 70 in the x-axis direction.

  The capacitor C1a is connected to a circular pillar bump 84 via a wiring formed on the semiconductor chip 70. When the semiconductor chip 70 is mounted on the mounting board, the capacitor C1a is electrically connected to the inductor L3a on the mounting board via the pillar bump 84. Similarly, the capacitor C1b is electrically connected to the inductor L3b on the mounting board via the pillar bump 85.

  The other circular pillar bumps 86 are connected to the collectors of the transistors Q1 and Q2 (FIG. 7), the matching circuits MN1 and MN3 (FIG. 7), and the like. The planar shape of the pillar bump 86 connected to the transistor Q2 may be substantially rectangular.

  FIG. 10A is a diagram showing a positional relationship between pillar bumps 82, operating regions 61 of a plurality (ten) of unit transistors 60 connected thereto, and a plurality of openings 45. Ten operation areas 61 are arranged in the x-axis direction, and eight openings 45 are arranged. FIG. 10A shows an example in which each of the unit transistors 60 includes one operation region 61 (FIG. 6), but may have a configuration in which each of the unit transistors 60 includes two operation regions 61 (FIG. 1).

  The displacement amount in the x-axis direction between each geometric center PA of the operation area 61 and the geometric center PO of the opening 45 closest thereto (hereinafter, referred to as “displacement amount of the closest opening”) is represented by Dx. The shift amount Dx of the closest opening is defined for each unit transistor 60. The geometric center PO of any of the openings 45 is arranged at a position shifted from the geometric center PA of the operation area 61 in the x-axis direction. That is, the shift amount Dx of the closest opening is not 0. Further, all the openings 45 are arranged inside the geometric center PA of the operation region 61 of the unit transistor 60 located at both ends, and the openings 45 are not arranged outside.

  The shift amount Dx of the closest openings corresponding to the unit transistors 60 at both ends is larger than the shift amount Dx of the closest openings corresponding to the eight inner unit transistors 60. Further, the shift amount Dx of the closest opening increases from the center to the end of the arrangement of the plurality of unit transistors 60.

  Regarding the other pillar bumps 81 and 83 (FIG. 9), the positional relationship between the pillar bumps 81 and 83, the operating regions 61 of the plurality of unit transistors 60 connected thereto, and the plurality of openings 45 is similar to that of the pillar bump 81. It is. The shape and size of the openings 45 arranged inside the pillar bumps 81, 82, 83 are all the same.

  FIG. 10B is a diagram illustrating a positional relationship between the circular pillar bump 84 and the opening 46 disposed therebelow. The pillar bump 84 is electrically connected to a wiring below the opening via the inside of the opening 46. One opening 46 is provided corresponding to one pillar bump 84. Similar openings are provided for the other circular pillar bumps 85 and 86 (FIG. 9).

  The shape and size of the openings 46 and the like provided corresponding to the circular pillar bumps 84, 85 and 86 (FIG. 9) are provided corresponding to the pillar bumps 81, 82 and 83 (FIG. 9) which are long in the x-axis direction. The shape and size of each of the openings 45 are the same.

  FIG. 11 is a sectional view of a semiconductor device according to the third embodiment. The semiconductor chip 70 is soldered to the mounting board 90 via pillar bumps 81, 82, 83, 86 and the like. As the mounting board 90, for example, a printed board made of alumina, ceramic, epoxy, or the like is used. In addition to the semiconductor chip 70, inductors L3a and L3b (FIG. 9) and other surface-mounted elements 91 are mounted on the mounting substrate 90. The semiconductor chip 70, the inductors L3a and L3b, and the surface-mounted element 91 are sealed with a sealing resin 93. Note that a surface-mount capacitor may be mounted on the mounting board 90 as necessary.

Next, excellent effects obtained by employing the configuration of the semiconductor device according to the third embodiment will be described.
In the third embodiment, as shown in FIG. 10A, the pillar bump 82, the operating region 61 of the plurality of unit transistors 60 connected thereto, and the plurality of openings 45 are different from those of the first embodiment or the second embodiment. Has the same positional relationship as. Therefore, the same effects as those of the semiconductor device according to the first embodiment or the second embodiment can be obtained.

  In the third embodiment, the capacitors C1a and C1b of the filter circuits 71 and 72 are connected near the unit transistors 60 at both ends of the plurality of unit transistors 60 arranged in the x-axis direction. As a result, the characteristics of the filter circuits 71 and 72 as a high-frequency terminal circuit are improved, and as a result, the performance of the power amplifier is improved.

  Further, in the third embodiment, the plurality of openings 45 (FIG. 10A) corresponding to the pillar bumps 81, 82, 83 (FIG. 9) and the openings 46 (FIG. 9) corresponding to the circular pillar bumps 84, 85, 86 (FIG. 9). The shape and size of FIG. Thereby, when the pillar bumps 81 and the like are formed by the plating method, the filling in the openings is made uniform, so that the production yield can be improved.

  In order to make the embedding uniform, it is preferable to arrange a plurality of openings 45 (FIG. 10A) corresponding to the pillar bumps 81, 82, 83 (FIG. 9) at equal intervals. Further, it is preferable to make the intervals of the plurality of openings 45 and the like provided corresponding to each of the pillar bumps 81, 82, 83 (FIG. 9) the same.

  Next, a modification of the third embodiment will be described. In the third embodiment, the power amplifier circuit has a two-stage configuration, but may have a single-stage configuration or a configuration having three or more stages.

[Fourth embodiment]
Next, a semiconductor device according to a fourth embodiment will be described with reference to FIGS. 12, 13, and 14. FIG. Hereinafter, description of the same configuration as the semiconductor device according to the third embodiment (the drawings from FIG. 7 to FIG. 11) will be omitted.

  FIG. 12 is an equivalent circuit diagram of a power amplifier circuit realized by the semiconductor device according to the fourth embodiment. In the third embodiment, two filter circuits 71 and 72 are connected in parallel between the ground and the transmission line from the collector of the transistor Q2 to the matching circuit MN3. In the fourth embodiment, one filter circuit 71 is connected. The filter circuit 71 is formed of a series resonance circuit in which a capacitor C1a and an inductor L3a are connected in series, as in the case of the third embodiment.

  The configuration of the transistor Q1 is the same as the configuration of the transistor Q1 (FIG. 7) of the semiconductor device according to the third embodiment. The transistor Q2 is composed of two unit transistor groups, similarly to the transistor Q2 (FIG. 7) of the semiconductor device according to the third embodiment. In the third embodiment, each of the two unit transistor groups forming the transistor Q2 includes ten unit transistors 60 (FIG. 1, FIG. 10A, etc.). On the other hand, in the fourth embodiment, each of the unit transistor groups includes eight unit transistors 60.

  FIG. 13 is a diagram showing a layout of each element of a semiconductor chip 70 constituting a semiconductor device according to the fourth embodiment. Eight unit transistors 60 are connected to each of the pillar bumps 82 and 83. Since the number of unit transistors 60 connected to each of the pillar bumps 82 and 83 is smaller in the fourth embodiment than in the third embodiment, the pillar bumps 82 and 83 of the semiconductor device according to the fourth embodiment are It is shorter than the pillar bumps 82 and 83 (FIG. 9) of the semiconductor device according to the embodiment. One pillar bump 83 is arranged on an extension of the other pillar bump 82 extending in the x-axis direction.

  In the fourth embodiment, the capacitor C1b (FIG. 9) of the semiconductor device according to the third embodiment is not provided, and only the capacitor C1a is provided. Correspondingly, in the fourth embodiment, the circular pillar bumps 85 (FIG. 9) are not provided. The capacitor C1a is disposed near one end of the pillar bump 82 near the unit transistor 60.

  FIG. 14 is a diagram showing a positional relationship between the pillar bumps 82, the operation regions 61 of the unit transistors 60, and the openings 45. The operating regions 61 of the eight unit transistors 60 are arranged side by side in the x-axis direction inside pillar pillars 82 having a long planar shape in the x-axis direction. Further, the eight openings 45 are also arranged inside the pillar bumps 82 in the x-axis direction.

  The shift amount Dx of the closest opening corresponding to the unit transistor 60 arranged at one end (right end) is the shift amount Dx of the closest opening corresponding to the unit transistor 60 arranged at the other end (left end). Greater than. Further, the shift amount Dx of the closest opening corresponding to the unit transistor 60 increases from one end (left end) to the other end (right end). The capacitor C1a (FIG. 13) of the filter circuit 71 is arranged near the left end of the pillar bump 82.

  Next, excellent effects obtained by employing the configuration of the semiconductor device according to the fourth embodiment will be described.

  When the filter circuit 71 (FIG. 13) operating as a harmonic termination circuit is connected to the collector of the transistor Q2 (FIG. 12), the inventors of the present application generate heat at the plurality of unit transistors 60 during high-frequency operation. It has been found that a phenomenon of non-uniformity occurs. For example, in the example shown in FIG. 14, it has been found that the amount of heat generated tends to gradually decrease from the leftmost unit transistor 60 toward the rightmost unit transistor 60.

  In the fourth embodiment, the heat radiation characteristic of the unit transistor 60 from the operating region 61 is adjusted so as to offset the variation in the amount of heat generated for each unit transistor 60. Specifically, by increasing the shift amount Dx of the closest opening corresponding to the unit transistor 60 from the left end to the right end, the heat radiation characteristic of the unit transistor 60 from the operation region 61 is increased from the left end to the right end. It is gradually decreasing. With such a configuration, the temperatures during operation of the plurality of unit transistors 60 can be equalized.

  Further, the average value of the heat value of the plurality of unit transistors 60 connected to one pillar bump 82 (FIG. 13) and the average value of the heat value of the plurality of unit transistors 60 connected to the other pillar bump 83 (FIG. 13). May not be equal to In the example shown in FIG. 13, the average value of the calorific value of the unit transistor 60 connected to the pillar bump 82 closer to the capacitor C1a of the filter circuit 71 is larger. In such a case, the average value of the shift amount Dx of the closest opening corresponding to the unit transistor 60 having the larger average value of the heat generation amount is determined by the unit of the smaller average value of the heat generation amount. It is preferable that the difference be smaller than the average value of the shift amount Dx of the closest opening corresponding to the transistor 60. Thus, the difference between the operating temperature of the plurality of unit transistors 60 connected to one pillar bump 82 and the operating temperature of the plurality of unit transistors 60 connected to the other pillar bump 83 can be reduced. .

  Depending on how to select the high frequency operation conditions of the semiconductor device, the distribution of the heat generation amount may be different from the above distribution. In such a case, the distribution of the shift amount Dx of the closest opening corresponding to the unit transistor 60 may be set so as to offset the variation in the heat generation amount.

  As in the semiconductor device according to the third embodiment (FIG. 7), even when two filter circuits 71 and 72 operating as a harmonic termination circuit are connected, the amount of heat generated between the plurality of unit transistors 60 is increased. May be uneven. In such a case, the distribution of the shift amount Dx of the nearest opening may be determined so as to offset the variation in the heat generation amount.

  Next, the reason why the heat generation amount varies for each unit transistor 60 will be described. The collectors of the plurality of unit transistors 60 are connected to a common collector wiring. When operating the plurality of unit transistors 60 at a high frequency, the inductance component of the collector wiring cannot be ignored. If the length of the collector wiring from the power supply terminal varies among the plurality of unit transistors 60, the inductance component of the collector wiring also varies. As a result, variations occur in output power and current consumption among the plurality of unit transistors 60.

Next, a semiconductor device according to a modification of the fourth embodiment will be described.
When a harmonic termination circuit is connected to the collector of the transistor Q2 (FIG. 12), the amount of heat generated among the unit transistors 60 tends to vary. If the variation in the amount of generated heat becomes extremely large, the filter circuit 71 (FIG. 12) functioning as a harmonic termination circuit may not be connected.

  In the fourth embodiment, a part of the matching circuit MN3 (FIG. 12) is formed on the semiconductor chip 70, and the remaining part is mounted on the mounting board 90 (FIG. 11). As a modification, all the matching circuits MN3 may be mounted on the mounting board 90.

  It is preferable to determine whether to adopt the configuration of the above-described modification in consideration of the optimum condition of the high-frequency characteristics and the ease of manufacturing.

[Fifth embodiment]
Next, a semiconductor device according to a fifth embodiment and a modification thereof will be described with reference to FIGS. 15A to 16D. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted. The configuration of the unit transistor 60 of the semiconductor device according to the fifth embodiment is the same as the configuration of the unit transistor 60 (FIG. 1) of the semiconductor device according to the first embodiment or the unit transistor 60 (FIG. 6) of the semiconductor device according to the second embodiment. It is. In the fifth embodiment, the positional relationship between the operation region 61 of the unit transistor 60 and the opening 45 immediately below the pillar bump 40 is different from that of the first or second embodiment. FIGS. 15A to 16D show an example in which one unit transistor 60 includes one operation region 61, but two operation regions 61 as in the semiconductor device according to the first embodiment (FIG. 1). May be included.

  FIG. 15A is a diagram showing a positional relationship between the operation region 61 of the unit transistor 60 and the opening 45 of the semiconductor device according to the fifth embodiment. A plurality of openings 45 are arranged inside the outer edge of the operation region 61 of the unit transistor 60 located at both ends in the x-axis direction. The opening 45 is not arranged outside the operation region 61 of the unit transistor 60 at both ends.

  The operation region 61 of the unit transistor 60 at one end (left end) partially overlaps with the opening 45, whereas the operation region 61 of the unit transistor 60 at the other end (right end) has the opening 45. Do not overlap.

  When priority is given to heat radiation from the operation region 61 of the unit transistor 60 located at the left end, the arrangement as shown in FIG. 15A may be adopted.

  In the example shown in FIG. 15B, the number of unit transistors 60 is odd, for example, five, and the number of openings 45 is also odd, for example, three. The geometric center PA of the operating region 61 of the central unit transistor 60 and the geometric center PO of the central opening 45 are arranged at the same position in the x-axis direction. The shift amount Dx of the closest opening corresponding to the unit transistor 60 increases from the central unit transistor 60 toward the unit transistors 60 at both ends. Therefore, the closer the unit transistor 60 is to both ends, the worse the heat radiation characteristic becomes.

  In this example, in a semiconductor device in which the calorific value of the central unit transistor 60 is relatively large and the calorific value tends to decrease toward both ends, the temperature during operation of the unit transistor 60 can be equalized.

  In the example shown in FIG. 15C, two unit transistors 60 and one opening 45 are arranged. Two unit transistors 60 are arranged at symmetric positions with respect to a virtual straight line passing through the geometric center PO of the opening 45 and parallel to the y-axis (second direction). Therefore, the shift amount Dx of the closest opening corresponding to one unit transistor 60 and the shift amount Dx of the closest opening corresponding to the other unit transistor 60 are equal. Therefore, heat radiation characteristics from the two unit transistors 60 can be made substantially equal. Further, the thermal stress generated in the emitter layer 34 and the like of the two unit transistors 60 can be reduced substantially uniformly.

  In the example shown in FIG. 15D, six unit transistors 60 and two openings 45 are arranged. The opening 45 is arranged only inside the operation region 61 of the unit transistor 60 at both ends. The operating regions 61 of the unit transistors 60 at both ends do not overlap with the openings 45. That is, the opening 45 is not disposed directly above the unit transistors 60 at both ends where the temperature tends to be relatively low.

  When the heat generation amount of the unit transistors 60 at both ends is smaller than the heat generation amount of the inner unit transistor 60, by employing this arrangement, the temperature of the junction of the plurality of unit transistors 60 can be equalized.

  In the example shown in FIG. 16A, a plurality of openings 45 are arranged in a matrix in the x-axis direction and the y-axis direction. This arrangement can be considered to be such that each of the plurality of openings 45 of the semiconductor device according to the first embodiment is divided into two in the y-axis direction.

  By dividing the opening 45 in the y-axis direction, the area of each of the openings 45 is reduced. As the flow path cross-sectional area of the heat path in the opening 45 decreases, the thermal resistance increases. Therefore, it becomes easy to control the heat radiation characteristics from the unit transistor 60. Furthermore, since the proportion of the insulating film 52 (FIGS. 2 and 3) where the opening 45 is not formed increases, the effect of relieving thermal stress increases.

  High-frequency signals tend to pass only through the surface of the conductor due to the skin effect. When the opening 45 is divided, the surface area of the conductor in the opening 45 increases, so that the effect of reducing the resistance to a high-frequency signal can be obtained. Further, since the area of each of the openings 45 is reduced, when forming the pillar bumps 40 (FIGS. 2 and 3) by plating or the like, the openings 45 are easily filled with a conductor, and the flatness of the upper surface of the pillar bumps 40 is improved. The effect is obtained.

  In FIG. 16A, two openings 45 are arranged in the y-axis direction, but three or more openings 45 may be arranged. When the number of openings 45 arranged in the y-axis direction is increased, the above-described effect is increased.

  In the example shown in FIG. 16B, the geometric center PO of the opening 45 is shifted in the x-axis direction and also shifted in the y-axis direction with respect to the geometric center PA of the operation region 61 of the unit transistor 60. The geometric center PA of the operation area 61 is also shifted in the y-axis direction with respect to the geometric center PP of the pillar bump 40. By displacing the geometric center PO of the opening 45 also in the y-axis direction with respect to the geometric center of the operation area 61, a structure in which the thermal resistance from the operation area 61 to the pillar bump 40 is easily increased can be obtained. As a result, an effect is obtained that the heat radiation characteristics of the unit transistor 60 can be easily adjusted. Further, the effect of relieving thermal stress is enhanced.

  In the example shown in FIG. 16C, the arrangement of the geometric centers PA of the operation regions 61 of the plurality of unit transistors 60 is in a staggered arrangement. Specifically, among the plurality of unit transistors 60 arranged in the x-axis direction, the geometric center PA of the operation region 61 of the odd-numbered unit transistor 60 is arranged on a straight line parallel to the x-axis direction. Similarly, the geometric center PA of the operation region 61 of the even-numbered unit transistor 60 is also arranged on a straight line parallel to the x-axis direction. The geometric center PA of the operation region 61 of the odd-numbered unit transistor 60 is arranged at a position different from the geometric center PA of the operation region 61 of the even-numbered unit transistor 60 in the y-axis direction.

  The geometric center PO of the opening 45 is shifted in the x-axis direction and the y-axis direction with respect to the geometric center PA of any of the operation areas 61. Therefore, the same effect as the example shown in FIG. 16B can be obtained.

  In the example shown in FIG. 16D, the amplitude of the staggered arrangement of the geometric center PA of the operation area 61 is larger than that in the example shown in FIG. 16C, and a part of the operation area 61 is outside the pillar bump 40 in plan view. Is jumping out. To avoid a significant increase in thermal resistance, a portion of each of the operating regions 61 is arranged to overlap the pillar bumps 40. The opening 45 is divided in the y-axis direction. The geometric center PO of the opening 45 is shifted in the x-axis direction and the y-axis direction with respect to the geometric center PA of any of the operation areas 61. Therefore, the same effect as the example shown in FIG. 16B can be obtained.

[Sixth embodiment]
Next, a semiconductor device according to a sixth embodiment will be described with reference to FIG. Hereinafter, description of the same configuration as the semiconductor device according to the first embodiment (FIGS. 1, 2, and 3) will be omitted.

  FIG. 17 is a sectional view of the semiconductor device according to the sixth embodiment. In the first embodiment, the pillar bumps 40 (FIGS. 2 and 3) are formed on the upper surface of the semiconductor chip on which the unit transistors 60 are formed. The semiconductor device according to the sixth embodiment is realized by a wafer level package including a semiconductor chip.

  On a package substrate 100, a semiconductor chip 110 is adhered and fixed. The semiconductor chip 110 has, for example, an element structure from the substrate 30 of the semiconductor device according to the first embodiment (FIGS. 1, 2 and 3) to the second-layer emitter wiring E2, and the second-layer emitter wiring E2 (first wiring). And an insulating film 52 covering the wiring. The semiconductor chip 110 includes a plurality of unit transistors 60. On the package substrate 100, in addition to the semiconductor chip 110, other surface-mounted devices are adhered and fixed.

  A semiconductor chip 110 and a surface mount type device are embedded in an insulating film 105 made of resin. The upper surface of the semiconductor chip 110 is located at the same height as the upper surface of the insulating film 105. A plurality of first-layer rewirings 101 (second wirings) are arranged on the semiconductor chip 110 and the insulating film 105. Part of the first-layer rewiring 101 is electrically connected to the lower emitter wiring E2 through an opening 103 formed in the insulating film 52. A plurality of second-layer rewirings 102 are arranged on the first-layer rewiring 101. The second-layer rewiring 102 is electrically connected to a terminal 106 such as a bump disposed thereon. For the first layer rewiring 101 and the second layer rewiring 102, for example, Cu formed by plating is used.

  The planar positional relationship between the first-layer rewiring 101, the opening 103, and the operation region 61 of the unit transistor 60 depends on the pillar bump 40, the opening 45, and the operation region 61 of the unit transistor 60 of the semiconductor device according to the first embodiment. This is equivalent to a planar positional relationship.

  Next, excellent effects obtained by employing the configuration of the semiconductor device according to the sixth embodiment will be described.

  In the sixth embodiment, the first-layer rewiring 101 has the same function as the pillar bumps 40 (FIGS. 1, 2, and 3) of the first embodiment. That is, the first-layer rewiring 101 functions as a heat path for radiating heat generated in the operation region 61 of the unit transistor 60 to the outside. The opening 103 connecting the first-layer rewiring 101 and the second-layer emitter wiring E2 has the same function as the opening 45 (FIGS. 1, 2, and 3) of the semiconductor device according to the first embodiment. Therefore, the same effect as that of the first embodiment can be obtained by setting the above-described positional relationship between the first-layer rewiring 101, the opening 103, and the operation region 61 of the unit transistor 60.

  Note that the first-layer rewiring 101, the opening 103, and the operation region 61 of the unit transistor 60 may have the same positional relationship as that of any of the second to fifth embodiments. . In this case, the same effect as any one of the second to fifth embodiments can be obtained.

[Seventh embodiment]
Next, a semiconductor device according to a seventh embodiment will be described with reference to FIG. Hereinafter, description of the same configuration as the semiconductor device according to the sixth embodiment (FIG. 17) will be omitted.

  FIG. 18 is a sectional view of the semiconductor device according to the seventh embodiment. In the sixth embodiment, as shown in FIG. 17, the semiconductor chip 110 was bonded to the package substrate 100, and the rewirings 101 and 102 were formed on the package substrate 100. In the seventh embodiment, a first-layer rewiring 101 and a second-layer rewiring 102 are formed on the uppermost insulating film 52 of a semiconductor chip 110. Terminals 106 for external connection are arranged on the second-layer rewiring 102. The first layer rewiring 101 is electrically connected to the second layer emitter wiring E2 via the inside of the opening 103 provided in the insulating film 52.

  Also in the seventh embodiment, the positional relationship between the rewiring 101 of the first layer, the opening 103, and the operation region 61 of the unit transistor 60 is made the same as the positional relationship in the semiconductor device according to the sixth embodiment. The same effects as in the sixth embodiment can be obtained.

[Eighth embodiment]
Next, a semiconductor device according to an eighth embodiment will be described with reference to FIGS. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted. The semiconductor device according to the eighth embodiment includes an HBT in which SiGe is used for a base layer.

  FIG. 19 is a sectional view of a semiconductor device according to the eighth embodiment. In the first embodiment, GaAs is used for the base layer 33, and InGaP is used for the emitter layer. On the other hand, in the eighth embodiment, SiGe is used for the base layer 33.

  A sub-collector layer 131 made of high-concentration n-type Si is arranged on a surface layer of a substrate 130 made of p-type Si, and a collector layer 132 made of n-type Si is arranged thereon. On the collector layer 132, a base layer 133 made of epitaxially grown SiGe is arranged.

  A plurality of active regions are defined by a shallow trench isolation structure extending from the upper surface of the base layer 133 to a position slightly deeper than the upper surface of the sub-collector layer 131, and the unit transistor 60 is arranged in each of the active regions. A plurality of unit transistors 60 are electrically isolated from surrounding circuits by a shallow trench isolation structure reaching the bottom surface of subcollector layer 131. FIG. 19 shows a cross section of two unit transistors 60.

  A p-type external base layer 134 is formed on the surface of a part of the active region. The external base layer 134 surrounds the base layer 133 made of p-type SiGe in plan view. Two base layers 133 are arranged in one active region.

  An insulating film 140 made of silicon oxide or the like is arranged on each of the base layers 133, and an emitter layer 135 made of n-type polysilicon or the like is arranged thereon. Emitter layer 135 contacts base layer 133 through an opening provided in insulating film 140. An operating current flows through the heterojunction interface between the emitter layer 135 and the base layer 133 in the thickness direction. In plan view, the outer peripheral line of the bonding interface defines the operation area 61. Each of unit transistors 60 includes two operation regions 61.

  A base electrode B0 is arranged on the surface of the external base layer 134. The base electrode B0 is formed of, for example, Ti silicide, Ni silicide, or the like. The base electrode B0 is arranged to lower the base resistance. If the base resistance becomes sufficiently low without disposing the base electrode B0, the base electrode B0 need not be disposed.

  An insulating film 141 made of silicon oxide or the like is arranged so as to cover the emitter layer 135, the external base layer 134, and the base electrode B0. On the insulating film 141, a first-layer emitter wiring E1 and a collector wiring C1 made of Al or the like are arranged. The first-layer emitter wiring E1 is electrically connected to the emitter layer 135 through an opening provided in the insulating film 141. The first-layer collector wiring C1 passes through an opening provided in the insulating film 141, and is electrically connected to the sub-collector layer 131 via a high-concentration n-type region 136 provided in a surface mounting portion of the substrate. . For the purpose of lowering the collector resistance, a collector electrode made of metal silicide may be arranged at the interface between the first-layer collector wiring C1 and the n-type region 136.

  The base electrode B0 is connected to the first-layer base wiring at a location not shown in the cross section of FIG.

  A second-layer insulating film 142 made of silicon oxide or silicon nitride is arranged on the insulating film 141 so as to cover the first-layer emitter wiring E1 and the collector wiring C1. A second-layer emitter wiring E2 is disposed on the insulating film 142. The second-layer emitter wiring E2 is electrically connected to the first-layer emitter wiring E1 through an opening provided in the insulating film 142, and mutually connects the emitter layers 135 of the plurality of unit transistors 60. .

  The third-layer insulating film 143, the third-layer wiring 150, the fourth-layer insulating film 144, the fourth-layer wiring 151, and the fifth-layer insulating film 145 are formed on the second-layer emitter wiring E2. They are arranged in order. The third-layer wiring 150 is electrically connected to the second-layer emitter wiring E2 through an opening 155 provided in the third-layer insulating film 143. The fourth-layer wiring 151 is electrically connected to the third-layer wiring 150 through an opening 156 provided in the fourth-layer insulating film 144. The bump 152 is arranged on the fifth insulating film 145. The bump 152 is electrically connected to the wiring 151 of the fourth layer through an opening 157 provided in the insulating film 145 of the fifth layer. The second-layer emitter wiring E2, the third-layer wiring 150, and the fourth-layer wiring 151 are formed of, for example, Al or Cu. The third insulating film 143, the fourth insulating film 144, and the fifth insulating film 145 are formed of, for example, silicon oxide or silicon nitride.

  The upper surfaces of the insulating films from the second insulating film 142 to the fifth insulating film 145 are flattened. Note that the upper surface of the first insulating film 141 may be planarized as necessary.

  FIG. 20 is a diagram showing a planar layout of components of the semiconductor device according to the eighth embodiment. A cross-sectional view taken along dashed-dotted line 19-19 in FIG. 20 corresponds to FIG. Assuming that the x-axis direction is a row direction and the y-axis direction is a column direction, eight unit transistors 60 are arranged in a matrix of 2 rows and 4 columns. Each of unit transistors 60 includes two operation regions 61. Each of the operation regions 61 has a planar shape that is long in the y-axis direction, and two operation regions 61 are arranged side by side in the x-axis direction in one unit transistor 60.

  A second-layer emitter wiring E2 is arranged for each row of the eight unit transistors 60 arranged in a matrix. The emitter wiring E2 of the second layer includes the inside of the operation region 61 of the unit transistor 60 in the corresponding row in a plan view.

  The third-layer wiring 150, the fourth-layer wiring 151, and the bump 152 are arranged so as to overlap with all of the operation regions 61 of the eight unit transistors 60. Four openings 155 provided in the third insulating film 143 (FIG. 19) are arranged in a matrix of 2 rows and 2 columns. One row of the opening 155 corresponds to one row of the unit transistor 60.

  With respect to a virtual straight line passing through the center of the bump 152 and parallel to the x-axis, the operation region 61 of the unit transistor 60 in the first row and the operation region 61 of the unit transistor 60 in the second row are arranged at line-symmetric positions. . Similarly, with respect to this virtual straight line, the openings 155 in the first row and the openings 155 in the second row are arranged at line-symmetric positions.

  The geometric center PO of the opening 155 is arranged at a position shifted from the geometric center PA of the operation region 61 of one unit transistor 60 in the x-axis direction. Focusing on each row of the unit transistors 60, as in the case of the first embodiment (FIG. 1), the shift amount Dx of the closest opening to the unit transistors 60 at both ends is the shift amount of the closest opening to the inner unit transistor 60. Greater than Dx.

  The opening 156 provided in the fourth insulating film 144 (FIG. 19) and the opening 157 provided in the fifth insulating film 145 (FIG. 19) have the same shape and the same dimensions. Almost overlap in plan view. The openings 156 and 157 are arranged inside the operation regions 61 at both ends in the x-axis direction. In the y-axis direction, the openings 156 and 157 partially overlap with the operation region 61 of the unit transistor 60 in the first row, and partially overlap with the operation region 61 of the unit transistor 60 in the second row.

  FIG. 21 is a diagram showing a planar layout of four unit transistors 60 arranged in one row of the semiconductor device according to the eighth embodiment. Each of the unit transistors 60 includes two operation regions 61 arranged at an interval in the x-axis direction. The base electrode B0 has a comb-shaped planar shape having three comb-tooth portions. The three comb teeth portions of the base electrode B0 are arranged between the two operation regions 61 and outside. The operating region 61 and the base electrode B0 are arranged inside the outer peripheral line 137 of the region where the base layer 133 (FIG. 19) and the external base layer 134 (FIG. 19) are combined.

  The n-type regions 136 are arranged between the unit transistors 60 arranged in the x-axis direction and outside the unit transistors 60 at both ends. The second-layer emitter wiring E2 is arranged so as to include the unit transistor 60 and the n-type region 136 inside in plan view.

  Next, excellent effects obtained by employing the configuration of the semiconductor device according to the eighth embodiment will be described.

  The opening 155 connecting the second-layer emitter wiring E2 and the third-layer wiring 150 functions as a heat path for transmitting heat generated in the operation region 61 to the outside. The opening 155 corresponds to the opening 45 of the semiconductor device (FIG. 1) according to the first embodiment from the viewpoint of radiating heat generated in the operation region 61.

  In the eighth embodiment, since the geometric center PO of the opening 155 is shifted in the x-axis direction with respect to the geometric center PA of the operation area 61, the same effect as in the first embodiment can be obtained.

[Ninth embodiment]
Next, a semiconductor device according to a ninth embodiment will be described with reference to FIGS. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted. In the first embodiment, the unit transistor 60 (FIGS. 1, 2, and 3) is a heterojunction bipolar transistor. In the ninth embodiment, the unit transistor 60 is a MOS field effect transistor (MOSFET).

  FIG. 22 is a sectional view of the semiconductor device according to the ninth embodiment. An active region 171 surrounded by a shallow trench isolation structure is formed in a surface layer portion of a substrate 170 made of silicon. In the active region 171, a plurality of unit transistors 60 are arranged side by side in the x-axis direction. In the ninth embodiment of FIG. 22, five unit transistors 60 are arranged. Each of the unit transistors 60 is a MOSFET, and includes a source region 175 and a drain region 176 spaced apart in the x-axis direction. A gate electrode G0 is arranged on a channel region between source region 175 and drain region 176. A source electrode S0 and a drain electrode D0 are electrically connected to the source region 175 and the drain region 176, respectively. The source region 175 and the drain region 176 other than both ends are shared by the unit transistors 60 on both sides. In the active region 171, an in-plane operation current flows in the operation region 61 directly below the gate electrode G <b> 0.

  A first-layer insulating film 190 is arranged so as to cover the unit transistor 60. On the first insulating film 190, a first layer source wiring S1 and a drain wiring D1 made of Al or the like are arranged. The source wiring S1 and the drain wiring D1 respectively pass through openings provided in the first insulating film 190, are electrically connected to the source region 175 via the source electrode S0, and are connected to the drain region 176 via the drain electrode D0. Is electrically connected to

  A second-layer insulating film 191 is arranged so as to cover the first-layer source wiring S1 and the drain wiring D1. The second-layer source wiring S2 is disposed on the second-layer insulating film 191. The source wiring S2 is electrically connected to a plurality of first-layer source wirings S1 through openings provided in the second-layer insulating film 191.

  A third-layer insulating film 192 is arranged so as to cover the second-layer source wiring S2. A third-layer wiring 180 is arranged on the third-layer insulating film 192. The third-layer wiring 180 is electrically connected to the second-layer source wiring S2 through a plurality of openings 185 provided in the third-layer insulating film 192. A fourth-layer insulating film 193 is arranged so as to cover the third-layer wiring 180.

  The source wiring S2 of the second layer and the wiring 180 of the third layer are formed of, for example, Al or Cu. Each of the insulating films from the first insulating film 190 to the fourth insulating film 193 is formed of, for example, silicon oxide or silicon nitride.

  FIG. 23 is a diagram showing a planar layout of components of the semiconductor device according to the ninth embodiment. Each of the five gate electrodes G0 arranged in the x-axis direction crosses a rectangular active region 171 that is long in the x-axis direction. Each of gate electrodes G0 has a planar shape that is long in the y-axis direction, and extends from one edge of active region 171 that is long in the x-axis direction to the other edge. The region where the active region 171 and the gate electrode G0 overlap (the region hatched in FIG. 23) functions as the operation region 61.

  The third-layer wiring 180 is arranged so as to overlap with all the operation regions 61. Three openings 185 are arranged in the x-axis direction inside the third-layer wiring 180 in plan view. The geometric center PO of the opening 185 is arranged at a position different from the geometric center PA of the operation area 61 in the x-axis direction. In the x-axis direction, the shift amount Dx of the closest opening increases from the central operation area 61 to the operation areas 61 at both ends.

  By setting the positional relationship between the operation region 61 and the opening 185 as described above, the same effect as that of the first embodiment can be obtained. That is, the thermal stress generated in the semiconductor portion of the unit transistor 60 is reduced, and the temperatures during operation of the plurality of unit transistors 60 can be equalized. As a result, an effect is obtained that the high-frequency characteristics are improved as a whole of the transistor circuit in which the unit transistors 60 are connected in parallel.

  In the ninth embodiment, a silicon substrate is used as the substrate 170, but a substrate made of a compound semiconductor may be used. For example, a GaAs substrate may be used as the substrate 170, and the unit transistor 60 may be configured by a high electron mobility transistor (HEMT) having a channel made of InGaAs. Alternatively, the unit transistor 60 may be constituted by a HEMT on a GaN substrate.

[Tenth embodiment]
Next, a semiconductor device according to a tenth embodiment will be described with reference to FIGS. 24A, 24B, and 25A. Hereinafter, description of the configuration common to the semiconductor device according to the first embodiment will be omitted. In each of the first to ninth embodiments, even when a plurality of operation regions 61 are arranged in one unit transistor 60, one geometric center PA of the operation region 61 is provided for each unit transistor 60. (FIG. 1) was defined. In the tenth embodiment, one effective operation area including a plurality of operation areas 61 is defined for each unit transistor 60.

  FIG. 24A is a diagram illustrating a positional relationship between the operation area 61 and the effective operation area 65. In FIG. 24A, the effective operation area 65 is hatched. Each of the unit transistors 60 is provided with a plurality of, for example, two operation regions 61. The smallest rectangle among the rectangles including the plurality of operation regions 61 of one unit transistor 60 is defined as the effective operation region 65. Actually, since the plurality of operation regions 61 included in one unit transistor 60 are arranged close to each other with the base electrode B0 interposed therebetween, one effective operation region 65 can be considered as one heating region.

  FIG. 24B is a diagram showing the arrangement of the effective operation region 65 of the semiconductor device according to the tenth embodiment, and a graph showing the temperature distribution of the effective operation region 65 when the heat radiation characteristics from the effective operation region 65 are constant. It is. A plurality of, for example, five effective operation areas 65 are arranged side by side in the x-axis direction. The planar shape of each of the plurality of effective operation regions 65 is a rectangle that is long in the y-axis direction, and the shapes and sizes of the plurality of effective operation regions 65 are the same.

  During the operation of the semiconductor device, the temperature of the effective operating region 65 located at the center in the x-axis direction becomes the highest, and the temperature tends to decrease toward both ends. For example, when the heat radiation characteristics from the effective operation area 65 are uniform, the effective operation area 65 at both ends has only one heat source on one side, so that the temperature rise is relatively suppressed. As a result, the temperature distribution shown in FIG. 24B occurs.

  FIG. 25A is a diagram showing a positional relationship between the effective operation area 65, the opening 45, and the pillar bump 40 of the semiconductor device according to the tenth embodiment. The influence range 62 is defined as follows corresponding to each of the effective operation areas 65. First, when attention is paid to each of the effective operation areas 65, it passes through the midpoint of a line segment having both ends at the geometric center of the effective operation area 65 of interest and the geometric center of the adjacent effective operation area 65, and the y-axis An area partitioned by a virtual straight line parallel to the direction is defined as an influence range 62 of the effective operation area 65 of interest. For the outermost effective operation area 65, for example, the influence range 62 is defined such that the effective operation area 65 is located at the center of the influence area 62 in the x-axis direction. The influence range 62 may be defined up to the end of the pillar bump 40 in the x-axis direction. With this definition, the effective operation area 65 and the influence range 62 correspond one-to-one.

  The influence range 62 is a band-shaped region extending in the y-axis direction. When the effective operation regions 65 are arranged at a constant pitch in the x-axis direction, the influence range 62 is formed by centering the corresponding effective operation region 65 in the x-axis direction. Included. The width (dimension in the x-axis direction) of the influence range 62 is equal to the pitch of the effective operation regions 65 arranged in the x-axis direction. For each of the influence ranges 62, a region where the influence range 62 and the opening 45 overlap is referred to as an overlap region 63. In FIG. 25A, the overlapping area 63 is hatched. The distance from any point in the influence range 62 to the geometric center of the effective operation area 65 in the influence range 62 is shorter than the distance from any point in the influence area 62 to the geometric center of any other effective operation area 65. The influence range 62 can be said to be a range relatively easily affected by the thermal from the effective operation region 65 located inside the plurality of effective operation regions 65.

  The thermal effect from the effective operation area 65 decreases as the distance from the effective operation area 65 increases in the y-axis direction. Therefore, the size of each of the influence ranges 62 in the y-axis direction is, for example, three times the dimension of the effective operation region 65 in the y-axis direction, and the effective operation region 65 is arranged at the center in the y-axis direction. Good.

  In the tenth embodiment, the area of the overlap region 63 differs depending on the influence range 62 of the effective operation region 65. Here, “different” does not mean that there is no overlapping region 63 having the same area, but means that there is an overlapping region 63 having a different area. That is, the overlap region 63 having the same area may exist.

  One opening 45 is arranged corresponding to each of the plurality of effective operation areas 65. Each of the openings 45 is arranged at the center of the corresponding effective operation area 65 in the y-axis direction. The dimension in the y-axis direction of the opening 45 corresponding to the effective operation area 65 located at the center with respect to the x-axis direction is the largest, and the size of the opening 45 corresponding to the effective operation area 65 in the y-axis direction is increased toward both ends in the x-axis direction. The dimensions are getting smaller. For example, the entire effective operating region 65 in the center in the x-axis direction overlaps with the opening 45. In the other effective operation area 65, only a part of the effective operation area 65 overlaps the opening 45. That is, a part of the effective operation area 65 extends to the outside of the opening 45. The area of the region where the effective operation region 65 and the opening 45 overlap each other decreases from the effective operation region 65 located at the center in the x-axis direction toward both ends.

  Next, excellent effects obtained by adopting the configuration of the semiconductor device according to the tenth embodiment will be described.

  The heat generated in the effective operation area 65 is transmitted to the outside through the pillar bumps 40 in the openings 45 located in the vicinity thereof. Therefore, the larger the area of the opening 45 in the affected area 62 is, the higher the heat radiation characteristic tends to be. In the tenth embodiment, since the area of the opening 45 within the influence range 62 of the central effective operation region 65 is relatively large, the heat radiation characteristics of the region where the temperature tends to be high are relatively good. As a result, the temperatures of the plurality of effective operation regions 65 during the operation of the semiconductor device can be equalized.

  Next, a semiconductor device according to a modification of the tenth embodiment will be described with reference to FIGS. 25B to 27. FIGS. 25B to 27 are diagrams showing the positional relationship among the effective operation region 65, the opening 45, and the pillar bump 40 of the semiconductor device according to the modification of the tenth embodiment. 25B to 27 are the same as the tenth embodiment (FIG. 25A) in that the area of the overlap region 63 differs depending on the influence range 62 of the effective operation region 65. Therefore, in the modified examples shown in FIGS. 25B to 27, the same effects as in the tenth embodiment can be obtained.

  In the modification shown in FIG. 25B, the sizes of the plurality of openings 45 are made equal, and the number of the openings 45 overlapping the effective operation area 65 is made different depending on the effective operation area 65. For example, three openings 45 are overlapped in the effective operation region 65 located at the center in the x-axis direction, and two openings 45 are respectively overlapped in the effective operation regions 65 on both sides thereof. Each of the openings 45 overlaps one opening 45.

  In the modification shown in FIG. 25C, one opening 45 is arranged over a plurality of effective operation areas 65. The boundary between adjacent influence ranges 62 passes through one opening 45. The dimension of the opening 45 in the y-axis direction decreases from the center in the x-axis direction to both ends. As a result, the area of the overlap region 63 decreases from the influence range 62 of the central effective operation region 65 to the influence range 62 of the effective operation regions 65 at both ends. Further, the dimension in the y-axis direction of the area where the effective operation area 65 and the opening 45 overlap is different depending on the effective operation area 65, and decreases from the center in the x-axis direction to both ends.

  In the modification shown in FIG. 26A, the size and the position in the y-axis direction of the opening 45 are the same as those in the tenth embodiment (FIG. 25A), but with respect to the x-axis direction between the effective operation area 65 and the opening 45. The relative positional relationship differs depending on the effective operation area 65. For example, the geometric center of the opening 45 is shifted from the geometric center of the effective operation area 65 in the x-axis direction. The shift amount corresponding to each of the effective operation areas 65 increases from the center in the x-axis direction to both ends.

  In the modification shown in FIG. 26B, one opening 45 is arranged for each of the effective operation areas 65, and the plurality of openings 45 have the same dimension in the y-axis direction and different dimensions in the x-axis direction. For example, each dimension of the opening 45 in the x-axis direction increases from the center in the x-axis direction to both ends.

  In the modification shown in FIG. 26C, a part of the plurality of openings 45 overlaps with the plurality of effective operation areas 65. For example, the openings 45 at both ends in the x-axis direction overlap with one effective operation region 65 at each end, and the remaining one opening 45 overlaps with three inner effective operation regions 65.

  In the modification shown in FIG. 27, none of the openings 45 overlaps with the effective operation area 65, and the openings 45 are arranged near the effective operation area 65. As an example, the opening 45 is arranged at a position shifted from the effective operation area 65 in the x-axis direction. Further, the number of openings 45 arranged near each of the effective operation areas 65 differs depending on the effective operation area 65.

  In the example shown in FIG. 27, two openings 45 are arranged near the central effective operation area 65, and one opening is arranged near the second effective operation area 65 from the center to the end. 45 are arranged. The openings 45 are not arranged near the effective operation areas 65 at both ends. Focusing on the influence range 62 of the effective operation region 65, two openings 45 are arranged in the influence range 62 of the central effective operation region 65, and one opening is disposed in each of the influence ranges 62 on both sides thereof. 45 are arranged. The openings 45 are not arranged in the influence ranges 62 at both ends.

[Eleventh embodiment]
Next, a semiconductor device according to an eleventh embodiment will be described with reference to FIGS. 28 and 29A. Hereinafter, description of the configuration common to the semiconductor device according to the tenth embodiment (FIGS. 24A, 24B, and 25A) will be omitted.

  FIG. 28 is a diagram showing the arrangement of the effective operation region 65 of the semiconductor device according to the eleventh embodiment, and a graph showing the temperature distribution in the effective operation region 65 when the heat radiation characteristics from the effective operation region 65 are constant. It is. In the tenth embodiment, the temperature in the central effective operating region 65 in the x-axis direction has the highest temperature, and the temperature tends to decrease toward both ends. In the eleventh embodiment, the temperature of the effective operating area 65 at one end (left end in FIG. 28) in the x-axis direction has the highest temperature, and the temperature tends to decrease toward the other end (right end in FIG. 28). . Such a temperature distribution may occur depending on the circuit arrangement in the semiconductor chip 70 (FIG. 9).

  FIG. 29A is a diagram showing a positional relationship between the effective operation area 65, the opening 45, and the pillar bump 40 of the semiconductor device according to the eleventh embodiment. In the tenth embodiment (FIG. 25A), the area of the overlap region 63 corresponding to the central effective operation region 65 was the largest. In the eleventh embodiment, the area of the overlap region 63 corresponding to the effective operation region 65 at the left end is the largest, and the area of the overlap region 63 corresponding to the effective operation region 65 decreases from the left end to the right end. As described above, the area of the overlap region 63 corresponding to the effective operation region 65 monotonously changes from one end in the x-axis direction to the other end.

  Next, excellent effects obtained by adopting the configuration of the semiconductor device according to the eleventh embodiment will be described.

  In the eleventh embodiment, the area of the overlapping region 63 corresponding to the effective operating region 65 where the temperature tends to be relatively high is relatively large. As a result, the temperatures of the plurality of effective operation regions 65 during the operation of the semiconductor device can be equalized.

  Next, a semiconductor device according to a modification of the eleventh embodiment will be described with reference to FIGS. 29B to 31. FIGS. 29B to 31 are views showing the positional relationship among the effective operation area 65, the opening 45, and the pillar bump 40 of the semiconductor device according to the modification of the eleventh embodiment. The modified examples of FIGS. 29B to 31 are similar to the modified examples of the tenth embodiment of FIGS. 25B to 27, respectively.

  In the modification shown in FIG. 29B, the number of the openings 45 within the influence range 62 monotonically changes from one end to the other end in the x-axis direction. In the modification shown in FIG. 29C, one opening 45 is arranged from the effective operation area 65 at one end in the x-axis direction to the effective operation area 65 at the other end, and from one end in the x-axis direction to the other end. The area of the overlap region 63 within the influence range 62 changes monotonically.

  In the modified example shown in FIG. 30A, the opening 45 is arranged to be shifted from the effective operation area 65 in the x-axis direction. The shift amount of the opening 45 monotonously changes from one end to the other end in the x-axis direction. In the modification shown in FIG. 30B, the dimension of the opening 45 corresponding to the effective operation area 65 in the x-axis direction monotonically changes from one end in the x-axis direction to the other end. In the modification shown in FIG. 30C, some of the plurality of openings 45 overlap the plurality of effective operation areas 65. The number of the effective operation areas 65 overlapping the opening 45 monotonically changes from one end in the x-axis direction to the other end.

  In the modification shown in FIG. 31, none of the openings 45 overlaps with the effective operation area 65, and the openings 45 are arranged near the effective operation area 65. The number of the openings 45 arranged near each of the effective operation regions 65 monotonically changes from one end in the x-axis direction to the other end.

  In each modification of the eleventh embodiment, the area of the overlap region 63 corresponding to the effective operation region 65 at one end is the largest, and the area of the overlap region 63 corresponding to the effective operation region 65 is increased toward the other end in the x-axis direction. Is getting smaller. Thereby, the same effects as in the eleventh embodiment can be obtained in the modified examples shown in FIGS. 29B to 31.

[Twelfth embodiment]
Next, a semiconductor device according to a twelfth embodiment will be described with reference to FIG. 32A. Hereinafter, the description of the configuration common to the semiconductor device (FIGS. 24A, 24B, and 25A) according to the tenth embodiment will be omitted.

  FIG. 32A is a diagram showing a positional relationship between the effective operation area 65, the opening 45, and the pillar bump 40 of the semiconductor device according to the twelfth embodiment. In the tenth embodiment, a plurality of effective operation areas 65 are arranged at a constant pitch in the x-axis direction. In the twelfth embodiment, the arrangement pitch of the plurality of effective operation areas 65 is not uniform, and the openings 45 are arranged at an equal pitch. The areas of the plurality of openings 45 are equal. Further, each of the openings 45 is arranged inside the influence range 62 of the corresponding effective operation area 65. For this reason, the areas of the plurality of overlapping regions 63 where the influence range 62 and the opening 45 overlap each other also become equal.

  It can be considered that the geometric center PA of the effective operation area 65 corresponds to the geometric center PA (FIG. 1) of the operation area 61 according to the first embodiment. As in the case of the third embodiment shown in FIG. 10A, the shift amount in the x-axis direction between each geometric center PA of the effective operation area 65 and the corresponding geometric center PO of the opening 45 (shift of the nearest opening). Amount) is represented by Dx. The shift amount Dx of the closest opening increases from the center to the end of the arrangement of the plurality of unit transistors 60. Therefore, similarly to the case of the tenth embodiment, the temperature of the unit transistor 60 during operation can be equalized.

Next, a semiconductor device according to a modification of the twelfth embodiment will be described with reference to FIG. 32B.
FIG. 32A is a diagram illustrating a positional relationship among an effective operation region 65, an opening 45, and a pillar bump 40 of a semiconductor device according to a modification of the twelfth embodiment. Also in this modification, a plurality of openings 45 are arranged at equal pitches in the x-axis direction. The effective operation areas 65 are arranged at an equal pitch or an irregular pitch.

  In the present modified example, the shift amount Dx of the closest opening increases from one end of the arrangement of the plurality of unit transistors 60 toward the other end. In this modification, as in the case of the eleventh embodiment shown in FIGS. 28 and 29A, the temperature of the unit transistor 60 during operation can be leveled.

  Each of the above-described embodiments is an exemplification, and it goes without saying that the configurations shown in the different embodiments can be partially replaced or combined. The same operation and effect of the same configuration of the plurality of embodiments will not be sequentially described for each embodiment. Furthermore, the invention is not limited to the embodiments described above. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

30 Substrate 31 Sub-collector layer 31A Isolation region 32 Collector layer 33 Base layer 34 Emitter layer 34A Emitter region 34B Ledge layer 35 Emitter mesa layer 40 Pillar bump (metal member)
41 Under bump metal layer 42 Metal post 43 Solder layer 45, 46 Opening 50, 51, 52 Insulating film 55 Capacitor 56 Ballast resistor 60 Unit transistor 61 Operating area 62 Influence area 63 Overlap area 65 where the influence area overlaps with the opening 65 Effective operating area Reference Signs List 70 semiconductor chip 71, 72 filter circuit 75, 76 bias circuit 81, 82, 83 pillar bump 84, 85, 86 circular pillar bump 90 mounting substrate 91 surface mounting element 93 sealing resin 100 package substrate 101 first layer rewiring 102 Second layer rewiring 103 Opening 105 Insulating film 106 Terminal 110 Semiconductor chip 130 Substrate 131 Subcollector layer 132 Collector layer 133 Base layer 134 External base layer 135 Emitter layer 136 N-type region 137 Base layer and external base layer are combined Territory Insulating film 150 Third layer wiring 151 Fourth layer wiring 152 Bump 155, 156, 157 Opening 170 Substrate 171 Active region 175 Source region 176 Drain region 180 Wiring 185 Openings 190, 191, 192, 193 Insulating film B0 Base electrode B1 First-layer base wiring C0 Collector electrode C1 First-layer collector wiring C1a, C1b Capacitor D0 Drain electrode D1 First-layer drain wiring E0 Emitter electrode E1 One-layer Second-layer emitter wiring E2 Second-layer emitter wiring G0 Gate electrodes L1, L2, L3a, L3b Inductor M2 Second-layer wiring MN1, MN2, MN3 Matching circuit Q1, Q2 Transistor S0 Source electrode S1 First-layer source wiring S2 Second layer source wiring

Regarding the other pillar bumps 81 and 83 (FIG. 9), the positional relationship between the pillar bumps 81 and 83, the operation regions 61 of the plurality of unit transistors 60 connected thereto, and the plurality of openings 45 is the same as that of the pillar bump 82. It is. The shape and size of the openings 45 arranged inside the pillar bumps 81, 82, 83 are all the same.

In the third embodiment, the capacitors C1a and C1b of the filter circuits 71 and 72 are connected near the unit transistors 60 at both ends of the plurality of unit transistors 60 arranged in the x-axis direction. As a result, the characteristics of the filter circuits 71 and 72 as a harmonic termination circuit are improved, and as a result, the performance of the power amplifier is improved.

In the modification shown in FIG. 26B, one opening 45 is arranged for each of the effective operation areas 65, and the plurality of openings 45 have the same dimension in the y-axis direction and different dimensions in the x-axis direction. For example, the size of each of the openings 45 in the x-axis direction decreases from the center in the x-axis direction to both ends.

Next, a semiconductor device according to a modification of the twelfth embodiment will be described with reference to FIG. 32B.
Figure 32 B is the effective operating region 65 of the semiconductor device according to a modification of the twelfth embodiment, and shows the positional relationship of the opening 45, and pillar bump 40. Also in this modification, a plurality of openings 45 are arranged at equal pitches in the x-axis direction. The effective operation areas 65 are arranged at an equal pitch or an irregular pitch.

Claims (16)

A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A first wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the first wiring, wherein the insulating film is provided with at least one opening that is entirely overlapped with the first wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the first wiring through the opening;
A plurality of the unit transistors are arranged side by side in the first direction on the substrate;
In a plan view, a geometric center of the opening is shifted in the first direction with respect to a geometric center of the operation region of each of the plurality of unit transistors,
When the opening having the geometric center closest to the geometric center of the operation region of each of the plurality of unit transistors is defined as the closest opening, the opening of the closest opening from the geometric center of the operation region of each of the unit transistors is defined. A semiconductor device in which a shift amount in the first direction from a geometric center increases from a center to an end of the arrangement of the plurality of unit transistors.   The opening is disposed between the geometric centers of the operation regions of the two unit transistors disposed at both ends in the first direction, and the two unit transistors disposed at both ends in the first direction 2. The semiconductor device according to claim 1, wherein the opening is not disposed outside a geometric center of the operation region.   The semiconductor device according to claim 1, wherein at least two of the openings are arranged at different positions in a direction orthogonal to the first direction.   4. The planar center according to claim 1, wherein a geometric center of the operation region of each of the plurality of unit transistors is shifted from a geometric center of the metal member in a direction orthogonal to the first direction. 2. The semiconductor device according to claim 1.   5. The semiconductor device according to claim 1, wherein the operation regions of the plurality of unit transistors have a planar shape that is long in a direction orthogonal to the first direction. 6.   The semiconductor device according to claim 1, wherein the metal member forms a pillar bump including a metal post containing copper as a main component. The metal member constitutes a second wiring disposed on the substrate,
And a terminal for external connection provided on the second wiring,
The semiconductor device according to claim 1, wherein the metal member is electrically connected to the external connection terminal.   The semiconductor device according to claim 1, wherein the insulating film includes at least one material of silicon oxide, silicon nitride, and resin.   Each of the plurality of unit transistors is a bipolar transistor including a collector layer, a base layer, and an emitter layer formed on the substrate, and the operation region is a region where an operation current flows in a thickness direction. Item 9. The semiconductor device according to any one of Items 1 to 8.   The collector layer, the base layer, and the emitter layer of each of the unit transistors are sequentially stacked on the substrate, and the emitter layer is electrically connected to the first wiring; 10. The semiconductor device according to claim 9, wherein an interface between the base layer and the emitter layer is a heterojunction.   The semiconductor device according to claim 10, wherein the substrate is formed of GaAs, and the emitter layer is formed of InGaP.   11. The semiconductor device according to claim 10, wherein each of said unit transistors is a heterojunction bipolar transistor including said base layer made of SiGe.   Each of the plurality of unit transistors is a field-effect transistor including a source, a drain, and a gate formed on the substrate, and the operation region is a region where an operation current flows in an in-plane direction of a surface of the substrate. The semiconductor device according to claim 1, wherein: A plurality of unit transistors formed on the substrate and including an operation region through which an operation current flows;
A wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the wiring, wherein the insulating film is provided with at least one opening, the entire area of which is overlapped with the wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the wiring through the opening;
A plurality of the unit transistors are arranged side by side in the first direction on the substrate;
In a plan view, a geometric center of the opening is shifted in the first direction with respect to a geometric center of the operation region of each of the plurality of unit transistors,
When the opening having the geometric center closest to the geometric center of the operation region of each of the plurality of unit transistors is defined as the closest opening, the unit transistor of the unit transistor arranged at one end with respect to the first direction is defined. The amount of shift in the first direction from the geometric center of the operation region to the geometric center of the closest opening is determined by the amount of shift from the geometric center of the operation region of the unit transistor disposed at the other end. A semiconductor device smaller than the shift amount in the first direction up to the geometric center of the semiconductor device.   The amount of shift in the first direction from the geometric center of the operation region of the plurality of unit transistors to the geometric center of the closest opening increases from one end in the first direction to the other end. The semiconductor device according to claim 14, wherein: A plurality of unit transistors formed on the substrate and including at least one operation region through which an operation current flows;
A wiring disposed above the operation region and serving as a path of a current flowing through the unit transistor;
An insulating film disposed on the wiring, wherein the insulating film is provided with at least one opening, the entire area of which is overlapped with the wiring in plan view;
A metal member disposed on the insulating film and electrically connected to the wiring through the opening;
A plurality of the unit transistors are arranged side by side in the first direction on the substrate;
In a plan view, a minimum rectangle including the operation region of each of the plurality of unit transistors is defined as an effective operation region, and passes through the midpoint of a line segment having both ends at the geometric centers of the adjacent effective operation regions. When defining a plurality of regions separated by a virtual straight line parallel to a second direction orthogonal to the first direction as an influence range corresponding to the effective operation region located inside the region, The area of the overlapping region, which is the region where the affected range and the opening overlap, is different depending on the effective operation region,
A semiconductor device in which the area of the overlap region corresponding to the effective operation region located at both ends in the first direction is smaller than the area of the overlap region corresponding to the effective operation region other than both ends.

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