JP5035588B2 - Semiconductor device having bipolar transistor - Google Patents

Description

  The present invention relates to a semiconductor device having a bipolar transistor used for radio frequency power amplification, and more particularly to a technique useful for improving radio frequency characteristics of a heterojunction bipolar transistor used for radio frequency power amplification.

Conventionally, a heterojunction bipolar transistor (hereinafter referred to as HBT) uses a heterojunction for the emitter-base junction of the bipolar transistor, and has a band cap of the emitter larger than that of the base region. As a result, the HBT has a small amount of minority carrier injection from the base to the emitter, and can increase the base impurity concentration while keeping the emitter injection efficiency high. Therefore, it is possible to lower the internal base resistance, the cut-off frequency f _T, can be greatly improved over conventional bipolar transistor.

Conventionally, the power amplification bipolar transistor is not limited to the HBT, and has a negative temperature dependence of the base-emitter junction forward voltage _VBE . As a result, it is known that current concentration occurs due to non-uniformity of a large-area base-emitter junction for power use, and the bipolar transistor causes thermal runaway and is destroyed.

High power bipolar transistors have historically started with silicon power transistors. In order to prevent the thermal runaway, a negative feedback resistor called a ballast resistor is connected to the emitter. When the emitter current increases due to temperature rise, the voltage across the emitter / ballast resistor rises. Then, the base-emitter junction forward voltage V _BE is lowered to suppress the increase in the emitter current.

  On the other hand, it has become an era when high-performance HBTs than bipolar transistors are adopted for RF power amplification for radio frequency (hereinafter referred to as RF) communications in battery-operated mobile communication terminals such as mobile phones. Since the HBT also has a risk of thermal runaway, it is necessary to prevent current concentration. However, taking into consideration the battery operation of a mobile phone or the like, a current concentration prevention measure with low power consumption is required. Therefore, as described in Patent Document 1 and Patent Document 2 below, it has become a main technique in HBT to connect a ballast resistor to a base having a small current instead of connecting to a emitter having a large current. .

  Since the current amplification factor β of the bipolar transistor made of silicon has a positive temperature dependency, the current amplification factor β increases as the temperature rises. On the other hand, the current amplification factor β of the HBT has a negative temperature dependency, and the current amplification factor β decreases as the temperature rises. Therefore, in the HBT, the voltage drop at the base ballast resistor increases at high temperatures. Therefore, the effectiveness of the HBT current concentration prevention measure by the base ballast resistor is described in Patent Document 1 below.

  On the other hand, an emitter ballast resistor is connected to the HBT, and in a normal operation state where the temperature of the HBT is low, the resistance value of the emitter ballast resistor is low. When the temperature of the HBT rises, the resistance value of the emitter ballast resistor increases. The current concentration prevention measure is described in Patent Document 3 below.

US Pat. No. 5,321,279 US Pat. No. 5,629,648 JP-A-6-349847

  Prior to the present invention, the inventors engaged in the development of a high-performance HBT for RF power amplification in battery-operated mobile communication terminals such as mobile phones.

  FIG. 1 is an equivalent circuit diagram showing an HBT adopting a base ballast system as a countermeasure against thermal runaway, which was first studied by the present inventors prior to the present invention, and a plan view of the device.

  As shown in the equivalent circuit diagram of FIG. 1, one power HBT is composed of a plurality of (N, N is an integer greater than 1) unit transistors Q1, Q2,. The collector-emitter current paths of these unit transistors Q1, Q2,... QN are connected in parallel. An RF input signal RFIN is supplied to the bases of these unit transistors Q1, Q2,... QN via coupling capacitors C1, C2,. The base bias voltage Vbias is supplied to the bases of these unit transistors Q1, Q2,... QN via base ballast resistors Rb1, Rb2,.

  As shown in the plan view of the device of FIG. 1, a plurality of one ends of coupling capacitors C1, C2,... CN to which an RF input signal RFIN is supplied in common are formed by a lower layer aluminum wiring M1 of a multilayer wiring of a semiconductor integrated circuit. The wiring area 100 is configured. On the other hand, the plurality of other ends of the coupling capacitors C1, C2,... CN connected to the individual bases of the plurality of unit transistors Q1, Q2,... QN are wires formed by the upper layer aluminum wiring M2 of the multilayer wiring of the semiconductor integrated circuit. Each of the regions 200_1, 200_2,... 200_N is configured. Dielectric layers for the coupling capacitors C1, C2,... CN are formed between the wiring region 100 and the wiring regions 200_1, 200_2,. The plurality of wiring regions 200_1, 200_2,... 200_N are connected to the plurality of unit transistors Q1, Q2,..., QN through contacts CNT_1, CNT_2,. Is connected to each of the base areas. 1 is similar to the equivalent circuit diagram of FIG. 1 and the plan view of the device. In FIG. 1, when the current of the unit transistor Q2 is significantly increased as compared to the other unit transistors, the voltage effect of the base ballast resistor Rb2 is increased and current concentration is avoided.

  On the other hand, the plurality of base ballast resistors Rb1, Rb2,... RbN must be two-dimensionally arranged on the semiconductor chip surface together with the plurality of unit transistors Q1, Q2,. However, it has been clarified by the study of the present inventors.

  Also, the thermal noise generated by the plurality of base ballast resistors Rb1, Rb2,... RbN is amplified by the plurality of unit transistors Q1, Q2,. However, it has been clarified by the study of the present inventors.

  FIG. 2 is an equivalent circuit diagram showing an HBT adopting an emitter ballast system as a countermeasure against thermal runaway studied by the inventors and the like prior to the present invention, and a plan view of the device. The emitter ballast type HBT is described in Patent Document 3.

  As shown in the equivalent circuit diagram of FIG. 2, one power HBT is composed of a plurality of (N, N is an integer larger than 1) unit transistors Q1, Q2,. The collector-emitter current paths of these unit transistors Q1, Q2,... QN are connected in parallel, and the RF input signal RFIN is supplied to the bases of these unit transistors Q1, Q2,. Commonly supplied. A base bias voltage Vbias is directly and commonly supplied to the bases of these unit transistors Q1, Q2,. The emitters of these unit transistors Q1, Q2,... QN are connected to emitter ballast resistors Re1, Re2,.

  As shown in the plan view of the device in FIG. 2, one end of one coupling capacitor C to which an RF input signal RFIN is supplied is a wiring region 100 formed by a lower layer aluminum wiring M1 of a multilayer wiring of a semiconductor integrated circuit. It is configured. On the other hand, the other end of one coupling capacitor C commonly connected to the plurality of bases of the plurality of unit transistors Q1, Q2,... QN is a wiring region formed by the upper layer aluminum wiring M2 of the multilayer wiring of the semiconductor integrated circuit. 201. Further, the wiring region 201 of the upper layer aluminum wiring M2 includes a plurality of unit transistors Q1, Q2,... QN through other wiring regions 202, 203, 204_1, 204_2... 204_N formed by the upper layer aluminum wiring M2 of the multilayer wiring. Are connected to the plurality of wiring regions 200_1, 200_2,... 200_N of the upper layer aluminum wiring M2 connected to the plurality of bases. A dielectric layer for one coupling capacitor C is formed between the wiring region 100 and the wiring region 201. The plurality of wiring regions 200_1, 200_2,... 200_N are respectively connected to the base regions of the plurality of unit transistors Q1, Q2,... QN through contacts that are openings provided in the interlayer insulating film and the surface protective insulating film of the multilayer wiring layer. It is connected. In FIG. 2, when the current of the unit transistor Q2 is significantly increased as compared with other unit transistors, the voltage effect of the emitter ballast resistor Re2 is increased and current concentration is avoided. Further, the plurality of emitter ballast resistors Re1, Re2,... ReN can be three-dimensionally arranged on the emitter regions of the plurality of unit transistors Q1, Q2,. This advantage has been clarified by the study of the present inventors. It is also described in Patent Document 3 that the emitter ballast resistor is three-dimensionally arranged on the surface of the HBT emitter region semiconductor chip.

  Further, even if thermal noise is generated by the plurality of emitter ballast resistors Re1, Re2,... ReN, the voltage amplification gain of the plurality of unit transistors Q1, Q2,. Accordingly, the inventors have clarified that the output noise characteristic is good because the voltage amplification gain of the generated noise is small.

  By the way, when the present inventors examined the HBT adopting the emitter ballast system as a countermeasure for the thermal runaway shown in FIG. 2, the following facts became clear.

  In conclusion, a phase difference occurs between a plurality of collector amplified output signals of a plurality of unit transistors Q1, Q2,... QN connected in parallel constituting one power HBT. This means that power gain and power efficiency are degraded. This is due to the following.

  1. In the plan view of the device of FIG. 2, the RF input signal RFIN supplied to one end of one coupling capacitor C which is a wiring region 100 formed by the lower layer aluminum wiring M1 is a dielectric layer for the coupling capacitor C. Is transmitted to the other end of one coupling capacitor C which is a wiring region 201 formed by the upper layer aluminum wiring M2 of the multilayer wiring of the semiconductor integrated circuit.

  2. The RF transmission signal at the other end of one coupling capacitor C, which is the wiring region 201, further passes through the other wiring regions 202, 203 formed by the upper layer aluminum wiring M2, and a plurality of unit transistors Q1, Q2,. Communicated to multiple bases.

  3. In the above case 2, the wiring length of the wiring region 203 arranged in the parallel connection direction is proportional to the number N of parallel connections of a plurality of unit transistors Q1, Q2,... QN connected in parallel constituting one power HBT. Become longer. In order to increase the transmission power output from the power HBT, the number N of parallel connections increases.

  4). In order to increase the transmission power, the wiring length of the wiring region 203 arranged in the parallel connection direction also increases.

  5). The RF signal is transmitted in the shortest distance to the base of the unit transistor QN in the vicinity of one coupling capacitor C in the wiring region 203 arranged in the direction of parallel connection, but the longest distance from one coupling capacitor C. The longest RF signal is transmitted to the base of a certain unit transistor Q1.

  6). Q1, Q2 due to the time difference of RF signal transmission to the bases of the plurality of unit transistors Q1, Q2,... QN on the wiring region 203 arranged at a long wiring distance in the direction of parallel connection described in 5 above. ... There is a phase difference between the multiple collector amplified output signals of QN.

  Therefore, the present invention has been made on the basis of the results of studies on an HBT that employs the emitter ballast system as a countermeasure against thermal runaway by the present inventors as described above. Accordingly, an object of the present invention is to reduce a phase difference between collector amplified output signals of power bipolar transistors for RF signal amplification that employs an emitter ballast method as a countermeasure against thermal runaway. Another object of the present invention is to improve the power gain and power efficiency of the entire RF power amplifier employing a power bipolar transistor for RF signal amplification that employs an emitter ballast system as a measure against thermal runaway. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present invention, one power bipolar transistor (HBT) includes a plurality of (N, N is an integer greater than 1) unit transistors (Q1, Q2) connected in parallel in one semiconductor chip. ... includes QN). Within the one semiconductor chip, the collector-emitter current paths of these unit transistors (Q1, Q2,... QN) are connected in parallel. In one semiconductor chip, the bases of these unit transistors (Q1, Q2,... QN) are commonly supplied with an RF input signal (RFIN) via one coupling capacitor (C). Further, emitter ballast resistors (Re1, Re2,... ReN) are connected to the emitters of these unit transistors (Q1, Q2,..., QN) in the one semiconductor chip. Within the one semiconductor chip, a plurality of signal injection wiring regions (204_1, 204_2,... 204_N) for base input signals of the plurality of unit transistors (Q1, Q2,... QN) are formed by the plurality of unit transistors (Q1). , Q2... QN) are arranged substantially parallel to the arrangement direction of the parallel connection. One electrode plate (100) constituting one end of the one coupling capacitor (C) to which the RF input signal (RFIN) is supplied in common in the one semiconductor chip is formed of the plurality of signal injection wiring regions. They are arranged substantially parallel to the arrangement direction with a wiring length (L) that straddles the arrangement locations of (204_1, 204_2... 204_N). The one electrode plate (100) has a wiring width (W) in a direction substantially perpendicular to the arrangement direction. The wiring width (W) is larger than the wiring width (w) of the plurality of signal injection wiring regions (204_1, 204_2,... 204_N). In the one semiconductor chip, the other electrode plate (201) configured as the other end of the one coupling capacitor (C) is electrically connected to the plurality of signal injection wiring regions (204_1, 204_2,... 204_N). It is connected to the. The one electrode plate (100) and the other electrode plate (201) of the one coupling capacitor (C) are a lower layer wiring (M1) and an upper layer wiring (M2) of the multilayer wiring in the one semiconductor chip. It is comprised by one and the other of each. A dielectric layer (205) for the one coupling capacitor (C) is disposed between the one electrode plate (100) and the other electrode plate (201) of the one coupling capacitor (C). Is formed (see FIG. 3).

  In another embodiment of the present invention, one power bipolar transistor (HBT) is a plurality of (N, N is an integer greater than 1) unit transistors (Q1) connected in parallel in one semiconductor chip. , Q2... QN). Within the one semiconductor chip, the collector-emitter current paths of these unit transistors (Q1, Q2,... QN) are connected in parallel. Within the one semiconductor chip, the bases of these unit transistors (Q1, Q2... QN) are connected via a plurality of (N, N is an integer greater than 1) coupling capacitors (C11, C12... C1N). An RF input signal (RFIN) is supplied. Further, emitter ballast resistors (Re1, Re2,... ReN) are connected to the emitters of these unit transistors (Q1, Q2,..., QN) in the one semiconductor chip. One end of the plurality of coupling capacitors (C11, C12... C1N) to which the RF input signal (RFIN) is supplied is commonly formed by one electrode plate (100) in the one semiconductor chip. Within the one semiconductor chip, a plurality of signal injection wiring regions (204_1, 204_2,... 204_N) for base input signals of the plurality of unit transistors (Q1, Q2,... QN) are formed by the plurality of unit transistors (Q1). , Q2... QN) are arranged substantially parallel to the arrangement direction of the parallel connection. In the one semiconductor chip, the one electrode plate (100) constituting one end of the plurality of coupling capacitors (C11, C12,... C1N) in common has the plurality of signal injection wiring regions (204_1, 204_2,...). 204_N) with a wiring length (L) straddling the arrangement location of 204_N) and being arranged substantially parallel to the arrangement direction. The one electrode plate (100) has a wiring width (W) in a direction substantially perpendicular to the arrangement direction. The wiring width (W) is larger than the wiring width (w) of the plurality of signal injection wiring regions (204_1, 204_2,... 204_N). A plurality (N, N is an integer greater than 1) of the other electrode plates (201_1, 201_2,... 201_N) configured as the other ends of the plurality of coupling capacitors (C11, C12,... C1N) in the one semiconductor chip. ) Are electrically connected to the plurality of signal injection wiring regions (204_1, 204_2,... 204_N), respectively. The one electrode plate (100) configured as the one end of the plurality of coupling capacitors (C11, C12... C1N) and the plurality of the plurality of coupling capacitors (C11, C12... C1N) configured as the other ends. The other electrode plate (201_1, 201_2... 201_N) is composed of one and the other of the lower layer wiring (M1) and the upper layer wiring (M2) of the multilayer wiring in the one semiconductor chip. Between the one electrode plate (100) of the plurality of coupling capacitors (C11, C12... C1N) and the plurality of other electrode plates (201_1, 201_2... 201_N), the plurality of coupling capacitors (C11, C12). ... a dielectric layer (205) for C1N) is formed (see FIG. 6).

  By any of the above means, the one electrode plate (100) constituting one end of the coupling capacitors (C, C1, C2,... CN) to which the RF input signal (RFIN) is commonly supplied is large In order to realize the capacitance, it has a relatively large wiring width (W). As a result, even if the one electrode plate (100) has a relatively long wiring length (L) that straddles the location of the plurality of signal injection wiring regions (204_1, 204_2,... 204_N), The wiring inductance of each electrode plate (100) is sufficiently small, and the coupling capacitors (C11, C12... C1N) function as a low impedance transmission line. Therefore, the time difference of RF signal transmission to the bases of the plurality of unit transistors Q1, Q2,... QN is reduced, and the phase difference between the plurality of collector amplified output signals of Q1, Q2,.

  In a more specific form of the present invention, each of the plurality of unit transistors includes a plurality of subunit transistors, and the base RF signal transmission line and the collector RF signal transmission line are substantially parallel in the semiconductor chip. Is arranged. Accordingly, the leftmost subunit transistor of one unit transistor receives the RF input signal first from the base RF signal transmission line, but the leftmost subunit transistor collector RF. The amplified signal is finally transmitted to the final output point via the collector RF signal transmission line. Conversely, the rightmost subunit transistor, which is the rightmost subunit transistor of one unit transistor, receives the last RF input signal from the base RF signal transmission line. Are first transmitted to the final output point via the collector RF signal transmission line.

  In another more specific form of the present invention, the semiconductor chip is made of a IIIV group compound semiconductor, and the power bipolar transistor is a hetero bipolar transistor.

  In a most specific embodiment of the present invention, each of the plurality of unit transistors includes a plurality of subunit transistors, and the semiconductor chip is connected to the semiconductor chip to ground a plurality of emitters of the plurality of subunit transistors. The formed emitter via is provided at a substantially central portion of the plurality of subunit transistors.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to reduce the phase difference between the collector amplified output signals of the power bipolar transistor for RF signal amplification that employs the emitter ballast method as a countermeasure for thermal runaway.

  Further, according to the present invention, it is possible to improve the power gain and power efficiency of the entire RF power amplifier that employs a power bipolar transistor for RF signal amplification that employs an emitter ballast system as a measure against thermal runaway.

≪Equivalent circuit and device structure of emitter ballast HBT≫
FIG. 3 is a diagram showing an equivalent circuit and device structure of an emitter ballast type HBT according to one embodiment of the first invention.

  As shown in the equivalent circuit of the HBT in the upper part of FIG. 3, one power bipolar transistor composed of the HBT is a plurality of units (N, N is an integer greater than 1) connected in parallel in one semiconductor chip. Transistors Q1, Q2 ... QN are included. Within one semiconductor chip, the collector-emitter current paths of these unit transistors Q1, Q2,..., QN are connected in parallel. The RF input signal RFIN is commonly supplied to the bases of these unit transistors Q1, Q2,... QN through one coupling capacitor C in one semiconductor chip. In addition, emitter ballast resistors Re1, Re2,... ReN are connected to the emitters of these unit transistors Q1, Q2,.

  As shown in the device plan view of the HBT in the upper part of FIG. 3, a plurality of signal injection wiring regions 204_1, 204_2,... 204_N for base input signals of a plurality of unit transistors Q1, Q2,. Are arranged substantially parallel to the arrangement direction of the parallel connection of the plurality of unit transistors Q1, Q2,. One electrode plate 100 constituting one end of one coupling capacitor C to which the RF input signal RFIN is supplied in common in one semiconductor chip is provided with a plurality of signal injection wiring regions 204_1, 204_2,. They are arranged substantially parallel to the arrangement direction with the wiring length L straddling. One electrode plate 100 has a wiring width W in a direction substantially perpendicular to the arrangement direction. This wiring width W is larger than the wiring width w of the plurality of signal injection wiring regions 204_1, 204_2,. The other electrode plate 201 configured as the other end of one coupling capacitor C in one semiconductor chip is electrically connected to the plurality of signal injection wiring regions 204_1, 204_2,... 204_N. In the embodiment of FIG. 3, one electrode plate 100 and the other electrode plate 201 of one coupling capacitor C are respectively composed of a lower layer wiring M1 and an upper layer wiring M2 of multilayer wiring in one semiconductor chip, and vice versa. Can also be configured. A dielectric layer 205 for one coupling capacitor C is formed between one electrode plate 100 and the other electrode plate 201 of one coupling capacitor C. The plurality of emitter ballast resistors Re1, Re2,... ReN are three-dimensionally arranged on the emitter regions of the plurality of unit transistors Q1, Q2,.

  FIG. 4 is a diagram for explaining in more detail one unit transistor of a plurality of unit transistors Q1, Q2,... QN constituting one power HBT shown in FIG. As shown in the figure, the unit transistors of the plurality of unit transistors Q1, Q2,... QN are configured as shown in the center of the figure. As shown in the center of the figure, each unit transistor includes 12 subunit transistors connected in parallel. One subunit transistor is shown as a square block containing the symbols E (emitter), B (base), and C (collector). 6 subunit transistors of 2 rows in 3 columns are arranged on the left side, 6 subunit transistors of 2 rows in 3 columns are arranged on the right side, and the emitters of 12 subunit transistors in the center Emitter vias EV for grounding are commonly disposed. As shown in the lower left of the figure, the emitter of one subunit transistor is shown as a square with an X in the center, the base is shown as a square with a triangle in the center, and the collector is a square with a blank in the center. It is shown in Therefore, one subunit transistor has an emitter and a base in the center and two collectors on the left and right. As an example, the base and collector of one subunit transistor are connected to the lower layer wiring M1 of the multilayer wiring, and the emitter is connected to the upper layer wiring M2 of the multilayer wiring. However, the reverse connection is also possible. As shown in the center of the figure, the emitters of a total of 12 subunit transistors are commonly grounded by the emitter via EV arranged in the center. RF input signals to the bases (B) of a total of 12 subunit transistors are supplied via the left upper layer wiring M2 (204_1). The RF amplified output signal from the collector (C) of the six subunit transistors in the upper row is taken out from above, and the RF amplified output signal from the collector (C) in the six subunit transistors in the lower row is taken out from below. It is. In this way, 12 RF amplified output signals are combined, and finally an RF amplified final output signal is obtained via the upper-layer wiring M2 (206_1) on the right side. Therefore, as shown in the upper part of FIG. 4, the base RF signal transmission line and the collector RF signal transmission line are arranged substantially in parallel in the semiconductor chip. Accordingly, the leftmost subunit transistor of one unit transistor receives the RF input signal first from the base RF signal transmission line, but the leftmost subunit transistor collector RF. The amplified signal is finally transmitted to the final output point via the collector RF signal transmission line. Conversely, the rightmost subunit transistor, which is the rightmost subunit transistor of one unit transistor, receives the last RF input signal from the base RF signal transmission line. Are first transmitted to the final output point via the collector RF signal transmission line. Accordingly, it is possible to reduce the phase difference between the collector amplified output signals of the 12 subunit transistors connected in parallel so as to constitute one unit transistor.

  Further, the emitter via EV for grounding the emitter is disposed at the center of the 12 subunit transistors, so that the heat generated from the power HBT is effectively radiated. When the semiconductor chip constituting the HBT is a IIIV group compound semiconductor such as GaAs, the thermal resistance of the chip is several times higher than that of a silicon semiconductor chip. In such a case, the central arrangement of the emitter vias EV is beneficial in terms of heat dissipation.

  4, the collector RF amplified signals of the plurality of unit transistors Q1, Q2,... QN are synthesized at the output pad M2 (207). A plurality of wire lines W1, W2,... W5 are connected to the output pad M2 (207) in order to increase the current capacity.

FIG. 5 is a diagram for explaining an emitter via EV for grounding the emitter of the subunit transistor shown in FIG. A plurality of mesa-shaped HBTQ15 and Q16 are formed on the surface of the semiconductor chip 500 made of a IIIV group compound semiconductor such as GaAs. The emitter region which is the highest peak of the mesa-shaped HBTs Q15 and Q16 includes an emitter ballast resistor region constituting the present invention. The region of the emitter ballast resistor is made of Al _X Ga _1-X As, and 0 <X ≦ 0.45. Thus, the resistance value of the emitter ballast resistor is low in a normal operation state at a low temperature, and the resistance value can be increased as the temperature rises. The emitters of the HBTQ15 and Q16 are commonly connected to the wiring layer 501 by the upper layer wiring M2 of the multilayer wiring through the emitter through hole Th_E. An emitter via EV is formed by a V-shaped conductive layer penetrating from the chip surface to the chip back surface. The emitter via EV is electrically connected to the metallized conductive layer 502 on the back surface of the chip. The metallized conductive layer 502 on the back surface of the chip is connected to the ground point of the mother board of the mobile phone terminal device by soldering. In this way, the emitters of the 12 subunit transistors connected in parallel to form one unit transistor can be maintained at a stable ground potential, and good heat dissipation characteristics can be obtained. be able to.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the other embodiment of FIG. 6, the one coupling capacitor C shown in FIGS. 3 and 4 is replaced with a plurality of coupling capacitors (C11, C12... C1N). This is an essential difference from the fourth embodiment. The other points are the same as those of the embodiment of FIG. 3, and detailed description thereof is omitted.

FIG. 1 is an equivalent circuit diagram showing an HBT adopting a base ballast system as a countermeasure against thermal runaway, which was first studied by the present inventors prior to the present invention, and a plan view of the device. FIG. 2 is an equivalent circuit diagram and a plan view of a device showing an HBT that employs an emitter ballast system as a countermeasure against thermal runaway studied by the present inventors prior to the present invention. FIG. 3 is an equivalent circuit diagram showing an HBT that employs an emitter ballast system as a countermeasure for thermal runaway according to one embodiment of the present invention, and a plan view of the device. FIG. 4 is a diagram for explaining in more detail one unit transistor of a plurality of unit transistors Q1, Q2,... QN constituting one power HBT shown in FIG. FIG. 5 is a diagram for explaining an emitter via EV for grounding the emitter of the subunit transistor shown in FIG. FIG. 6 is an equivalent circuit diagram showing another embodiment of the present invention and a plan view of the device.

Explanation of symbols

Q1, Q2... QN Unit transistors Re1, Re2... ReN Emitter ballast resistor C One coupling capacitor RFIN RF input signal 100 One electrode plate 201 constituting one end of the coupling capacitor (C) The other end of the coupling capacitor (C) 204_N, a plurality of signal injection wiring regions W for base input signals, a wiring width w of one electrode plate, a wiring width of a plurality of signal injection wiring regions (204_1, 204_2,... 204_N)

Claims (7)

A power bipolar transistor including a plurality of unit transistors connected in parallel;
The collector-emitter current paths of the plurality of unit transistors are connected in parallel,
An RF input signal is commonly supplied to the bases of the plurality of unit transistors through one coupling capacitor,
An emitter ballast resistor is connected to each of the emitters of the plurality of unit transistors,
Are arranged in the arrangement direction and the flat row of a plurality of signal injection line area parallel connection of said plurality of unit transistors for base input signal of the plurality of unit transistors,
One electrode plate constituting one end of the one coupling capacitor to which the RF input signal is supplied in common has a wiring length that straddles the arrangement positions of the plurality of signal injection wiring regions and the arrangement direction . They are placed in flat row,
The one electrode plate has a wiring width of the arrangement direction and a straight direction orthogonal, the wiring width is set larger than the wiring width of the plurality of signal injection wiring region,
The other electrode plate configured as the other end of the one coupling capacitor is electrically connected to the plurality of signal injection wiring regions,
The one electrode plate and the other electrode plate of the one coupling capacitor are respectively composed of a lower layer wiring and an upper layer wiring of a multilayer wiring in the one semiconductor chip,
A semiconductor device in which a dielectric layer for the one coupling capacitor is formed between the one electrode plate and the other electrode plate of the one coupling capacitor. Each of the plurality of unit transistors includes a plurality of subunit transistors,
Base RF signal transmission line and the collector RF signal transmission line is placed on a flat row,
The subunit transistor disposed at the most end side within each of the plurality of unit transistors receives the RF input signal first from the base RF signal transmission line and is disposed at the most end side. The collector RF amplification signal is finally transmitted to the final output point via the collector RF signal transmission line. On the contrary, the subunit transistor arranged at the other end side is the base RF signal transmission line. The RF amplified signal of the collector of the sub-unit transistor disposed at the other end side is received last from the first RF signal, and is first transmitted to the final output point via the collector RF signal transmission line. 2. The semiconductor device according to 1.   2. The semiconductor device according to claim 1, wherein the power bipolar transistor is a hetero-bipolar transistor.   3. The semiconductor device according to claim 2, wherein the power bipolar transistor is a hetero-bipolar transistor composed of a group IIIV compound semiconductor. Each of the plurality of unit transistors includes a plurality of subunit transistors, and an emitter via is disposed on the most end side inside the plurality of unit transistors to ground a plurality of emitters of the plurality of subunit transistors. Sub-uni
The semiconductor device according to any one of claims 1 to 4 having a central portion in the Tsu preparative transistors and most other end to the arrangement sequence of the subunit transistor. A power bipolar transistor including a plurality of unit transistors connected in parallel;
The collector-emitter current paths of the plurality of unit transistors are connected in parallel,
An RF input signal is commonly supplied to the bases of the plurality of unit transistors through a plurality of coupling capacitors,
An emitter ballast resistor is connected to each of the emitters of the plurality of unit transistors,
One end of the plurality of coupling capacitors to which the RF input signal is supplied is configured in common by one electrode plate,
Are arranged in the arrangement direction and the flat row of a plurality of signal injection line area parallel connection of said plurality of unit transistors for base input signal of the plurality of unit transistors,
One electrode plate constituting one end of one of said coupling capacitors said RF input device signals is supplied in common to the said arrangement direction with the wiring length as to straddle the arrangement position of the plurality of signal injection wiring region They are placed in flat row,
The one electrode plate has a wiring width of the arrangement direction and a straight direction orthogonal, the wiring width is set larger than the wiring width of the plurality of signal injection wiring region,
The plurality of other electrode plates configured as the other ends of the plurality of coupling capacitors are electrically connected to the plurality of signal injection wiring regions, respectively.
The said one electrode plate of one of said coupling capacitor and the other electrode plate is constituted respectively by the one and the other of the lower layer wiring and the upper wiring of the multilayer wiring in the single semiconductor chip,
Dielectric layer for one of the coupling capacitor is formed between the one electrode plate of one of said coupling capacitor and the other electrode plate,
Each of the plurality of unit transistors includes a plurality of subunit transistors,
The base RF signal transmission line and the collector RF signal transmission line are arranged in parallel,
The subunit transistor disposed at the most end side within each of the plurality of unit transistors receives the RF input signal first from the base RF signal transmission line and is disposed at the most end side. The collector RF amplification signal is finally transmitted to the final output point via the collector RF signal transmission line. On the contrary, the subunit transistor arranged at the other end side is the base RF signal transmission line. The RF amplified signal of the collector of the subunit transistor disposed on the other end side is received from the last through the collector RF signal transmission line and is first transmitted to the final output point.
In order to ground the plurality of emitters of the plurality of subunit transistors, an emitter via is disposed in the plurality of unit transistors at the most end side, and the subunit transistor is disposed on the other end side. Device having a central portion of the arrangement. 7. The semiconductor device according to claim 6 , wherein the power bipolar transistor is a heterobipolar transistor made of a IIIV group compound semiconductor.

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