JP2021040059A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which the stress applied to a joint of a semiconductor chip is relaxed and an increase in thermal resistance of a heat dissipation path is suppressed.SOLUTION: A semiconductor device 1 includes an insulating heat conductive substrate 40 placed in parallel with a semiconductor chip 20 whose main surface is bonded to a first metal plate 10 and a second metal plate 30 and bonded to the first metal plate 10 and the second metal plate 30. At least one of a joint between the heat conductive substrate 40 and the first metal plate 10 and a joint between the heat conductive substrate 40 and the second metal plate 30 is a joint in which a high strength region with high joint strength and a low strength region with low joint strength are mixed. The low strength region is sandwiched between a high strength region located near the semiconductor chip 20 and a high strength region located far from the semiconductor chip 20.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device.

When a current flows through a semiconductor element formed on a semiconductor chip, the semiconductor chip generates heat due to internal resistance. Various measures are being studied to release the heat generated by the semiconductor chip. For example, a cooler is joined to the main surface of the semiconductor element, and the semiconductor chip is cooled by the cooling water flowing through the cooler. Further, there is a method of cooling the semiconductor chip from the upper surface and the lower surface by a structure in which conductive members having high thermal conductivity are connected to the upper surface and the lower surface of the semiconductor chip and a cooler is joined to each conductive member via an insulating member. Yes (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-40899

However, when different materials are used for the semiconductor chip, the conductive member and the insulating member, a metal such as a cooler to which the conductive member is bonded due to a temperature change of the semiconductor chip due to the difference in the coefficient of thermal expansion of these materials. The board warps. The force generated by this warp is transmitted to the joint between the semiconductor chip and the conductive member via the conductive member, so that stress is applied to the joint between the semiconductor chip and the conductive member. For this reason, deterioration or peeling of the joint portion occurs, and problems such as an increase in thermal resistance and electrical resistance between the semiconductor chip and the conductive member occur.

On the other hand, there is a method of making the conductive member easily deformed to relieve the stress applied to the joint portion between the semiconductor chip and the conductive member. For example, by using a conductive member having a small cross-sectional area perpendicular to the joint surface with the semiconductor chip, the conductive member can be easily deformed. However, when the cross-sectional area of the conductive member is reduced, the transfer of heat in the conductive member is restricted, and the thermal resistance of the path through which heat is transferred (hereinafter, referred to as "heat dissipation path") increases. As described above, there is a trade-off relationship between the decrease in the cross-sectional area of the conductive member and the increase in the thermal resistance of the heat dissipation path.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that relieves stress applied to a joint portion of a semiconductor chip and suppresses an increase in thermal resistance of a heat dissipation path. is there.

In the semiconductor device according to one aspect of the present invention, at least one of the joint portion between the heat conductive substrate and the first metal plate and the joint portion between the heat conductive substrate and the second metal plate has a high strength region having high joint strength. The gist is that the joint is a mixture of low-strength regions. The low-strength region is sandwiched between a high-strength region located near the semiconductor chip and a high-strength region located far from the semiconductor chip.

According to the present invention, it is possible to provide a semiconductor device in which the stress applied to the joint portion of the semiconductor chip is relaxed and the increase in thermal resistance of the heat dissipation path is suppressed.

It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a schematic plan view which shows the other structure of the semiconductor device which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on the modification of 1st Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on the modification of 1st Embodiment. It is a schematic plan view which shows the other structure of the semiconductor device which concerns on the modification of 1st Embodiment. It is a schematic cross-sectional view which shows the other structure of the semiconductor device which concerns on the modification of 1st Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is a schematic plan view which shows the other structure of the semiconductor device which concerns on 4th Embodiment. It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on 5th Embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same parts are designated by the same reference numerals and the description thereof will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each part, and the like include parts that are different from the actual ones. In addition, there are parts in which the relations and ratios of the dimensions of the drawings are different from each other.

(First Embodiment)
As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a first metal plate 10, a semiconductor chip 20, a second metal plate 30, and an insulating heat conductive substrate 40. The first main surface of the semiconductor chip 20 is joined to the first metal plate 10, and the second main surface of the semiconductor chip 20 facing the first main surface is joined to the second metal plate 30. The heat conductive substrate 40 is arranged in parallel with the semiconductor chip 20, and its main surface is joined to the first metal plate 10 and the second metal plate 30.

For the first metal plate 10 and the second metal plate 30, for example, an aluminum plate or a copper plate is used. The first metal plate 10 has a function of a heat radiating plate that releases heat generated in the semiconductor chip 20 to the outside.

The first metal plate 10 and the second metal plate 30 may be used as electrodes of a semiconductor element formed on the semiconductor chip 20. For example, in a semiconductor chip 20 in which a semiconductor element having a first main electrode exposed on a first main surface and a second main electrode exposed on a second main surface is formed, a first metal plate 10 and a second metal plate are formed. 30 is used as an electrode. That is, the first main electrode of the semiconductor element is electrically connected to the first metal plate 10, and the second main electrode is electrically connected to the second metal plate 30. Then, the main current flows through the semiconductor element via the first metal plate 10 and the second metal plate 30.

The semiconductor chip 20 and the first metal plate 10 are joined by a first chip bonding material 51. Further, the semiconductor chip 20 and the second metal plate 30 are joined by a second chip bonding material 52. When the first metal plate 10 or the second metal plate 30 is used as an electrode, the first chip bonding material 51 or the second chip bonding material 52 may be, for example, a solder or a sintered metal bonding material. Conductive bonding materials such as are used. At this time, the semiconductor chip 20, the first metal plate 10, and the second metal plate 30 are metal-bonded. In the following, the joint portion between the semiconductor chip 20 and the first metal plate 10 and the joint portion between the semiconductor chip 20 and the second metal plate 30 are also collectively referred to as a joint portion of the semiconductor chip 20.

The heat conductive substrate 40 arranged in parallel with the semiconductor chip 20 between the first metal plate 10 and the second metal plate 30 has one main surface of the first metal plate 10 and the first substrate bonding material 61. It is joined by. Further, the other main surface of the heat conductive substrate 40 and the second metal plate 30 are bonded by a second substrate bonding material 62.

The materials having thermal conductivity are the heat conductive substrate 40, the first substrate bonding material 61 and the second, so that heat can be transferred between the first metal plate 10 and the second metal plate 30. Used for the substrate bonding material 62. The heat conductive substrate 40 has an insulating property to the extent that a current path is not formed between the first metal plate 10 and the second metal plate 30. For example, a silicon nitride substrate or the like is used for the heat conductive substrate 40.

A heat conductive substrate 40 having a metal pattern formed on a main surface facing the second metal plate 30 may be used. As a result, when the second metal plate 30 is used as an electrode of the semiconductor chip 20, the metal pattern formed on the second substrate bonding material 62 and the heat conductive substrate 40 can be used as the current path. In this case, as the second substrate bonding material 62, a conductive bonding material such as solder or a sintered metal bonding material is used. A metal film may be formed on the main surface of the heat conductive substrate 40, and the heat conductive substrate 40 may be metal-bonded to the first metal plate 10 and the second metal plate 30.

In the semiconductor device 1, when the semiconductor chip 20 generates heat, direct heat transfer from the semiconductor chip 20 to the first metal plate 10 and the semiconductor chip 20 to the first via the second metal plate 30 and the heat conductive substrate 40. Heat transfer to the metal plate 10 occurs. The heat transfer of these two paths can reduce the thermal resistance of the heat dissipation path of the semiconductor device 1.

As shown in FIG. 1, in the joint portion between the heat conductive substrate 40 and the second metal plate 30, the region where the second substrate bonding material 62 is arranged and the second substrate bonding material 62 are not arranged. Areas are mixed. On the other hand, the first substrate bonding material 61 is uniformly arranged at the bonding portion between the heat conductive substrate 40 and the first metal plate 10.

In the joint portion between the heat conductive substrate 40 and the second metal plate 30, the region where the second substrate bonding material 62 is arranged is stronger than the region where the second substrate bonding material 62 is not arranged. Is a relatively high region (hereinafter referred to as "high strength region"). On the other hand, the remaining region of the region where the second substrate bonding material 62 is arranged is a region where the bonding strength is relatively low as compared with the region where the second substrate bonding material 62 is arranged (hereinafter, "low strength"). It is called "area"). The low-strength region is a region sandwiched between a high-strength region located near the semiconductor chip 20 and a high-strength region located far from the semiconductor chip 20.

By providing a space in which the second substrate bonding material 62 is not arranged at the joint portion between the heat conductive substrate 40 and the second metal plate 30, a portion easily deformed is generated in the second metal plate 30. That is, the low-strength region, which is the space where the second substrate bonding material 62 is not arranged, is the region where the second metal plate 30 is easily deformed.

In the semiconductor device 1, the force generated by the warp of the first metal plate 10 and transmitted to the second metal plate 30 is applied to the high-strength region near the semiconductor chip 20 and the high-strength region far from the semiconductor chip 20. Be distributed. Therefore, the position of the stress force point applied to the joint portion of the semiconductor chip 20 is farther from the semiconductor chip 20 than in the case where the joint strength between the heat conductive substrate 40 and the second metal plate 30 is uniform at the joint portion. .. Further, since the bending rigidity of the second metal plate 30 is weak in the low strength region, the second metal plate 30 bends when a force is transmitted to the second metal plate 30. Therefore, in the semiconductor device 1, even if the semiconductor device 1 is warped due to a temperature change of the semiconductor chip 20, the influence of the warp is absorbed by the deformation of the second metal plate 30. Therefore, according to the semiconductor device 1, the stress applied to the joint portion of the semiconductor chip 20 can be relaxed.

Further, in the semiconductor device 1, it is not necessary to reduce the cross-sectional area of the second metal plate 30 in order to make the second metal plate 30 easily deformed. Therefore, according to the semiconductor device 1, it is possible to suppress an increase in the thermal resistance of the heat dissipation path.

FIG. 2 shows a plan view of the semiconductor device 1. In FIG. 2, the second chip bonding material 52 is not displayed, and the semiconductor chip 20, the second substrate bonding material 62, the heat conductive substrate 40, and the first metal plate pass through the second metal plate 30. 10 is displayed. FIG. 1 corresponds to a cross-sectional view taken along the I-I direction of FIG. In the semiconductor device 1 shown in FIG. 2, the second substrate bonding material 62 is formed in a ring shape. That is, the region surrounded by the second substrate bonding material 62 is the low strength region.

FIG. 3 shows a plan view of another example of the semiconductor device 1. FIG. 1 corresponds to a cross-sectional view taken along the I-I direction of FIG. In the semiconductor device 1 shown in FIG. 3, the region sandwiched between the two second substrate bonding members 62 arranged apart from each other is the low strength region. That is, each of the high-strength region near the semiconductor chip 20 and the high-strength region far from the semiconductor chip 20 has a band shape extending perpendicular to the direction from the semiconductor chip 20 toward the heat conductive substrate 40. In this way, by separately arranging the high-strength region located near the semiconductor chip 20 and the high-strength region located far from the semiconductor chip 20, the stress applied to the joint portion of the semiconductor chip 20 can be further relaxed. ..

The semiconductor device 1 is suitably used for a power conversion device or the like used under severe conditions having a temperature cycle. For example, in an in-vehicle power converter mounted on an automobile, a large amount of current flows through a semiconductor element and a large amount of heat is generated by a semiconductor chip. In addition, in-vehicle power converters are used in environments with harsh temperature cycles. However, by applying the semiconductor device 1, it is possible to alleviate the stress applied to the joint portion of the semiconductor chip and suppress the increase in the thermal resistance of the heat dissipation path in the in-vehicle power conversion device.

<Modification example>
In the semiconductor device 1 according to the modified example of the first embodiment shown in FIG. 4, a space is provided as a low strength region in the first substrate bonding material 61 for bonding the heat conductive substrate 40 and the first metal plate 10. ing. That is, a high-strength region and a low-strength region coexist at the joint portion between the heat conductive substrate 40 and the first metal plate 10. On the other hand, the second substrate bonding material 62 is uniformly arranged at the bonding portion between the heat conductive substrate 40 and the second metal plate 30.

In the semiconductor device 1 shown in FIG. 4, a region having high bonding strength between the heat conductive substrate 40 and the first metal plate 10 is dispersed at a position close to the semiconductor chip 20 and a position far from the semiconductor chip 20. Therefore, the position of the point of stress applied to the joint portion of the semiconductor chip 20 due to the influence of the warp generated on the first metal plate 10 is the same as the joint strength between the heat conductive substrate 40 and the first metal plate 10 at the joint portion. It is farther from the semiconductor chip 20 than in the case of the above. Further, since the bending rigidity of the first metal plate 10 is weak in the low strength region, the first metal plate 10 bends. Therefore, the influence of the warp of the semiconductor device 1 is absorbed by the deformation of the first metal plate 10. As a result, according to the semiconductor device 1 shown in FIG. 4, the stress applied to the joint portion of the semiconductor chip 20 can be relaxed.

FIG. 5 shows a plan view of the semiconductor device 1 shown in FIG. In FIG. 5, the first substrate bonding material 61 is displayed through the heat conductive substrate 40. FIG. 4 is a cross-sectional view taken along the IV-IV direction of FIG. In the semiconductor device 1 shown in FIG. 5, the first substrate bonding material 61 is formed in a ring shape. That is, the region surrounded by the first substrate bonding material 61 is the low strength region.

FIG. 6 shows a plan view of another example of the semiconductor device 1 shown in FIG. In the semiconductor device 1 shown in FIG. 6, a region sandwiched between two strip-shaped first substrate bonding members 61 arranged apart from each other is a low-strength region.

A high-strength region and a low-strength region may be mixed in both the joint portion between the heat conductive substrate 40 and the first metal plate 10 and the joint portion between the heat conductive substrate 40 and the second metal plate 30. .. That is, as shown in FIG. 7, a space sandwiched between the second substrate bonding material 62 is provided as a low strength region at the joint portion between the heat conductive substrate 40 and the second metal plate 30, and the heat conductive substrate 40 is provided. A space sandwiched between the first substrate bonding material 61 and the joint portion between the metal plate 10 and the first metal plate 10 is provided as a low-strength region. As a result, the bending rigidity of both the first metal plate 10 and the second metal plate 30 is weakened. Therefore, the stress applied to the joint portion of the semiconductor chip 20 can be reduced.

(Second Embodiment)
In the semiconductor device 1 according to the second embodiment, as shown in FIG. 8, the length of the second metal plate 30 which is rectangular in a plan view is the length X in the row direction X from the semiconductor chip 20 toward the heat conductive substrate 40. , The shape is longer than the length of the column direction Y perpendicular to the row direction X in a plan view. Other configurations are the same as in the first embodiment.

According to the semiconductor device 1 shown in FIG. 8, the bending rigidity of the second metal plate 30 is weakened by forming the second metal plate 30 into an elongated shape with the row direction X as the longitudinal direction. Therefore, by bending the second metal plate 30, the influence of the warp of the first metal plate 10 is absorbed. As a result, the stress applied to the joint portion of the semiconductor chip 20 can be reduced.

FIG. 9 shows an example in which a space in which the second substrate bonding material 62 is not arranged is provided as a low strength region at the joint portion between the heat conductive substrate 40 and the second metal plate 30. A space in which the first substrate bonding material 61 is not arranged may be provided as a low strength region at the joint portion between the heat conductive substrate 40 and the first metal plate 10. Further, a low strength region may be provided at both the joint portion between the heat conductive substrate 40 and the second metal plate 30 and the joint portion between the heat conductive substrate 40 and the first metal plate 10.

(Third Embodiment)
As shown in FIGS. 10 and 11, in the semiconductor device 1 according to the third embodiment, the first partial electrode plate 31 and the second portion are formed on the second main surface of the semiconductor chip 20 by the second chip bonding material 52. The electrode plates 32 are connected to each other. The first heat conductive substrate 41 and the second heat conductive substrate 42, which correspond to the heat conductive substrate 40, are individually bonded to the first partial electrode plate 31 and the second partial electrode plate 32. That is, the difference from the semiconductor device 1 of FIG. 1 is that the second metal plate 30 is divided into the first partial electrode plate 31 and the second partial electrode plate 32. Other configurations are the same as in the first embodiment.

The semiconductor device 1 according to the third embodiment has a direct heat dissipation path from the semiconductor chip 20 to the first metal plate 10, a heat dissipation path via the first partial electrode plate 31 and the first heat conductive substrate 41, and a first heat conduction path. It has a heat dissipation path via the two-part electrode plate 32 and the second heat conduction substrate 42. By heat transfer in these plurality of heat dissipation paths, the thermal resistance of the heat dissipation paths of the semiconductor device 1 can be reduced. Further, the bending rigidity of the first partial electrode plate 31 and the second partial electrode plate 32 may be weakened by forming the first partial electrode plate 31 and the second partial electrode plate 32 into an elongated shape. As a result, the stress applied to the joint portion of the semiconductor chip 20 can be reduced.

In FIG. 11, the second substrate bonding material 62 is arranged at the joint portion between the first heat conductive substrate 41 and the first partial electrode plate 31 and the joint portion between the second heat conductive substrate 42 and the second partial electrode plate 32. An example is shown in which a space that is not provided is provided as a low-intensity region. However, a space may be provided as a low-strength region in the first substrate bonding material 61 for bonding the first heat conductive substrate 41, the second heat conductive substrate 42, and the first metal plate 10. Alternatively, a low-strength region may be provided in all of these joints.

(Fourth Embodiment)
As shown in FIG. 12, the semiconductor device 1 according to the fourth embodiment has a Young's modulus lower than that of the second substrate bonding material 62 in the remaining region of the region where the second substrate bonding material 62 is arranged. In addition, the low elastic material 70 having thermal conductivity is arranged. That is, in the semiconductor device 1 shown in FIG. 12, the low elastic material 70 is arranged in the low strength region sandwiched between the high strength regions in which the second substrate bonding material 62 is arranged. Other configurations are the same as those of the first embodiment shown in FIG.

For the low elastic material 70, a material having at least a higher thermal conductivity than air is used. As a result, the thermal resistance of the heat dissipation path via the second metal plate 30 and the heat conductive substrate 40 is reduced, and the amount of heat transferred from the semiconductor chip 20 to the first metal plate 10 is increased.

As described above, according to the semiconductor device 1 shown in FIG. 12, the thermal resistance of the heat dissipation path is increased by embedding the low elastic material 70 having thermal conductivity in the space where the second substrate bonding material 62 is not arranged. It can be further lowered. Then, by using the low elastic material 70 having a low Young's modulus, the bending rigidity of the second metal plate 30 can be weakened in the low strength region. Therefore, when a space is provided in the second substrate bonding material 62, it is possible to suppress a decrease in the effect of reducing the stress applied to the bonding portion of the semiconductor chip 20. Others are substantially the same as those in the first embodiment, and duplicate description will be omitted.

FIG. 13 shows a plan view of the semiconductor device 1 shown in FIG. In the semiconductor device 1 shown in FIG. 13, the second substrate bonding material 62 is formed in a ring shape. That is, the region in which the low elastic material 70 is arranged so as to be surrounded by the second substrate bonding material 62 is the low strength region.

FIG. 14 shows a plan view of another example of the semiconductor device 1 shown in FIG. In the semiconductor device 1 shown in FIG. 14, the region where the low elastic material 70 is arranged is low, sandwiched between two second substrate bonding materials 62 arranged at positions close to and far from the semiconductor chip 20. It is a strength region.

In the joint portion between the heat conductive substrate 40 and the first metal plate 10, the Young's modulus is lower than that of the first substrate bonding material 61 in the remaining region of the region where the first substrate bonding material 61 is arranged. Moreover, a low elastic material having thermal conductivity may be arranged. Alternatively, both the joint portion between the heat conductive substrate 40 and the first metal plate 10 and the joint portion between the heat conductive substrate 40 and the second metal plate 30 are low in the remaining region of the region where the bonding material is arranged. The elastic material 70 may be arranged.

(Fifth Embodiment)
As shown in FIG. 15, the semiconductor device 1 according to the fifth embodiment has a first metal plate 10 on another main surface of the first metal plate 10 facing the main surface on which the semiconductor chip 20 is arranged. It is a configuration in which a reinforcing plate 80 having a higher bending rigidity than that of the reinforcing plate 80 is joined. Other configurations are the same as in the first embodiment.

According to the semiconductor device 1 shown in FIG. 15, the warp of the first metal plate 10 can be suppressed by joining the reinforcing plate 80 to the first metal plate 10. For example, even when parts that are greatly affected by warpage, such as a cooler and metal components, are arranged on the other main surface of the first metal plate 10 facing the main surface to be joined to the semiconductor chip 20, the reinforcing plate 80 This suppresses the warp of the entire semiconductor device 1.

Also in the semiconductor device 1 shown in FIG. 15, the stress applied to the joint portion of the semiconductor chip 20 is relaxed by mixing the high-strength region and the low-strength region in the joint portion of the semiconductor chip 20. As shown in FIG. 15, a space in which the second substrate bonding material 62 is not arranged may be provided as a low strength region at the joint portion between the heat conductive substrate 40 and the second metal plate 30, or this space may be provided as a low strength region. It may be embedded with an elastic material 70. Alternatively, a space in which the first substrate bonding material 61 is not arranged may be provided as a low-strength region at the joint portion between the heat conductive substrate 40 and the first metal plate 10, and this space may be provided by the low elastic material 70. It may be embedded. Further, a low strength region may be provided at both the joint portion between the heat conductive substrate 40 and the second metal plate 30 and the joint portion between the heat conductive substrate 40 and the first metal plate 10.

1 ... Semiconductor device 10 ... First metal plate 20 ... Semiconductor chip 30 ... Second metal plate 40 ... Heat conductive substrate 51 ... First chip bonding material 52 ... Second chip bonding material 61 ... First substrate bonding Material 62 ... Second substrate bonding material 70 ... Low elastic material 80 ... Reinforcing plate

Claims (6)

A first metal plate and a semiconductor chip in which a first main surface is bonded to the first metal plate,
A second metal plate joined to the second main surface of the semiconductor chip facing the first main surface, and
It is provided with an insulating heat conductive substrate arranged in parallel with the semiconductor chip and bonded to the first metal plate and the second metal plate.
At least one of the joint portion between the heat conductive substrate and the first metal plate and the joint portion between the heat conductive substrate and the second metal plate is relative to a high strength region where the joint strength is relatively high. It is a joint with a mixture of low-strength regions and low strength regions.
A semiconductor device characterized in that the low-strength region is sandwiched between the high-strength region at a position close to the semiconductor chip and the high-strength region at a position far from the semiconductor chip. The high-strength region is a region where the bonding material is arranged.
The semiconductor device according to claim 1, wherein the low-strength region is a residual region of a region in which the bonding material is arranged. The semiconductor device according to claim 2, wherein a low elastic material having a Young's modulus lower than that of the bonding material and having thermal conductivity is arranged in the low strength region. The second metal plate has a rectangular shape in a plan view and has a rectangular shape.
The length of the second metal plate along the row direction from the region where the semiconductor chips are joined to the region where the heat conductive substrate is joined is the second along the column direction perpendicular to the row direction. The semiconductor device according to any one of claims 1 to 3, wherein the length is longer than the length of the metal plate of the above. The claim is characterized in that a reinforcing plate having a bending rigidity higher than that of the first metal plate is joined to another main surface of the first metal plate facing the main surface on which the semiconductor chip is arranged. The semiconductor device according to any one of 1 to 4. Each of the high-strength region located near the semiconductor chip and the high-strength region located far from the semiconductor chip have a strip shape extending perpendicular to the direction from the semiconductor chip toward the heat conductive substrate and are separated from each other. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is arranged.

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