JP2021028921A - Pressure-welded type semiconductor device and method of manufacturing pressure-welded type semiconductor device - Google Patents

Pressure-welded type semiconductor device and method of manufacturing pressure-welded type semiconductor device Download PDF

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JP2021028921A
JP2021028921A JP2017237678A JP2017237678A JP2021028921A JP 2021028921 A JP2021028921 A JP 2021028921A JP 2017237678 A JP2017237678 A JP 2017237678A JP 2017237678 A JP2017237678 A JP 2017237678A JP 2021028921 A JP2021028921 A JP 2021028921A
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electrode plate
semiconductor chip
pressure
frame
semiconductor device
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成人 宮川
Shigeto Miyagawa
成人 宮川
塩田　裕基
Hironori Shioda
裕基 塩田
崇夫 釣本
Takao Tsurimoto
崇夫 釣本
哲男 本宮
Tetsuo Motomiya
哲男 本宮
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Mitsubishi Electric Corp
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Priority to PCT/JP2018/039473 priority patent/WO2019116736A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

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Abstract

To enhance insulation of an outer peripheral part of a semiconductor chip with simple constitution.SOLUTION: A pressure-welded type semiconductor device 100 comprises: a first electrode plate 12; a semiconductor chip 11 which has its reverse side fixed to the first electrode plate 12; a second electrode plate 13 which is opposed to the first electrode plate 12; a flexible member 16 which covers an outer peripheral part 114 provided along a circumference of the top surface of the semiconductor chip 11; a frame 15 which is arranged between the first electrode 12 and second electrode 13, and provided to surround the semiconductor chip 11; and a module case 18 which is arranged to surround the frame 15, and has one end joined to the first electrode plate 12 and the other end joined to the second electrode plate 13, respectively. The frame 15 further comprises a cover 17 which is provided on an inner side face, and projects inward from a terminal end of an outer peripheral part 114 to press and fix the flexible member 16 to the outer peripheral part 114.SELECTED DRAWING: Figure 2

Description

本発明は、圧接型半導体装置に関し、特に半導体チップ外周部の絶縁を保護する圧接型半導体装置及び圧接型半導体装置の製造方法に関する。 The present invention relates to a pressure-welded semiconductor device, and more particularly to a pressure-welded semiconductor device for protecting the insulation of the outer peripheral portion of a semiconductor chip and a method for manufacturing the pressure-welding semiconductor device.

従来の縦型の半導体装置、特に圧接型の半導体装置では、半導体基板は、ＯＮ動作時には電流を通電する通電パスとして、ＯＦＦ動作時には電流を遮断し、高電圧を保持する絶縁層としての役割を果たす。高電圧は、数ｋＶから数１０ｋＶまでに及ぶ可能性があるが、半導体基板が十分な絶縁性能を保有していたとしても表面電極と半導体基板との間で、表面保護層の表面のガス層において沿面放電が発生し、半導体装置が絶縁破壊してしまう可能性がある。 In conventional vertical semiconductor devices, especially pressure-welded semiconductor devices, the semiconductor substrate serves as an energizing path for energizing current during ON operation and as an insulating layer that cuts off current during OFF operation and maintains a high voltage. Fulfill. High voltage can range from a few kV to a few tens of kV, but even if the semiconductor substrate has sufficient insulation performance, the gas layer on the surface of the surface protective layer between the surface electrode and the semiconductor substrate. There is a possibility that creeping discharge will occur in the semiconductor device and the semiconductor device will undergo dielectric breakdown.

従来の縦型の半導体装置、特に圧接型の半導体装置では、装置内部の半導体チップの外周部を、ポリイミド、シリコーンゴム等の樹脂コーティングによって絶縁保護することによって半導体装置の表面保護を行っていた。 In conventional vertical semiconductor devices, particularly pressure-welded semiconductor devices, the surface of the semiconductor device is protected by insulatingly protecting the outer peripheral portion of the semiconductor chip inside the device with a resin coating such as polyimide or silicone rubber.

近年、半導体チップは、サイリスタからＩＧＢＴ、ＭＯＳＦＥＴへの素子へと置き換わっており、素子置き換えに伴う半導体チップのマルチチップ化、素子の耐圧設計の高度化によって、表面電極の端部と半導体基板の端部との距離、つまり半導体チップの外周部の距離である終端距離が縮小化している。 In recent years, semiconductor chips have been replaced by elements from thyristors to IGBTs and MOSFETs. Due to the multi-chip of semiconductor chips accompanying the replacement of elements and the sophistication of withstand voltage design of elements, the edge of the surface electrode and the edge of the semiconductor substrate The distance from the portion, that is, the termination distance, which is the distance from the outer peripheral portion of the semiconductor chip, is reduced.

沿面放電は、終端距離を十分に長くするほど防止することが可能であるが、半導体装置の小型化によって、半導体チップの終端距離が縮小化しているため、半導体チップの外周部への樹脂コーティングのみによる、外周部の絶縁性の確保が困難になっている。 Creeping discharge can be prevented by making the termination distance sufficiently long, but since the termination distance of the semiconductor chip is reduced due to the miniaturization of the semiconductor device, only the resin coating on the outer peripheral portion of the semiconductor chip is required. This makes it difficult to ensure the insulation of the outer peripheral portion.

上記の問題を解決するために、特許文献１では、半導体チップの外周部の絶縁性を確保するために、半導体チップの外周部上にチップフレームを接着剤によって接着することで、半導体チップの外周部の絶縁強化を行う圧接型半導体装置が提案されている。 In order to solve the above problem, in Patent Document 1, in order to secure the insulating property of the outer peripheral portion of the semiconductor chip, the outer peripheral portion of the semiconductor chip is adhered to the outer peripheral portion of the semiconductor chip with an adhesive. A pressure-welded semiconductor device that reinforces the insulation of the part has been proposed.

特開平８−８８２４０Japanese Patent Application Laid-Open No. 8-88240

特許文献１に記載の圧接型半導体装置においては、長期運転における半導体チップの温度変化によって、半導体チップとチップフレーム間の接着剤に対して、各部材の熱膨張係数の差から熱応力が発生し、チップフレームが半導体チップの外周部から剥離してしまうおそれがあった。 In the pressure welding type semiconductor device described in Patent Document 1, thermal stress is generated with respect to the adhesive between the semiconductor chip and the chip frame due to the difference in the coefficient of thermal expansion of each member due to the temperature change of the semiconductor chip during long-term operation. , The chip frame may be peeled off from the outer peripheral portion of the semiconductor chip.

本発明は、上記のような問題点を解決するためになされたものであり、簡易なアセンブリ工程によって半導体チップの外周部の絶縁性を強化することを目的としている。 The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to enhance the insulating property of the outer peripheral portion of the semiconductor chip by a simple assembly process.

本発明に係る圧接型半導体装置は、第１電極板と、第１電極板に裏面が固着された半導体チップと、第１電極板と対向する第２電極板と、半導体チップ表面の周辺に沿って設けられた外周部を覆う可撓性部材と、第１電極板と第２電極板との間に配置され、半導体チップを取り囲むように設けられるフレームと、フレームを取り囲むように配置され、一端で第１電極板と、他端で第２電極板とそれぞれ接合されるモジュールケースと、を備え、フレームは、内側面に設けられ、外周部の終端よりも内側に突出することにより、可撓性部材を外周部へと圧接固定するカバーと、をさらに備える。 The pressure-welded semiconductor device according to the present invention includes a first electrode plate, a semiconductor chip whose back surface is fixed to the first electrode plate, a second electrode plate facing the first electrode plate, and a periphery of the surface of the semiconductor chip. A flexible member that covers the outer peripheral portion, a frame that is arranged between the first electrode plate and the second electrode plate and is provided so as to surround the semiconductor chip, and a frame that is arranged so as to surround the frame at one end. A first electrode plate and a module case joined to the second electrode plate at the other end are provided, and the frame is provided on the inner side surface and is flexible by projecting inward from the end of the outer peripheral portion. A cover for pressing and fixing the sex member to the outer peripheral portion is further provided.

本発明に係る圧接型半導体装置の製造方法は、半導体チップを第１電極板上に固着する工程と、中間電極を第２電極板に固着する工程と、第１電極板上で半導体チップを取り囲むようにフレームを配置する工程と、フレームを取り囲むようにモジュールケースを配置する工程と、フレームに設けられ、半導体チップ表面の外周部の終端よりも内側に突出したカバーと外周部との間に可撓性部材を配置する工程と、中間電極が半導体チップ上に位置するように、モジュールケース上に第２電極板を配置する工程と、第１電極板と、第２電極板と、モジュールケースとを圧接治具によって圧接することにより、第１電極板、第２電極板、中間電極及び半導体チップとを電気的に接続する主回路の形成と、カバーによる外周部への可撓性部材の圧接固定と、を行う工程と、を備える。 The method for manufacturing a pressure-welded semiconductor device according to the present invention includes a step of fixing the semiconductor chip on the first electrode plate, a step of fixing the intermediate electrode to the second electrode plate, and surrounding the semiconductor chip on the first electrode plate. The process of arranging the frame as described above, the process of arranging the module case so as to surround the frame, and the process of arranging the module case and the outer peripheral portion of the cover provided on the frame and protruding inward from the end of the outer peripheral portion of the semiconductor chip surface are possible. The process of arranging the flexible member, the process of arranging the second electrode plate on the module case so that the intermediate electrode is located on the semiconductor chip, the first electrode plate, the second electrode plate, and the module case. Is formed by pressure welding with a pressure welding jig to form a main circuit that electrically connects the first electrode plate, the second electrode plate, the intermediate electrode, and the semiconductor chip, and the flexible member is pressure-welded to the outer peripheral portion by the cover. It is provided with a step of fixing and performing.

本発明に係る圧接型半導体装置によれば、フレームに設けられたカバーが、半導体チップの外周部を覆う可撓性部材を加圧するため、熱応力による可撓性部材の外周部からの剥離を防止でき、半導体チップの外周部の長期的絶縁信頼性を達成することができる。 According to the pressure-welding semiconductor device according to the present invention, the cover provided on the frame pressurizes the flexible member that covers the outer peripheral portion of the semiconductor chip, so that the flexible member is peeled off from the outer peripheral portion due to thermal stress. This can be prevented and long-term insulation reliability of the outer peripheral portion of the semiconductor chip can be achieved.

本発明に係る圧接型半導体装置の製造方法によれば、簡易的なプロセスによって半導体チップの外周部の絶縁保護を行うことができる。 According to the method for manufacturing a pressure-welded semiconductor device according to the present invention, insulation protection of the outer peripheral portion of a semiconductor chip can be performed by a simple process.

本発明の実施の形態１に係る圧接型半導体装置を示す概略図である。It is a schematic diagram which shows the pressure welding type semiconductor apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る圧接型半導体装置の半導体チップを示す断面図である。It is sectional drawing which shows the semiconductor chip of the pressure welding type semiconductor apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る圧接型半導体装置の圧接方法を示す断面図である。It is sectional drawing which shows the pressure welding method of the pressure welding type semiconductor apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る圧接型半導体装置の圧接前の組立パターンを示す図である。It is a figure which shows the assembly pattern before pressure welding of the pressure welding type semiconductor apparatus which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 5 of this invention. 本発明の実施の形態６に係る圧接型半導体装置の断面図である。It is sectional drawing of the pressure welding type semiconductor apparatus which concerns on Embodiment 6 of this invention.

実施の形態１．
本発明の実施の形態１に係る圧接型半導体装置１００の構成について説明する。図１は、実施の形態１に係る圧接型半導体装置１００の概略図である。図２は、実施の形態１に係る圧接型半導体装置１００の断面図であり、図１のＡ−Ａ断面図である。図２に示すように、圧接型半導体装置１００は、半導体チップ１１と、第１電極板１２と、第２電極板１３と、中間電極１４と、フレーム１５と、可撓性部材１６と、カバー１７と、モジュールケース１８とを有する。半導体チップ１１の構成については、以下に示す。 Embodiment 1.
The configuration of the pressure welding type semiconductor device 100 according to the first embodiment of the present invention will be described. FIG. 1 is a schematic view of the pressure welding type semiconductor device 100 according to the first embodiment. FIG. 2 is a cross-sectional view of the pressure welding type semiconductor device 100 according to the first embodiment, and is a cross-sectional view taken along the line AA of FIG. As shown in FIG. 2, the pressure welding type semiconductor device 100 includes a semiconductor chip 11, a first electrode plate 12, a second electrode plate 13, an intermediate electrode 14, a frame 15, a flexible member 16, and a cover. It has 17 and a module case 18. The configuration of the semiconductor chip 11 is shown below.

図３は、実施の形態１に係る圧接型半導体装置１００の半導体チップ１１を示す断面図である。半導体チップ１１は、半導体基板１１０と、第１の電極１１１と、第２の電極１１２と、表面保護部材１１３とを有する。半導体チップ１１の第２の電極１１２側を表面、第１の電極１１１側を裏面とする。なお、半導体基板１１０内部に設けられた詳細な構造は、個々の素子構造によって異なるため省略する。
半導体チップ１１として、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）、金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ）、などのトランジスタ、ゲートターンオフサイリスタ（ＧＴＯ）等が挙げられる。第１の電極１１１は、半導体基板１１０の裏面上に設けられる。第２の電極１１２は、半導体基板１１０の表面上に設けられる。半導体チップ１１表面の周辺に沿って設けられた、第２の電極１１２と半導体基板１１０の端部との間の部位を外周部１１４とする。表面保護部材１１３は、半導体チップ１１の外周部１１４の全周にわたって設けられる。表面保護部材１１３は、ＴＥＯＳ、Ｓｉ３Ｎ４、ＤＬＣ（Ｄｉａｍｏｎｄ Ｌｉｋｅ Ｃａｒｂｏｎ）、ＳＩＰＯＳ（Ｓｅｍｉ Ｉｎｓｕｌａｔｉｎｇ ｐｏｌｙｃｒｙｓｔａｌｌｉｎｅ ｓｉｌｉｃｏｎ）、パリレン、ポリイミド等の絶縁部材によって構成される。 FIG. 3 is a cross-sectional view showing a semiconductor chip 11 of the pressure welding type semiconductor device 100 according to the first embodiment. The semiconductor chip 11 has a semiconductor substrate 110, a first electrode 111, a second electrode 112, and a surface protection member 113. The second electrode 112 side of the semiconductor chip 11 is the front surface, and the first electrode 111 side is the back surface. The detailed structure provided inside the semiconductor substrate 110 is omitted because it differs depending on the individual element structures.
Examples of the semiconductor chip 11 include transistors such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs), gate turn-off thyristors (GTOs), and the like. The first electrode 111 is provided on the back surface of the semiconductor substrate 110. The second electrode 112 is provided on the surface of the semiconductor substrate 110. The outer peripheral portion 114 is a portion between the second electrode 112 and the end portion of the semiconductor substrate 110 provided along the periphery of the surface of the semiconductor chip 11. The surface protection member 113 is provided over the entire circumference of the outer peripheral portion 114 of the semiconductor chip 11. Surface protection member 113, TEOS, Si 3 N 4, DLC (Diamond Like Carbon), SIPOS (Semi Insulating polycrystalline silicon), parylene, constituted by an insulating member such as polyimide.

実施の形態１に係る圧接型半導体装置１００は、図２に示すように、３個の半導体チップ１１を含む。圧接型半導体装置１００に含まれる半導体チップ１１の数は、３個に限られない。半導体チップ１１の基材として、Ｓｉ、ＳｉＣ、ＧａＮ、Ｇａ２Ｏ３等の半導体材料が挙げられる。 As shown in FIG. 2, the pressure welding type semiconductor device 100 according to the first embodiment includes three semiconductor chips 11. The number of semiconductor chips 11 included in the pressure welding type semiconductor device 100 is not limited to three. Examples of the base material of the semiconductor chip 11 include semiconductor materials such as Si, SiC, GaN, and Ga 2 O 3.

中間電極１４は、半導体チップ１１の第２の電極１１２上に配置されている。中間電極１４は、半導体チップ１１と第２電極板１３との間に挟持され、半導体チップ１１の第２の電極１１２と第２電極板１３とを電気的に接続する。中間電極１４は、バネ状に伸縮する性質を持つ。中間電極１４は、例えば、バルク状金属の弾性を利用することもできるし、金属加工によりバネ構造を形成しておいてもよい。 The intermediate electrode 14 is arranged on the second electrode 112 of the semiconductor chip 11. The intermediate electrode 14 is sandwiched between the semiconductor chip 11 and the second electrode plate 13, and electrically connects the second electrode 112 and the second electrode plate 13 of the semiconductor chip 11. The intermediate electrode 14 has a property of expanding and contracting like a spring. For the intermediate electrode 14, for example, the elasticity of a bulk metal may be utilized, or a spring structure may be formed by metal processing.

フレーム１５は、個々の半導体チップ１１をそれぞれ取り囲むように設けられている。フレーム１５は、半導体チップ１１の位置決めを行う機能がある。フレーム１５は、電気的に絶縁性を有しており、例えば、セラミック、ＰＰＳ、ＰＥＥＫ、エポキシ、フッ素樹脂等の絶縁樹脂によって構成されている。 The frame 15 is provided so as to surround each of the semiconductor chips 11. The frame 15 has a function of positioning the semiconductor chip 11. The frame 15 is electrically insulating, and is made of, for example, an insulating resin such as ceramic, PPS, PEEK, epoxy, or fluororesin.

可撓性部材１６は、半導体チップ１１の外周部１１４を覆うように配置されている。可撓性部材１６は可撓性絶縁体からなる硬化物である。すなわち、可撓性部材１６は、シリコーン、エポキシ、ポリイミド、ポリアミド、フッ素樹脂、及びそれらの複合樹脂等の可撓性絶縁体によって構成されている。 The flexible member 16 is arranged so as to cover the outer peripheral portion 114 of the semiconductor chip 11. The flexible member 16 is a cured product made of a flexible insulator. That is, the flexible member 16 is composed of a flexible insulator such as silicone, epoxy, polyimide, polyamide, fluororesin, and a composite resin thereof.

カバー１７は、フレーム１５の内側面に設けられており、半導体チップ１１の外周部１１４の終端よりも内側に突出しており、可撓性部材１６と接する。なお、カバー１７は電気的に絶縁性を有しており、例えば、セラミック、ＰＰＳ、ＰＥＥＫ、エポキシ、フッ素樹脂等の絶縁樹脂によって構成されている。 The cover 17 is provided on the inner side surface of the frame 15, projects inward from the end of the outer peripheral portion 114 of the semiconductor chip 11, and comes into contact with the flexible member 16. The cover 17 has an electrically insulating property, and is made of, for example, an insulating resin such as ceramic, PPS, PEEK, epoxy, or fluororesin.

第１電極板１２及び第２電極板１３は、半導体チップ１１と、中間電極１４と、フレーム１５と、可撓性部材１６と、カバー１７とを挟持する。なお、第１電極板１２は、ベース板電極とも称し、第２電極板１３は、天板電極とも称される。 The first electrode plate 12 and the second electrode plate 13 sandwich the semiconductor chip 11, the intermediate electrode 14, the frame 15, the flexible member 16, and the cover 17. The first electrode plate 12 is also referred to as a base plate electrode, and the second electrode plate 13 is also referred to as a top plate electrode.

半導体チップ１１は、第１電極板１２の上に載置されている。第２電極板１３は、半導体チップ１１及び中間電極１４の上側に、第１電極版１２に対向するように配置されている。半導体チップ１１の裏面は、例えば、はんだを用いて、第１電極板１２の上に固着される。第１電極板１２は、半導体チップ１１の第１の電極１１１と電気的に接続される。 The semiconductor chip 11 is placed on the first electrode plate 12. The second electrode plate 13 is arranged on the upper side of the semiconductor chip 11 and the intermediate electrode 14 so as to face the first electrode plate 12. The back surface of the semiconductor chip 11 is fixed on the first electrode plate 12 by using, for example, solder. The first electrode plate 12 is electrically connected to the first electrode 111 of the semiconductor chip 11.

第１電極板１２及び第２電極板１３を通じて、圧接型半導体装置１００の外部から半導体チップ１１に電力が供給される。第１電極板１２及び第２電極板１３の材料の一例として、銅板が挙げられる。第１電極板１２及び第２電極板１３は、モジュールケース１８によって半導体チップ１１の方に圧接されながら、半導体チップ１１及び中間電極１４に電気的に接続される。 Electric power is supplied to the semiconductor chip 11 from the outside of the pressure-welding semiconductor device 100 through the first electrode plate 12 and the second electrode plate 13. An example of the material of the first electrode plate 12 and the second electrode plate 13 is a copper plate. The first electrode plate 12 and the second electrode plate 13 are electrically connected to the semiconductor chip 11 and the intermediate electrode 14 while being pressure-contacted toward the semiconductor chip 11 by the module case 18.

フレーム１５は、第１電極板１２及び第２電極板１３に狭持される。第１電極板１２及び第２電極板１３は、モジュールケース１８によって半導体チップ１１の方に圧接されるため、フレーム１５も圧接される。フレーム１５に設けられたカバー１７は、半導体チップ１１の外周部１１４の終端よりもさらに中間電極１４側に向かって設けられ、可撓性部材１６と接しているため、半導体チップ１１の外周部１１４を覆うように配置されている可撓性部材１６を圧接固定する。 The frame 15 is sandwiched between the first electrode plate 12 and the second electrode plate 13. Since the first electrode plate 12 and the second electrode plate 13 are pressure-welded toward the semiconductor chip 11 by the module case 18, the frame 15 is also pressure-welded. Since the cover 17 provided on the frame 15 is provided toward the intermediate electrode 14 side from the end of the outer peripheral portion 114 of the semiconductor chip 11 and is in contact with the flexible member 16, the outer peripheral portion 114 of the semiconductor chip 11 The flexible member 16 arranged so as to cover the above is pressure-welded and fixed.

モジュールケース１８は、フレーム１５を取り囲むように設けられ、第１電極板１２と接する部分と、第２電極板１３と接する部分とが、それぞれ接合されている。モジュールケース１８は、第１電極板１２及び第２電極板１３を半導体チップ１１の方に圧接する力を与える。 The module case 18 is provided so as to surround the frame 15, and a portion in contact with the first electrode plate 12 and a portion in contact with the second electrode plate 13 are joined to each other. The module case 18 applies a force for pressing the first electrode plate 12 and the second electrode plate 13 toward the semiconductor chip 11.

次に、実施の形態１に係る圧接型半導体装置１００の製造方法について説明する。 Next, a method of manufacturing the pressure-welding semiconductor device 100 according to the first embodiment will be described.

圧接型半導体装置１００は、半導体チップ１１の上方に中間電極１４を備え、半導体チップ１１と中間電極１４とを、第１電極板１２と第２電極板１３とで上下方向から挟持した構成となっている。また、フレーム１５も第１電極板１２と第２電極板１３とで上下方向から挟持されている。カバー１７は、フレーム１５に設けられており、半導体チップ１１の外周部１１４の終端よりもさらに中間電極１４側に向かって設けられ、可撓性部材１６と接する。さらに、モジュールケース１８が、フレーム１５を取り囲むように設けられている。 The pressure-welding semiconductor device 100 includes an intermediate electrode 14 above the semiconductor chip 11, and has a configuration in which the semiconductor chip 11 and the intermediate electrode 14 are sandwiched between the first electrode plate 12 and the second electrode plate 13 from the vertical direction. ing. Further, the frame 15 is also sandwiched between the first electrode plate 12 and the second electrode plate 13 from the vertical direction. The cover 17 is provided on the frame 15, is provided toward the intermediate electrode 14 side from the end of the outer peripheral portion 114 of the semiconductor chip 11, and is in contact with the flexible member 16. Further, the module case 18 is provided so as to surround the frame 15.

半導体チップ１１を第１電極板１２上に固着する工程では、半導体チップ１１は、はんだを用いて第１電極板１２の上に固着される。 In the step of fixing the semiconductor chip 11 on the first electrode plate 12, the semiconductor chip 11 is fixed on the first electrode plate 12 by using solder.

中間電極１４を第２電極板１３に固着する工程では、中間電極１４は、はんだを用いて第２電極板１３の上に固着される。 In the step of fixing the intermediate electrode 14 to the second electrode plate 13, the intermediate electrode 14 is fixed on the second electrode plate 13 by using solder.

第１電極板１２上に固着された半導体チップ１１を取り囲むようにフレーム１５が配置されて、フレーム１５を取り囲むようにモジュールケース１８が配置される。 The frame 15 is arranged so as to surround the semiconductor chip 11 fixed on the first electrode plate 12, and the module case 18 is arranged so as to surround the frame 15.

フレーム１５に設けられ、半導体チップ１１表面の外周部１１４の終端よりも内側に突出したカバー１７と外周部１１４との間に可撓性部材１６が配置される。 A flexible member 16 is arranged between the cover 17 provided on the frame 15 and projecting inward from the end of the outer peripheral portion 114 on the surface of the semiconductor chip 11 and the outer peripheral portion 114.

第１電極板１２上に固着された半導体チップ１１の第２の電極１１２の上に、中間電極１４が位置するようにモジュールケース１８の上に第２電極板１３が配置される。 The second electrode plate 13 is arranged on the module case 18 so that the intermediate electrode 14 is located on the second electrode 112 of the semiconductor chip 11 fixed on the first electrode plate 12.

図４は、実施の形態１に係る圧接型半導体装置の圧接方法を示す断面図である。実施の形態１に係る圧接型半導体装置１００は、圧接治具５０を用いて圧接を行っている。 FIG. 4 is a cross-sectional view showing a pressure welding method of the pressure welding type semiconductor device according to the first embodiment. The pressure welding type semiconductor device 100 according to the first embodiment performs pressure welding using a pressure welding jig 50.

圧接治具５０は、ロッド５１と、ナット５２と、第１の板５３と、第２の板５４とを含む。第１の板５３に設けられた孔と第２の板５４に設けられた孔とにロッド５１が通される。ロッド５１の両端は、ねじ山を有するボルト（図示せず）である。圧接治具５０は、第１電極板１２及び第２電極板１３を、半導体チップ１１の方に圧接する。具体的には、ロッド５１のボルトにナット５２を締め付けることによって、第１電極板１２及び第２電極板１３が半導体チップ１１の方に圧接される。かかる方法により、第１電極板１２及び第２電極板１３は、中間電極１４を介して半導体チップ１１に電気的に接続され、主回路を形成する。 The pressure welding jig 50 includes a rod 51, a nut 52, a first plate 53, and a second plate 54. The rod 51 is passed through a hole provided in the first plate 53 and a hole provided in the second plate 54. Both ends of the rod 51 are bolts (not shown) having threads. The pressure welding jig 50 presses the first electrode plate 12 and the second electrode plate 13 toward the semiconductor chip 11. Specifically, by tightening the nut 52 to the bolt of the rod 51, the first electrode plate 12 and the second electrode plate 13 are pressed against the semiconductor chip 11. By such a method, the first electrode plate 12 and the second electrode plate 13 are electrically connected to the semiconductor chip 11 via the intermediate electrode 14 to form a main circuit.

圧接治具５０は、緩衝部材５５をさらに含む構成でも良い。緩衝部材５５は、第１の板５３と第１電極板１２との間、及び、第２の板５４と第２電極板１３との間にそれぞれ配置される。緩衝部材５５によって、圧接型半導体装置１００は、均一な力で圧接される。 The pressure welding jig 50 may be configured to further include a cushioning member 55. The cushioning member 55 is arranged between the first plate 53 and the first electrode plate 12 and between the second plate 54 and the second electrode plate 13, respectively. The pressure-welding semiconductor device 100 is pressure-welded with a uniform force by the buffer member 55.

図４に示す圧接方法において、半導体チップ１１と中間電極１４が最初に接触することになる。中間電極１４は、バルク状金属または金属加工によりバネ構造に形成されているため、フレーム１５が第１電極板１２と第２電極板１３とによって挟持される距離に、縮むことができる。したがって、第１電極板１２及び第２電極板１３は、中間電極１４を介して半導体チップ１１と電気的に接続されるため、圧接治具５０を用いた圧接によって、圧接型半導体装置１００の主回路を形成することができる。 In the pressure welding method shown in FIG. 4, the semiconductor chip 11 and the intermediate electrode 14 come into contact with each other first. Since the intermediate electrode 14 is formed in a spring structure by bulk metal or metal processing, the frame 15 can be contracted to a distance sandwiched between the first electrode plate 12 and the second electrode plate 13. Therefore, since the first electrode plate 12 and the second electrode plate 13 are electrically connected to the semiconductor chip 11 via the intermediate electrode 14, the main part of the pressure welding type semiconductor device 100 is pressure welding using the pressure welding jig 50. A circuit can be formed.

カバー１７は、フレーム１５の内側面に設けられており、半導体チップ１１の外周部１１４の終端よりも内側に突出している。カバー１７は、圧接治具５０による圧接力によって、可撓性部材１６を圧接固定する。カバー１７が半導体チップ１１の外周部１１４に可撓性部材１６を圧接固定することで、半導体チップ１１の外周部１１４がフレーム１５と可撓性部材１６によって絶縁される。したがって、圧接治具５０を用いた圧接によって、圧接型半導体装置１００の主回路形成と、半導体チップ１１の絶縁保護を達成することができる。 The cover 17 is provided on the inner side surface of the frame 15 and projects inward from the end of the outer peripheral portion 114 of the semiconductor chip 11. The cover 17 presses and fixes the flexible member 16 by the pressure contact force of the pressure welding jig 50. The cover 17 presses and fixes the flexible member 16 to the outer peripheral portion 114 of the semiconductor chip 11, so that the outer peripheral portion 114 of the semiconductor chip 11 is insulated from the frame 15 by the flexible member 16. Therefore, by pressure welding using the pressure welding jig 50, it is possible to achieve the formation of the main circuit of the pressure welding type semiconductor device 100 and the insulation protection of the semiconductor chip 11.

圧接治具５０を用いた圧接によって、第１電極板１２とモジュールケース１８、第２電極板１３とモジュールケース１８はそれぞれ圧接される。モジュールケース１８は、圧接型半導体装置１００内部の気密性を保持するためにセラミックによって構成される場合が多く、モジュールケース１８と第１電極板１２と接する部分と、モジュールケース１８と第２電極板１３と接する部分とは、それぞれセラミックのメタライズと溶接によって圧接される場合が多いが、実施の形態１に係る圧接型半導体装置１００では、モジュールケース１８と第１電極板１２、モジュールケース１８と第２電極板１３の圧接方法は特に限定されるわけではなく、公知の接合方法が適用可能である。 By pressure welding using the pressure welding jig 50, the first electrode plate 12 and the module case 18 and the second electrode plate 13 and the module case 18 are pressure-welded, respectively. The module case 18 is often made of ceramic in order to maintain the airtightness inside the pressure welding type semiconductor device 100, and the portion in contact between the module case 18 and the first electrode plate 12 and the module case 18 and the second electrode plate The portions in contact with 13 are often pressure-welded by metallization and welding of ceramics, respectively, but in the pressure-welding semiconductor device 100 according to the first embodiment, the module case 18 and the first electrode plate 12, the module case 18 and the first The pressure welding method of the two electrode plates 13 is not particularly limited, and a known bonding method can be applied.

圧接治具５０を用いた圧接によって、モジュールケース１８と第１電極板１２と、モジュールケース１８と第２電極板１３とがそれぞれ圧接されると、モジュールケース１８は、第１電極板１２及び第２電極板１３を半導体チップ１１の方に圧接する力を与えるため、圧接治具５０を取り外しても圧接型半導体装置１００の主回路形成及び半導体チップ１１の絶縁保護は達成される。 When the module case 18 and the first electrode plate 12 and the module case 18 and the second electrode plate 13 are pressure-welded by pressure welding using the pressure welding jig 50, the module case 18 becomes the first electrode plate 12 and the first electrode plate 12. Since the force for pressing the two electrode plates 13 toward the semiconductor chip 11 is applied, the main circuit formation of the pressure welding type semiconductor device 100 and the insulation protection of the semiconductor chip 11 can be achieved even if the pressure welding jig 50 is removed.

図５は、実施の形態１に係る圧接型半導体装置１００の圧接前の半導体チップ１１と可撓性部材１６とカバー１７との組立パターンを示す図である。 FIG. 5 is a diagram showing an assembly pattern of the semiconductor chip 11 before pressure welding, the flexible member 16 and the cover 17 of the pressure welding type semiconductor device 100 according to the first embodiment.

図５（ａ）においては、可撓性部材１６は半導体チップ１１の外周部１１４上に載置されている。図５（ｂ）においては、可撓性部材１６はフレーム１５のカバー１７下面に対して、はめ込まれるようにして予め固定されている。 In FIG. 5A, the flexible member 16 is placed on the outer peripheral portion 114 of the semiconductor chip 11. In FIG. 5B, the flexible member 16 is preliminarily fixed to the lower surface of the cover 17 of the frame 15 so as to be fitted.

図５に示すいずれの組立パターンにおいても、接着剤等による可撓性部材１６とフレーム１５との接合プロセスを必要とせずに、圧接型半導体装置１００を構成するための圧接を行うことで、可撓性部材１６を半導体チップ１１とカバー１７との間で固定することができる。つまり、接着剤等によるフレーム１５の接合プロセスを必要としないため、簡易的なプロセスによって半導体チップ１１の外周部１１４の絶縁保護を行うことができる。 In any of the assembly patterns shown in FIG. 5, it is possible to perform pressure welding to form the pressure welding type semiconductor device 100 without requiring a joining process between the flexible member 16 and the frame 15 by an adhesive or the like. The flexible member 16 can be fixed between the semiconductor chip 11 and the cover 17. That is, since the process of joining the frame 15 with an adhesive or the like is not required, the insulation protection of the outer peripheral portion 114 of the semiconductor chip 11 can be performed by a simple process.

実施の形態１に係る圧接型半導体装置１００の製造方法では、圧接治具５０を用いた第１電極板１２及び第２電極板１３への圧接によって、半導体チップ１１と、第１電極板１２と、第２電極板１３と、中間電極１４とが、電気的に接続され、半導体チップ１１の外周部１１４がフレーム１５と可撓性部材１６によって絶縁される。 In the method for manufacturing the pressure welding type semiconductor device 100 according to the first embodiment, the semiconductor chip 11 and the first electrode plate 12 are formed by pressure welding to the first electrode plate 12 and the second electrode plate 13 using the pressure welding jig 50. The second electrode plate 13 and the intermediate electrode 14 are electrically connected, and the outer peripheral portion 114 of the semiconductor chip 11 is insulated by the frame 15 and the flexible member 16.

実施の形態１に係る圧接型半導体装置１００の製造方法によって、圧接型半導体装置１００の主回路形成と同時に、半導体チップ１１の絶縁保護を達成することができる。また、接着剤等によるフレーム１５の接合プロセスを必要としないため、簡易的なプロセスによって半導体チップ１１の外周部１１４の絶縁保護を行うことができる。 According to the method for manufacturing the pressure-welded semiconductor device 100 according to the first embodiment, it is possible to achieve the insulation protection of the semiconductor chip 11 at the same time as forming the main circuit of the pressure-welding semiconductor device 100. Further, since the frame 15 joining process with an adhesive or the like is not required, the insulation protection of the outer peripheral portion 114 of the semiconductor chip 11 can be performed by a simple process.

実施の形態１に係る圧接型半導体装置１００の効果を以下に説明する。 The effects of the pressure-welding semiconductor device 100 according to the first embodiment will be described below.

圧接型半導体装置１００は、半導体チップ１１と、第１電極板１２と、第２電極板１３と、中間電極１４と、フレーム１５と、可撓性部材１６と、カバー１７を含む。可撓性部材１６は、半導体チップ１１の外周部１１４を覆うように配置されている。カバー１７は、フレーム１５に設けられており、半導体チップ１１の外周部１１４の終端よりも内側に突出しており、可撓性部材１６と接する。フレーム１５は、第１電極板１２及び第２電極板１３に狭持される。接型半導体装置１００は、モジュールケース１８による、第１電極板１２及び第２電極板１３の半導体チップ１１の方への圧接によって、半導体チップ１１、第１電極板１２、第２電極板１３及び中間電極１４が電気的に接続され、主回路を形成する。第１電極板１２及び第２電極板１３は、モジュールケース１８によって半導体チップ１１の方に圧接されるため、フレーム１５も圧接される。フレーム１５に設けられたカバー１７は、半導体チップ１１の外周部１１４の終端よりも内側に突出し、可撓性部材１６と接しているため、半導体チップ１１の外周部１１４を覆うように配置されている可撓性部材１６を圧接する。カバー１７が可撓性部材１６を圧接することによって、半導体チップ１１の外周部１１４に可撓性部材１６が圧接固定されるため、半導体チップ１１の外周部１１４がフレーム１５と可撓性部材１６によって絶縁される。 The pressure welding type semiconductor device 100 includes a semiconductor chip 11, a first electrode plate 12, a second electrode plate 13, an intermediate electrode 14, a frame 15, a flexible member 16, and a cover 17. The flexible member 16 is arranged so as to cover the outer peripheral portion 114 of the semiconductor chip 11. The cover 17 is provided on the frame 15, projects inward from the end of the outer peripheral portion 114 of the semiconductor chip 11, and comes into contact with the flexible member 16. The frame 15 is sandwiched between the first electrode plate 12 and the second electrode plate 13. In the tangent semiconductor device 100, the semiconductor chip 11, the first electrode plate 12, the second electrode plate 13, and the second electrode plate 13 are formed by pressure welding of the first electrode plate 12 and the second electrode plate 13 toward the semiconductor chip 11 by the module case 18. The intermediate electrodes 14 are electrically connected to form a main circuit. Since the first electrode plate 12 and the second electrode plate 13 are pressure-welded toward the semiconductor chip 11 by the module case 18, the frame 15 is also pressure-welded. Since the cover 17 provided on the frame 15 projects inward from the end of the outer peripheral portion 114 of the semiconductor chip 11 and is in contact with the flexible member 16, it is arranged so as to cover the outer peripheral portion 114 of the semiconductor chip 11. The flexible member 16 is press-welded. When the cover 17 presses against the flexible member 16, the flexible member 16 is pressed and fixed to the outer peripheral portion 114 of the semiconductor chip 11, so that the outer peripheral portion 114 of the semiconductor chip 11 is pressed against the frame 15 and the flexible member 16. Insulated by.

したがって、実施の形態１に係る圧接型半導体装置１００では、圧接型半導体装置１００の主回路形成と同時に、半導体チップ１１の絶縁保護を達成することができる。また、フレーム１５に設けられたカバー１７によって、可撓性部材１６が加圧され、半導体チップ１１の外周部１１４が絶縁保護されている。さらに、可撓性部材１６は、フレーム１５に設けられたカバー１７によって加圧されているため、熱応力による可撓性部材１６の外周部１１４からの剥離を防止でき、半導体チップ１１の外周部１１４の長期的絶縁信頼性が達成される。加えて、接着剤等によるフレーム１５の接合プロセスを必要としないため、簡易的なプロセスによって半導体チップ１１の外周部１１４の絶縁保護を行うことができる。 Therefore, in the pressure-welding semiconductor device 100 according to the first embodiment, the insulation protection of the semiconductor chip 11 can be achieved at the same time as the formation of the main circuit of the pressure-welding semiconductor device 100. Further, the flexible member 16 is pressurized by the cover 17 provided on the frame 15, and the outer peripheral portion 114 of the semiconductor chip 11 is insulated and protected. Further, since the flexible member 16 is pressurized by the cover 17 provided on the frame 15, it is possible to prevent the flexible member 16 from peeling from the outer peripheral portion 114 due to thermal stress, and the outer peripheral portion of the semiconductor chip 11 can be prevented from peeling off. A long-term insulation reliability of 114 is achieved. In addition, since the frame 15 joining process with an adhesive or the like is not required, the insulation protection of the outer peripheral portion 114 of the semiconductor chip 11 can be performed by a simple process.

実施の形態２．
本発明の実施の形態２に係る圧接型半導体装置２００の構成について説明する。なお、実施の形態１と同一または対応する構成については、その説明を省略し、構成の異なる部分のみを説明する。 Embodiment 2.
The configuration of the pressure welding type semiconductor device 200 according to the second embodiment of the present invention will be described. The same or corresponding configurations as those in the first embodiment will be omitted, and only the parts having different configurations will be described.

図６は、実施の形態２に係る圧接型半導体装置２００の断面図である。実施の形態２に係る圧接型半導体装置２００は、圧接型半導体装置２００のカバー１７の一部が、第２電極板１３と接する構成とするものである。 FIG. 6 is a cross-sectional view of the pressure welding type semiconductor device 200 according to the second embodiment. The pressure-welding semiconductor device 200 according to the second embodiment has a configuration in which a part of the cover 17 of the pressure-welding semiconductor device 200 is in contact with the second electrode plate 13.

実施の形態２に係る圧接型半導体装置２００では、フレーム１５に設けられたカバー１７の一部が、第２電極板１３と接するため、第２電極板１３とフレーム１５との接触面積が増加することによって、より安定したフレーム１５の保持が可能となる。 In the pressure contact type semiconductor device 200 according to the second embodiment, since a part of the cover 17 provided on the frame 15 comes into contact with the second electrode plate 13, the contact area between the second electrode plate 13 and the frame 15 increases. This makes it possible to hold the frame 15 more stably.

実施の形態３．
本発明の実施の形態３に係る圧接型半導体装置３００の構成について説明する。なお、実施の形態１、２と同一または対応する構成については、その説明を省略し、構成の異なる部分のみを説明する。 Embodiment 3.
The configuration of the pressure welding type semiconductor device 300 according to the third embodiment of the present invention will be described. The same or corresponding configurations as those of the first and second embodiments will be omitted, and only the parts having different configurations will be described.

図７は、実施の形態３に係る圧接型半導体装置３００の断面図である。実施の形態３に係る圧接型半導体装置３００は、フレーム１５が締結部材２１によって第１電極板１２に固定されている構成である。締結部材２１として、例えば、固定ねじ、ボルト等が挙げられる。 FIG. 7 is a cross-sectional view of the pressure welding type semiconductor device 300 according to the third embodiment. The pressure-welding semiconductor device 300 according to the third embodiment has a configuration in which the frame 15 is fixed to the first electrode plate 12 by the fastening member 21. Examples of the fastening member 21 include fixing screws and bolts.

実施の形態３に係る圧接型半導体装置３００では、締結部材２１によって第１電極板１２にフレーム１５が固定されているため、半導体チップ１１に対するフレーム１５のずれを抑制することができる結果、圧接アセンブリ工程を容易に行うことができる。また、可撓性部材１６に加えられる圧力は、第１電極板１２にフレーム１５を締結部材２１によって固定させる際の圧力を利用することができるため、主回路の圧接力とは独立して、可撓性部材１６に加える圧力の設計が可能となる。 In the pressure welding type semiconductor device 300 according to the third embodiment, since the frame 15 is fixed to the first electrode plate 12 by the fastening member 21, the displacement of the frame 15 with respect to the semiconductor chip 11 can be suppressed, and as a result, the pressure welding assembly The process can be easily performed. Further, as the pressure applied to the flexible member 16, the pressure when the frame 15 is fixed to the first electrode plate 12 by the fastening member 21 can be used, so that the pressure is independent of the pressure contact force of the main circuit. It is possible to design the pressure applied to the flexible member 16.

実施の形態４．
本発明の実施の形態４に係る圧接型半導体装置４００の構成について説明する。なお、実施の形態１、２、３と同一または対応する構成については、その説明を省略し、構成の異なる部分のみを説明する。 Embodiment 4.
The configuration of the pressure-welding semiconductor device 400 according to the fourth embodiment of the present invention will be described. The same or corresponding configurations as those of the first, second, and third embodiments will be omitted, and only the parts having different configurations will be described.

図８は、実施の形態４に係る圧接型半導体装置４００の断面図である。実施の形態４に係る圧接型半導体装置４００は、フレーム１５が締結部材２１によって第２電極板１３に固定されている構成である。締結部材２１として、例えば、固定ねじ、ボルト等が挙げられる。 FIG. 8 is a cross-sectional view of the pressure welding type semiconductor device 400 according to the fourth embodiment. The pressure-welding semiconductor device 400 according to the fourth embodiment has a configuration in which the frame 15 is fixed to the second electrode plate 13 by the fastening member 21. Examples of the fastening member 21 include fixing screws and bolts.

実施の形態４に係る圧接型半導体装置４００では、締結部材２１によって第２電極板１３にフレーム１５が固定されているため、半導体チップ１１に対するフレーム１５のずれを抑制することができる結果、圧接アセンブリ工程を容易に行うことができる。 In the pressure welding type semiconductor device 400 according to the fourth embodiment, since the frame 15 is fixed to the second electrode plate 13 by the fastening member 21, the displacement of the frame 15 with respect to the semiconductor chip 11 can be suppressed, and as a result, the pressure welding assembly The process can be easily performed.

実施の形態５．
本発明の実施の形態５に係る圧接型半導体装置５００の構成について説明する。なお、実施の形態１、２、３、４と同一または対応する構成については、その説明を省略し、構成の異なる部分のみを説明する。 Embodiment 5.
The configuration of the pressure welding type semiconductor device 500 according to the fifth embodiment of the present invention will be described. The same or corresponding configurations as those of the first, second, third, and fourth embodiments will be omitted, and only the parts having different configurations will be described.

図９は、実施の形態５に係る圧接型半導体装置５００の断面図である。実施の形態５に係る圧接型半導体装置５００は、フレーム１５とモジュールケース１８とが嵌合部３１を介して嵌合されている構成である。 FIG. 9 is a cross-sectional view of the pressure welding type semiconductor device 500 according to the fifth embodiment. The pressure welding type semiconductor device 500 according to the fifth embodiment has a configuration in which a frame 15 and a module case 18 are fitted via a fitting portion 31.

実施の形態５に係る圧接型半導体装置５００では、モジュールケース１８が、第１電極板１２及び第２電極板１３とそれぞれ接合されているのに加えて、さらに、嵌合部３１を介してフレーム１５とモジュールケース１８とが嵌合されているため、フレーム１５をより一層安定して固定することが可能である。 In the pressure welding type semiconductor device 500 according to the fifth embodiment, in addition to the module case 18 being joined to the first electrode plate 12 and the second electrode plate 13, respectively, the module case 18 is further joined to the frame via the fitting portion 31. Since the 15 and the module case 18 are fitted together, the frame 15 can be fixed more stably.

実施の形態６．
本発明の実施の形態６に係る圧接型半導体装置６００の構成について説明する。なお、実施の形態１、２、３、４、５と同一または対応する構成については、その説明を省略し、構成の異なる部分のみを説明する。 Embodiment 6.
The configuration of the pressure welding type semiconductor device 600 according to the sixth embodiment of the present invention will be described. The same or corresponding configurations as those of the first, second, third, fourth, and fifth embodiments will be omitted, and only the parts having different configurations will be described.

図１０は、実施の形態６に係る圧接型半導体装置６００の断面図である。実施の形態６に係る圧接型半導体装置６００は、フレーム１５がゲート信号を入力するためのゲート配線機構４１を備えた構成である。ゲート配線機構４１は、半導体チップ１１と電気的に接続するための、ばね接触子４２を有している。なお、ばね接触子４２は、弾性機能を備えており、例えば、板バネ、皿ばね、コイルばね等の形状が挙げられる。 FIG. 10 is a cross-sectional view of the pressure welding type semiconductor device 600 according to the sixth embodiment. The pressure welding type semiconductor device 600 according to the sixth embodiment has a configuration in which the frame 15 includes a gate wiring mechanism 41 for inputting a gate signal. The gate wiring mechanism 41 has a spring contactor 42 for electrically connecting to the semiconductor chip 11. The spring contactor 42 has an elastic function, and examples thereof include a leaf spring, a disc spring, and a coil spring.

圧接型半導体装置６００の圧接アセンブリ工程によって、中間電極１４と半導体チップ１１間で圧接型半導体装置６００の主回路が形成される他に、ばね接触子４２が半導体チップ１１上のゲートパッドに電気的に接続されて制御回路が形成される。 By the pressure welding assembly step of the pressure welding type semiconductor device 600, the main circuit of the pressure welding type semiconductor device 600 is formed between the intermediate electrode 14 and the semiconductor chip 11, and the spring contactor 42 is electrically attached to the gate pad on the semiconductor chip 11. A control circuit is formed by being connected to.

実施の形態６に係る圧接型半導体装置６００では、フレーム１５がゲート信号を入力するためのゲート配線機構４１を備えるため、圧接型半導体装置６００の圧接アセンブリ工程によって主回路形成、制御回路形成、絶縁信頼性を同時に達成することができる。 In the pressure welding type semiconductor device 600 according to the sixth embodiment, since the frame 15 includes a gate wiring mechanism 41 for inputting a gate signal, main circuit formation, control circuit formation, and insulation are performed by the pressure welding assembly step of the pressure welding type semiconductor device 600. Reliability can be achieved at the same time.

本発明は、実施の形態１から６で説明した形状に限定されるものでなく、発明の範囲内において、各実施の形態を自由に組み合わせることや、各実施の形態を適宜、変形、省略することが可能である。 The present invention is not limited to the shapes described in the first to sixth embodiments, and within the scope of the invention, each embodiment can be freely combined, and each embodiment may be appropriately modified or omitted. It is possible.

１００，２００，３００，４００，５００，６００ 圧接型半導体装置
１１ 半導体チップ、１２ 第１電極板、１３ 第２電極板、１４ 中間電極
１５ フレーム、１６ 可撓性部材、１７ カバー、１８ モジュールケース
２１ 締結部材
３１ 嵌合部
４１ ゲート配線機構、４２ ばね接触子
５０ 圧接治具、５１ ロッド、５２ ナット、５３ 第１の板、５４ 第２の板
５５ 緩衝部材
１１０ 半導体基板、１１１ 第１の電極、１１２ 第２の電極、１１３ 表面保護部材１１４ 外周部 100,200,300,400,500,600 Pressure welding type semiconductor device 11 Semiconductor chip, 12 1st electrode plate, 13 2nd electrode plate, 14 Intermediate electrode 15 frame, 16 Flexible member, 17 Cover, 18 Module case 21 Fastening member 31 Fitting part 41 Gate wiring mechanism, 42 Spring contactor 50 Pressure welding jig, 51 Rod, 52 Nut, 53 First plate, 54 Second plate 55 Cushioning member 110 Semiconductor substrate, 111 First electrode, 112 Second electrode, 113 Surface protection member 114 Outer circumference

Claims (9)

第１電極板と、
前記第１電極板に裏面が固着された半導体チップと、
前記第１電極板と対向する第２電極板と、
前記半導体チップ表面の周辺に沿って設けられた外周部を覆う可撓性部材と、
前記第１電極板と前記第２電極板との間に配置され、前記半導体チップを取り囲むように設けられるフレームと、
前記フレームを取り囲むように配置され、一端で前記第１電極板と、他端で前記第２電極板とそれぞれ接合されるモジュールケースと、を備え、
前記フレームは、内側面に設けられ、前記外周部の終端よりも内側に突出することにより、前記可撓性部材を前記外周部へと圧接固定するカバーと、
をさらに備える圧接型半導体装置。 With the first electrode plate
A semiconductor chip whose back surface is fixed to the first electrode plate and
A second electrode plate facing the first electrode plate and
A flexible member that covers the outer peripheral portion provided along the periphery of the surface of the semiconductor chip, and
A frame arranged between the first electrode plate and the second electrode plate and provided so as to surround the semiconductor chip,
A module case that is arranged so as to surround the frame and is joined to the first electrode plate at one end and the second electrode plate at the other end is provided.
The frame is provided on the inner side surface, and by projecting inward from the end of the outer peripheral portion, the flexible member is pressure-welded and fixed to the outer peripheral portion.
A pressure welding type semiconductor device further equipped with. 前記半導体チップと前記第２電極板との間に挟持され、前記半導体チップと前記第２電極板とを電気的に接続する中間電極をさらに備える請求項１に記載の圧接型半導体装置。 The pressure-welded semiconductor device according to claim 1, further comprising an intermediate electrode sandwiched between the semiconductor chip and the second electrode plate and electrically connecting the semiconductor chip and the second electrode plate. 前記半導体チップは、複数設けられ、前記フレームによってそれぞれ取り囲まれる請求項１または請求項２に記載の圧接型半導体装置。 The pressure-welding semiconductor device according to claim 1 or 2, wherein a plurality of the semiconductor chips are provided and surrounded by the frame, respectively. 前記フレームは、前記第１電極板及び前記第２電極板の間に挟持される請求項１から請求項３のいずれか１項に記載の圧接型半導体装置。 The pressure-welding semiconductor device according to any one of claims 1 to 3, wherein the frame is sandwiched between the first electrode plate and the second electrode plate. 前記カバーは、前記第２電極板に接する部位を有する請求項１から請求項４のいずれか１項に記載の圧接型半導体装置。 The pressure-welding semiconductor device according to any one of claims 1 to 4, wherein the cover has a portion in contact with the second electrode plate. 前記フレームは、前記第１電極板あるいは前記第２電極板のいずれか一方と締結部材によって固定される請求項１から請求項５のいずれか１項に記載の圧接型半導体装置。 The pressure-welding semiconductor device according to any one of claims 1 to 5, wherein the frame is fixed to either one of the first electrode plate or the second electrode plate by a fastening member. 前記フレームは、前記モジュールケースと嵌合部を介して嵌合されている請求項１から請求項６のいずれか１項に記載の圧接型半導体装置。 The pressure-welding semiconductor device according to any one of claims 1 to 6, wherein the frame is fitted to the module case via a fitting portion. 前記フレームは、ゲート信号を入力するためのゲート配線機構をさらに備え、
前記ゲート配線機構は、前記半導体チップと導通する可撓性体接触子を有する請求項１から請求項７のいずれか１項に記載の圧接型半導体装置。 The frame further comprises a gate wiring mechanism for inputting a gate signal.
The pressure-welding semiconductor device according to any one of claims 1 to 7, wherein the gate wiring mechanism has a flexible body contactor that conducts with the semiconductor chip. 半導体チップを第１電極板上に固着する工程と、
中間電極を第２電極板に固着する工程と、
前記第１電極板上で前記半導体チップを取り囲むようにフレームを配置する工程と、
前記フレームを取り囲むようにモジュールケースを配置する工程と、
前記フレームに設けられ、前記半導体チップ表面の外周部の終端よりも内側に突出したカバーと前記外周部との間に可撓性部材を配置する工程と、
前記中間電極が前記半導体チップ上に位置するように、前記モジュールケース上に前記第２電極板を配置する工程と、
前記第１電極板と、前記第２電極板と、前記モジュールケースとを圧接治具によって圧接することにより、前記第１電極板、前記第２電極板、前記中間電極及び前記半導体チップとを電気的に接続するとともに、前記カバーによる前記外周部への前記可撓性部材の圧接固定と、を行う工程と、
を備える圧接型半導体装置の製造方法。 The process of fixing the semiconductor chip on the first electrode plate and
The process of fixing the intermediate electrode to the second electrode plate and
A step of arranging a frame on the first electrode plate so as to surround the semiconductor chip, and
The process of arranging the module case so as to surround the frame and
A step of arranging a flexible member between a cover provided on the frame and projecting inward from the end of the outer peripheral portion of the surface of the semiconductor chip and the outer peripheral portion.
A step of arranging the second electrode plate on the module case so that the intermediate electrode is located on the semiconductor chip, and
By pressure-welding the first electrode plate, the second electrode plate, and the module case with a pressure welding jig, the first electrode plate, the second electrode plate, the intermediate electrode, and the semiconductor chip are electrically connected. A step of performing pressure welding and fixing of the flexible member to the outer peripheral portion by the cover while connecting the flexible members.
A method for manufacturing a pressure-welded semiconductor device.
JP2017237678A 2017-12-12 2017-12-12 Pressure-welded type semiconductor device and method of manufacturing pressure-welded type semiconductor device Pending JP2021028921A (en)

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