JP2021027418A - Bidirectional level shift circuit - Google Patents

Abstract

To provide a bidirectional level shift circuit capable of increasing output signal responsiveness against a high frequency input signal.SOLUTION: A second one-shot circuit (3B) generates a one-shot pulse of a second driving signal (PGTB) having an on level for a predetermined second time width based on rise of a signal at a first signal terminal (Tda), and generates the second driving signal having an off level based on fall of the signal at the first signal terminal. A first one-shot circuit (3A) includes a first CR circuit, a one-shot pulse generating unit (33A) for generating a one-shot pulse of a first driving signal (PGTA) having an on level for a predetermined first time width according to the time constant of the first CR circuit based on rise of a second signal terminal (Tdb), and a fall detection unit (35A) for detecting fall of the signal at the first signal terminal and changing the time constant of the first CR circuit based on the detection result.SELECTED DRAWING: Figure 8

Description

The present invention relates to a bidirectional level shift circuit.

Conventionally, when there are systems operating at different power supply voltages, a bidirectional level shift circuit is used to transmit signals in both directions between the systems. An example of a bidirectional level shift circuit is disclosed in Patent Document 1.

Japanese Unexamined Patent Publication No. 2012-147173

Here, the bidirectional level shift circuit is required to improve the responsiveness of the output signal when a high frequency input signal is input.

In view of the above circumstances, it is an object of the present invention to provide a bidirectional level shift circuit capable of enhancing the responsiveness of an output signal to a high frequency input signal.

The bidirectional level shift circuit according to one aspect of the present invention in order to achieve the above object is
1st signal terminal and
2nd signal terminal and
The first power supply terminal to which the first power supply voltage is applied and
The second power supply terminal to which the second power supply voltage is applied and
A first pull-up resistor connected between the first power supply terminal and the first signal terminal,
A second pull-up resistor connected between the second power supply terminal and the second signal terminal,
A first transistor connected between both ends of the first pull-up resistor and
A second transistor connected between both ends of the second pull-up resistor and
A third transistor arranged between the first signal terminal and the second signal terminal,
The drive circuit that drives the control end of the third transistor and
A first one-shot circuit that generates a first drive signal that drives the control end of the first transistor, and
A second one-shot circuit that generates a second drive signal that drives the control end of the second transistor, and
With
The second one-shot circuit generates a one-shot pulse of the second drive signal which is turned on level by a predetermined second time width based on the rising edge of the signal of the first signal terminal, and generates a signal of the first signal terminal. Generates the off-level second drive signal based on the falling edge of
The first one-shot circuit is
A one-shot pulse of the first drive signal including the first CR circuit is generated based on the rising edge of the signal of the second signal terminal and turned on level by a predetermined first time width according to the time constant of the first CR circuit. One-shot pulse generator and
The configuration includes a falling edge detection unit that detects the falling edge of the signal of the first signal terminal and changes the time constant of the first CR circuit to a small value based on the detection result (first configuration).

Further, in the first configuration, the falling detection unit is a first inverter having a CMOS configuration consisting of a p-channel MOSFET and an n-channel MOSFET, and the p-channel MOSFET has a threshold value of Vgs as compared with the n-channel MOSFET. It may be lowered (second configuration).

Further, in the first configuration, the fall detection unit may be a comparator that compares the signal of the first signal terminal with the reference voltage (third configuration).

Further, in any of the first to third configurations, the first one-shot circuit masks the detection result of the falling detection unit for a predetermined period when the signal of the second signal terminal rises. It may further have a mask generation unit for generating a mask signal (fourth configuration).

Further, in the fourth configuration, the mask generation unit may have a second CR circuit that determines the predetermined period by a time constant (fifth configuration).

Further, in the fifth configuration, the mask generation unit is
A NAND circuit having one input end to which the second signal terminal is electrically connected and the other input end to which the output end of the second CR circuit is connected.
A second inverter having an input terminal to which the second signal terminal is electrically connected and an output end connected to the input terminal of the second CR circuit may be further provided (sixth configuration). ).

Further, in any one of the first to sixth configurations, the one-shot pulse generator has a switch connected between both ends of the resistor included in the first CR circuit, and the switch is the falling edge. On / off may be controlled according to the detection result of the detection unit (seventh configuration).

Further, in the seventh configuration, the one-shot pulse generation unit is
An AND circuit having one input terminal to which the second signal terminal is electrically connected and the other input terminal connected to the output terminal of the first CR circuit.
A third inverter having an input end to which the second signal terminal is electrically connected and an output end connected to the input end of the first CR circuit.
A fourth inverter having an input end connected to the output end of the AND circuit may be further provided (eighth configuration).

Further, in any of the first to eighth configurations, the second power supply voltage is higher than the first power supply voltage, and the first one-shot circuit is supplied with the first power supply voltage as a power supply. The first one-shot circuit further provides a level shift unit for level-shifting the signal of the second signal terminal from the second power supply voltage to the first power supply voltage on the front stage side of the one-shot pulse generation unit. It may have (9th configuration).

Further, in the ninth configuration, the first one-shot circuit may further have a Schmitt trigger arranged between the level shift unit and the one-shot pulse generation unit (tenth configuration). ..

Further, in any of the first to tenth configurations, in the chip, the plurality of resistors included in the first CR circuit may be arranged adjacent to each other to form a first group (11th). Configuration).

Further, in the fifth or sixth configuration, in the chip, the first capacitor included in the first CR circuit and the second capacitor included in the second CR circuit are arranged adjacent to each other to form a second group. It may be done (12th configuration).

Further, another aspect of the present invention operates with the bidirectional level shift circuit having any of the first to twelfth configurations, the first system operated by the first power supply voltage, and the second power supply voltage. A data communication system including a second system.

According to the bidirectional level shift circuit of the present invention, the responsiveness of the output signal to the high frequency input signal can be enhanced.

It is a figure which shows one configuration example of a data communication system. It is a circuit diagram which shows one configuration example of a bidirectional level shift circuit. It is a circuit diagram which shows one configuration example of a gate drive circuit. It is a circuit diagram which shows the 1st connection mode to the signal terminal of the bidirectional level shift circuit shown in FIG. It is a timing chart which shows an example of the behavior of various signals in the case shown in FIG. It is a circuit diagram which shows the 2nd connection mode to the signal terminal of the bidirectional level shift circuit shown in FIG. It is a timing chart which shows an example of the behavior of various signals in the case shown in FIG. It is a circuit diagram which shows the bidirectional level shift circuit which concerns on the exemplary embodiment of this invention, and the 2nd connection mode to the signal terminal. It is a timing chart which shows an example of the behavior of various signals in the case shown in FIG. It is a circuit diagram which shows one configuration example of the 1st one-shot circuit. It is a circuit diagram which shows one configuration example of the 2nd one-shot circuit. It is a figure which shows one configuration example of the inverter as a fall detection part. It is a timing chart including the operation of the one-shot circuit in the case shown in FIG. It is a circuit diagram which shows the modification of the 1st one-shot circuit. It is a circuit diagram which shows the modification of the 2nd one-shot circuit. It is a schematic diagram which shows an example of the layout in the chip of the bidirectional level shift circuit. It is a block diagram which shows the application example of the data communication system shown in FIG.

An exemplary embodiment of the present invention will be described below with reference to the drawings.

<1. System configuration>
FIG. 1 is a diagram showing a configuration example of a data communication system that performs data communication between systems operating at different power supply voltages. The data communication system shown in FIG. 1 includes system controllers 20A and 20B that operate at different power supply voltages, and a bidirectional level shift circuit 1.

The system controller 20A operates by the power supply voltage VCSA. The system controller 20B operates by the power supply voltage VCSB. The magnitude relationship between the power supply voltage VCSB and VCSA is VCSB> VCSA. For example, VCSA = 1.8V and VCSB = 3.3V.

The bidirectional level shift circuit 1 is a circuit that performs bidirectional signal transmission between the system controllers 20A and 20B, and is configured as a semiconductor IC. The bidirectional level shift circuit 1 has power supply terminals Tva and Tvb and signal terminals Tda and Tdb.

A power supply voltage VCSA is applied to the power supply terminal Tva, and a power supply voltage VCSB is applied to the power supply terminal Tvb.

When data is transmitted from the system controller 20A to 20B, the input signal as data is input to the signal terminal Tda, and the output signal as data is output from the signal terminal Tdb. In this case, the input signal is level-shifted from VCSA to VCSB to become an output signal.

On the other hand, when data is transmitted from the system controller 20B to 20A, the input signal as data is input to the signal terminal Tdb, and the output signal as data is output from the signal terminal Tda. In this case, the input signal is level-shifted from VCSB to VCSA to become an output signal.

<2. Bidirectional level shift circuit configuration>
FIG. 2 is a circuit diagram showing a configuration example of the bidirectional level shift circuit 1 (FIG. 1). The bidirectional level shift circuit 1 shown in FIG. 2 is a basic configuration according to an embodiment of the present invention, which will be described later.

As shown in FIG. 2, the bidirectional level shift circuit 1 includes a transistor N1 composed of an n-channel MOSFET, a gate drive circuit 2, one-shot circuits 3A and 3B, and a transistor PA composed of a p-channel MOSFET. It has a PB and resistors RA and RB.

The transistor N1 is arranged between the signal terminals Tda and Tdb. The first end of the transistor N1 other than the gate is connected to the signal terminal Tda. The second end of the transistor N1 other than the gate is connected to the signal terminal Tdb.

The gate drive circuit 2 generates a gate signal NGT to drive the gate of the transistor N1. A power supply voltage VCCA is applied to the gate drive circuit 2. Details of the configuration of the gate drive circuit 2 will be described later.

The resistor RA is connected between the power supply terminal Tva to which the power supply voltage VCSA is applied and the signal terminal Tda. The resistor RA is a pull-up resistor, for example, 10 kΩ.

The source of the transistor PA is connected to the connection node NDA to which the power supply terminal Tva and the resistor RA are connected. The drain of the transistor PA is connected to the signal terminal Tda. The one-shot circuit 3A outputs a gate signal PGTA, which is one pulse having a predetermined time width, to the gate of the transistor PA according to the rising edge of the signal of the signal terminal Tdb. A power supply voltage VCCA is applied to the one-shot circuit 3A.

The resistor RB is connected between the power supply terminal Tvb to which the power supply voltage VCSB is applied and the signal terminal Tdb. The resistor RB is a pull-up resistor, for example, 10 kΩ.

The source of the transistor PB is connected to the connection node NDB to which the power supply terminal Tvb and the resistor RB are connected. The drain of the transistor PB is connected to the signal terminal Tdb. The one-shot circuit 3B outputs a gate signal PGTB, which is one pulse having a predetermined time width, to the gate of the transistor PB according to the rising edge of the signal of the signal terminal Tda. A power supply voltage VCSB is applied to the one-shot circuit 3B.

<3. Gate drive circuit configuration>
FIG. 3 is a circuit diagram showing a configuration example of the gate drive circuit 2. As shown in FIG. 3, the gate drive circuit 2 is composed of transistors P21, P22, P231, P232, P24, P25, P26 composed of p-channel MOSFETs and N21, N22, N231, N232 composed of n-channel MOSFETs. , N24, N25, N26, and so on.

The source of the transistor P21 is connected to the application end TV of the power supply voltage VCSA. The drain of the transistor P21 is connected to the drain of the transistor N21. The source of the transistor N21 is connected to the ground potential application end TG. The connection node between the gate of the transistor P21 and the gate of the transistor N21 is connected to the input terminal TAin. The input terminal TAin is connected to the signal terminal Tda.

The connection node between the drain of the transistor P21 and the drain of the transistor N21 is connected to the gate of the transistor P231 and also to the gate of the transistor N231.

The source of the transistor P232 is connected to the application end TV of the power supply voltage VCSA. The drain of transistor P232 is connected to the source of transistor P231. The drain of the transistor P231 is connected to the drain of the transistor N232. The source of the transistor N232 is connected to the ground potential application end TG.

The source of the transistor P22 is connected to the application end TV of the power supply voltage VCSA. The drain of the transistor P22 is connected to the drain of the transistor N22. The source of the transistor N22 is connected to the ground potential application end TG. The connection node between the gate of the transistor P22 and the gate of the transistor N22 is connected to the input terminal TBin. The input terminal TBin is connected to the signal terminal Tdb.

The connection node between the drain of the transistor P22 and the drain of the transistor N22 is connected to the connection node between the gate of the transistor P232 and the gate of the transistor N232.

The drain of the transistor N231 is connected to a connection node between the drain of the transistor P231 and the drain of the transistor N232. The source of the transistor N231 is connected to the application end TG of the ground potential.

The source of the transistor P24 is connected to the application end TV of the power supply voltage VCSA. The drain of the transistor P24 is connected to the drain of the transistor N24. The source of the transistor N24 is connected to the ground potential application end TG. The connection node between the drain of the transistor P231 and the drain of the transistor N232 is connected to the connection node between the gate of the transistor P24 and the gate of the transistor N24.

The source of the transistor P25 is connected to the application end TV of the power supply voltage VCSA. The drain of the transistor P25 is connected to the drain of the transistor N25. The source of the transistor N25 is connected to the ground potential application end TG. The connection node between the drain of the transistor P24 and the drain of the transistor N24 is connected to the connection node between the gate of the transistor P25 and the gate of the transistor N25.

The source of the transistor P26 is connected to the application end TV of the power supply voltage VCSA. The drain of the transistor P26 is connected to the drain of the transistor N26. The source of the transistor N26 is connected to the ground potential application end TG. The connection node between the drain of the transistor P25 and the drain of the transistor N25 is connected to the connection node between the gate of the transistor P26 and the gate of the transistor N26.

The connection node between the drain of the transistor P26 and the drain of the transistor N26 is connected to the output terminal Tout. The gate signal NGT is output from the output terminal Tout to the transistor N1.

<4. First example of signal transmission operation>
Next, a first example of the signal transmission operation by the bidirectional level shift circuit 1 having the configuration as described above will be described. FIG. 4 is a diagram showing an example of a configuration in which the bidirectional level shift circuit 1 is connected to the input side and the output side.

In the example of FIG. 4, one end of the resistor R1 and one end of the capacitor C1 are commonly connected to the signal terminal Tda on the input side. The input power supply voltage VA generated by the power supply 50 is applied to the other end of the resistor R1.

Further, in the example of FIG. 4, a series connection configuration of the resistor R2 and the capacitor C2 is connected to the signal terminal Tdb on the output side. The resistor R2 and the capacitor C2 form a load 100. The resistor R2 corresponds to, for example, a wiring resistor.

Here, refer to the timing chart shown in FIG. 5 for the behavior of the output signal (voltage) Bo generated in the node ND100 to which the resistor R2 and the capacitor C2 are connected when the input power supply voltage VA is started by the power supply 50. And describe.

As shown in FIG. 5, when the input power supply voltage VA is raised to the VCSA at the timing t0, the input signal (voltage) AIN generated at the signal terminal Tda gradually rises according to the time constant by the resistor R1 and the capacitor C1. Then, at the timing t1 when the input signal AIN reaches a certain level, the one-shot circuit 3B detects the rise of the input signal AIN, lowers the gate signal PGTB from the VCSB, and causes one pulse (one) of the predetermined time width TWB. Shot pulse) is generated.

Since the transistor PB is turned on during the predetermined time width TWB, the VCSB is applied to the signal terminal Tdb, but the output signal Bo rises slowly due to the time constant of the resistor R2 and the capacitor C2 at the load 100. Then, since the gate signal PGTB is raised to the VCSB at the timing t2 when the predetermined time width TWB has elapsed from the timing t1, the transistor PB is turned off. As a result, the output signal Bo rises according to the time constant due to the resistors RB and R2 and the capacitor C2. Since the resistance RB has a sufficiently higher resistance value than R2, the time constant becomes large, and the output signal Bo rises with a slope significantly smaller than the slope at the timings t1 to t2.

As described above, if the predetermined time width TWB corresponding to the pulse width of the one-shot pulse is short, the increase of the output signal Bo is suppressed before reaching the VCSB. Therefore, in order for the output signal Bo to reach the VCSB, it is necessary to lengthen the predetermined time width TWB.

Also, when the input / output is reversed (the signal terminal Tdb is the input side and Tda is the output side), the pulse width of the one-shot pulse generated by the one-shot circuit 3A (predetermined time width TWA) is the same as above. Needs to be long.

<5. Second example of signal transmission operation>
Next, a second example of the signal transmission operation by the bidirectional level shift circuit 1 will be described. FIG. 6 is a diagram showing an example of a configuration connected to the input side of the bidirectional level shift circuit 1.

In the example of FIG. 6, one end of the terminating resistor Re (for example, 50Ω) is connected to the signal terminal Tda on the input side, and the input power supply voltage VA generated by the power supply 50 is applied to the other end of the terminating resistor Re. .. The behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in the configuration shown in FIG. 6 will be described with reference to the timing chart shown in FIG.

When the input power supply voltage VA is raised to VCSA at the timing t10 as shown in FIG. 7, the input signal AIN generated at the signal terminal Tda is also raised to VCSA. When the input signal AIN rises, the one-shot circuit 3B lowers the gate signal PGTB. As a result, the transistor PB is turned on, and the output signal BOUT rises to the VCSB. When AIN and BOUT rise, the gate signal NGT is set to the Low level by the gate drive circuit 2, and the transistor N1 is turned off.

When the output signal BOUT rises, the gate signal PGTA rises from the VCSA by the one-shot circuit 3A. As a result, the transistor PA is turned on.

Here, when the pulse widths (predetermined time widths TWB, TWA) of the gate signals PGTB and PGTA are set long for the reason described in the first example above, the input power supply voltage VA has a high frequency as shown in FIG. When falling at timing t11, the gate signal PGTA is still at the Low level. As a result, since the transistor PA is on, a voltage Vd obtained by dividing the VCSA by the on resistance of the transistor PA and the terminating resistance Re is generated in the input signal AIN even though the input power supply voltage VA has dropped.

As a result, the one-shot circuit 3B detects that the input signal AIN is at the High level and maintains the gate signal PGTB at the Low level. Therefore, the transistor PB is turned on, and the output signal BOUT becomes VCSB. That is, although the input power supply voltage VA is falling, the output signal BOUT maintains the high level, which causes a problem in the responsiveness of the output signal BOUT.

According to the first and second examples as described above, it is an issue to improve the responsiveness of the output to a high frequency input while increasing the pulse width of the one-shot pulse, and the embodiment of the present invention described later is described. It was devised to solve this problem.

<6. Bidirectional level shift circuit according to the embodiment of the present invention>
Next, a bidirectional level shift circuit according to an exemplary embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a bidirectional level shift circuit 1 according to an exemplary embodiment of the present invention.

The difference between the configuration shown in FIG. 8 and the configuration shown in FIG. 6 described above is that the detection line LA for detecting the falling edge of the input signal AIN generated at the signal terminal Tda between the signal terminal Tda and the one-shot circuit 3A. Is provided. The detection line LB provided between the signal terminal Tdb and the one-shot circuit 3B shown in FIG. 8 is provided to detect the falling edge of the input signal BIN generated at the signal terminal Tdb with the signal terminal Tdb side as an input.

The behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in the configuration according to the present embodiment shown in FIG. 8 will be described with reference to the timing chart shown in FIG.

When the input power supply voltage VA is raised to VCSA at the timing t20 as shown in FIG. 9, the input signal AIN generated at the signal terminal Tda is also raised to VCSA. When the input signal AIN rises, the one-shot circuit 3B lowers the gate signal PGTB. As a result, the transistor PB is turned on, and the output signal BOUT rises to the VCSB. When AIN and BOUT rise, the gate signal NGT is set to the Low level by the gate drive circuit 2, and the transistor N1 is turned off.

When the output signal BOUT rises, the gate signal PGTA rises from the VCSA by the one-shot circuit 3A. As a result, the transistor PA is turned on.

Here, when the pulse widths (predetermined time widths TWB, TWA) of the gate signals PGTB and PGTA are set long for the reason described in the first example above, the input power supply voltage VA has a high frequency as shown in FIG. When falling at the timing t21, the gate signal PGTA is still at the Low level. As a result, since the transistor PA is on, a voltage Vd obtained by dividing the VCSA by the on resistance of the transistor PA and the terminating resistance Re is generated in the input signal AIN even though the input power supply voltage VA has dropped.

However, in the present embodiment, since the fall of the input signal AIN from the VCSA to the voltage Vd is detected by the one-shot circuit 3A, the one-shot circuit 3A raises the gate signal PGTA to the VCSA. That is, the one-shot circuit 3A can shorten the pulse width (predetermined time width TWA) of the one-shot pulse by ΔW as compared with the case of FIG. 7 (broken line).

As a result, the transistor PA is turned off at the timing t21, and the input signal AIN is lowered to the Low level. Therefore, the one-shot circuit 3B raises the gate signal PGTB to the High level and turns off the transistor PB. At this time, since the input signal AIN is lowered to the Low level, the gate signal NGT is set to the High level and the transistor N1 is turned on by the gate drive circuit 2. Therefore, the output signal BOUT has the same Low level as the input signal AIN.

The configuration shown in FIG. 8 according to the present embodiment is used in the same connection configuration as the connection configuration to the signal terminals Tda and Tdb (including input / output opposite to that in FIG. 4) as shown in FIG. 4 described above. In this case, the output signal (Bo in FIG. 4) can reach a desired level (VCCB in FIG. 4) by setting a long pulse width of the one-shot pulse.

As described above, according to the present embodiment, even when the pulse width of the one-shot pulse is set to be long, when the high frequency input power supply voltage VA is input, the pulse width is made shorter than the original value, and the input power supply voltage VA is set. The output signal BOUT can be immediately lowered with respect to the falling edge, and the responsiveness of the output signal BOUT can be improved.

<7. One-shot circuit configuration>
Here, a detailed configuration of the one-shot circuits 3A and 3B in the configuration according to the present embodiment shown in FIG. 8 will be described.

FIG. 10 is a circuit diagram showing a configuration example of the one-shot circuit 3A according to the present embodiment. As shown in FIG. 10, the one-shot circuit 3A includes a level shift unit 31A, a Schmitt trigger 32A, a one-shot pulse generation unit 33A, a mask generation unit 34A, and a fall detection unit 35A.

The level shift unit 31A is a circuit that level-shifts the signal applied to the signal terminal Tdb from VCSB to VCSA. The Schmitt trigger 32A converts the output of the level shift unit 31A into a High / Low output with hysteresis.

The one-shot pulse generation unit 33A includes an inverter 33A1, a resistor 33A2, a resistor 33A3, a capacitor 33A4, an AND circuit 33A5, an inverter 33A6, and a switch 33A7.

The output of the Schmitt trigger 32A is input to one input end of the AND circuit 33A5 and is also input to the inverter 33A1. The output end of the inverter 33A1 is connected to one end of the resistor 33A2. The other end of the resistor 33A2 is connected to one end of the resistor 33A3. The other end of the resistor 33A3 is connected to one end of the capacitor 33A4 as well as the other input end of the AND circuit 33A5. The output end of the AND circuit 33A5 is connected to the input end of the inverter 33A6. The output of the inverter 33A6 becomes the gate signal PGTA, and the gate signal PGTA is input to the gate of the transistor PA.

A CR circuit is composed of resistors 33A2 and 33A3 and capacitors 33A4. Here, in the bidirectional level shift circuit 1 (FIG. 8) according to the present embodiment, when the input signal BIN is input to the signal terminal Tdb by reversing the connection configuration and input / output to the signal terminals Tda and Tdb of FIG. When the input signal BIN rises to High, the output of the AND circuit 33A5 becomes High, and the gate signal PGTA becomes Low. On the other hand, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit decreases according to the time constant of the CR circuit. Then, when the output CRA reaches a certain level, the output of the AND circuit 33A5 becomes Low, and the gate signal PGTA becomes High. That is, the pulse width of the gate signal PGTA as a one-shot pulse is determined by the time constant of the CR circuit. By making the time constant relatively large, the pulse width can be set long.

Further, a switch 33A7 composed of an n-channel MOSFET is connected between both ends of the resistor 33A2. By turning the switch 33A7 on and off, the resistor 33A2 is disabled / enabled, and the time constant of the CR circuit is switched.

Further, the mask generation unit 34A includes an inverter 34A1, a resistor 34A2, a capacitor 34A3, and a NAND circuit 34A4. The output of the Schmitt trigger 32A is input to the input end of the inverter 34A1 together with one input end of the NAND circuit 34A4. The output of the inverter 34A1 is input to a CR circuit composed of a resistor 34A2 and a capacitor 34A3. The output of the CR circuit is input to the other input end of the NAND circuit 34A4. The output of the NAND circuit 34A4 becomes the mask signal MSK1.

When the input signal BIN is input to the signal terminal Tdb as described above, when the input signal BIN rises to High, the mask signal MSK1 first becomes Low. On the other hand, since the output of the inverter 34A1 becomes Low, the output CR1 of the CR circuit decreases according to the time constant. When the output CR1 decreases and reaches a certain level, the mask signal MSK1 is set to High. That is, by setting the mask signal MSK1 to Low for a predetermined period after the input signal BIN rises, the signal of the signal terminal Tda is connected to the AND circuit 36A from the signal terminal Tda described later via the inverter 35A1. It is suppressed that the output of the AND circuit 36A becomes High due to the influence of. As a result, it is possible to prevent the switch 33A7 from being turned on to reduce the time constant and accidentally shortening the pulse width. When the gate signal PGTA becomes Low, the transistor PA is turned on, and when the signal of the signal terminal Tda is High, the output of the inverter 35A1 is Low and the switch 33A7 is not turned on, so that the time constant is maintained. To.

The mask signal MSK1 is input to one input end of the AND circuit 36A. On the other hand, the fall detection unit 35A is configured by the inverter 35A1 in the example of FIG. That is, the signal terminal Tda is connected to the other input terminal of the AND circuit 36A via the inverter 35A1. The output of the AND circuit 36A is input to the gate of the switch 33A7. The falling edge detection unit 35A detects the falling edge of the signal of the signal terminal Tda toward Low.

Further, FIG. 11 is a circuit diagram showing a configuration example of the one-shot circuit 3B according to the present embodiment. As shown in FIG. 11, the one-shot circuit 3B includes a Schmitt trigger 31B, a one-shot pulse generation unit 32B, a mask generation unit 33B, and a fall detection unit 34B.

The Schmitt trigger 31B converts the signal of the signal terminal Tda into a High / Low output with hysteresis.

The one-shot pulse generation unit 32B includes an inverter 32B1, a resistor 32B2, a resistor 32B3, a capacitor 32B4, an AND circuit 32B5, an inverter 32B6, a level shift unit 32B7, and a switch 32B8.

The output of the Schmitt trigger 31B is input to one input end of the AND circuit 32B5 and is also input to the inverter 32B1. The output end of the inverter 32B1 is connected to one end of the resistor 32B2. The other end of the resistor 32B2 is connected to one end of the resistor 32B3. The other end of the resistor 32B3 is connected to one end of the capacitor 32B4 as well as the other input end of the AND circuit 32B5. The output end of the AND circuit 32B5 is connected to the input end of the inverter 32B6. The output of the inverter 32B6 is level-shifted from VCSA to VCSB by the level shift unit 32B7. The output of the level shift unit 32B7 becomes the gate signal PGTB, and the gate signal PGTB is input to the gate of the transistor PB.

A CR circuit is composed of resistors 32B2 and 32B3 and capacitors 32B4. Here, as a connection configuration similar to the connection configuration of FIG. 4, when the input signal AIN is input to the signal terminal Tda and the input signal AIN rises to High, the output of the AND circuit 32B5 first becomes High, and the gate signal. PGTB becomes Low. On the other hand, the output of the inverter 32B1 becomes Low, and the output CRB of the CR circuit decreases according to the time constant of the CR circuit. Then, when the output CRB reaches a certain level, the output of the AND circuit 32B5 becomes Low, and the gate signal PGTB becomes High. That is, the pulse width of the gate signal PGTB as a one-shot pulse is determined by the time constant of the CR circuit. By making the time constant relatively large, the pulse width can be set long.

Further, a switch 32B8 composed of an n-channel MOSFET is connected between both ends of the resistor 32B2. By turning the switch 32B8 on and off, the resistor 32B2 is disabled / enabled, and the time constant of the CR circuit is switched.

Further, the mask generation unit 33B includes an inverter 33B1, a resistor 33B2, a capacitor 33B3, and a NAND circuit 33B4. The output of the Schmitt trigger 31B is input to the input end of the inverter 33B1 together with one input end of the NAND circuit 33B4. The output of the inverter 33B1 is input to a CR circuit composed of a resistor 33B2 and a capacitor 33B3. The output of the CR circuit is input to the other input end of the NAND circuit 33B4. The output of the NAND circuit 33B4 becomes the mask signal MSK2.

When the input signal AIN is input to the signal terminal Tda as described above, when the input signal AIN rises to High, the mask signal MSK2 first becomes Low. On the other hand, since the output of the inverter 33B1 becomes Low, the output CR2 of the CR circuit decreases according to the time constant. When the output CR2 drops and reaches a certain level, the mask signal MSK2 is set to High. That is, by setting the mask signal MSK2 to Low for a predetermined period after the input signal AIN rises, the signal of the signal terminal Tdb is connected to the AND circuit 35B from the signal terminal Tdb described later via the inverter 34B1. It is suppressed that the output of the AND circuit 35B becomes High due to the influence of. As a result, it is possible to prevent the switch 32B8 from being turned on to reduce the time constant and accidentally shortening the pulse width. When the gate signal PGTB becomes Low, the transistor PB is turned on, and when the signal of the signal terminal Tdb is High, the output of the inverter 34B1 is Low and the switch 32B8 is not turned on, so that the time constant is maintained. To.

The mask signal MSK2 is input to one input end of the AND circuit 35B. On the other hand, the fall detection unit 34B is configured by the inverter 34B1 in the example of FIG. That is, the signal terminal Tdb is connected to the other input terminal of the AND circuit 35B via the inverter 34B1. The output of the AND circuit 35B is input to the gate of the switch 32B8. The falling edge detection unit 34B detects the falling edge of the signal of the signal terminal Tdb toward Low.

Next, regarding the behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in the configuration according to the present embodiment shown in FIG. 8, including the operation in the one-shot circuits 3A and 3B having such a configuration. , The timing chart shown in FIG. 13 will be referred to. Note that FIG. 13 partially overlaps with FIG. 9 described above.

When the input power supply voltage VA is raised to VCSA at the timing t30 as shown in FIG. 13, the input signal AIN generated at the signal terminal Tda is also raised to VCSA. As a result, in the one-shot circuit 3B shown in FIG. 11, the output of the AND circuit 32B5 becomes High, and the gate signal PGTB becomes Low. As a result, the transistor PB is turned on, and the output signal BOUT of the signal terminal Tdb rises to the VCSB.

Then, in the one-shot circuit 3A shown in FIG. 10, the output of the AND circuit 33A5 becomes High, and the gate signal PGTA becomes Low. As a result, the transistor PA is turned on. At this time, since the mask signal MSK1 falls to Low, the output VAND (FIG. 10) of the AND circuit 36A becomes Low, and the switch 33A7 is turned off. At this time, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit starts to decrease according to the time constant of the resistors 33A2, 33A3 and the capacitor 33A4.

After that, when the output CR1 decreases at the timing t31 and reaches a certain level, the mask signal MSK1 is set to High. However, since the input signal AIN of the signal terminal Tda is High, the output VAND becomes Low and the switch 33A7 is kept off.

Then, even if the input signal AIN is turned off at the timing t32, the gate signal PGTA is still Low and the transistor PA is turned on. As a result, the input signal AIN tends to decrease to Vd, which is the voltage obtained by dividing the VCSA by the on-resistance of the transistor PA and the terminating resistor Re. At this time, the inverter 35A1 (falling down detection unit 35A) can detect the falling edge of the input signal AIN toward Low.

Here, the inverter 35A1 has a CMOS configuration of a transistor PM using a p-channel MOSFET and a transistor NM using an n-channel MOSFET as shown in FIG. Since the transistor PM has a lower threshold value of Vgs than the transistor NM, it is possible to detect a small falling change of the signal of the signal terminal Tda. At this time, since the output of the inverter 35A1 is High, the output VAND is High and the switch 33A7 is turned on.

As a result, the resistor 33A2 is bypassed and the time constant of the CR circuit becomes small. Therefore, as shown in FIG. 13, the output CRA decreases with a relatively large slope at the timing t32, and when the predetermined threshold level CR_TH is reached at the timing t33, the gate signal PGTA becomes High. As a result, as shown in FIG. 13, the pulse width (predetermined time width TWA) of the gate signal PGTA can be shortened by ΔW from the original pulse width when the output CRA is reduced by the time constant before the small change. ..

Therefore, the transistor PA is turned off, and the input signal AIN drops to Low. As a result, in the one-shot circuit 3B shown in FIG. 11, the output of the AND circuit 32B5 becomes Low, and the gate signal PGTB becomes High, so that the transistor PB is turned off. At this time, since the input signal AIN is Low, the gate signal NGT is set to High by the gate drive circuit 2, and the transistor N1 is turned on. Therefore, the output signal BOUT is set to the same Low as the input signal AIN.

Since the output signal BOUT becomes Low at the timing t33, the mask signal MSK1 becomes High, and the input signal AIN becomes Low, so that the output of the inverter 35A1 becomes High, the output VAND becomes High, and the switch 33A7 turns on. Since the output signal BOUT is Low, the output of the inverter 33A1 in the one-shot circuit 3A becomes High. Therefore, the resistor 33A2 is bypassed, and the output CRA of the CR circuit starts to rise according to the time constant of the resistor 33A3 and the capacitor 33A4.

Then, when the input power supply voltage VA rises at the timing t34 before the output CRA reaches the predetermined maximum level CR_MAX, the input signal AIN also rises to the VCSA. As a result, the output of the AND circuit 32B5 in the one-shot circuit 3B becomes High, and the gate signal PGTB becomes Low. As a result, the transistor PB is turned on, and the output signal BOUT rises to the VCSB.

Then, in the one-shot circuit 3A, the output of the AND circuit 33A5 becomes High, and the gate signal PGTA becomes Low. As a result, the transistor PA is turned on. At this time, since the mask signal MSK1 falls to Low, the output VAND becomes Low and the switch 33A7 is turned off. At this time, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit starts to decrease according to the time constant of the resistors 33A2, 33A3 and the capacitor 33A4.

After that, when the output CR1 decreases at the timing t35 and reaches a certain level, the mask signal MSK1 is set to High. However, since the input signal AIN is High, the output VAND becomes Low and the switch 33A7 is kept off.

Then, when the output CRA reaches the threshold level CR_TH at the timing t36, the output of the AND circuit 33A5 becomes Low, the gate signal PGTA becomes High, and the transistor PA turns off. As a result, when the input power supply voltage VA drops at the timing t37, the input signal AIN also drops to Low. Therefore, the one-shot circuit 3B turns the gate signal PGTB high and the transistor PB off. At this time, since the input signal AIN is Low, the gate signal NGT is set to High by the gate drive circuit 2, and the transistor N1 is turned on. Therefore, the output signal BOUT is set to the same Low as the input signal AIN.

In this way, the responsiveness of the output signal BOUT to the high frequency input power supply voltage VA can be improved. In particular, after timing t33, the input power supply voltage VA rises before the output CRA reaches the maximum level CR_MAX, and the output CRA drops, so that the pulse width (predetermined time width TWA) of the gate signal PGTA is automatically shortened. .. As a result, the input signal AIN can be lowered to Low according to the falling edge of the input power supply voltage VA, and the responsiveness of the output signal BOUT can be enhanced. However, an embodiment may be adopted in which the output CRA is immediately raised to the maximum level CR_MAX at the timing t33. When the input / output of FIG. 8 is reversed, the same operation as described above is performed, and the responsiveness of the output signal of the signal terminal Tda can be improved with respect to the high frequency input power supply voltage of the power supply connected to the signal terminal Tdb.

<8. Modification example of one-shot circuit>
The one-shot circuits 3A and 3B may be modified as follows. FIG. 14 is a circuit diagram showing the configuration of the one-shot circuit 3A ′ according to the modified example. The difference between the one-shot circuit 3A'and the one-shot circuit 3A (FIG. 10) is the configuration of the fall detection unit 35A'.

The fall detection unit 35A'is composed of the comparator 35A1'. A signal terminal Tda is connected to the inverting input terminal (-) of the comparator 35A1', and a reference voltage is applied to the non-inverting input terminal (+). The comparator 35A1'outputs the comparison result between the signal of the signal terminal Tda and the reference voltage to the AND circuit 36A. As a result, when the signal terminal Tda goes down toward Low, High is output from the comparator 35A1'and the switch 33A7 can be turned on.

FIG. 15 is a circuit diagram showing the configuration of the one-shot circuit 3B ′ according to the modified example. The difference between the one-shot circuit 3B'and the one-shot circuit 3B (FIG. 11) is the configuration of the fall detection unit 34B'.

The fall detection unit 34B'is composed of the comparator 34B1'. A signal terminal Tdb is connected to the inverting input terminal (-) of the comparator 34B1', and a reference voltage is applied to the non-inverting input terminal (+). The comparator 34B1'outputs the comparison result between the signal of the signal terminal Tdb and the reference voltage to the AND circuit 35B. As a result, when the signal terminal Tdb goes down toward Low, High is output from the comparator 34B1'and the switch 32B8 can be turned on.

As described above, when the comparator is used as the falling detection unit, the accuracy of the detection threshold value can be improved. However, it is more advantageous to use an inverter as the fall detection unit from the viewpoint of cost reduction.

<9. Layout on the chip>
FIG. 16 is a schematic diagram showing an example of the layout of the bidirectional level shift circuit 1 in the chip CP. The chip CP extends in the X-axis direction and the Y-axis direction orthogonal to each other. In FIG. 16, one side in the X-axis direction is shown as X1, the other side is shown as X2, one side in the Y-axis direction is shown as Y1, and the other side is shown as Y2. The X2 side and the Y2 side are in the direction of approaching each other.

A transistor N1 is arranged at the end of the chip CP on the X1 side. The gate drive circuit 2 is arranged adjacent to the X2 side of the transistor N1. The gate drive circuit 2 is sandwiched in the Y-axis direction by the resistor RB and the resistor RA. The resistor RB is arranged on the Y1 side of the resistor RA. The transistors PA and PB are arranged on the X2 side of the gate drive circuit 2. The transistor PB is arranged on the Y1 side of the transistor PA.

Capacitors 33B3, 32B4, 33A4, 34A3 are arranged adjacent to each other toward the Y2 side in this order at the end of the chip CP on the X2 side, forming one first group. The capacitors 33B3 and 32B4 are provided in the one-shot circuit 3B (FIG. 11) as described above, and the capacitors 33A4 and 34A3 are provided in the one-shot circuit 3A (FIG. 10) as described above. By arranging the capacitors 33B3, 32B4, 33A4, 34A3 so as to form one group, the relative variation is reduced.

The resistors 32B3 and 32B2 are arranged adjacent to each other toward the X2 side in this order to form one second group. The second group is arranged on the Y1 side of the first group. The resistors 32B3 and 32B2 are provided in the one-shot circuit 3B (FIG. 11) as described above. As a result, the relative variation of the resistors 32B3 and 32B2 is reduced.

The resistors 33A3 and 33A2 are arranged adjacent to each other toward the X2 side in this order to form one third group. The third group is arranged on the Y2 side of the first group. The resistors 33A3 and 33A2 are provided in the one-shot circuit 3A (FIG. 10) as described above. This reduces the relative variation of the resistors 33A3 and 33A2.

Further, the signal terminal Tdb is arranged on the Y1 side of the transistor PB and on the X2 side of the resistor RB in a top view. The signal terminal Tda is arranged on the Y2 side of the transistor PA and on the X2 side of the resistor RA in a top view. The power supply terminal Tvb to which the VCSB is applied is arranged on the X2 side of the signal terminal Tdb and adjacent to the X1 side of the second group in the top view. The power supply terminal Tva to which the VCSA is applied is arranged on the X2 side of the signal terminal Tda and adjacent to the X1 side of the third group in the top view. Further, the ground terminal Tgd is arranged so as to be sandwiched in the X-axis direction by the signal terminal Tda and the power supply terminal Tva.

Each of the signal terminals Tdb and Tda and the power supply terminals Tvb and Tva overlap with the ESD protection diode when viewed from above.

<10. System application example>
FIG. 17 is a configuration diagram showing an application example of the data communication system shown in FIG. In the example of FIG. 17, the HDD (hard disk drive) 30 is provided with the system controller 20A and the bidirectional level shift circuit 1, and the tester 40 is provided with the system controller 20B. As a result, the bidirectional level shift circuit 1 functions as an interface that enables data communication between the system controllers operating at different power supply voltages between the HDD 30 and the tester 40.

<11. Others>
Although the embodiments of the present invention have been described above, the embodiments can be modified in various ways within the scope of the gist of the present invention.

The present invention can be used in various systems operating at different power supply voltages.

1 Bidirectional level shift circuit 2 Gate drive circuit 3A, 3B One-shot circuit 31A Level shift part 32A, 31B Schmitt trigger 33A, 32B One-shot pulse generation part 34A, 33B Mask generation part 35A, 34B Fall detection part N1 transistor (n) Channel MOSFET)
PA, PB transistor (p-channel MOSFET)
RA, RB resistor Tva, Tvb power supply terminal Tda, Tdb signal terminal Re terminating resistor 20A, 20B system controller 30 HDD (hard disk drive)
40 tester 50 power supply

Claims (13)

1st signal terminal and
2nd signal terminal and
The first power supply terminal to which the first power supply voltage is applied and
The second power supply terminal to which the second power supply voltage is applied and
A first pull-up resistor connected between the first power supply terminal and the first signal terminal,
A second pull-up resistor connected between the second power supply terminal and the second signal terminal,
A first transistor connected between both ends of the first pull-up resistor and
A second transistor connected between both ends of the second pull-up resistor and
A third transistor arranged between the first signal terminal and the second signal terminal,
A drive circuit that drives the control end of the third transistor,
A first one-shot circuit that generates a first drive signal that drives the control end of the first transistor, and
A second one-shot circuit that generates a second drive signal that drives the control end of the second transistor, and
With
The second one-shot circuit generates a one-shot pulse of the second drive signal which is turned on level by a predetermined second time width based on the rising edge of the signal of the first signal terminal, and generates a signal of the first signal terminal. Generates the off-level second drive signal based on the falling edge of
The first one-shot circuit is
A one-shot pulse of the first drive signal including the first CR circuit is generated based on the rising edge of the signal of the second signal terminal and turned on level by a predetermined first time width according to the time constant of the first CR circuit. One-shot pulse generator and
It has a falling edge detection unit that detects the falling edge of the signal of the first signal terminal and changes the time constant of the first CR circuit to a small value based on the detection result.
Bidirectional level shift circuit. The fall detection unit is a first inverter having a CMOS configuration consisting of a p-channel MOSFET and an n-channel MOSFET.
The bidirectional level shift circuit according to claim 1, wherein the p-channel MOSFET has a lower threshold value of Vgs as compared with the n-channel MOSFET. The bidirectional level shift circuit according to claim 1, wherein the fall detection unit is a comparator that compares a signal of the first signal terminal with a reference voltage. The first one-shot circuit further includes a mask generating unit that generates a mask signal that masks the detection result of the falling detection unit for a predetermined period when the signal of the second signal terminal rises. The bidirectional level shift circuit according to any one of claims 3. The bidirectional level shift circuit according to claim 4, wherein the mask generation unit has a second CR circuit that determines the predetermined period by a time constant. The mask generator
A NAND circuit having one input end to which the second signal terminal is electrically connected and the other input end to which the output end of the second CR circuit is connected.
A second inverter having an input end to which the second signal terminal is electrically connected and an output end connected to the input end of the second CR circuit.
The bidirectional level shift circuit according to claim 5, further comprising. The one-shot pulse generator has a switch connected between both ends of the resistor included in the first CR circuit.
The bidirectional level shift circuit according to any one of claims 1 to 6, wherein the switch is controlled to be turned on and off according to the detection result of the falling detection unit. The one-shot pulse generator
An AND circuit having one input terminal to which the second signal terminal is electrically connected and the other input terminal connected to the output terminal of the first CR circuit.
A third inverter having an input end to which the second signal terminal is electrically connected and an output end connected to the input end of the first CR circuit.
A fourth inverter having an input end connected to the output end of the AND circuit,
7. The bidirectional level shift circuit according to claim 7. The second power supply voltage is higher than the first power supply voltage.
The first one-shot circuit is supplied with the first power supply voltage as a power source.
The first one-shot circuit further provides a level shift unit for level-shifting the signal of the second signal terminal from the second power supply voltage to the first power supply voltage on the front stage side of the one-shot pulse generation unit. The bidirectional level shift circuit according to any one of claims 1 to 8. The bidirectional level shift circuit according to claim 9, wherein the first one-shot circuit further includes a Schmitt trigger arranged between the level shift unit and the one-shot pulse generation unit. The bidirectional level shift circuit according to any one of claims 1 to 10, wherein a plurality of resistors included in the first CR circuit are arranged adjacent to each other to form a first group on the chip. The fifth or sixth aspect of the chip, wherein the first capacitor included in the first CR circuit and the second capacitor included in the second CR circuit are arranged adjacent to each other to form a second group. Bidirectional level shift circuit. The bidirectional level shift circuit according to any one of claims 1 to 12.
The first system that operates by the first power supply voltage and
The second system that operates by the second power supply voltage and
A data communication system including.

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