JP7339805B2 - Bi-directional level shift circuit - Google Patents

Description

The present invention relates to bidirectional level shift circuits.

Conventionally, when there are systems operating with different power supply voltages, bidirectional level shift circuits are used to bidirectionally transmit signals between the systems. An example of a bidirectional level shift circuit is disclosed in US Pat.

JP 2012-147173 A

Here, the bidirectional level shift circuit is required to improve the responsiveness of the output signal when a high-frequency input signal is input.

SUMMARY OF THE INVENTION In view of the above situation, it is an object of the present invention to provide a bidirectional level shift circuit capable of improving the responsiveness of an output signal to a high frequency input signal.

In order to achieve the above object, a bidirectional level shift circuit according to one aspect of the present invention includes:
a first signal terminal;
a second signal terminal;
a first power supply terminal to which the first power supply voltage is applied;
a second power supply terminal to which a second power supply voltage is applied;
a first pull-up resistor connected between the first power terminal and the first signal terminal;
a second pull-up resistor connected between the second power terminal and the second signal terminal;
a first transistor connected across the first pull-up resistor;
a second transistor connected across the second pull-up resistor;
a third transistor arranged between the first signal terminal and the second signal terminal;
a driving circuit for driving the control terminal of the third transistor;
a first one-shot circuit for generating a first drive signal for driving a control end of the first transistor;
a second one-shot circuit for generating a second drive signal for driving the control end of the second transistor;
with
The second one-shot circuit generates a one-shot pulse of the second drive signal that is turned on for a predetermined second time width based on the rising edge of the signal at the first signal terminal, and outputs the signal at the first signal terminal. generating the off-level second drive signal based on the falling edge of
The first one-shot circuit is
A first CR circuit is included, and a one-shot pulse of the first drive signal is generated based on the rising edge of the signal at the second signal terminal and turned on for a predetermined first time width corresponding to the time constant of the first CR circuit. a one-shot pulse generator;
and a fall detector that detects the fall of the signal of the first signal terminal and changes the time constant of the first CR circuit to be smaller based on the detection result (first structure).

Further, in the first configuration, the falling edge detection unit is a first inverter having a CMOS configuration with a p-channel MOSFET and an n-channel MOSFET, and the p-channel MOSFET has a lower Vgs threshold than the n-channel MOSFET. It may be lowered (second configuration).

Further, in the first configuration, the fall detection section may be a comparator that compares the signal at the first signal terminal and a reference voltage (third configuration).

In any one of the first to third configurations, the first one-shot circuit masks the detection result of the fall detector for a predetermined period when the signal at the second signal terminal rises. It may further include a mask generator that generates a mask signal (fourth configuration).

Further, in the fourth configuration, the mask generator may have a second CR circuit that determines the predetermined period by a time constant (fifth configuration).

Further, in the above fifth configuration, the mask generation unit
a NAND circuit having one input terminal electrically connected to the second signal terminal and the other input terminal connected to the output terminal of the second CR circuit;
It may further include a second inverter having an input terminal electrically connected to the second signal terminal and an output terminal connected to the input terminal of the second CR circuit (sixth configuration ).

Further, in any one of the first to sixth configurations, the one-shot pulse generator has a switch connected across the resistor included in the first CR circuit, and the switch is connected to the falling edge. On/off may be controlled according to the detection result of the detection unit (seventh configuration).

Further, in the seventh configuration, the one-shot pulse generation unit
an AND circuit having one input terminal electrically connected to the second signal terminal and the other input terminal connected to the output terminal of the first CR circuit;
a third inverter having an input terminal electrically connected to the second signal terminal and an output terminal connected to the input terminal of the first CR circuit;
and a fourth inverter having an input terminal connected to the output terminal of the AND circuit (eighth configuration).

In any one of the first to eighth configurations, the second power supply voltage is higher than the first power supply voltage, and the first one-shot circuit is supplied with the first power supply voltage as a power supply, The first one-shot circuit further includes a level shifter for level-shifting the signal of the second signal terminal from the second power supply voltage to the first power supply voltage on the preceding stage side of the one-shot pulse generator. (9th configuration).

In the ninth configuration, the first one-shot circuit may further include a Schmitt trigger arranged between the level shifter and the one-shot pulse generator (tenth configuration). .

Further, in any one of the first to tenth configurations, in the chip, the plurality of resistors included in the first CR circuit may be arranged adjacent to each other to form a first group (the eleventh resistor). configuration).

In the above fifth or sixth configuration, in the chip, the first capacitor included in the first CR circuit and the second capacitor included in the second CR circuit are arranged adjacently to form a second group. (12th configuration).

In another aspect of the present invention, there is provided a bidirectional level shift circuit having any one of the first to twelfth configurations, a first system operated by the first power supply voltage, and a second system operated by the second power supply voltage. and a second system.

According to the bidirectional level shift circuit of the present invention, it is possible to improve the responsiveness of the output signal to the high frequency input signal.

It is a figure which shows one structural example of a data communication system. 1 is a circuit diagram showing a configuration example of a bidirectional level shift circuit; FIG. It is a circuit diagram which shows one structural example of a gate drive circuit. 4 is a circuit diagram showing a first connection mode to signal terminals of the bidirectional level shift circuit shown in FIG. 3; FIG. 5 is a timing chart showing an example of behavior of various signals in the case shown in FIG. 4; 4 is a circuit diagram showing a second connection mode to signal terminals of the bidirectional level shift circuit shown in FIG. 3; FIG. 7 is a timing chart showing an example of behavior of various signals in the case shown in FIG. 6; FIG. 4 is a circuit diagram showing a bi-directional level shift circuit and a second connection to its signal terminals according to an exemplary embodiment of the invention; 9 is a timing chart showing an example of behavior of various signals in the case shown in FIG. 8; 4 is a circuit diagram showing a configuration example of a first one-shot circuit; FIG. It is a circuit diagram which shows one structural example of a 2nd one-shot circuit. FIG. 10 is a diagram showing a configuration example of an inverter as a fall detector; 9 is a timing chart including the operation of the one-shot circuit in the case shown in FIG. 8; It is a circuit diagram which shows the modification of a 1st one-shot circuit. It is a circuit diagram which shows the modification of a 2nd one-shot circuit. FIG. 3 is a schematic diagram showing an example layout of a bidirectional level shift circuit on a chip; FIG. 2 is a configuration diagram showing an application example of the data communication system shown in FIG. 1;

Exemplary embodiments of the invention are described below with reference to the drawings.

<1. System configuration>
FIG. 1 is a diagram showing a configuration example of a data communication system that performs data communication between systems operating at different power supply voltages. The data communication system shown in FIG. 1 is composed of system controllers 20A and 20B that operate with different power supply voltages, and a bidirectional level shift circuit 1. FIG.

The system controller 20A operates with the power supply voltage VCCA. The system controller 20B operates with the power supply voltage VCCB. The magnitude relationship between the power supply voltages VCCB and VCCA is VCCB>VCCA. For example, VCCA=1.8V and VCCB=3.3V.

The bidirectional level shift circuit 1 is a circuit for bidirectional signal transmission between the system controllers 20A and 20B, and is configured as a semiconductor IC. The bidirectional level shift circuit 1 has power supply terminals Tva, Tvb and signal terminals Tda, Tdb.

A power supply voltage VCCA is applied to the power supply terminal Tva, and a power supply voltage VCCB is applied to the power supply terminal Tvb.

When transmitting data from the system controller 20A to 20B, an input signal as data is input to the signal terminal Tda, and an output signal as data is output from the signal terminal Tdb. In this case, the input signal is level-shifted from VCCA to VCCB to become the output signal.

On the other hand, when data is transmitted from the system controller 20B to 20A, an input signal as data is input to the signal terminal Tdb, and an output signal as data is output from the signal terminal Tda. In this case, the input signal is level-shifted from VCCB to VCCA to become the output signal.

<2. Configuration of Bidirectional Level Shift Circuit>
FIG. 2 is a circuit diagram showing a configuration example of the bidirectional level shift circuit 1 (FIG. 1). Note that the bidirectional level shift circuit 1 shown in FIG. 2 is a basic configuration of a configuration according to an embodiment of the present invention, which will be described later.

As shown in FIG. 2, the bidirectional level shift circuit 1 includes a transistor N1 composed of an n-channel MOSFET, a gate drive circuit 2, one-shot circuits 3A and 3B, and a transistor PA composed of p-channel MOSFETs. It has PB and resistors RA and RB.

Transistor N1 is arranged between signal terminals Tda and Tdb. A first terminal other than the gate of the transistor N1 is connected to the signal terminal Tda. A second terminal other than the gate of the transistor N1 is connected to the signal terminal Tdb.

The gate drive circuit 2 generates a gate signal NGT to drive the gate of the transistor N1. A power supply voltage VCCA is applied to the gate drive circuit 2 . The details of the configuration of the gate drive circuit 2 will be described later.

The resistor RA is connected between the power supply terminal Tva to which the power supply voltage VCCA is applied and the signal terminal Tda. A resistor RA is a pull-up resistor and is, for example, 10 kΩ.

The source of the transistor PA is connected to a connection node NDA where the power supply terminal Tva and the resistor RA are connected. The drain of transistor PA is connected to signal terminal Tda. The one-shot circuit 3A outputs a gate signal PGTA, which is one pulse with a predetermined time width, to the gate of the transistor PA in response to the rise of the signal at the signal terminal Tdb. A power supply voltage VCCA is applied to the one-shot circuit 3A.

The resistor RB is connected between the power supply terminal Tvb to which the power supply voltage VCCB is applied and the signal terminal Tdb. A resistor RB is a pull-up resistor and is, for example, 10 kΩ.

The source of the transistor PB is connected to a connection node NDB where the power supply terminal Tvb and the resistor RB are connected. The drain of transistor PB is connected to signal terminal Tdb. The one-shot circuit 3B outputs a gate signal PGTB, which is one pulse with a predetermined time width, to the gate of the transistor PB in response to the rise of the signal at the signal terminal Tda. A power supply voltage VCCB is applied to the one-shot circuit 3B.

<3. Configuration of Gate Drive Circuit>
FIG. 3 is a circuit diagram showing a configuration example of the gate drive circuit 2. As shown in FIG. As shown in FIG. 3, the gate drive circuit 2 includes transistors P21, P22, P231, P232, P24, P25 and P26 formed of p-channel MOSFETs, and N21, N22, N231 and N232 formed of n-channel MOSFETs. , N24, N25, N26.

The source of the transistor P21 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P21 is connected to the drain of transistor N21. The source of the transistor N21 is connected to the ground potential application terminal TG. A connection node between the gate of the transistor P21 and the gate of the transistor N21 is connected to the input terminal TAin. The input terminal TAin is connected to the signal terminal Tda.

A connection node between the drain of the transistor P21 and the drain of the transistor N21 is connected to the gate of the transistor P231 and the gate of the transistor N231.

The source of the transistor P232 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P232 is connected to the source of transistor P231. The drain of transistor P231 is connected to the drain of transistor N232. The source of the transistor N232 is connected to the ground potential application terminal TG.

The source of the transistor P22 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P22 is connected to the drain of transistor N22. The source of the transistor N22 is connected to the ground potential application terminal TG. A connection node between the gate of the transistor P22 and the gate of the transistor N22 is connected to the input terminal TBin. The input terminal TBin is connected to the signal terminal Tdb.

A connection node between the drain of the transistor P22 and the drain of the transistor N22 is connected to a connection node between the gate of the transistor P232 and the gate of the transistor N232.

The drain of transistor N231 is connected to the connection node between the drain of transistor P231 and the drain of transistor N232. The source of the transistor N231 is connected to the ground potential application terminal TG.

The source of the transistor P24 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P24 is connected to the drain of transistor N24. The source of the transistor N24 is connected to the ground potential application terminal TG. A connection node between the drain of the transistor P231 and the drain of the transistor N232 is connected to a connection node between the gate of the transistor P24 and the gate of the transistor N24.

The source of the transistor P25 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P25 is connected to the drain of transistor N25. The source of the transistor N25 is connected to the ground potential application terminal TG. A connection node between the drain of the transistor P24 and the drain of the transistor N24 is connected to a connection node between the gate of the transistor P25 and the gate of the transistor N25.

The source of the transistor P26 is connected to the application terminal TV of the power supply voltage VCCA. The drain of transistor P26 is connected to the drain of transistor N26. The source of the transistor N26 is connected to the ground potential application terminal TG. A connection node between the drain of the transistor P25 and the drain of the transistor N25 is connected to a connection node between the gate of the transistor P26 and the gate of the transistor N26.

A connection node between the drain of the transistor P26 and the drain of the transistor N26 is connected to the output terminal Tout. A gate signal NGT is output from the output terminal Tout to the transistor N1.

<4. First example of signal transmission operation>
Next, a first example of signal transmission operation by the bidirectional level shift circuit 1 having the configuration described above will be described. FIG. 4 is a diagram showing an example of a configuration connected to the input side and the output side of the bidirectional level shift circuit 1. As shown in FIG.

In the example of FIG. 4, one end of the resistor R1 and one end of the capacitor C1 are commonly connected to the signal terminal Tda on the input side. An input power supply voltage VA generated by a power supply 50 is applied to the other end of the resistor R1.

Further, in the example of FIG. 4, a series connection configuration of a resistor R2 and a capacitor C2 is connected to the signal terminal Tdb on the output side. A resistor R2 and a capacitor C2 form a load 100. FIG. The resistance R2 corresponds to, for example, wiring resistance.

Here, refer to the timing chart shown in FIG. 5 for the behavior of the output signal (voltage) Bo generated at the node ND100 where the resistor R2 and the capacitor C2 are connected when the input power supply voltage VA is raised by the power supply 50. and state.

As shown in FIG. 5, when the input power supply voltage VA rises to VCCA at timing t0, the input signal (voltage) AIN generated at the signal terminal Tda gently rises according to the time constant of the resistor R1 and capacitor C1. Then, at the timing t1 when the input signal AIN reaches a certain level, the one-shot circuit 3B detects the rise of the input signal AIN, lowers the gate signal PGTB from VCCB, and generates one pulse (one pulse) having a predetermined time width TWB. shot pulse).

Since the transistor PB is turned on during the predetermined time width TWB, VCCB is applied to the signal terminal Tdb. The gate signal PGTB rises to VCCB at timing t2 after a predetermined time width TWB has elapsed from timing t1, so that the transistor PB is turned off. As a result, the output signal Bo rises according to the time constant of the resistors RB, R2 and capacitor C2. Since the resistance value of the resistor RB is sufficiently higher than that of R2, the time constant becomes large, and the output signal Bo rises with a much smaller slope than the slope between timings t1 and t2.

Thus, if the predetermined time width TWB corresponding to the pulse width of the one-shot pulse is short, the rise of the output signal Bo is suppressed before reaching VCCB. Therefore, in order for the output signal Bo to reach VCCB, it is necessary to lengthen the predetermined time width TWB.

Also, when the input and output are reversed (the signal terminal Tdb is on the input side and Tda is on the output side), for the same reason as above, the pulse width (predetermined time width TWA) of the one-shot pulse generated by the one-shot circuit 3A should be lengthened.

<5. Second example of signal transmission operation>
Next, a second example of signal transmission operation by the bidirectional level shift circuit 1 will be described. FIG. 6 is a diagram showing an example of a configuration connected to the input side of the bidirectional level shift circuit 1. As shown in FIG.

In the example of FIG. 6, one end of a termination resistor Re (for example, 50Ω) is connected to a signal terminal Tda on the input side, and an input power supply voltage VA generated by a power supply 50 is applied to the other end of the termination resistor Re. . The behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in such a configuration shown in FIG. 6 will be described with reference to the timing chart shown in FIG.

As shown in FIG. 7, when the input power supply voltage VA rises to VCCA at timing t10, the input signal AIN generated at the signal terminal Tda also rises to VCCA. The rise of the input signal AIN causes the one-shot circuit 3B to cause the gate signal PGTB to fall. As a result, the transistor PB is turned on, and the output signal BOUT rises to VCCB. It should be noted that the rise of AIN and BOUT causes the gate signal NGT to be set to Low level by the gate drive circuit 2, and the transistor N1 is turned off.

As the output signal BOUT rises, the gate signal PGTA falls from VCCA by the one-shot circuit 3A. This turns on the transistor PA.

Here, when the pulse widths (predetermined time widths TWB, TWA) of the gate signals PGTB, PGTA are set long for the reason described in the first example, the input power supply voltage VA is high-frequency as shown in FIG. When it falls at timing t11, the gate signal PGTA is still at Low level. As a result, since the transistor PA is on, the voltage Vd obtained by dividing VCCA by the on-resistance of the transistor PA and the terminating resistor Re is generated in the input signal AIN even though the input power supply voltage VA has fallen.

As a result, the one-shot circuit 3B detects that the input signal AIN is at High level, and maintains the gate signal PGTB at Low level. Therefore, the transistor PB is turned on, and the output signal BOUT becomes VCCB. In other words, although the input power supply voltage VA has fallen, the output signal BOUT maintains the High level, causing a problem in the responsiveness of the output signal BOUT.

According to the first and second examples as described above, it becomes a problem to increase the responsiveness of the output to high-frequency input while increasing the pulse width of the one-shot pulse. It was devised to solve this problem.

<6. Bidirectional Level Shift Circuit According to Embodiment of Present Invention>
A bidirectional level shift circuit according to an exemplary embodiment of the present invention will now be described. FIG. 8 is a circuit diagram showing the configuration of a bidirectional level shift circuit 1 according to an exemplary embodiment of the invention.

The difference between the configuration shown in FIG. 8 and the configuration shown in FIG. 6 described above is that a detection line LA for detecting the falling edge of the input signal AIN generated at the signal terminal Tda between the signal terminal Tda and the one-shot circuit 3A. is provided. A detection line LB provided between the signal terminal Tdb and the one-shot circuit 3B shown in FIG. 8 is provided to detect the fall of the input signal BIN generated at the signal terminal Tdb with the signal terminal Tdb side as an input.

The behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in the configuration according to this embodiment shown in FIG. 8 will be described with reference to the timing chart shown in FIG.

As shown in FIG. 9, when the input power supply voltage VA rises to VCCA at timing t20, the input signal AIN generated at the signal terminal Tda also rises to VCCA. The rise of the input signal AIN causes the one-shot circuit 3B to cause the gate signal PGTB to fall. As a result, the transistor PB is turned on, and the output signal BOUT rises to VCCB. It should be noted that the rise of AIN and BOUT causes the gate signal NGT to be set to Low level by the gate drive circuit 2, and the transistor N1 is turned off.

As the output signal BOUT rises, the gate signal PGTA falls from VCCA by the one-shot circuit 3A. This turns on the transistor PA.

Here, when the pulse widths (predetermined time widths TWB, TWA) of the gate signals PGTB, PGTA are set long for the reason described in the first example, the input power supply voltage VA is high-frequency as shown in FIG. When falling at timing t21, the gate signal PGTA is still at Low level. As a result, since the transistor PA is on, the voltage Vd obtained by dividing VCCA by the on-resistance of the transistor PA and the terminating resistor Re is generated in the input signal AIN even though the input power supply voltage VA has fallen.

However, in this embodiment, the one-shot circuit 3A detects the fall of the input signal AIN from VCCA to the voltage Vd, so the one-shot circuit 3A raises the gate signal PGTA to VCCA. That is, the one-shot circuit 3A can shorten the pulse width (predetermined time width TWA) of the one-shot pulse by .DELTA.W compared to the case (broken line) in FIG.

As a result, the transistor PA is turned off at timing t21, and the input signal AIN falls to Low level. Therefore, the one-shot circuit 3B raises the gate signal PGTB to a high level, turning off the transistor PB. At this time, since the input signal AIN has fallen to Low level, the gate signal NGT is set to High level by the gate drive circuit 2, and the transistor N1 is turned on. Therefore, the output signal BOUT is set to the same Low level as the input signal AIN.

The configuration shown in FIG. 8 according to the present embodiment is used in a connection configuration similar to the connection configuration to the signal terminals Tda and Tdb as shown in FIG. In this case, the output signal (Bo in FIG. 4) can reach a desired level (VCCB in FIG. 4) by setting the pulse width of the one-shot pulse long.

As described above, according to the present embodiment, even when the pulse width of the one-shot pulse is set long, when the high-frequency input power supply voltage VA is input, the pulse width is shortened and the input power supply voltage VA is shortened. The output signal BOUT can be immediately lowered when it falls, and the responsiveness of the output signal BOUT can be improved.

<7. Configuration of one-shot circuit>
Here, the detailed configuration of the one-shot circuits 3A and 3B in the configuration according to this embodiment shown in FIG. 8 will be described.

FIG. 10 is a circuit diagram showing a configuration example of a one-shot circuit 3A according to this embodiment. As shown in FIG. 10, the one-shot circuit 3A has a level shifter 31A, a Schmitt trigger 32A, a one-shot pulse generator 33A, a mask generator 34A, and a trailing edge detector 35A.

The level shifter 31A is a circuit that level-shifts the signal applied to the signal terminal Tdb from VCCB to VCCA. The Schmitt trigger 32A converts the output of the level shifter 31A into a High/Low output with hysteresis.

The one-shot pulse generator 33A has an inverter 33A1, a resistor 33A2, a resistor 33A3, a capacitor 33A4, an AND circuit 33A5, an inverter 33A6, and a switch 33A7.

The output of the Schmitt trigger 32A is input to one input terminal of the AND circuit 33A5 and is also input to the inverter 33A1. The output end of inverter 33A1 is connected to one end of resistor 33A2. The other end of the resistor 33A2 is connected to one end of the resistor 33A3. The other end of the resistor 33A3 is connected to one end of the capacitor 33A4 and the other input end of the AND circuit 33A5. The output terminal of the AND circuit 33A5 is connected to the input terminal of the inverter 33A6. The output of the inverter 33A6 becomes the gate signal PGTA, and the gate signal PGTA is input to the gate of the transistor PA.

A CR circuit is composed of the resistors 33A2 and 33A3 and the capacitor 33A4. Here, in the bidirectional level shift circuit 1 (FIG. 8) according to the present embodiment, when the input signal BIN is input to the signal terminal Tdb by reversing the connection configuration with respect to the signal terminals Tda and Tdb in FIG. Then, when the input signal BIN rises to High, first the output of the AND circuit 33A5 becomes High and the gate signal PGTA becomes Low. On the other hand, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit decreases according to the time constant of the CR circuit. Then, when the output CRA reaches a certain level, the output of the AND circuit 33A5 becomes Low and the gate signal PGTA becomes High. That is, the pulse width of the gate signal PGTA as a one-shot pulse is determined by the time constant of the CR circuit. By making the time constant relatively large, the pulse width can be set long.

A switch 33A7 composed of an n-channel MOSFET is connected across the resistor 33A2. By turning the switch 33A7 on and off, the resistance 33A2 is switched between invalid and valid, and the time constant of the CR circuit is switched.

The mask generator 34A also has an inverter 34A1, a resistor 34A2, a capacitor 34A3, and a NAND circuit 34A4. The output of Schmitt trigger 32A is input to the input terminal of inverter 34A1 together with one input terminal of NAND circuit 34A4. The output of the inverter 34A1 is input to a CR circuit composed of a resistor 34A2 and a capacitor 34A3. The output of the CR circuit is input to the other input terminal of the NAND circuit 34A4. The output of the NAND circuit 34A4 becomes the mask signal MSK1.

When the input signal BIN is input to the signal terminal Tdb as described above, the mask signal MSK1 first becomes Low when the input signal BIN rises to High. On the other hand, since the output of the inverter 34A1 becomes Low, the output CR1 of the CR circuit decreases according to the time constant. When the output CR1 falls and reaches a certain level, the mask signal MSK1 is made high. That is, by setting the mask signal MSK1 to Low for a predetermined period after the rise of the input signal BIN, the signal at the signal terminal Tda is controlled by a path connecting the signal terminal Tda to the AND circuit 36A via the inverter 35A1, which will be described later. suppresses the output of the AND circuit 36A from becoming High due to the influence of . As a result, it is possible to prevent the pulse width from being erroneously shortened due to the switch 33A7 being turned on and the time constant being reduced. When the gate signal PGTA becomes Low, the transistor PA is turned on, and when the signal at the signal terminal Tda becomes High, the output of the inverter 35A1 becomes Low and the switch 33A7 is not turned on, so the time constant is maintained. be.

The mask signal MSK1 is input to one input terminal of the AND circuit 36A. On the other hand, in the example of FIG. 10, the fall detector 35A is configured by an inverter 35A1. That is, the signal terminal Tda is connected to the other input terminal of the AND circuit 36A via the inverter 35A1. The output of AND circuit 36A is input to the gate of switch 33A7. The trailing edge of the signal at the signal terminal Tda toward Low is detected by the trailing edge detection unit 35A.

FIG. 11 is a circuit diagram showing one configuration example of the one-shot circuit 3B according to this embodiment. As shown in FIG. 11, the one-shot circuit 3B has a Schmidt trigger 31B, a one-shot pulse generator 32B, a mask generator 33B, and a trailing edge detector 34B.

The Schmitt trigger 31B converts the signal of the signal terminal Tda into a High/Low output with hysteresis.

The one-shot pulse generator 32B has an inverter 32B1, a resistor 32B2, a resistor 32B3, a capacitor 32B4, an AND circuit 32B5, an inverter 32B6, a level shifter 32B7, and a switch 32B8.

The output of the Schmitt trigger 31B is input to one input terminal of the AND circuit 32B5 and is also input to the inverter 32B1. The output end of inverter 32B1 is connected to one end of resistor 32B2. The other end of resistor 32B2 is connected to one end of resistor 32B3. The other end of the resistor 32B3 is connected to one end of the capacitor 32B4 and the other input end of the AND circuit 32B5. The output terminal of the AND circuit 32B5 is connected to the input terminal of the inverter 32B6. The output of inverter 32B6 is level-shifted from VCCA to VCCB by level shifter 32B7. The output of the level shifter 32B7 becomes the gate signal PGTB, and the gate signal PGTB is input to the gate of the transistor PB.

A CR circuit is composed of resistors 32B2 and 32B3 and a capacitor 32B4. Here, as a connection configuration similar to the connection configuration of FIG. 4, when the input signal AIN is input to the signal terminal Tda, when the input signal AIN rises to High, the output of the AND circuit 32B5 first becomes High, and the gate signal PGTB becomes Low. On the other hand, the output of the inverter 32B1 becomes Low, and the output CRB of the CR circuit decreases according to the time constant of the CR circuit. Then, when the output CRB reaches a certain level, the output of the AND circuit 32B5 becomes Low and the gate signal PGTB becomes High. That is, the pulse width of the gate signal PGTB as a one-shot pulse is determined by the time constant of the CR circuit. By making the time constant relatively large, the pulse width can be set long.

A switch 32B8 composed of an n-channel MOSFET is connected across the resistor 32B2. By turning on/off the switch 32B8, the resistor 32B2 is switched between invalid and valid, and the time constant of the CR circuit is switched.

Also, the mask generator 33B has an inverter 33B1, a resistor 33B2, a capacitor 33B3, and a NAND circuit 33B4. The output of the Schmitt trigger 31B is input to the input terminal of the inverter 33B1 together with one input terminal of the NAND circuit 33B4. The output of the inverter 33B1 is input to a CR circuit composed of a resistor 33B2 and a capacitor 33B3. The output of the CR circuit is input to the other input terminal of the NAND circuit 33B4. The output of the NAND circuit 33B4 becomes the mask signal MSK2.

When the input signal AIN is input to the signal terminal Tda as described above, the mask signal MSK2 first becomes Low when the input signal AIN rises to High. On the other hand, since the output of the inverter 33B1 becomes Low, the output CR2 of the CR circuit decreases according to the time constant. When the output CR2 falls and reaches a certain level, the mask signal MSK2 is made high. That is, by setting the mask signal MSK2 to Low for a predetermined period after the rise of the input signal AIN, the signal at the signal terminal Tdb is controlled by a path connecting the signal terminal Tdb to the AND circuit 35B via the inverter 34B1, which will be described later. suppresses the output of the AND circuit 35B from becoming High due to the influence of . As a result, it is possible to prevent the switch 32B8 from turning on, reducing the time constant, and erroneously shortening the pulse width. When the gate signal PGTB becomes Low, the transistor PB is turned on, and when the signal at the signal terminal Tdb becomes High, the output of the inverter 34B1 becomes Low and the switch 32B8 does not turn on, so the time constant is maintained. be.

The mask signal MSK2 is input to one input terminal of the AND circuit 35B. On the other hand, in the example of FIG. 11, the fall detector 34B is configured by an inverter 34B1. That is, the signal terminal Tdb is connected to the other input terminal of the AND circuit 35B via the inverter 34B1. The output of the AND circuit 35B is input to the gate of the switch 32B8. The fall detection unit 34B detects the fall of the signal at the signal terminal Tdb toward Low.

Next, the behavior of the output signal BOUT generated at the signal terminal Tdb with respect to the input power supply voltage VA in the configuration according to the present embodiment shown in FIG. , with reference to the timing chart shown in FIG. Note that FIG. 13 partially overlaps with FIG. 9 described above.

As shown in FIG. 13, when the input power supply voltage VA rises to VCCA at timing t30, the input signal AIN generated at the signal terminal Tda also rises to VCCA. As a result, in the one-shot circuit 3B shown in FIG. 11, the output of the AND circuit 32B5 becomes High, and the gate signal PGTB becomes Low. As a result, the transistor PB is turned on, and the output signal BOUT from the signal terminal Tdb rises to VCCB.

Then, in the one-shot circuit 3A shown in FIG. 10, the output of the AND circuit 33A5 becomes High, and the gate signal PGTA becomes Low. This turns on the transistor PA. At this time, the mask signal MSK1 falls to Low, so the output VAND (FIG. 10) of the AND circuit 36A becomes Low and the switch 33A7 is turned off. At this time, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit starts decreasing according to the time constant of the resistors 33A2, 33A3 and the capacitor 33A4.

After that, when the output CR1 decreases and reaches a certain level at timing t31, the mask signal MSK1 is set to High. However, since the input signal AIN of the signal terminal Tda is High, the output VAND becomes Low and the switch 33A7 is kept off.

Even when the input signal AIN falls at timing t32, the gate signal PGTA is still Low and the transistor PA is turned on. As a result, the input signal AIN tends to drop to Vd, which is the voltage obtained by dividing VCCA by the on-resistance of the transistor PA and the terminating resistor Re. At this time, the inverter 35A1 (fall detection unit 35A) can detect the fall of the input signal AIN going to Low.

Here, the inverter 35A1 has a CMOS configuration including a transistor PM made up of a p-channel MOSFET and a transistor NM made up of an n-channel MOSFET as shown in FIG. Since the transistor PM has a lower Vgs threshold than the transistor NM, it can detect a small falling change in the signal at the signal terminal Tda. At this time, since the output of the inverter 35A1 becomes High, the output VAND becomes High and the switch 33A7 is turned on.

This bypasses the resistor 33A2 and reduces the time constant of the CR circuit. Therefore, as shown in FIG. 13, the output CRA decreases with a relatively large slope at timing t32, and when it reaches a predetermined threshold level CR_TH at timing t33, the gate signal PGTA becomes High. As a result, as shown in FIG. 13, the pulse width (predetermined time width TWA) of the gate signal PGTA can be shortened by ΔW from the original pulse width when it is reduced by the time constant before the output CRA is reduced. .

Therefore, the transistor PA is turned off and the input signal AIN falls to Low. As a result, in the one-shot circuit 3B shown in FIG. 11, the output of the AND circuit 32B5 becomes Low and the gate signal PGTB becomes High, thereby turning off the transistor PB. At this time, since the input signal AIN is Low, the gate signal NGT is set to High by the gate drive circuit 2, and the transistor N1 is turned on. Therefore, the output signal BOUT is set to the same Low level as the input signal AIN.

At timing t33, the output signal BOUT becomes Low, so the mask signal MSK1 becomes High. Since the input signal AIN is Low, the output of the inverter 35A1 becomes High, the output VAND becomes High, and the switch 33A7 is turned on. Since the output signal BOUT is Low, the output of the inverter 33A1 in the one-shot circuit 3A becomes High. Therefore, the resistor 33A2 is bypassed and the output CRA of the CR circuit starts rising according to the time constant of the resistor 33A3 and capacitor 33A4.

When the input power supply voltage VA rises at timing t34 before the output CRA reaches a predetermined maximum level CR_MAX, the input signal AIN also rises VCCA. As a result, the output of the AND circuit 32B5 in the one-shot circuit 3B becomes High, and the gate signal PGTB becomes Low. This turns on the transistor PB and the output signal BOUT rises to VCCB.

Then, in the one-shot circuit 3A, the output of the AND circuit 33A5 becomes High, and the gate signal PGTA becomes Low. This turns on the transistor PA. At this time, since the mask signal MSK1 falls to Low, the output VAND becomes Low and the switch 33A7 is turned off. At this time, the output of the inverter 33A1 becomes Low, and the output CRA of the CR circuit starts decreasing according to the time constant of the resistors 33A2, 33A3 and the capacitor 33A4.

After that, when the output CR1 drops and reaches a certain level at timing t35, the mask signal MSK1 is set to High. However, since the input signal AIN is High, the output VAND becomes Low and the switch 33A7 is kept off.

When the output CRA reaches the threshold level CR_TH at timing t36, the output of the AND circuit 33A5 becomes Low, the gate signal PGTA becomes High, and the transistor PA is turned off. As a result, when the input power supply voltage VA falls at timing t37, the input signal AIN also falls to Low. Therefore, the gate signal PGTB becomes High by the one-shot circuit 3B, and the transistor PB is turned off. At this time, since the input signal AIN is Low, the gate signal NGT is set to High by the gate drive circuit 2, and the transistor N1 is turned on. Therefore, the output signal BOUT is set to the same Low level as the input signal AIN.

In this way, the responsiveness of the output signal BOUT to the high-frequency input power supply voltage VA can be improved. In particular, after timing t33, the input power supply voltage VA rises before the output CRA reaches the maximum level CR_MAX, and the output CRA drops, so the pulse width (predetermined time width TWA) of the gate signal PGTA automatically shortens. . As a result, the input signal AIN can be lowered to Low in accordance with the fall of the input power supply voltage VA, and the responsiveness of the output signal BOUT can be improved. However, an embodiment may be adopted in which the output CRA is immediately raised to the maximum level CR_MAX at timing t33. It should be noted that even if the inputs and outputs of FIG. 8 are reversed, the operation is the same as described above, and the responsiveness of the output signal of the signal terminal Tda to the high-frequency input power supply voltage from the power supply connected to the signal terminal Tdb can be improved.

<8. Modified example of one-shot circuit>
The one-shot circuits 3A and 3B may be modified as follows. FIG. 14 is a circuit diagram showing the configuration of a one-shot circuit 3A' according to a modification. The difference between the one-shot circuit 3A' and the one-shot circuit 3A (FIG. 10) is the configuration of the trailing edge detection section 35A'.

The trailing edge detection section 35A' is composed of a comparator 35A1'. A signal terminal Tda is connected to the inverting input terminal (-) of the comparator 35A1', and a reference voltage is applied to the non-inverting input terminal (+). The comparator 35A1' outputs the comparison result between the signal of the signal terminal Tda and the reference voltage to the AND circuit 36A. As a result, when the signal terminal Tda falls to Low, the comparator 35A1' outputs High to turn on the switch 33A7.

FIG. 15 is a circuit diagram showing the configuration of a one-shot circuit 3B' according to the modification. The difference between the one-shot circuit 3B' and the one-shot circuit 3B (FIG. 11) is the configuration of the trailing edge detection section 34B'.

The fall detection section 34B' is composed of a comparator 34B1'. A signal terminal Tdb is connected to the inverting input terminal (-) of the comparator 34B1', and a reference voltage is applied to the non-inverting input terminal (+). The comparator 34B1' outputs the comparison result between the signal of the signal terminal Tdb and the reference voltage to the AND circuit 35B. As a result, when the signal terminal Tdb falls to Low, the comparator 34B1' outputs High to turn on the switch 32B8.

Using the comparator as the falling edge detection unit in this way can improve the accuracy of the detection threshold. However, the use of an inverter as the trailing edge detection unit is more advantageous from the viewpoint of cost reduction.

<9. Layout in Chip>
FIG. 16 is a schematic diagram showing an example layout of the bidirectional level shift circuit 1 on the chip CP. The chips CP extend in the X-axis direction and the Y-axis direction that are orthogonal to each other. In FIG. 16, one side in the X-axis direction is indicated by X1 and the other side by X2, and one side in the Y-axis direction is indicated by Y1 and the other side by Y2. The X2 side and the Y2 side are directions in which they approach each other.

A transistor N1 is arranged at the end of the chip CP on the X1 side. A gate drive circuit 2 is arranged adjacent to the X2 side of the transistor N1. The gate drive circuit 2 is sandwiched in the Y-axis direction by the resistor RB and the resistor RA. The resistor RB is arranged on the Y1 side of the resistor RA. Transistors PA and PB are arranged on the X2 side of gate drive circuit 2 . The transistor PB is arranged closer to the Y1 side than the transistor PA.

At the X2 side end of the chip CP, capacitors 33B3, 32B4, 33A4, and 34A3 are arranged adjacently in this order toward the Y2 side to form one first group. Capacitors 33B3 and 32B4 are provided in one-shot circuit 3B (FIG. 11) as described above, and capacitors 33A4 and 34A3 are provided in one-shot circuit 3A (FIG. 10) as described above. By arranging the capacitors 33B3, 32B4, 33A4, and 34A3 so as to form one group, relative variations are reduced.

The resistors 32B3 and 32B2 are arranged adjacently in this order toward the X2 side to form one second group. The second group is arranged on the Y1 side of the first group. The resistors 32B3 and 32B2 are provided in the one-shot circuit 3B (FIG. 11) as described above. This reduces relative variations in the resistors 32B3 and 32B2.

The resistors 33A3 and 33A2 are arranged adjacently in this order toward the X2 side to form one third group. The third group is arranged on the Y2 side of the first group. The resistors 33A3 and 33A2 are provided in the one-shot circuit 3A (FIG. 10) as described above. This reduces relative variations in the resistors 33A3 and 33A2.

In addition, the signal terminal Tdb is arranged on the Y1 side of the transistor PB and on the X2 side of the resistor RB when viewed from above. The signal terminal Tda is arranged on the Y2 side of the transistor PA and on the X2 side of the resistor RA when viewed from above. The power supply terminal Tvb to which VCCB is applied is arranged on the X2 side of the signal terminal Tdb in top view, and is arranged adjacent to the X1 side of the second group. The power supply terminal Tva to which VCCA is applied is arranged on the X2 side of the signal terminal Tda in top view, and is arranged adjacent to the X1 side of the third group. Further, the ground terminal Tgd is sandwiched between the signal terminal Tda and the power terminal Tva in the X-axis direction.

Each of the signal terminals Tdb, Tda and the power terminals Tvb, Tva overlaps the ESD protection diode when viewed from above.

<10. Application example of the system>
FIG. 17 is a configuration diagram showing an application example of the data communication system shown in FIG. In the example of FIG. 17, an HDD (hard disk drive) 30 is provided with a system controller 20A and a bidirectional level shift circuit 1, and a tester 40 is provided with a system controller 20B. Thus, the bidirectional level shift circuit 1 functions as an interface that enables data communication between system controllers that operate with different power supply voltages for the HDD 30 and the tester 40 .

<11. Others>
Although the embodiments of the present invention have been described above, various modifications of the embodiments are possible within the scope of the present invention.

INDUSTRIAL APPLICABILITY The present invention can be used in various systems operating with different power supply voltages.

1 bidirectional level shift circuit 2 gate drive circuit 3A, 3B one-shot circuit 31A level shift section 32A, 31B Schmitt trigger 33A, 32B one-shot pulse generation section 34A, 33B mask generation section 35A, 34B trailing edge detection section N1 transistor (n channel MOSFET)
PA, PB Transistor (p-channel MOSFET)
RA, RB resistors Tva, Tvb power terminals Tda, Tdb signal terminals Re termination resistors 20A, 20B system controller 30 HDD (hard disk drive)
40 tester 50 power supply

Claims (13)

a first signal terminal;
a second signal terminal;
a first power supply terminal to which the first power supply voltage is applied;
a second power supply terminal to which a second power supply voltage is applied;
a first pull-up resistor connected between the first power terminal and the first signal terminal;
a second pull-up resistor connected between the second power terminal and the second signal terminal;
a first transistor connected across the first pull-up resistor;
a second transistor connected across the second pull-up resistor;
a third transistor arranged between the first signal terminal and the second signal terminal;
a driving circuit for driving the control terminal of the third transistor;
a first one-shot circuit for generating a first drive signal for driving a control end of the first transistor;
a second one-shot circuit for generating a second drive signal for driving the control end of the second transistor;
with
The second one-shot circuit generates a one-shot pulse of the second drive signal that is turned on for a predetermined second time width based on the rising edge of the signal at the first signal terminal, and outputs the signal at the first signal terminal. generating the off-level second drive signal based on the falling edge of
The first one-shot circuit is
A first CR circuit is included, and a one-shot pulse of the first drive signal is generated based on the rising edge of the signal at the second signal terminal and turned on for a predetermined first time width corresponding to the time constant of the first CR circuit. a one-shot pulse generator;
a fall detection unit that detects the fall of the signal of the first signal terminal and changes the time constant of the first CR circuit to be smaller based on the detection result;
Bi-directional level shift circuit. The fall detection unit is a first inverter having a CMOS configuration with a p-channel MOSFET and an n-channel MOSFET,
2. The bi-directional level shift circuit of claim 1, wherein the p-channel MOSFET has a lower Vgs threshold than the n-channel MOSFET. 2. The bi-directional level shift circuit according to claim 1, wherein said fall detector is a comparator that compares the signal of said first signal terminal with a reference voltage. 2. The first one-shot circuit further comprises a mask generation section for generating a mask signal for masking the detection result of the fall detection section for a predetermined period when the signal at the second signal terminal rises. 4. The bi-directional level shift circuit according to any one of claims 3 to 4. 5. The bidirectional level shift circuit according to claim 4, wherein said mask generating section has a second CR circuit that determines said predetermined period by a time constant. The mask generation unit
a NAND circuit having one input terminal electrically connected to the second signal terminal and the other input terminal connected to the output terminal of the second CR circuit;
a second inverter having an input terminal electrically connected to the second signal terminal and an output terminal connected to the input terminal of the second CR circuit;
6. The bi-directional level shift circuit of claim 5, further comprising: The one-shot pulse generator has a switch connected across a resistor included in the first CR circuit,
7. The bidirectional level shift circuit according to any one of claims 1 to 6, wherein said switch is ON/OFF-controlled according to a detection result of said falling edge detection section. The one-shot pulse generator is
an AND circuit having one input terminal electrically connected to the second signal terminal and the other input terminal connected to the output terminal of the first CR circuit;
a third inverter having an input terminal electrically connected to the second signal terminal and an output terminal connected to the input terminal of the first CR circuit;
a fourth inverter having an input terminal connected to the output terminal of the AND circuit;
8. The bi-directional level shift circuit of claim 7, further comprising: The second power supply voltage is higher than the first power supply voltage,
The first one-shot circuit is supplied with the first power supply voltage as a power supply,
The first one-shot circuit further includes a level shifter for level-shifting the signal of the second signal terminal from the second power supply voltage to the first power supply voltage on the preceding stage side of the one-shot pulse generator. 9. A bidirectional level shift circuit as claimed in any one of claims 1 to 8, comprising: 10. The bi-directional level shift circuit of claim 9, wherein said first one-shot circuit further comprises a Schmitt trigger arranged between said level shifter and said one-shot pulse generator. 11. The bi-directional level shifter circuit according to any one of claims 1 to 10, wherein in a chip a plurality of resistors included in said first CR circuit are arranged adjacent to each other to form a first group. 7. The chip according to claim 5, wherein the first capacitor included in the first CR circuit and the second capacitor included in the second CR circuit are arranged adjacently to form a second group. Bi-directional level shift circuit. a bidirectional level shift circuit according to any one of claims 1 to 12;
a first system operated by the first power supply voltage;
a second system operated by the second power supply voltage;
A data communication system comprising:

Images