JP2021019167A - Electronic component built-in substrate and method for manufacturing the same - Google Patents

Abstract

To prevent separation of an electronic component in an electronic component built-in substrate with an electronic component such as a semiconductor IC buried in a phase-up system.SOLUTION: An electronic component built-in substrate 1 includes: a substrate formed by depositing wiring layers L1 to L4 and insulating layers 11 to 14; and an electronic component 40 having a back surface 44 and a side surface 43 located in an opposite side to a main side 42 where a terminal electrode 41 is formed, the electronic component being buried in the substrate so that the back surface 44 is covered by an insulating layer 13 and the main surface 42 and the side surface 43 are covered by the insulating film 12. The back surface 44 and the side surface 43 of the electronic component 40 are covered with a metal film 50. Since not only the back surface 44 but also the side surface 43 of the electronic component 40 are covered with a metal film 50, it becomes possible to prevent separation in a corner part as the interface between the back surface 44 and the side surface 43.SELECTED DRAWING: Figure 1

Description

The present invention relates to an electronic component-embedded substrate and a method for manufacturing the same, and more particularly to an electronic component-embedded substrate in which electronic components such as a semiconductor IC are embedded by a face-up method and a method for manufacturing the same.

As an electronic component-embedded substrate in which electronic components such as a semiconductor IC are embedded by a face-up method, the electronic component-embedded substrates described in Patent Documents 1 and 2 are known. However, since the silicon material constituting the semiconductor IC has low adhesion to the resin material constituting the insulating layer, when the temperature rises due to the operation of the semiconductor IC, stress due to the difference in the coefficient of thermal expansion occurs, and the semiconductor IC And peeling may occur at the interface of the insulating layer.

Here, in the electronic component-embedded substrate described in Patent Document 2, since the back surface of the semiconductor IC is covered with a metal film, the metal film functions as an adhesion layer, and peeling on the back surface of the semiconductor IC is unlikely to occur. Become.

Japanese Unexamined Patent Publication No. 2011-205853 JP-A-2007-150002

However, when the semiconductor IC is embedded by the face-up method, the portion most easily peeled off is the corner portion that is the boundary between the back surface and the side surface of the semiconductor IC, and the peeling in this portion simply forms a metal film on the back surface of the semiconductor IC. It was difficult to prevent it just by doing it.

Therefore, an object of the present invention is to more effectively prevent peeling of electronic components in an electronic component-embedded substrate in which electronic components such as semiconductor ICs are embedded by a face-up method and a method for manufacturing the same.

The substrate for incorporating electronic components according to the present invention is a substrate in which a plurality of wiring layers and a plurality of insulating layers including at least the first and second insulating layers are laminated, and the opposite of the main surface and the main surface on which the terminal electrodes are formed. It has a back surface located on the side and a main surface and a side surface perpendicular to the back surface, and is embedded in the substrate so that the back surface is covered with the first insulating layer and the main surface and the side surface are covered with the second insulating layer. It is characterized in that the back surface and the side surface of the electronic component are covered with a metal film.

According to the present invention, since not only the back surface of the electronic component but also the side surface is covered with the metal film, it is possible to prevent peeling at the corner portion which is the boundary between the back surface and the side surface.

In the present invention, the thickness of the metal film formed on the side surface of the electronic component may become thinner from the back surface side to the main surface side. According to this, since the region near the corner where the filler is difficult to enter is filled with the metal film, it is possible to alleviate the difference in the coefficient of thermal expansion.

In the present invention, the side surface of the electronic component may have a lower region located on the back surface side and covered with a metal film and an upper region located on the main surface side and not covered with the metal film. According to this, the metal film does not wrap around the main surface of the electronic component.

In the present invention, the upper region may protrude from the lower region. Such a structure is obtained by half-cutting a wafer or an assembly substrate on which electronic components are formed from the back surface side, and it is possible to reliably prevent the metal film from wrapping around to the main surface side.

In the method for manufacturing an electronic component-embedded substrate according to the present invention, an electronic component having a main surface on which terminal electrodes are formed, a back surface located on the opposite side of the main surface, and a side surface perpendicular to the main surface and the back surface is prepared. The back surface is a first insulating layer on a substrate in which a metal film is formed on the back surface and the side surface, and a plurality of wiring layers and a plurality of insulating layers including at least the first and second insulating layers are laminated. It is characterized by comprising a step of embedding an electronic component so as to be covered and the main surface and the side surface are covered with a second insulating layer.

According to the present invention, not only the back surface of the electronic component but also the side surface thereof is covered with the metal film, so that it is possible to prevent peeling at the corner portion of the electronic component.

In the present invention, the step of forming the metal film may be performed in a state where a part of the side surface is exposed by half-cutting the wafer or the collective substrate on which the electronic component is formed from the back surface side. According to this, it is possible to surely prevent the metal film from wrapping around to the main surface side.

As described above, according to the present invention, it is possible to more effectively prevent the peeling of the electronic component in the electronic component built-in substrate in which the electronic component such as the semiconductor IC is embedded by the face-up method and the manufacturing method thereof.

FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention. FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component 40. FIG. 3 is a schematic diagram for explaining a first method of forming the metal film 50 on the electronic component 40. FIG. 4 is a schematic diagram for explaining a second method of forming the metal film 50 on the electronic component 40. FIG. 5 is a schematic diagram for explaining the shape of the electronic component 40 created by the method shown in FIG. FIG. 6 is a schematic diagram for explaining a third method of forming the metal film 50 on the electronic component 40. FIG. 7 is a schematic diagram for explaining a fourth method of forming the metal film 50 on the electronic component 40. FIG. 8 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 9 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 10 is a process diagram for explaining a method of manufacturing the electronic component built-in substrate 1. FIG. 11 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 12 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 13 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 14 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 15 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 16 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 17 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 18 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 19 is a process diagram for explaining a method of manufacturing the electronic component built-in substrate 1. FIG. 20 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention.

As shown in FIG. 1, the electronic component-embedded substrate 1 according to the present embodiment has four insulating layers 11 to 14, wiring layers L1 to L4 formed on the surfaces of the insulating layers 11 to 14, and wiring layers L2, respectively. An electronic component 40 embedded between the wiring layer L3 and the wiring layer L3 is provided. Although not particularly limited, the insulating layer 11 located at the top layer and the insulating layer 14 located at the bottom layer are core layers in which a core material such as glass fiber is impregnated with a resin material such as glass epoxy. It doesn't matter. On the other hand, the insulating layers 12 and 13 may be made of a resin material that does not contain a core material such as glass cloth. In particular, the coefficient of thermal expansion of the insulating layers 11 and 14 is preferably smaller than the coefficient of thermal expansion of the insulating layers 12 and 13.

The type of the electronic component 40 is not particularly limited, but may be, for example, a semiconductor IC in a bare chip state. In the example shown in FIG. 1, the electronic component 40 is embedded in a face-up manner so that the main surface 42 on which the terminal electrode 41 is formed faces upward. Therefore, the main surface 42 and the side surface 43 of the electronic component 40 are covered with the insulating layer 12, and the back surface 44 of the electronic component 40 is covered with the insulating layer 13.

The wiring layer L1 is a wiring layer located at the uppermost layer, and most of the wiring layer L1 is covered with the solder resist 21. A region of the wiring layer L1 that is not covered by the solder resist 21 constitutes an external terminal E1 on which chip components and the like are mounted. The wiring layer L4 is a wiring layer located at the lowest layer, and most of the wiring layer L4 is covered with the solder resist 22. A region of the wiring layer L4 that is not covered by the solder resist 22 constitutes an external terminal E2 that is connected to the motherboard via solder. On the other hand, the wiring layers L2 and L3 are located in the inner layer. Of these, the wiring layer L2 is located between the insulating layer 11 and the insulating layer 12, and the wiring layer L3 is located between the insulating layer 13 and the insulating layer 14. The wiring layer L1 and the wiring layer L2 are connected via the via conductor 31, the wiring layer L2 and the terminal electrode 41 of the electronic component 40 are connected via the via conductor 32, and the wiring layer L2 and the wiring layer L3 are connected via the via conductor. It is connected via 33, and the wiring layer L3 and the wiring layer L4 are connected via the via conductor 34.

FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component 40.

As shown in FIG. 2, in the electronic component 40 embedded in the substrate in the present embodiment, the entire surface of the back surface 44 and a part of the side surface 43 are covered with the metal film 50. The back surface 44 is a surface located on the opposite side of the main surface 42 and not provided with the terminal electrode 41. The side surface 43 is a surface perpendicular to the main surface 42 and the back surface 44. The metal film 50 has a single-layer structure or a laminated structure, and plays a role of enhancing the adhesion between the electronic component 40 and the insulating layers 12 and 13. The metal film 50 may have a single-layer structure made of copper (Cu), or may have a laminated structure in which thin layers made of titanium (Ti) or the like having high adhesion are provided on both sides of the copper (Cu). It doesn't matter. As described above, in the present embodiment, since the entire surface of the back surface 44 and a part of the side surface 43 of the electronic component 40 are covered with the metal film 50, it is the boundary between the back surface 44 and the side surface 43 where peeling is most likely to occur. The adhesion between the electronic component 40 and the insulating layers 12 and 13 in the vicinity of the corner portion is enhanced.

Although not particularly limited, in the example shown in FIG. 2, the side surface 43 of the electronic component 40 is partially covered with the metal film 50. Specifically, the side surface 43 of the electronic component 40 includes a lower region 43a located on the back surface 44 side and covered with the metal film 50 and an upper region 43b located on the main surface 42 side and not covered with the metal film 50. Have. According to this, since the metal film 50 does not wrap around to the main surface 42 side, it is possible to prevent the metal film 50 from coming into contact with the terminal electrode 41. Here, in order to further improve the adhesion, it is preferable that the ratio of the thickness L of the lower region 43a to the thickness T of the electronic component 40 is large, but if the ratio of the thickness L is too large, the metal film 50 is the main surface 42. It becomes easier to go around to the side. Considering this point, the L / T value is preferably in the range of 0.7 to 0.9.

Further, in the present embodiment, the thickness of the metal film 50 formed on the side surface 43 of the electronic component 40 becomes thinner from the back surface 44 side to the main surface 42 side. As a result, the angle θ formed by the front surface of the metal film 50 formed on the side surface 43 and the front surface of the metal film 50 formed on the back surface 44 is less than 90 °. As a result, as compared with the case where the angle θ is vertical, a filler having a small coefficient of thermal expansion such as silica contained in the insulating layer 12 is filled closer to the electronic component 40, so that the difference in the coefficient of thermal expansion is alleviated. Moreover, in the present embodiment, since the shape of the metal film 50 is rounded at the portion covering the corner portion of the electronic component 40, the adhesion between the metal film 50 and the insulating layer 12 is also enhanced.

The method of forming the metal film 50 on the electronic component 40 is not particularly limited, but since it is necessary to form the metal film 50 not only on the back surface 44 but also on the side surface 43, the wafer or the assembly substrate is individually separated. When a large number of electronic components 40 are taken, it is necessary to form the metal film 50 after the electronic components 40 are fragmented or the wafer or the assembly substrate is half-cut.

In the example shown in FIG. 3A, after the electronic component 40 is fragmented, sputtering is performed from the direction indicated by the arrow A in a state where the main surface 42 of the electronic component 40 is covered with the protective film 90. As a result, as shown in FIG. 3B, the metal film 50 can be selectively formed on the back surface 44 and the side surface 43 of the electronic component 40. In this case, since the side surface 43 of the electronic component 40 is horizontal with respect to the sputtering direction, the metal film 50 is less likely to be formed as the distance from the back surface 44 increases, and as a result, the shape shown in FIG. 2 can be obtained. It becomes.

In the example shown in FIG. 4A, the wafer 60 on which the electronic component 40 is formed is half-cut from the back surface 44 side to form a groove 61 on the wafer 60 to expose a part of the side surface 43. In this state, by performing sputtering from the direction indicated by the arrow A, a metal film 50 is formed on the back surface 44 of the electronic component 40 and the inner wall of the groove 61 as shown in FIG. 4 (b). After that, if the wafer 60 is cut along the dicing line 62 located in the groove 61, the metal film 50 can be selectively formed on the back surface 44 and the side surface 43 of the electronic component 40. In this case, as shown in FIG. 5, the electronic component 40 has a shape in which the upper region 43b protrudes from the lower region 43a.

Further, as shown in FIG. 6A, a mask pattern 63 is formed on the bottom surface of the groove 61 formed in the wafer 60 by half-cutting, and sputtering is performed in this state as shown in FIG. 6B. As a result, if the mask pattern 63 is removed as shown in FIG. 6C after the metal film 50 is formed, the metal film 50 adhering to the mask pattern 63 is lifted off. As a result, a region where the metal film 50 does not exist is formed on the bottom surface of the groove 61. Therefore, if the dicing line 62 is set along this region, contact between the blade used for dicing and the metal film 50 can be prevented. It will be possible.

Alternatively, as shown in FIG. 7A, after forming the metal film 50 by performing sputtering in a state where the groove 61 is formed in the wafer 60 by half-cut, the groove 61 is formed as shown in FIG. 7B. The mask pattern 64 may be formed so that a part of the bottom portion of the wafer is exposed, and the exposed metal film 50 may be removed from the mask pattern 64 as shown in FIG. 7 (c). As a result, a region where the metal film 50 does not exist is formed on the bottom surface of the groove 61. Therefore, if the dicing line 62 is set along this region, contact between the blade used for dicing and the metal film 50 can be prevented. It will be possible.

The electronic component 40 produced in this way is embedded inside the substrate by the steps described below.

8 to 20 are process diagrams for explaining the manufacturing method of the electronic component built-in substrate 1 according to the present embodiment.

First, as shown in FIG. 8, a base material having a metal film L3a formed on one surface of an insulating layer 14 containing a core material such as glass fiber and a laminated film of metal films L4a and L4b formed on the other surface. (Workboard) is prepared and attached to a support 70 made of stainless steel or the like via a release layer 71.

Next, as shown in FIG. 9, the wiring layer L3 is formed by patterning the metal film L3a by using a photolithography method or the like. Next, as shown in FIG. 10, the insulating layer 13 is formed by laminating, for example, an uncured (B stage state) resin sheet or the like on the surface of the insulating layer 14 by vacuum pressure bonding or the like so as to embed the wiring layer L3. To do.

Next, as shown in FIG. 11, an electronic component 40 having a metal film 50 formed on the surface of the insulating layer 13 is placed. The electronic component 40 is, for example, a semiconductor IC in a bare chip state, and is mounted in a face-up manner so that the main surface 42 on which the terminal electrode 41 is formed faces upward. Therefore, the metal film 50 is interposed between the back surface 44 of the electronic component 40 and the insulating layer 13.

Next, as shown in FIG. 12, the insulating layer 12 and the metal film L2a are formed so as to cover the electronic component 40. As a result, the side surface 43 of the electronic component 40 is covered with the insulating layer 12 directly or via the metal film 50. The insulating layer 12 is formed, for example, by applying a thermosetting resin in an uncured or semi-cured state, heating the uncured resin to semi-cure it, and further using a pressing means together with the metal film L2a. Curing molding is preferable. As the insulating layer 12, a resin sheet that does not contain fibers that hinder the embedding of the electronic component 40 is desirable.

Next, as shown in FIG. 13, after removing a part of the metal film L2a by etching using a known method such as a photolithography method, a known blast is applied to a predetermined portion from which the metal film L2a has been removed. Via holes 82 and 83 are formed by processing or laser processing. Of these, the via hole 83 is provided so as to penetrate the insulating layers 12 and 13, and the wiring layer L3 is exposed at the bottom of the via hole 83. Further, the via hole 82 exposes the terminal electrode 41 of the electronic component 40.

Next, as shown in FIG. 14, by performing electroless plating and electrolytic plating, a metal film L2b is formed on the surface of the insulating layer 12, and via conductors 32 and 33 are formed inside the via holes 82 and 83, respectively. To do. Then, as shown in FIG. 15, the wiring layer L2 is formed by patterning the metal film L2b using a photolithography method or the like.

Next, as shown in FIG. 16, a sheet in which the insulating layer 11 and the metal films L1a and L1b are laminated is vacuum-heat pressed so as to embed the wiring layer L2. The material and thickness used for the insulating layer 11 may be the same as that of the insulating layer 14. Next, as shown in FIG. 17, the substrate is separated from the support 70 by peeling off the interface between the metal films L1a and L1b and peeling off the interface between the metal films L4a and L4b.

Next, as shown in FIG. 18, after a part of the metal films L1a and L4a is removed by etching using a known method such as a photolithography method, the metal films L1a and L4a are removed from the predetermined portion. The via hole 81 is formed in the insulating layer 11 and the via hole 84 is formed in the insulating layer 14 by performing a known blasting process or laser processing. The via hole 81 is provided so as to penetrate the insulating layer 11, and the wiring layer L2 is exposed at the bottom of the via hole 81. Further, the via hole 84 is provided so as to penetrate the insulating layer 14, and the wiring layer L3 is exposed at the bottom of the via hole 84.

Next, as shown in FIG. 19, by performing electroless plating and electrolytic plating, metal films L1c and L4c are formed on the surfaces of the insulating layers 11 and 14, respectively, and via conductors are formed inside the via holes 81 and 84, respectively. Form 31, 34. As a result, the via conductor 31 is in contact with the wiring layer L2, and the via conductor 34 is in contact with the wiring layer L3. Then, as shown in FIG. 20, the wiring layers L1 and L4 are formed by patterning the metal films L1c and L4c by using a photolithography method or the like.

Then, if solder resists 21 and 22 are formed on the surfaces of the insulating layers 11 and 14, respectively, the electronic component-embedded substrate 1 shown in FIG. 1 is completed.

As described above, in the present embodiment, the electronic component 40 having the metal film 50 formed on the back surface 44 and the side surface 43 is placed on the surface of the insulating layer 13 by a face-up method, and then the electronic component 40 is mounted by the insulating layer 12. Since it is embedded, it is possible to improve the adhesion at the corners of the electronic component 40, which is most likely to be peeled off. As a result, even if the temperature rises due to the operation of the electronic component 40, it is possible to prevent the electronic component 40 and the insulating layers 12 and 13 from peeling off due to the difference in the coefficient of thermal expansion.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and these are also the present invention. It goes without saying that it is included in the range.

1 Electronic component built-in substrate 11-14 Insulation layer 21 and 22 Solder resist 31-34 Via conductor 40 Electronic component 41 Terminal electrode 42 Main surface 43 Side surface 43a Lower area 43b Upper area 44 Back surface 50 Metal film 60 Wafer 61 Groove 62 Dicing line 63 , 64 Mask pattern 70 Support 71 Peeling layer 81-84 Via hole 90 Protective film E1, E2 External terminals L1 to L4 Wiring layer L1a to L1c, L2a, L2b, L3a, L4a to L4c Metal film

Claims (6)

A substrate in which a plurality of wiring layers and a plurality of insulating layers including at least the first and second insulating layers are laminated.
It has a main surface on which terminal electrodes are formed, a back surface located on the opposite side of the main surface, and a side surface perpendicular to the main surface and the back surface, and the back surface is covered with the first insulating layer. An electronic component embedded in the substrate so that the main surface and the side surface are covered with the second insulating layer.
An electronic component-embedded substrate, characterized in that the back surface and the side surface of the electronic component are covered with a metal film. The electronic component-embedded substrate according to claim 1, wherein the thickness of the metal film formed on the side surface of the electronic component decreases from the back surface side toward the main surface side. A claim characterized in that the side surface of the electronic component has a lower region located on the back surface side and covered with the metal film and an upper region located on the main surface side and not covered with the metal film. Item 2. The electronic component built-in substrate according to item 2. The electronic component built-in substrate according to claim 3, wherein the upper region protrudes from the lower region. An electronic component having a main surface on which terminal electrodes are formed, a back surface located on the opposite side of the main surface, and a side surface perpendicular to the main surface and the back surface is prepared, and a metal film is formed on the back surface and the side surface. The process of forming and
The back surface is covered with the first insulating layer, and the main surface and the side surface are the first surface on a substrate formed by laminating a plurality of wiring layers and a plurality of insulating layers including at least the first and second insulating layers. A method for manufacturing a substrate containing an electronic component, which comprises a step of embedding the electronic component so as to be covered with the insulating layer of 2. 5. The step of forming the metal film is performed in a state where a part of the side surface is exposed by half-cutting the wafer or the assembly substrate on which the electronic component is formed from the back surface side. The method for manufacturing a substrate with built-in electronic components described in 1.

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