JP2021009955A - Semiconductor device - Google Patents

Abstract

To effectively alleviate concentration of stress generated at a triple point in a semiconductor device.SOLUTION: A semiconductor device disclosed in the present specification comprises: a semiconductor substrate; a first electrode film; a second electrode film; and a protective film. The first electrode film is provided on the semiconductor substrate, and the second electrode film is provided on the first electrode film. The protective film is provided next to the second electrode film, on the first electrode film, and brought into contact with a side surface of the second electrode film. The side surface of the second electrode film has an at least partially uneven shape.SELECTED DRAWING: Figure 3

Description

The techniques disclosed herein relate to semiconductor devices.

Patent Document 1 discloses a semiconductor device. The semiconductor device is adjacent to the semiconductor substrate, the first electrode film provided on the semiconductor substrate, the second electrode film provided on the first electrode film, and the second electrode film on the first electrode film. It is provided with a protective film that comes into contact with the side surface of the second electrode film. This semiconductor device is used, for example, in a semiconductor module, and a conductor member constituting the semiconductor module is bonded to the second electrode film via a solder layer.

JP-A-2015-23305

In a semiconductor module, the temperature of a component including a semiconductor device fluctuates repeatedly by intermittently energizing the semiconductor module. If a large stress is generated inside the semiconductor device when this temperature fluctuation is repeated, the semiconductor device may be damaged. In this regard, in the above-mentioned semiconductor device, the second electrode film and the protective film are provided adjacent to each other on the first electrode film, and there is a triple point where three kinds of different materials constituting them gather together. At such triple points, stress is particularly likely to concentrate. Therefore, the present specification provides a technique capable of relaxing the concentration of stress generated at the triple point.

The semiconductor device disclosed in the present specification includes a semiconductor substrate, a first electrode film, a second electrode film, and a protective film. The first electrode film is provided on the semiconductor substrate, and the second electrode film is provided on the first electrode film. The protective film is provided on the first electrode film adjacent to the second electrode film, and comes into contact with the side surface of the second electrode film. The side surface of the second electrode film has an uneven shape at least partially.

In the above-mentioned semiconductor device, the side surface of the second electrode film in contact with the protective film has an uneven shape at least partially. Therefore, the protective film and the second electrode film are firmly adhered to each other by the anchor effect. As a result, the relative displacement of the semiconductor device due to temperature fluctuation is suppressed between the protective film and the second electrode film. In particular, the uneven shape is provided on the side surface of the second electrode film and is close to the triple point. As a result, the stress concentration at the triple point can be effectively relaxed.

FIG. 5 is a plan view showing the appearance of the semiconductor module 10 in which the semiconductor element 12 of the first embodiment is incorporated. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. Enlarged view in Part III of FIG. FIG. 5 is a cross-sectional view showing some modifications of the concave-convex shape 40d of the second electrode film 40. FIG. 5 is a cross-sectional view schematically showing a step of forming a first electrode film 38 and a second electrode film 40 on a semiconductor substrate 12a. The figure which shows typically the process of forming the resist film 44 on the exposed first electrode film 38 and the second electrode film 40, respectively. The figure which shows typically the process of forming the concave-convex shape 40d on the side surface 40c of the 2nd electrode film 40. The figure which shows typically the process of removing a resist film 44. The figure which shows typically the process of applying the resin solution 43s on the semiconductor substrate 12a (the first electrode film 38 and the second electrode film 40). The figure which shows typically the process of prebaking the semiconductor substrate 12a on which the resin film 43 was formed. The figure which shows typically the process of the exposure processing of the prebaked semiconductor substrate 12a. The figure which shows typically the process of developing a semiconductor substrate 12a which has been exposed. The figure which shows typically the process of post-baking the developed semiconductor substrate 12a. FIG. 5 is a cross-sectional view showing the internal structure of the semiconductor element 112 of the second embodiment.

(Example 1) With reference to the drawings, a method of manufacturing the semiconductor module 10 and the semiconductor element 12 incorporating the semiconductor element 12 of the first embodiment will be described. Here, the semiconductor element 12 is an example of a semiconductor device in the technology disclosed in the present specification. The semiconductor module 10 of this embodiment is adopted in, for example, a power control device for an electric vehicle, and can form a part of a power conversion circuit such as a converter or an inverter. The electric vehicle in the present specification broadly means an electric vehicle having a motor for driving wheels, and for example, an electric vehicle charged by an external electric power, a hybrid vehicle having an engine in addition to the motor, and a fuel cell as a power source. Includes fuel cell vehicles, etc.

As shown in FIG. 1, the semiconductor module 10 includes a plurality of semiconductor elements 12, a sealing body 20, a plurality of power terminals 22, 24, 26, and a plurality of signal terminals 28, 30. The plurality of semiconductor elements 12 are sealed inside the sealing body 20. The sealing body 20 is constructed by using a thermosetting resin material such as an epoxy resin. The sealing body 20 has a first main surface 20a, a second main surface 20b located on the opposite side of the first main surface 20a, and a side surface 20c extending between the first main surface 20a and the second main surface 20b. Have. The plurality of power terminals 22, 24, 26 and the plurality of signal terminals 28, 30 extend inside and outside the sealing body 20 on the side surface 20c of the sealing body 20. Each of the power terminals 22, 24, and 26 is electrically connected to at least one semiconductor element 12 inside the sealing body 20. Each of the signal terminals 28 and 30 is electrically connected to a signal pad (not shown) of at least one semiconductor element 12 by wire bonding, for example.

As shown in FIG. 2, the semiconductor module 10 includes a plurality of conductor spacers 14, a plurality of first heat radiating plates 16, and a plurality of second heat radiating plates 18. The first heat radiating plate 16 and the second heat radiating plate 18 face each other with the semiconductor element 12 interposed therebetween. The plurality of conductor spacers 14, the plurality of first heat radiating plates 16, and the plurality of second heat radiating plates 18 are integrally sealed inside the sealing body 20. Each of the first heat radiating plates 16 is exposed on the first main surface 20a of the sealing body 20, and each second heat radiating plate 18 is exposed on the second main surface 20b of the sealing body 20. Therefore, the first heat radiating plate 16 and the second heat radiating plate 18 function as heat radiating plates that dissipate the heat generated by each semiconductor element 12 to the outside. Each conductor spacer 14 is inserted between the semiconductor element 12 and the second heat radiating plate 18.

The semiconductor element 12 includes a semiconductor substrate 12a, a top electrode 12b, and a bottom electrode 12c. The upper surface electrode 12b is located on the upper surface of the semiconductor substrate 12a, and the lower surface electrode 12c is located on the lower surface of the semiconductor substrate 12a. The semiconductor substrate 12a is constructed using, for example, silicon carbide (SiC). However, the semiconductor substrate 12a is not limited to silicon carbide, and can be configured by using various semiconductor materials such as silicon (Si) and gallium nitride (GaN). For the upper surface electrode 12b and the lower surface electrode 12c, for example, aluminum-based or other metal can be adopted. The semiconductor element 12 is a power semiconductor element, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the specific configuration of the semiconductor element 12 is not limited. The semiconductor element 12 is not limited to the IGBT, and other power semiconductor elements such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode may be adopted. Further, the semiconductor element 12 is not limited to a configuration consisting of a single power semiconductor element, and may be configured by combining different types of power semiconductor elements such as an RC-IGBT (Reverse Conducting IGBT) containing an IGBT and a diode. .. Alternatively, the semiconductor element 12 may be configured by combining a MOSFET and a diode.

The conductor spacer 14 generally has a block shape and is formed using a conductor material such as copper. The conductor spacer 14 has an upper surface 14a and a lower surface 14b located on the opposite side of the upper surface 14a. The lower surface 14b of the conductor spacer 14 is bonded to the upper surface electrode 12b of the semiconductor element 12 via the solder layer 34. The upper surface 14a of the conductor spacer 14 is joined to the lower surface 18b of the second heat radiating plate 18, which will be described later, via the solder layer 36. Although not particularly limited, the conductor spacer 14 secures a space for connecting (for example, wire bonding) a plurality of signal terminals 28 and 30 to a signal pad (not shown) of the semiconductor element 12.

The first heat radiating plate 16 and the second heat radiating plate 18 generally have a rectangular parallelepiped shape, and are formed by using a conductor material such as copper. The first heat radiating plate 16 has an upper surface 16a and a lower surface 16b located on the opposite side of the upper surface 16a. The lower surface 16b of the first heat radiating plate 16 is exposed on the first main surface 20a of the sealing body 20. The upper surface 16a of the first heat radiation plate 16 is joined to the lower surface electrode 12c of the semiconductor element 12 via the solder layer 32. As a result, the first heat radiating plate 16 is electrically and thermally connected to the semiconductor element 12. Similarly, the second heat radiating plate 18 has an upper surface 18a and a lower surface 18b located on the opposite side of the upper surface 18a. The upper surface 18a of the second heat radiating plate 18 is exposed on the second main surface 20b of the sealing body 20. The lower surface 18b of the second heat radiating plate 18 is joined to the upper surface 14a of the conductor spacer 14 via the solder layer 36. Therefore, the second heat radiating plate 18 is electrically and thermally connected to the semiconductor element 12 via the conductor spacer 14. As a result, the first heat radiating plate 16 and the second heat radiating plate 18 also function as a part of the electric circuit of the semiconductor module 10.

The details of the semiconductor element 12 on the upper surface electrode 12b side will be described with reference to FIG. As shown in FIG. 4, the semiconductor element 12 includes a first electrode film 38 and a second electrode film 40. The first electrode film 38 is provided on the semiconductor substrate 12a, and the second electrode film 40 is provided on the first electrode film 38. A conductor spacer 14 is bonded to the second electrode film 40 via a solder layer 34. The second electrode film 40 has an upper surface 40a in contact with the solder layer 34, a lower surface 40b in contact with the first electrode film 38, and side surfaces 40c adjacent to the two surfaces 40a and 40b. Although not particularly limited, the side surface 40c of the second electrode film 40 has a fillet shape in which the cross-sectional area of the second electrode film 40 expands from the upper surface 40a to the lower surface 40b. The cross-sectional area referred to here indicates the cross-sectional area when the second electrode film 40 is cut perpendicularly in the thickness direction.

Further, the side surface 40c of the second electrode film 40 has an uneven shape 40d at least partially. The concave-convex shape 40d is provided, for example, over the entire circumference of the side surface 40c of the second electrode film 40 or partially. As an example, the concave-convex shape 40d is composed of a plurality of concave portions and / or a plurality of convex portions randomly arranged on the side surface 40c. However, the specific configuration of the concave-convex shape 40d is not particularly limited. The concave-convex shape 40d may be composed of a plurality of grooves and / or a plurality of ridges. The first electrode film 38 is made of, for example, an aluminum-based film or another metal. The second electrode film 40 is made of, for example, a nickel-based or other metal. The term "aluminum" as used herein refers to pure aluminum or an alloy containing aluminum as a main component (for example, aluminum-silicon), and the term "nickel" refers to pure nickel or an alloy containing nickel as a main component.

The semiconductor element 12 includes a protective film 42 that partially covers the top electrode 12b. The protective film 42 is provided on the first electrode film 38 adjacent to the second electrode film 40. The protective film 42 is in contact with the side surface 40c of the second electrode film 40 (particularly, the range having the uneven shape 40d of the side surface 40c). Further, the protective film 42 extends in a frame shape along the peripheral edge 12e of the semiconductor substrate 12a. The protective film 42 has an opening 42w, and the second electrode film 40 of the top electrode 12b is exposed to the outside of the semiconductor element 12 at the opening 42w. Therefore, the second electrode film 40 is bonded to the solder layer 34 through the opening 42w. The protective film 42 is a resin material having an insulating property, and is made of, for example, polyimide or the like. The protective film 42 has a function of maintaining the withstand voltage of the semiconductor element 12 and preventing foreign matter from coming into contact with the semiconductor element 12.

Generally, in the semiconductor module 10, the temperature of the component component including the semiconductor element 12 fluctuates repeatedly by intermittently energizing the semiconductor module 10. If a large stress is generated inside the semiconductor element 12 when this temperature fluctuation is repeated, the semiconductor element 12 may be damaged. In this regard, in the semiconductor element 12 described above, the second electrode film 40 and the protective film 42 are provided adjacent to each other on the first electrode film 38. Therefore, there is a triple point TP in which three different materials such as the first electrode film 38, the second electrode film 40, and the protective film 42 gather together. In such a triple point TP, stress tends to be particularly concentrated.

In view of the above problems, in the semiconductor element 12 of the first embodiment, the side surface 40c of the second electrode film 40 in contact with the protective film 42 has an uneven shape 40d at least partially. Therefore, the protective film 42 and the second electrode film 40 are firmly adhered to each other by the anchor effect. As a result, the relative displacement of the semiconductor element 12 due to the temperature fluctuation is suppressed between the protective film 42 and the second electrode film 40. In particular, the uneven shape 40d is provided on the side surface 40c of the second electrode film 40 and is close to the triple point TP. As a result, the stress concentration at the triple point TP can be effectively relaxed.

The concave-convex shape 40d provided on the second electrode film 40 is not limited to the shape illustrated in FIG. 3, and can be changed in various ways. As shown in FIGS. 4A to 4C, the concave-convex shape 40d may be composed of a plurality of grooves provided on the side surface 40c. The shape of the groove, the depth dimension of the groove, the width dimension of the groove, the distance between the grooves, and the number of grooves are not particularly limited. As an example, as shown in FIG. 4A, the cross-sectional shape of the groove may be generally rectangular. As shown in FIG. 4 (B), the cross-sectional shape of the groove may be generally semicircular, or as shown in FIG. 4 (C), the cross-sectional shape of the groove may be generally triangular. The cross-sectional shape of the groove referred to here indicates the cross-sectional shape when cut perpendicularly to the longitudinal direction of the groove. In addition, the position of the concave-convex shape 40d on the side surface 40c of the second electrode film 40 should have a short distance from the triple point TP. In this case, the stress concentration generated at the triple point TP can be relaxed more effectively. Further, the uneven shape 40d may be provided on the side surface 40c of the second electrode film 40 over the entire circumference. Alternatively, the uneven shape 40d may be partially provided in a range of the side surface 40c of the second electrode film 40, which is located at a plurality of corners of the upper surface electrode 12b, for example. Since stress is particularly likely to be concentrated on the corners, the stress generated at the triple point TP can be efficiently relieved.

A method for manufacturing the semiconductor element 12 will be described with reference to FIGS. 5 to 13. Here, in particular, the formation of the first electrode film 38, the second electrode film 40, and the protective film 42 of the upper surface electrode 12b will be described. Other configurations of the semiconductor device 12 can be manufactured using known techniques. However, the method described below is an example and is not limited to this. Here, the semiconductor substrate 12a is made of silicon carbide, and an oxide film (for example, silicon dioxide (SiO ₂ )) and a titanium-based metal film (for example, titanium nitride (TiN)) (not shown) and a titanium-based metal film (for example, titanium nitride (TiN)) are not shown on the semiconductor substrate 12a. / Titanium (Ti)) is formed.

As shown in FIG. 5, after the first electrode film 38 is formed on the prepared semiconductor substrate 12a, the second electrode film 40 is formed on the first electrode film 38. The first electrode film 38 and the second electrode film 40 can be formed by a plating process.

As shown in FIG. 6, a resist film 44 is formed on the exposed first electrode film 38 and the exposed second electrode film 40 (that is, the upper surface 40a), respectively. At this time, the resist film 44 forms the resist film 44 except for at least a part of the side surface 40c of the second electrode film 40. The resist film 44 protects surfaces other than the side surface 40c of the second electrode film 40, which is etched in a subsequent step.

As shown in FIG. 7, a concave-convex shape 40d is formed on the side surface 40c of the second electrode film 40. As an example, the uneven shape 40d is formed by dry etching. As shown in FIG. 8, the resist film 44 is removed. The resist film 44 is decomposed and removed by an ashing treatment.

A method of forming the protective film 42 will be described with reference to FIGS. 9 to 13. First, as shown in FIG. 9, the resin solution 43s, which is a component of the protective film 42, is applied onto the semiconductor substrate 12a (that is, the first electrode film 38 and the second electrode film 40). At this time, although it is an example, the resin solution 43s is applied onto the semiconductor substrate 12a by the spin coating method. Then, as shown in FIG. 10, prebaking is performed. By this prebaking, the solvent volatilizes in the applied resin solution 43s, and the resin film 43 is formed. Here, the prebake temperature may be, for example, about 90 ° C. As a result, the resin film 43 is stabilized.

Next, as shown in FIG. 11, the prebaked semiconductor substrate 12a is exposed. Specifically, light is irradiated toward the surface of the resin film 43 on the semiconductor substrate 12a through a photomask (also referred to as a reticle) (not shown), and a predetermined range of the resin film 43 (here, a protective film) is applied. The range excluding the region where 42 is formed) is exposed. Next, as shown in FIG. 12, the exposed semiconductor substrate 12a is developed. By the developing process, the exposed unnecessary portion (the range excluding the region where the protective film 42 is formed) is removed and washed. As a result, the protective film 42 is formed. Finally, as shown in FIG. 13, the developed semiconductor substrate 12a is post-baked. By this post-baking, the adhesion between the protective film 42 and the semiconductor substrate 12a (that is, the first electrode film 38 and the second electrode film 40) is enhanced. Here, the post-bake temperature may be, for example, about 110 ° C.

The manufacturing of the semiconductor element 12 is completed by the above manufacturing method. The manufactured semiconductor element 12 is incorporated into the semiconductor module 10 by soldering. In Example 1, the first electrode film 38 and the second electrode film 40 are formed, and then the protective film 42 is formed, but the production order is not particularly limited. Further, the uneven shape 40d of the second electrode film 40 is formed by dry etching, but the forming method is not particularly limited. The manufacturing method can be appropriately changed according to the shape of the semiconductor element 12.

(Example 2) In the semiconductor module 10 described in the first embodiment, the semiconductor element 112 of the second embodiment may be adopted instead of the semiconductor element 12 of the first embodiment. The semiconductor element 112 of the second embodiment built in the semiconductor module 10 will be described with reference to FIG. As shown in FIG. 14, the semiconductor element 112 includes a semiconductor substrate 12a, an upper surface electrode 112b, and a lower surface electrode (not shown). The semiconductor element 112 of the second embodiment is different from the semiconductor element 12 of the first embodiment only in the configuration of the top electrode 112b. Since the other configurations are the same as those in the first embodiment, the description thereof will be omitted. In the case of the same configuration as in the first embodiment, the same reference number is attached.

The semiconductor element 112 includes a first electrode film 38 and a second electrode film 140. The first electrode film 38 is provided on the semiconductor substrate 12a, and the second electrode film 140 is provided on the first electrode film 38. A conductor spacer 14 is bonded to the second electrode film 140 via a solder layer 34. The second electrode film 140 has an upper surface 140a in contact with the solder layer 34, a lower surface 140b in contact with the first electrode film 38, and side surfaces 140c adjacent to the two surfaces 140a and 140b.

The side surface 140c of the second electrode film 140 has an uneven shape 40d at least partially. As an example, the concave-convex shape 140d is composed of a plurality of concave portions and / or a plurality of convex portions randomly arranged on the side surface 140c. However, the specific configuration of the concave-convex shape 140d is not particularly limited. The concave-convex shape 140d may be composed of a plurality of grooves and / or a plurality of ridges. The first electrode film 38 is made of, for example, an aluminum-based film or another metal. The second electrode film 140 is made of, for example, a nickel-based or other metal. The term "aluminum" as used herein refers to pure aluminum or an alloy containing aluminum as a main component (for example, aluminum-silicon), and the term "nickel" refers to pure nickel or an alloy containing nickel as a main component.

The semiconductor element 112 includes a protective film 142 that partially covers the top electrode 112b. The protective film 142 is provided on the first electrode film 38 adjacent to the second electrode film 140. The protective film 142 is in contact with the side surface 140c of the second electrode film 140 (particularly, the range having the uneven shape 140d of the side surface 140c). Further, the protective film 142 extends in a frame shape along the peripheral edge 12e of the semiconductor substrate 12a. The protective film 142 has an opening 142w, and at the opening 142w, the second electrode film 140 of the top electrode 112b is exposed to the outside of the semiconductor element 12. Therefore, the second electrode film 140 is bonded to the solder layer 34 via the opening 142w. The protective film 142 has an inner wall 142a extending from the opening 142w toward the first electrode film 38, and the inner wall 142a is in contact with the side surface 140c of the second electrode film 140. The point that the inner wall 142a contacts the side surface 140c is different from that of the first embodiment.

Also in the case of the semiconductor element 112 of the second embodiment, the side surface 140c of the second electrode film 140 in contact with the protective film 142 has an uneven shape 140d at least partially. Therefore, the protective film 142 and the second electrode film 140 are firmly adhered to each other by the anchor effect. As a result, the relative displacement of the semiconductor element 112 due to the temperature fluctuation is suppressed between the protective film 142 and the second electrode film 140. In particular, the uneven shape 140d is provided on the side surface 140c of the second electrode film 140 and is close to the triple point TP. As a result, the stress concentration at the triple point TP can be effectively relaxed.

The inventors assume that the semiconductor element 12 of Example 1 or the semiconductor module 10 incorporating the semiconductor element 112 of Example 2 is used (that is, when the semiconductor elements 12 and 112 repeatedly change in temperature). Under the above conditions, the nonlinear strain amplitude Δε generated on the surface of the first electrode film 38 in contact with the second electrode films 40 and 140 is investigated by simulation. The non-linear strain amplitude Δε referred to here is the sum of the plastic strain (that is, plastic deformation) and the creep strain (creep deformation). The relationship between this nonlinear strain amplitude Δε and the lifetime N _f (the number of cycles in which cracks first occur) can be expressed by the following equation according to the Coffin-Manson law, and the nonlinear strain amplitude Δε can be expressed as the lifetime N _f. It is commonly used as an index of the judgment criteria of. Here, α and C are material constants.
Δε · N _f ^α = C
Further, as a comparative example of the first embodiment, a semiconductor module having a conventional semiconductor element in which the side surface 40c of the second electrode film 40 does not have the concave-convex shape 40d in the configuration of the first embodiment is used. At this time, in the case of the semiconductor element 12 of Example 1, the nonlinear distortion amplitude Δε was reduced by a maximum of about 79% as compared with the prior art.
As a comparative example of the second embodiment, a semiconductor module having a conventional semiconductor element in which the side surface 140c of the second electrode film 140 does not have the uneven shape 140d in the configuration of the second embodiment is used. In the case of the semiconductor element 112 of the second embodiment, the nonlinear distortion amplitude Δε was reduced by up to about 45% as compared with the prior art.
From this, the strain generated at the triple point TP is reduced by having the side surfaces 40c and 140c of the second electrode films 40 and 140 in contact with the protective films 42 and 142 having the uneven shapes 40d and 140d. That is, it is inferred that the above-mentioned structure also reduces the stress generated at the triple point TP.

Although specific examples of the techniques disclosed in the present specification have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The techniques illustrated in this specification or drawings can achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor module 12, 112: Semiconductor element 12a: Semiconductor substrate 12b, 112b: Top electrode 12c: Bottom electrode 14: Conductor spacer 16, 18: Heat dissipation plate 20: Encapsulant 22, 24, 26: Power terminal 28, 30 : Signal terminals 32, 34, 36: Solder layer 38: First electrode film 40: Second electrode film 40c, 140c: Side surface 40d, 140d of second electrode film: Concavo-convex shape 42, 142: Protective film 42w, 142w: Opening 142a: Inner wall TP: Triple point

Claims (1)

With a semiconductor substrate
The first electrode film provided on the semiconductor substrate and
The second electrode film provided on the first electrode film and
On the first electrode film, a protective film provided adjacent to the second electrode film and in contact with the side surface of the second electrode film is provided.
The side surface of the second electrode film has an uneven shape at least partially.
Semiconductor device.

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