JP2021005682A - Print circuit board - Google Patents

Abstract

To provide a print circuit board in which deterioration of a signal quality is suppressed even when the signal is transmitted to a lamination direction of a multilayer substrate.SOLUTION: A print circuit board 100 comprises: a multi layer substrate 1 formed by laminating built-up layers 51A and 51B on both sides of a core layer 50; a signal wiring 4 formed inside of at least any one of two layers of a wiring layer of a principal face on both sides of the multi layer substrate 1 and the wiring layer in an inner part and the inner part of the multi layer substrate 1; and a ground wiring 5 that is formed in at least any one of two layers of the wiring layer of the principal face of both sides of the multi layer substrate 1 and the wiring layer of the inner part and the inner part of the multi layer substrate 1, and is electrically insulated with and is grounded to the signal wiring 4. The signal wiring 4 includes a signal via 11 penetrating at least one layer of the built-up layers 51A and 51B in a lamination direction. The ground wiring 5 circumferences the signal via 11 in an annular shape without a gap, and includes annular ground vias 7A and 7B provided in the built-up layers 51A and 51B without the hap in the lamination direction.SELECTED DRAWING: Figure 1

Description

The present invention relates to a printed wiring board.

Japanese Patent No. 4067313 and Japanese Patent No. 3384995 disclose a printed wiring board including a coaxial line extending along a surface.

On the other hand, Japanese Patent No. 4067313 and Japanese Patent No. 3384995 do not disclose a configuration in which the coaxial line extends in the stacking direction at which the surface of the printed wiring board intersects, that is, in the thickness direction.

In Japanese Patent Application Laid-Open No. 2011-187812, when a signal is transmitted in the laminated direction in a printed wiring board, each part of the signal wiring and the ground wiring is used as a signal wiring via and a ground wiring via in a through hole penetrating the substrate in the stacking direction. It is formed. Such signal wiring vias and ground wiring vias are generally formed in through holes formed by drilling. Therefore, in the conventional printed wiring board, the ground wiring via is formed so as to discretely surround the signal wiring via.

Patent No. 4067313 Patent No. 3384995 JP 2011-187812

In such a printed wiring board, the signal transmitted through the signal wiring leaks to the outside through an insulating layer arranged between a plurality of ground wires, resulting in deterioration of signal quality or interference between the leaked signal and other signals. May be triggered.

A main object of the present invention is to provide a printed wiring board in which deterioration of signal quality is suppressed even when a signal is transmitted in a stacking direction of a multilayer substrate.

The printed wiring board according to the present invention includes a multilayer board in which build-up layers are laminated on both sides of a core layer, at least two layers of wiring layers on the main surface on both sides of the multilayer board and internal wiring layers, and the inside of the multilayer board. It is formed inside the multilayer board and at least two layers of the wiring layer on the main surface on both sides of the multilayer board and the internal wiring layer, and is electrically insulated from the signal wiring. It has a grounded wiring that is grounded. The signal wiring has a signal via that penetrates at least one build-up layer in the stacking direction. The grounding wiring has an annular grounding via that surrounds the signal via in an annular manner and is seamlessly provided in the build-up layer in the stacking direction.

According to the present invention, it is possible to provide a printed wiring board in which deterioration of signal quality is suppressed even when a signal is transmitted in the stacking direction of the multilayer substrate.

It is sectional drawing which shows the printed wiring board which concerns on this embodiment. It is a top view seen from the arrow II in FIG. It is sectional drawing seen from the arrow III-III in FIG. It is sectional drawing seen from the arrow IV-IV in FIG. It is sectional drawing seen from the arrow VV in FIG. It is sectional drawing seen from the arrow VI-VI in FIG. It is sectional drawing seen from the arrow VII-VII in FIG. It is a top view seen from the arrow VIII-VIII in FIG. It is sectional drawing which shows one process of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 9 of the manufacturing method of the printed wiring board shown in FIG. It is a top view seen from the arrow XI in FIG. It is sectional drawing which shows one step after the process shown in FIG. 10 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 12 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 13 of the manufacturing method of the printed wiring board shown in FIG. It is a top view seen from the arrow XV in FIG. It is sectional drawing which shows one step after the process shown in FIG. 14 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 16 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 17 of the manufacturing method of the printed wiring board shown in FIG. It is a top view seen from the arrow XIX in FIG. It is sectional drawing which shows one step after the process shown in FIG. 18 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 20 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 21 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 22 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 23 of the manufacturing method of the printed wiring board shown in FIG. It is a top view seen from the arrow XXV in FIG. 24. It is a top view seen from the arrow XXVI in FIG. 24. It is sectional drawing which shows one step after the process shown in FIG. 24 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 27 of the manufacturing method of the printed wiring board shown in FIG. It is sectional drawing which shows one step after the process shown in FIG. 28 of the manufacturing method of the printed wiring board shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings below, the same or corresponding parts are given the same reference numbers and the explanations are not repeated.

FIG. 1 is a cross-sectional view showing a printed wiring board according to the present embodiment. 2 to 8 are a plan view or a cross-sectional view seen from the direction of the arrow shown in FIG. As shown in FIG. 1, the printed wiring board 100 according to the present embodiment includes a multilayer board 1, a signal wiring 4, and a ground wiring 5. The multilayer substrate 1 includes a core insulating layer 2, a plurality of first build-up insulating layers 3A, and a plurality of second build-up insulating layers 3B. The plurality of first build-up insulating layers 3A and the plurality of second build-up insulating layers 3B are arranged so as to sandwich the core insulating layer 2. The printed wiring board 100 has two layers of the first build-up insulating layer 3A and two layers of the second build-up insulating layer 3B. At least one of the first build-up insulating layer 3A and the second build-up insulating layer 3B may be two or more layers. The number of layers of the first build-up insulating layer 3A and the second build-up insulating layer 3B may be different. In the following, the direction in which the plurality of first build-up insulating layers 3A, the core insulating layer 2, and the plurality of second build-up insulating layers 3B are laminated is referred to as the stacking direction A. The printed wiring board 100 has a first surface 1A and a second surface 1B that intersect the stacking direction A. In other words, the direction in which the first surface 1A and the second surface 1B intersect is the stacking direction A. The second surface 1B is located on the opposite side of the first surface 1A. The first surface 1A and the second surface 1B are the main surfaces on both sides of the multilayer substrate 1.

The core insulating layer 2 has a third surface 2A and a fourth surface 2B that intersect the stacking direction A. The fourth surface 2B is located on the opposite side of the third surface 2A. The third surface 2A faces the same side as the first surface 1A. The fourth surface 2B faces the same side as the second surface 1B. The material constituting the core insulating layer 2 includes, for example, an epoxy resin.

The first build-up insulating layer 3A is laminated on the third surface 2A of the core insulating layer 2. Of the first build-up insulating layer 3A, the surface of the first build-up insulating layer 3A farthest from the core insulating layer 2 becomes the first surface 1A of the printed wiring board 100. The first build-up insulating layer 3A and the second build-up insulating layer 3B are made of, for example, a resin obtained by heating and curing a prepreg.

The second build-up insulating layer 3B is laminated on the fourth surface 2B of the core insulating layer 2. Of the second build-up insulating layer 3B, the surface of the second build-up insulating layer 3B farthest from the core insulating layer 2 becomes the second surface 1B of the printed wiring board 100. Inside the multilayer board 1, between the core insulating layer 2 and the first build-up insulating layer 3A or the second build-up insulating layer 3B, between the first build-up insulating layers 3, and between the second build-up insulating layers 3B. A wiring layer is provided between them.

As shown in FIGS. 1 and 5, the multilayer substrate 1 is formed with a first through hole 21 and a plurality of second through holes 22 that penetrate the core insulating layer 2 in the stacking direction A. When the core insulating layer 2 is viewed from the stacking direction A, the plurality of second through holes 22 are arranged around the first through holes 21 at intervals. Each center of the plurality of second through holes 22 is arranged concentrically with respect to the center of the first through hole 21. The distance between two adjacent second through holes 22 among the plurality of second through holes 22 is equal to each other. The distance (pitch) between two adjacent second through holes 22 among the plurality of second through holes 22 is, for example, 1/16 or less of the wavelength λ of the signal input to the signal wiring 4. The number of the second through holes 22 may be any number, but is, for example, eight. The angle formed by the centers of the two adjacent second through holes 22 with respect to the center of the first through holes 21 is, for example, 45 degrees.

As shown in FIG. 1, each inner peripheral surface of the first through hole 21 and the plurality of second through holes 22 is orthogonal to, for example, the third surface 2A and the fourth surface 2B. The first through hole 21 and the plurality of second through holes 22 are formed by, for example, drilling.

As shown in FIGS. 1 and 3, the first build-up insulating layer 3A of the surface layer is formed with a third through hole 31A and a seventh bottomed hole 32C penetrating in the stacking direction A. The first through hole 21, the third through hole 31A, and the fifth through hole 31B (provided in the second build-up insulating layer 3B) are provided after laminating the first build-up insulating layer 3A and the second build-up insulating layer 3B. Therefore, the axes passing through the centers of the first through hole 21, the third through hole 31A, and the fifth through hole 31B coincide with each other. The seventh bottomed hole 32C is a portion corresponding to the lower side in the figure of the surface signal wiring 4A in the circle surrounding the third through hole 31A so as not to overlap the surface signal wiring 4A (shown in FIG. 2) in the stacking direction A. Besides, it is formed in the shape of C in the alphabet.

As shown in FIGS. 1 and 7, the second build-up insulating layer 3B of the surface layer is formed with a fifth through hole 31B and an eighth bottomed hole 32D penetrating in the stacking direction A. The eighth bottomed hole 32D is a portion of the circle surrounding the third through hole 31A other than the portion corresponding to the upper side in the figure of the surface signal wiring 4B so as not to overlap the surface signal wiring 4B (shown in FIG. 7) in the stacking direction A. It is formed in a C shape.

As shown in FIGS. 1 and 4, the first build-up insulating layer 3A, which is not the surface layer, is formed with a third through hole 31A and a fourth bottomed hole 32A penetrating in the stacking direction A. The fourth bottomed hole 32A is formed in an annular shape (doughnut shape) so as to seamlessly surround the third through hole 31A. The fourth bottomed hole 32A is formed in an annular shape with respect to the center of, for example, the third through hole 31A.

As shown in FIG. 4, the donut-shaped fourth bottomed hole 32A has an inner surface 321A and an outer surface 322A facing each other in the radial direction. The inner side surface 321A faces the outer peripheral side in the radial direction, and the outer side surface 322A faces the inner peripheral side in the radial direction. The circle passing through the center of the inner side surface 321A and the outer side surface 322A in the radial direction is formed so as to overlap the circle passing through the centers of the plurality of second through holes 22.

As shown in FIG. 1, the inner peripheral surface of the third through hole 31A is orthogonal to, for example, the third surface 2A and the fourth surface 2B. The inner surface 321A and the outer surface 322A of the fourth bottomed hole 32A are inclined with respect to, for example, the third surface 2A and the fourth surface 2B. The inner side surface 321A is formed so as to be inclined so as to be located on the outer peripheral side in the radial direction toward the core insulating layer 2 side in the stacking direction A. The outer side surface 322A is formed so as to be inclined so as to be located on the inner peripheral side in the radial direction toward the core insulating layer 2 side in the stacking direction A. The third through hole 31A is formed by, for example, drilling. The fourth bottomed hole 32A is formed by, for example, laser machining.

As shown in FIGS. 1 and 6, the multilayer substrate 1 is formed with a fifth through hole 31B and a sixth bottomed hole 32B that penetrate the second build-up insulating layer 3B in the stacking direction A. The sixth bottomed hole 32B is formed in an annular shape so as to seamlessly surround the fifth through hole 31B.

As shown in FIG. 6, the sixth bottomed hole 32B is formed in an annular shape so as to seamlessly surround the fifth through hole 31B, for example. The donut-shaped sixth bottomed hole 32B has an inner surface 321B and an outer surface 322B facing each other in the radial direction. The inner side surface 321B faces the outer peripheral side in the radial direction, and the outer side surface 322B faces the inner peripheral side in the radial direction. The circle passing through the center of the inner side surface 321B and the outer side surface 322B in the radial direction is formed so as to overlap the circle passing through the centers of the plurality of second through holes 22.

The signal wiring 4 includes a surface signal wiring 4A formed on the first surface 1A of the multilayer substrate 1, a surface signal wiring 4B formed on the second surface 1B of the multilayer substrate 1, and the inside of the multilayer substrate 1. The surface signal wiring 4A and the surface signal wiring 4B are connected to the surface signal wiring 4A. As shown in FIGS. 2 and 8, the surface signal wiring 4A and the surface signal wiring 4B extend linearly along the plane direction B parallel to the first surface 1A and the second surface 1B. The face-to-face signal wiring 4C extends along the stacking direction A. In the signal wiring 4, the surface signal wiring 4A, the interfaceted signal wiring 4C, and the surface signal wiring 4B are connected in series in this order. Wiring other than the signal wiring 4 and the ground wiring 5 (described later) is provided on the first surface 1A, the second surface 1B, and the wiring layer inside the multilayer board 1. Here, the wiring other than the signal wiring 4 and the ground wiring 5 will be omitted from the illustration and description.

The face-to-face signal wiring 4C includes a signal via 11, a first signal wiring 12A, a second signal wiring 12B, a third signal wiring 13A, and a fourth signal wiring 13B. The signal via 11 is formed inside the first through hole 21 of the core insulating layer 2, the third through hole 31A of the first build-up insulating layer 3A, and the fifth through hole 31B of the second build-up insulating layer 3B. There is. The signal via 11 extends along the stacking direction A. The first signal wiring 12A is formed in a circular shape in the wiring layer between the core insulating layer 2 and the first build-up insulating layer 3A. The second signal wiring 12B is formed in a circular shape in the wiring layer between the core insulating layer 2 and the second build-up insulating layer 3B. The first signal wiring 12A and the second signal wiring 12B are connected to a signal via 11 passing through the center thereof. The third signal wiring 13A is formed in a circle in the wiring layer between the first build-up insulating layers 3A. The third signal wiring 13A is connected to the signal via 11 passing through the center thereof. The fourth signal wiring 13B is formed in a circle in the wiring layer between the second build-up insulating layers 3B. The fourth signal wiring 13B is connected to the signal via 11 passing through the center thereof.

The ground wiring 5 is electrically isolated from the signal wiring 4. The grounding wiring 5 includes a surface grounding wiring 5A formed on the first surface 1A of the multilayer board 1, a surface grounding wiring 5B formed on the second surface 1B of the multilayer board 1, and the inside of the multilayer board 1. The surface grounding wiring 5A and the surface grounding wiring 5B are connected to the surface grounding wiring 5C. As shown in FIGS. 2 and 8, the surface grounding wiring 5A is arranged at a distance from the surface signal wiring 4A. The surface ground wiring 5B is arranged at a distance from the surface signal wiring 4B. The face-to-face ground wiring 5C extends along the stacking direction A. In the grounding wiring 5, the surface grounding wiring 5A, the surface grounding wiring 5C, and the surface grounding wiring 5B are connected in series in this order.

The face-to-face grounding wiring 5C includes a first grounding via 6, a second grounding via 7A, a third grounding via 7B, a fourth grounding via 7C, a fifth grounding via 7D, a first grounding wiring 8A, a second grounding wiring 8B, and a first. 3 The ground wiring 9A and the 4th ground wiring 9B are included. The first grounding via 6 is formed inside a plurality of second through holes 22 of the core insulating layer 2. The first grounding via 6 is formed in an annular shape on the inner peripheral surface of each of the second through holes 22, for example. When viewed from the stacking direction A, an embedded member 10 that fills the inside of each of the second through holes 22 is arranged inside the first grounding via 6. The material constituting the embedding member 10 may be any material that can fill the inside of the second through hole 22, and includes, for example, resin or metal. The embedded member 10 may be formed of, for example, a conductive paste. The second grounding via 7A is formed inside the fourth bottomed hole 32A provided in the first build-up insulating layer 3A, which is not the surface layer. The third grounding via 7B is formed inside the sixth bottomed hole 32B provided in the second build-up insulating layer 3B, which is not the surface layer. The fourth grounding via 7C is formed inside the seventh bottomed hole 32C provided in the first build-up insulating layer 3A on the surface layer. The fifth grounding via 7D is formed inside the eighth bottomed hole 32D provided in the second build-up insulating layer 3B on the surface layer.

As shown in FIGS. 2 and 3, the fourth grounding via 7C formed inside the seventh bottomed hole 32C is formed so as not to overlap the surface signal wiring 4A when viewed from the stacking direction A. .. As shown in FIGS. 7 and 8, the fifth grounding via 7D formed inside the eighth bottomed hole 32D is formed so as not to overlap the surface signal wiring 4B when viewed from the stacking direction A. ..

The first grounded wiring 8A connects the first grounded via 6 and the second grounded via 7A. The first ground wiring 8A is formed so as to surround the signal via 11 and the first signal wiring 12A in a ring shape without a break at intervals from the first signal wiring 12A. The second grounded wiring 8B connects the first grounded via 6 and the third grounded via 7B. The second ground wiring 8B is formed so as to surround the signal via 11 and the second signal wiring 12B in a ring shape without a break at intervals from the second signal wiring 12B.

The third grounding wiring 9A connects between the second grounding via 7A and the fourth grounding via 7C that are adjacent to each other in the stacking direction A. The third ground wiring 9A is formed so as to surround the signal via 11 and the third signal wiring 13A in a ring shape without a break at intervals from the third signal wiring 13A. The fourth grounded wiring 9B connects between the third grounded via 7B and the fifth grounded via 7D that are adjacent to each other in the stacking direction A. The fourth grounded wiring 9B is formed so as to surround the signal via 11 and the fourth signal wiring 13B in a ring shape without a break at intervals from the fourth signal wiring 13B.

In the face-to-face grounding wiring 5C, from the surface grounding wiring 5A side, the fourth grounding via 7C, the third grounding wiring 9A, the second grounding via 7A, the first grounding wiring 8A, the first grounding via 6, the second grounding wiring 8B, The third grounded via 7B, the fourth grounded wire 9B, and the fifth grounded via 7D are connected in series in this order. In the first build-up insulating layer 3A and the second build-up insulating layer 3B, which are not surface layers, the face-to-face signal wiring 4C and the face-to-face grounding wiring 5C are configured as so-called coaxial lines. The distance of the face-to-face ground wiring 5C with respect to the face-to-face signal wiring 4C is set according to the relative permittivity and impedance inside the multilayer board 1.

From a different point of view, the printed wiring board 100 is a so-called build-up board, which includes a core layer 50, at least two first build-up layers 51A, and at least two second build-up layers 51B. The core layer 50 includes a core insulating layer 2, a part of the signal via 11, a first signal wiring 12A, a second signal wiring 12B, a first ground via 6, a first ground wiring 8A, and a second ground wiring 8B. The first build-up layer 51A includes a first build-up insulating layer 3A, a part of the signal via 11, a third signal wiring 13A, a second ground via 7A or a fourth ground via 7C, and a third ground wiring 9A. The second build-up layer 51B includes a second build-up insulating layer 3B, a part of the signal via 11, a fourth signal wiring 13B, a third ground via 7B or a fifth ground via 7D, and a fourth ground wiring 9B.
<Manufacturing method of printed wiring board>

A method of manufacturing the printed wiring board 100 according to the present embodiment will be described with reference to FIGS. 9 to 29. The printed wiring board 100 is manufactured by a so-called build-up method.

First, as shown in FIG. 9, a laminated plate 20 in which the insulator 23, the conductor layer 24A, and the conductor layer 24B are laminated is prepared. The insulator 23 has a fifth surface 23A and a sixth surface 23B located on the opposite side of the fifth surface 23A. The conductor layer 24A is formed on the fifth surface 23A. The conductor layer 24B is formed on the sixth surface 23B. The material constituting the insulator 23 may be any material having an electrical insulating property, and includes, for example, an epoxy resin. The insulator 23 may thermoset the prepreg. The material constituting the conductor layer 24A and the conductor layer 24B may be any material having conductivity, and includes, for example, copper (Cu).

Next, as shown in FIGS. 10 and 11, a plurality of second through holes 22 are formed in the laminated plate 20. The plurality of second through holes 22 are formed so as to penetrate the insulator 23, the conductor layer 24A, and the conductor layer 24B. The plurality of second through holes 22 are arranged side by side in the circumferential direction of the circle centered on the point where the center of the first through hole 21 shown in FIG. 1 is arranged. The plurality of second through holes 22 are formed by, for example, drilling. In a cross-sectional view such as FIG. 10, only the cross section to be cut is displayed in order to make the figure easy to understand.

Next, as shown in FIG. 12, the conductor layer 25 is formed on each inner peripheral surface of the plurality of second through holes 22 and on each surface of the conductor layer 24A and the conductor layer 24B. The conductor layer 25 is formed by, for example, a plating method. The material constituting the conductor layer 25 may be any material having conductivity and capable of forming a film by a plating method, and includes, for example, copper (Cu). As a result, a laminate of the conductor layer 24A and the conductor layer 25 is formed on the fifth surface 23A, and a laminate of the conductor layer 24B and the conductor layer 25 is formed on the sixth surface 23B. Further, a conductor layer 25 is formed on each inner peripheral surface of the plurality of second through holes 22.

Next, as shown in FIG. 13, the embedded member 10 is formed inside the plurality of second through holes 22. When the inside of the second through hole 22 is filled with resin and the filled resin is solidified, the embedded member 10 is formed. A conductor layer 26 is formed on the embedded member 10. The conductor layer 26 is formed by, for example, a plating method. The material constituting the conductor layer 26 may be any material having conductivity and capable of forming a film by a plating method, and includes, for example, copper (Cu). As a result, a laminate of the conductor layer 24A, the conductor layer 25, and the conductor layer 26 is formed on the fifth surface 23A, and the conductor layer 24B, the conductor layer 25, and the conductor layer 26 are laminated on the sixth surface 23B. The body is formed.

Next, the laminated body of the conductor layers formed on the fifth surface 23A and the sixth surface 23B of the insulator 23 shown in FIG. 13 is patterned. Patterning is the formation of a circuit pattern in the conductor layer. Patterning is performed, for example, by photolithography and dry etching processes. As a result, the core substrate 27 shown in FIG. 14 is formed. The core substrate 27 includes an insulator 23, a plurality of first grounding vias 6 formed inside the insulator 23, and a first signal wiring 12A and a first grounding formed on the fifth surface 23A of the insulator 23. The wiring 8A includes a second signal wiring 12B and a second ground wiring 8B formed on the sixth surface 23B of the insulator 23. The first grounding via 6 is composed of a conductor layer 25 provided on the inner peripheral surface of the second through hole 22.

As shown in FIG. 15, the first ground wiring 8A is formed so as to surround the first signal wiring 12A in an annular shape without a break. The second ground wiring 8B is formed so as to surround the second signal wiring 12B in an annular shape without a break. A plurality of first grounding vias 6 are formed inside the insulator 23. The insulator 23, the fifth surface 23A, and the sixth surface 23B of the core substrate 27 shown in FIG. 14 constitute the core insulating layer 2, the third surface 2A, and the fourth surface 2B in the printed wiring board 100 shown in FIG. To do. Next, the adhesion force with the resin to the fifth surface 23A, the first ground wiring 8A, the first signal wiring 12A, and the sixth surface 23B, the second ground wiring 8B, and the second signal wiring 12B of the core substrate 27. Roughening treatment is applied to raise the surface.

Next, as shown in FIG. 16, the prepreg 33A and the conductor layer 34A are laminated on the fifth surface 23A side of the core substrate 27. The conductor layer 34A and the core substrate 27 are laminated so as to sandwich the prepreg 33A in the lamination direction A. The prepreg 33B and the conductor layer 34B are laminated on the sixth surface 23B side of the core substrate 27. The conductor layer 34B and the core substrate 27 are laminated so as to sandwich the prepreg 33B in the stacking direction A. By pressurizing and heating the laminated body after laminating, the laminated body shown in FIG. 17 is formed. The laminate includes a conductor layer 34A, a conductor layer 34B, an insulator 35A formed by thermosetting the prepreg 33A, and an insulator 35B formed by thermosetting the prepreg 33B.

Next, as shown in FIG. 18, a fourth bottomed hole 32A is formed in the conductor layer 34A and the insulator 35A. The fourth bottomed hole 32A is formed by laser processing. The first ground wiring 8A is exposed at the bottom of the fourth bottomed hole 32A. As shown in FIG. 19, the fourth bottomed hole 32A is formed in an annular shape without a break along the circumferential direction of the circle centered on the point where the center of the first through hole 21 shown in FIG. 1 is arranged. To.

Similarly, the sixth bottomed hole 32B is formed in the conductor layer 34B and the insulator 33B. The sixth bottomed hole 32B is formed by laser machining. The second ground wiring 8B is exposed at the bottom of the sixth bottomed hole 32B. The sixth bottomed hole 32B is formed in an annular shape without a break along the circumferential direction of the circle centered on the point where the center of the first through hole 21 is arranged.

Next, as shown in FIG. 20, the conductor layer 37 is formed inside the fourth bottom hole 32A and the sixth bottom hole 32B, and on the conductor layer 34A and the conductor layer 34B. The conductor layer 37 is formed by filling the inside of the fourth bottom hole 32A and the sixth bottom hole 32B with the conductor. The conductor layer 37 is formed by, for example, a plating method. The material constituting the conductor layer 37 may be any material having conductivity and capable of forming a film by a plating method, and includes, for example, copper (Cu). The conductor layer 37 formed inside the fourth bottomed hole 32A becomes the second grounding via 7A formed inside the insulator 35A. The conductor layer 37 formed inside the sixth bottomed hole 32B becomes the third grounding via 7B formed inside the insulator 35B. The second ground via 7A is connected to the first ground via 6 via the first ground wiring 8A. The third ground via 7B is connected to the first ground via 6 via the second ground wiring 8B.

Next, as shown in FIG. 21, the conductor layer 37 and the conductor layer 34A formed on the insulator 35A are patterned. Similarly, the conductor layer 37 and the conductor layer 34B formed on the insulator 35B are patterned. Patterning is performed, for example, by photolithography and dry etching processes. As a result, the third signal wiring 13A and the third ground wiring 9A formed on the insulator 35A are formed from the conductor layer 37 and the conductor layer 34A. From the conductor layer 37 and the conductor layer 34B, the fourth signal wiring 13B and the fourth ground wiring 9B formed on the insulator 35B are formed. The third signal wiring 13A and the fourth signal wiring 13B are formed so as to overlap the first signal wiring 12A and the second signal wiring 12B in the stacking direction A.

Next, as shown in FIG. 22, the prepreg 38A and the conductor layer 39A are laminated on the insulator 35A side of the laminate shown in FIG. The conductor layer 39A and the insulator 35A are laminated so as to sandwich the prepreg 38A in the lamination direction A. Further, the prepreg 38B and the conductor layer 39B are laminated on the insulator 35B side of the laminate shown in FIG. The conductor layer 39B and the insulator 35B are laminated so as to sandwich the prepreg 38B in the lamination direction A. By pressurizing and heating the laminated body after laminating, the laminated body shown in FIG. 23 is formed. The laminate includes a conductor layer 39A, a conductor layer 39B, an insulator 40A formed by thermosetting the prepreg 38A, and an insulator 40B formed by thermosetting the prepreg 38B.

Next, as shown in FIG. 24, bottomed holes are formed in the conductor layer 39A and the insulator 40A. Further, bottomed holes are formed in the conductor layer 39B and the insulator 40B. This step is carried out in the same manner as the step of forming the bottomed holes in the conductor layer 34A and the insulator 35A and forming the bottomed holes in the conductor layer 34B and the insulator 33B described above. However, the shape of the bottomed hole to be formed is different. As a result, the seventh bottomed hole 32C is formed in the conductor layer 39A and the insulator 40A. The third ground wiring 9A is exposed at the bottom of the seventh bottom hole 32C. Further, an eighth bottomed hole 32D is formed in the conductor layer 39B and the insulator 40B. The fourth ground wiring 9B is exposed at the bottom of the eighth bottomed hole 32D. As shown in FIG. 25, the seventh bottomed hole 32C is connected to the surface signal wiring 4A along the circumferential direction of the circle centered on the point where the center of the first through hole 21 shown in FIG. 1 is arranged. It is formed in a C shape except for the overlapping portion. As shown in FIG. 26, the eighth bottomed hole 32D is C except for a portion overlapping the surface signal wiring 4B along the circumferential direction of the circle centered on the point where the center of the first through hole 21 is arranged. It is formed in the shape of.

Next, as shown in FIG. 27, the conductor layer 42 is formed inside the fourth bottom hole 32A and the sixth bottom hole 32B, and on the conductor layer 39A and the conductor layer 39B. The conductor layer 42 is formed by, for example, a plating method so as to embed the inside of the fourth bottomed hole 32A and the sixth bottomed hole 32B. The material constituting the conductor layer 42 may be any material having conductivity and capable of forming a film by a plating method, and includes, for example, copper (Cu).

Next, as shown in FIG. 28, a ninth through hole 43 is formed through the laminate shown in FIG. 27 in the stacking direction A. Of the ninth through hole 43, the portion penetrating the insulator 23 is the first through hole 21, the portion penetrating the insulator 35A and the insulator 40A is the third through hole 31A, and the insulator 35B and the insulator 40B. The penetrating portion constitutes the fifth through hole 31B. The axis passing through the center of the ninth through hole 43 is the center of the circle passing through each center of the plurality of second through holes 22, and the fourth bottom hole 32A, the sixth bottom hole 32B, the seventh bottom hole 32C, and the like. It is formed so as to pass through the center of a circle passing through each center of the eighth bottomed hole 32D. Such a ninth through hole 43 penetrates the first signal wiring 12A, the second signal wiring 12B, the third signal wiring 13A, and the fourth signal wiring 13B. The ninth through hole 43 is formed by, for example, drilling.

Next, as shown in FIG. 29, the conductor layer 44 is formed on the exposed layer of the laminate shown in FIG. 28. The conductor layer 44 is formed so as to cover the inner peripheral surface of the ninth through hole 43. The conductor layer 44 is formed by, for example, a plating method. The material constituting the conductor layer 44 may be any material having conductivity and capable of forming a film by a plating method, and includes, for example, copper (Cu). The conductor layer 44 formed on the inner peripheral surface of the ninth through hole 43 is the signal via 11.

Next, the conductor layer 39A, the conductor layer 42, and the conductor layer 44 formed on the insulator 40A are patterned. Similarly, the conductor layer 39B, the conductor layer 42, and the conductor layer 44 formed on the insulator 40B are patterned. Patterning is performed, for example, by photolithography and dry etching processes. As a result, the surface signal wiring 4A and the surface grounding wiring 5A are formed from the conductor layer 39A, the conductor layer 42, and the conductor layer 44. The surface signal wiring 4B and the surface grounding wiring 5B are formed from the conductor layer 39B, the conductor layer 42, and the conductor layer 44. As a post-process, solder resist coating, surface treatment, and outer shape processing are performed. As described above, the printed wiring board 100 shown in FIG. 1 is manufactured.

In FIGS. 1, 16, 17, 19 to 26, the connection interface of the core insulating layer 2, the first build-up insulating layer 3A, and the second build-up insulating layer 3B, or the connecting interface of each insulator, is It is illustrated by a solid line for convenience of explanation. In the actual printed wiring board 100, each connection interface is not always observed.
<Effect>

In the conventional printed wiring board, a plurality of ground wires are formed inside the multilayer board so as to discretely surround the signal wiring. In this case, the signal transmitted through the signal wiring may leak to the outside through the insulating layer arranged between the plurality of ground wirings, which may cause deterioration of signal quality or interference between the leaked signal and other signals. ..

On the other hand, the printed wiring board 100 according to the present embodiment is formed on both sides and inside of the multilayer board 1, the signal wiring 4 formed on both sides and inside of the multilayer board 1, and the signal. The wiring is provided with a ground wiring 5 that is electrically isolated from the wiring. The ground wiring 5 includes a second ground via 7A and a third ground via 7B as an annular portion that seamlessly surrounds the signal wiring extending in the stacking direction A intersecting both surfaces inside the substrate.

Specifically, in the printed wiring board 100, the multilayer board 1 has a core insulating layer 2 and a first build-up insulating layer 3A and a second build-up insulating layer 3B laminated so as to sandwich the core insulating layer 2. Including. The ground wiring 5 has a plurality of first ground vias 6 that discretely surround the signal wiring 4 extending in the stacking direction A inside the core insulating layer 2, and the grounding direction A inside the first build-up insulating layer 3A. A second grounding via 7A that seamlessly surrounds the periphery of the extending signal wiring 4 and a third grounding via 7B that seamlessly surrounds the signal wiring 4 extending in the stacking direction A inside the second build-up insulating layer 3B. And include. The second grounding via 7A and the third grounding via 7B form a part of the annular portion.

Therefore, in the printed wiring board 100, leakage of signals from the signal wiring 4 surrounded by the second ground via 7A and the third ground via 7B is prevented. Therefore, in the printed wiring board 100, deterioration of signal quality and interference of the leaked signal with other signals are suppressed as compared with the conventional printed wiring board.

In the printed wiring board 100, the grounding wiring 5 connects between the first grounding via 6 and the second grounding via 7A and surrounds the signal wiring 4 extending in the stacking direction A without a break in the first grounding wiring 8A. Further includes a second grounded wiring 8B that connects between the first grounded via 6 and the third grounded via 7B and surrounds the signal wiring 4 extending in the stacking direction A without a break in an annular shape. The first ground wire 8A and the second ground wire 8B also form a part of the annular portion.

The first ground wire 8A and the second ground wire 8B connect a plurality of first ground wires 8A to each other on both sides of the plurality of first ground vias 6. The first ground wiring 8A and the second ground wiring 8B set a plurality of first ground vias 6 to ground potentials. The first grounded wiring 8A more reliably connects the first grounded via 6 and the second grounded via 7A. The second grounded wiring 8B more reliably connects the first grounded via 6 and the third grounded via 7B.

In the printed wiring board 100, the multilayer board 1 includes a first build-up insulating layer 3A laminated in the stacking direction A and a second build-up insulating layer 3B laminated in the stacking direction A. The ground wiring 5 includes a third ground wiring 9A that connects the second ground vias 7A of the first build-up insulating layers 3A adjacent to each other in the stacking direction A, and a second build-up insulating layer 3B adjacent to each other in the stacking direction A. Further includes a fourth grounded wire 9B connecting between each of the third grounded vias 7B. The third ground wiring 9A and the fourth ground wiring 9B also form a part of the annular portion.

In the multilayer board 1 of the printed wiring board 100, the first through hole 21 and the plurality of second through holes 22 that penetrate the core insulating layer 2 in the stacking direction A, and the first build-up insulating layer 3A penetrate in the stacking direction A. The third through hole 31A, the fourth bottom hole 32A and the seventh bottom hole 32C, and the fifth through hole 31B, the sixth bottom hole 32B and the third through hole 32B that penetrate the second build-up insulating layer 3B in the stacking direction A. 8 bottomed holes 32D are formed. The plurality of second through holes 22 are arranged around the first through holes 21 at intervals from each other. The fourth bottomed hole 32A is formed in an annular shape without a break so as to surround the third through hole 31A. The seventh bottomed hole 32C is formed in a C shape so as to surround the third through hole 31A. The sixth bottomed hole 32B is formed in an annular shape without a break so as to surround the fifth through hole 31B. The eighth bottomed hole 32D is formed in a C shape so as to surround the fifth through hole 31B. The third through hole 31A and the fifth through hole 31B are formed so as to be connected to the first through hole 21. The fourth bottomed hole 32A and the sixth bottomed hole 32B are formed so as to be connected to the plurality of second through holes 22. The signal wiring 4 includes a signal via 11 formed inside the first through hole 21, the third through hole 31A, and the fifth through hole 31B. Each of the plurality of first grounding vias 6 is formed inside each of the plurality of second through holes 222. The second grounding via 7A is formed inside the fourth bottomed hole 32A. The third grounding via 7B is formed inside the sixth bottomed hole 32B. The second grounded via 7A and the third grounded via 7B surround the signal via 11 in an annular shape. The fourth grounding via 7C is formed inside the seventh bottomed hole 32C. The fifth grounding via 7D is formed inside the eighth bottomed hole 32D. The fourth grounded via 7C and the fifth grounded via 7D surround the signal via 11 in a C shape.

The printed wiring board 100 has a signal wiring 4 and a ground wiring 5 that connect the main surfaces on both sides of the multilayer board 1. Signal wiring and ground wiring may be formed inside at least two layers of the wiring layer on the main surface on both sides of the multilayer board and the wiring layer inside, and inside the multilayer board. The grounded wiring is electrically isolated from the signal wiring and is grounded. The signal wiring may have a signal via that penetrates at least one build-up layer in the stacking direction. The build-up layer is a first build-up layer or a second build-up layer. The ground wiring may be provided in the build-up layer without a break in the stacking direction, and may have an annular ground via that surrounds the signal via without a break. The fact that the annular grounding vias are provided in the build-up layer seamlessly in the stacking direction means that the annular grounding vias are provided so as to exist between both surfaces of the build-up layer. Since the annular grounding vias surround the signal vias in an annular shape without a break, the annular grounding vias are cylindrically provided in the build-up layer through which the signal vias penetrate.

The signal via 11 is a conductor provided on the inner peripheral surface of the ninth through hole 43, which is a through hole penetrating the core layer 50, the first build-up layer 51A, and the second build-up layer 51B. The signal via may be provided on the inner peripheral surface of the through hole penetrating at least one build-up layer.

The first signal wiring 12A and the third signal wiring 13A are provided on the wiring layers on both sides of the first build-up layer 51A through which the signal via 11 penetrates in the stacking direction. The second signal wiring 12B and the fourth signal wiring 13B are provided on the wiring layers on both sides of the second build-up layer 51B through which the signal via 11 penetrates in the stacking direction. The first signal wiring 12A, the second signal wiring 12B, the third signal wiring 13A, and the fourth signal wiring 13B are signal vias provided on the wiring layers on both sides in the stacking direction of the build-up layer through which the signal via penetrates. It is a signal conductor connected to.

The second grounding via 7A is provided inside the fourth bottomed hole 32A that seamlessly surrounds the third signal wiring 13A provided on the surface of the first build-up layer 51A on the side far from the core layer 50. The third grounding via 7B is provided inside the sixth bottomed hole 32B that seamlessly surrounds the fourth signal wiring 13B provided on the surface of the second build-up layer 51B far from the core layer 50. The fourth bottomed hole 32A and the sixth bottomed hole 32B seamlessly surround the signal conductor provided on the surface far from the core layer of the build-up layer, and the wiring layer on the core layer side of the build-up layer is exposed. It is an annular hole provided so as to be used.

The second grounding via 7A and the third grounding via 7B are annular grounding vias provided inside the annular hole and provided in the build-up layer seamlessly in the stacking direction to surround the signal via in an annular shape.

When a signal via penetrates a plurality of adjacent build-up layers, a plurality of annular ground vias provided in each of the plurality of adjacent build-up layers through which the signal via penetrates are connected surfaces of the plurality of build-up layers. In the ring, it is connected seamlessly.

In the printed wiring board 100, a plurality of core layer grounding vias arranged on the core layer 50 so as to surround the signal via 11 in a ring shape at intervals from the signal via 11 are the first grounding vias 6. The first ground wiring 8A and the second ground wiring 8B provided on both side surfaces of the core layer are the first signals provided in the wiring layer between each of the build-up layers on both sides of the core layer and the core layer. An annular core grounding conductor that seamlessly surrounds the first signal wiring 12A or the third signal wiring 13A in an annular shape with a distance from the wiring 12A or the second signal wiring 12B. The first grounded via 6 and the second grounded via 7A are connected to the first signal wiring 12A. The first grounded via 6 and the third grounded via 7B are connected to the second signal wiring 12B. That is, the first ground wiring 8A and the second ground wiring 8B, which are the annular core ground conductors, are connected to the core layer ground via and the annular ground via.

The second grounding via 7A and the third grounding via 7B are provided by filling the inside of the annular hole with a conductor. The second grounding via and the third grounding via may be conductors provided on the inner surface of the annular hole with a predetermined thickness. The inside of the second grounding via and the third grounding via may be filled with an insulating resin in an annular shape. On the surface of the build-up layer on which the second ground via or the third ground via is provided, which is far from the core layer, the second ground via or the third ground via and the insulating resin are covered, and the signal via is cut in a ring shape. An annular grounding conductor may be provided to surround the ground.

When the annular grounding conductor is provided, the plurality of annular grounding vias provided in each of the plurality of adjacent buildup layers through which the signal via penetrates are annularly formed via the annular grounding conductor at the connecting surface of the plurality of buildup layers. Connect seamlessly. Even in that case, the plurality of annular grounding vias provided in each of the plurality of adjacent build-up layers are connected in an annular shape without a break.

Although the embodiment of the present invention has been described above, it is possible to modify the above-described embodiment in various ways. Moreover, the scope of the present invention is not limited to the above-described embodiment. The scope of the present invention is indicated by the scope of claims and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 Multi-layer substrate, 1A 1st surface (main surface), 1B 2nd surface (main surface), 2 core insulating layer, 2A 3rd surface, 2B 4th surface, 3A 1st build-up insulating layer, 3B 2nd build-up Insulation layer, 4 signal wiring, 4A, 4B surface signal wiring, 4C inter-plane signal wiring, 5 ground wiring, 5A, 5B surface ground wiring, 5C inter-plane ground wiring, 6th ground via (core layer ground via), 7A 2nd ground via (annular ground via), 7B 3rd ground via (annular ground via), 7C 4th ground via, 7D 5th ground via, 8A 1st ground wiring (annular core ground conductor), 8B 2nd ground wiring (Annual core grounding conductor), 9A 3rd grounding wiring, 9B 4th grounding wiring, 10 embedded members, 11 signal vias, 12A 1st signal wiring (signal conductor), 12B 2nd signal wiring (signal conductor), 13A 1st 3 Signal wiring (signal conductor), 13B 4th signal wiring (signal conductor), 20 Laminated plate, 21 1st through hole, 22 2nd through hole, 23, 33B, 35A, 35B, 40A, 40B insulator, 23A 5th surface, 23B 6th surface, 24A, 24B, 25, 26, 34A, 34B, 37, 39A, 39B, 42, 44 Conductor layer, 27 core substrate, 30 core layer, 31A 3rd through hole, 31B 5th through Hole, 32A 4th bottom hole (annular hole), 32B 6th bottom hole (annular hole), 32C 7th bottom hole, 32D 8th bottom hole, 33A, 33B, 38A, 38B prepreg, 43 9th Through hole (through hole), 51A 1st build-up layer, 51B 2nd build-up layer, 100 printed wiring board.

Claims (7)

A multilayer board with build-up layers laminated on both sides of the core layer,
At least two layers of the wiring layer on the main surface on both sides of the multilayer board and the wiring layer inside, and the signal wiring formed inside the multilayer board.
It is formed inside the multilayer board with at least two layers of the wiring layer on the main surface on both sides of the multilayer board and the wiring layer inside, and is electrically insulated from the signal wiring and grounded. Equipped with grounding wiring
The signal wiring has at least one signal via that penetrates the build-up layer in the stacking direction.
The ground wiring is a printed wiring board having an annular ground via that surrounds the signal via in an annular shape and is provided in the build-up layer without a break in the stacking direction. The signal via is a conductor provided on the inner peripheral surface of the through hole penetrating the build-up layer.
A signal conductor connecting to the signal via is provided on the wiring layer on both sides of the build-up layer through which the signal via penetrates in the stacking direction.
The annular ground via seamlessly surrounds the signal conductor provided on the surface of the build-up layer on the side far from the core layer, and exposes the wiring layer on the core layer side of the build-up layer. The printed wiring board according to claim 1, which is provided inside the provided annular hole. The printed wiring board according to claim 2, wherein the annular hole is formed by laser processing. The signal via penetrates a plurality of adjacent build-up layers,
1. The plurality of annular grounding vias provided in each of the plurality of adjacent build-up layers through which the signal via penetrates are seamlessly connected in an annular shape on the connection surface of the plurality of build-up layers. The printed wiring board according to any one of claims 3. The signal via is provided so as to penetrate the core layer in the stacking direction.
The core layer is provided with a plurality of core layer grounding vias arranged so as to surround the signal via in a ring shape at intervals from the signal via.
Each of the build-up layers on both sides of the core layer and the wiring layer between the core layers are provided with an annular core grounding conductor that seamlessly and annularly surrounds the signal conductor at intervals from the signal conductor. And
The printed wiring board according to any one of claims 1 to 4, wherein the core layer grounding via and the annular grounding via are connected to the annular core grounding conductor. The printed wiring board according to any one of claims 1 to 5, wherein the annular grounding via is provided by filling the inside of the annular hole with a conductor. The annular grounding via is a conductor provided on the inner surface of the annular hole with a predetermined thickness.
The inside of the annular grounding via is filled with an insulating resin in an annular shape.
An annular grounding conductor that covers the annular grounding via and the insulating resin and surrounds the signal via in an annular shape is provided on the surface of the build-up layer on the side far from the core layer in which the annular grounding via is provided. The printed wiring board according to any one of claims 1 to 5.

Images