JP2020522728A - Flexible component with a layered structure having a metal layer - Google Patents

Abstract

Maintaining electrical conductivity in the plane of a Mo-based layer applied directly or through one or more intermediate layers on a flexible substrate subjected to one or repeated bending stress, tensile stress, and/or torsional stress. Use of an additive which is Cu, Ag, Au or a mixture thereof, and a flexible component and a metal layer containing MoX in which X is one or more elements selected from the group of Cu, Ag and Au. A flexible coated component having the layered structure and a method for producing such a flexible coated component.

Description

The invention relates to the use of an additive for maintaining the electrical conductivity in the plane of a Mo-based layer having the features of the preamble of claim 1, a flexible coated component having the features of the preamble of claim 2, and A method of manufacturing a flexible coated component having the features of the premise of claim 20.

Technological advances in the field of flexible components are closely linked to advances in the field of thin film materials. In particular, this progress has been made in electronics, especially in electronics (display screens), such as liquid crystal displays (liquid crystal display screens: TFT-LCDs), AM-OLEDs (active matrix organic light emitting diodes) or micro LED (light emitting diode) displays. It enables further development in the field of thin-film components, such as thin-film transistors (TFTs), as part of the structure for active control of the screen (active matrix). The active matrix structure can also be used in other applications, for example in sensor arrays for X-ray radiation. In these applications, the conductor paths are arranged in rows (“gate lines”, “rows”) and columns (“signal lines”, “row lines”, “data lines”) in a matrix. Conductor tracks provide a conductive path for transmitting electrical signals, currents or voltages from one point to another.

The rows or columns of each active matrix are long and narrow conductor tracks (eg, lengths of a few centimeters to less than 2 meters, widths of a few micrometers to tens of micrometers, and tens of nanometers to hundreds of nanometers). Up to a total thickness of up to) and this conductor path forms the gate electrode (“control electrode”) or source/drain electrode (“inflow electrode” and “outflow electrode”) of the TFT in the thin film transistor area, respectively. It has one or more extensions. The conductor paths are gate electrodes or source/drain electrodes of the TFT, contact areas for external contact (“conductor pads”) or gate driver structures and data driver structures (row driver and column driver) for display screen control. ) Is connected to the peripheral area of the substrate where

With active matrix control, the brightness of each individual pixel can be individually adjusted over a TFT (eg, TFT-LCD) or multiple TFTs (eg, AM-OLED display screen). In this case, it is important that the voltage drop along the long gate and signal conductor paths is as low as possible. This is because an unnecessary luminance difference depending on the length occurs in the pixel (the human eye reacts very sensitively to the luminance difference).

Particularly in the case of active matrix structures arranged on flexible, flexible or rotatable substrates, long row and column conductor tracks exhibit high deformation and/or bending and/or torsion stresses. is recieving. This stress is much smaller because the spatial extent (generally a rectangular surface with side lengths of a few micrometers to tens of micrometers) is much smaller at the gate and source/drain electrodes in the TFT structure. This stress quickly increases the electrical resistance by many orders of magnitude, especially if the conductor track material is brittle. As a result, the TFTs arranged along the conductor tracks no longer supply a defined voltage evenly, which may lead to a length-dependent brightness difference for display screen applications. In the extreme case, the conductor track completely loses its electrical conductivity, causing a total extinction of the pixel.

Especially in the case of display screens for mobile applications, such as mobile phones, tablet PCs, PDAs (Personal Digital Assistants), on the display screen substrate, in addition to the actual unit for displaying the image content, further surroundings An electric circuit is mounted. It is, for example, a gate electrode control circuit (gate driver), a source/drain electrode control circuit (data driver), a DC-DC converter, a digital-analog converter, a timing controller, or a buffer circuit and an interface circuit. The combination of such a display screen and its control unit is a system-on-panel (SOP) (system mounted on a display screen panel) or a system-on-glass (SOG) (mounted on glass) if the substrate consists of glass. System). Instead of being implemented as an external integrated circuit (IC) that includes a separate housing, it is advantageous to place the peripheral electrical circuits for display screen control directly on the substrate. The basic advantages are low manufacturing costs, low current consumption, small space requirements and high reliability. System-on-panel display screens are often implemented with low temperature poly-Silicon (LTPS) technology, but are also possible with amorphous silicon or another semiconductor such as a metal oxide. A part of the peripheral circuit arranged on the substrate is connected to the TFT of each pixel through the electric conductor path, the gate line and the signal line, and its length is from several mm depending on the size of the display screen. Up to 200 cm. The resistance change of the conductor path under deformation, bending or torsional stress is caused by preventing the individual pixels of the display screen or the entire row or column from being extinguished, or unwanted differences in brightness or color of the display screen (“mura”). Should be as small as possible to prevent

Flexible contact sensors (eg, resistive or capacitive sensors) also use matrix-arranged x and y electrodes, but generally do not have an active TFT structure. For larger sensors up to a few cm up to a few m, conductor track structures are used which are very long and thin, for example with a length between 10 cm and 100 cm and a width between 5 μm and 50 μm. Also in this application, the resistance change (increase) of the conductor path subjected to deformation, bending or torsional stress should be as small as possible. Otherwise, sensor failure (eg, due to reduced signal-to-noise ratio) may occur.

Patent Document 1 (FIG. 7), in order to reduce the mechanical stress in a conductor path under bending stress, it is non-linear, for example sinusoidal, corrugated, rectangular corrugated, meandering or sawtooth corrugated conductor. A structure is proposed. In order to prevent crack propagation, a branched and recombined conductor track structure (FIG. 8c in the above document) has been proposed. However, all of these structures require more space than simple straight conductor paths, and the current has to travel an overall longer path between the two points, thus adding additional voltage drop or signal to noise ratio. May decrease.

Furthermore, advances in the development of new integration technologies allow the combination of electronic devices and flexible substrates, and consequently the production of more flexible electronic components. This type of prior art in question is formed by US Pat. See this document for more information on the prior art.

International Publication No. 2016/032175 Austrian Utility Model No. 15048

It is an object of the present invention to maintain the electrical conductivity of a metal layer applied on a flexible substrate that is subjected to single or repeated bending, tensile and/or torsional stress. In particular, the object of the invention is an electrical conductor track (metal layer) on a flexible substrate. The electrical resistance of the conductor track along the electric conductor track, that is to say in the layer plane, changes only slightly, in particular less than 10%, when subjected to deformation, bending or torsional stresses.

The object is solved by the use of the additive according to claim 1, the flexible coated component according to claim 2 and the method for producing a flexible coated component having the features of claim 20. Preferred embodiments of the invention are defined in the dependent claims.

According to the present invention, the electrical conductivity of a Mo-based (molybdenum-based) layer or a metal layer in a layer plane when subjected to one-time or repeated bending stress and/or tensile stress and/or torsion stress of a flexible component. Guarantee maintenance. This is achieved by improving the ductility of the flexible part.

A plurality of metal layers can be provided on the flexible substrate as defined in claim 2. In that case, each metal layer is directly adjacent to the semiconductor layer or the electrically insulating layer on both sides, and the metal layer itself is formed as a single-layer structure, a two-layer structure or a three-layer structure according to claim 2. There are restrictions.

The Mo-based layer or MoX layer contains at least 50% by weight Mo, in particular at least 60% by weight Mo.

The MoX layer may be composed of a plurality of MoX partial layers having another MoX partial layer containing X.

In addition to maintaining electrical conductivity, improving ductility increases tolerance for mechanical damage. For example, it reduces the risk of delamination of multilayer composites.

Of course, the Mo-based layer (MoX layer) does not need to be pure Mo except for the additive X, but rather impurities, especially PVD (physical vapor deposition) method, especially sputtering method (cathode sputtering). There may be impurities (for example, Ar, O, N, C) derived from the process atmosphere. However, the metal impurities should be 0.5 atomic% or less.

Among the above elements Cu, Ag, and Au, Cu is particularly preferable. Lower atomic percentages are sufficient herein to achieve the desired effect. Moreover, Cu is more cost effective than Ag and Au.

According to the invention, the layered structure comprises a metal layer having a semiconductor layer or an electrically insulating layer directly adjacent to one side and a semiconductor layer or an electrically insulating layer directly adjacent to the metal layer on the other side. And layers. These properties are fulfilled at least in certain areas of the flexible coated component (however, not necessarily in all areas of the flexible component, in particular of the flexible electronic component). In addition, possible adjacent layers are described in detail below. In this case, "electrically insulating" should be understood to mean an electrical resistance of greater than 1 megohm.

As used herein, flexibility and "flexible" should be understood as the property of absorbing bending stress and/or withstanding such stress without adversely affecting the properties associated with the use of the component. That is, a sufficiently flexible component also has significantly improved ductility.

Significantly improved ductility means, in the sense of the present invention, that the component and/or of course also the one or more layers included are highly resistant to crack initiation and crack growth, up to the cracked elongation. It should be understood to mean either not formed, or only formed with greater elongation, or a change in crack progression.

To account for ductility and the resulting flexibility, critical elongation is used within the scope of the present invention. The elongation ε _{k at} which the electrical resistance R of one or more layers on the flexible substrate is 10% higher than in the initial state (R/R ₀ =1.1) is defined as the critical elongation. In a sufficiently high flexible part, the critical elongation ε _k is greatly increased and the conductivity of one or more layers is maintained significantly longer.

A flexible substrate is to be understood within the scope of the invention as a substrate which, when subjected to bending stresses, causes the elongation ε in one or more layers (coatings) deposited on the substrate. The elongation is approximately described by ε=ds/2R where one or more layers are much thinner than the substrate, where ds is the thickness of the substrate and R is the bend radius. If the layer or layers are very thin compared to the substrate, the elongation in the layer or layers can be set approximately equal to the tensile or compressive stress only. For example, the flexible substrate can be composed of one or more polymeric materials such as polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, polyether sulfone, polyarylate or polycyclic olefins. Most flexible substrates based on one or more polymeric materials have a modulus of 8 GPa or less. Thin glass (glass having a thickness of 1 mm or less), a metal plate having a thickness of 1 mm or less, for example, a steel plate, an aluminum foil having a thickness of 1 mm or less, a copper plate or a titanium foil, or a mineral material such as mica. Is also a flexible substrate suitable for the flexible component according to the present invention.

Flexible substrates suitable for the present invention can likewise consist of one or more layers and/or one or more materials. Such substrates can already be pre-completely or only partially coated with one or more layers of other materials.

The component is preferably a flexible coated component. For example, a flexible coated electronic component has at least one current conducting layer as compared to a flexible coated component such as a packaging film having a metal vapor barrier layer or an optical layer. This may be, for example, a flexible circuit, a flexible display screen, a flexible sensor element, a flexible thin film capacitor, a flexible thin film battery or a simple conductive thin film, for example a flexible printed circuit board. Examples of the above flexible electronic components that can be constructed in accordance with the present invention were described at the beginning of this specification.

The metal layer of the flexible coated component according to the present invention preferably has a thickness of 1 μm or less. The metal layer preferably has a minimum thickness of 5 nm, more preferably at least 10 nm. Moreover, a thickness of 5 nm to 300 nm and a thickness of 5 nm to 100 nm are even more preferable. The above layer thicknesses are particularly advantageous when the metal layer is used as an adhesive structure layer or a diffusion barrier layer. Alternatively, a thickness range of 150 nm to 400 nm is advantageous. A layer thickness of 150 nm to 400 nm is particularly well suited for using the coated flexible component according to the invention in a display screen, for example as a gate electrode layer.

One or more metal layers as defined in claim 2 or one of its dependent claims can be part of a thin film transistor (TFT).

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is elemental Cu, the MoCu layer containing 0.5 atom% or less to 50 atom% or less Cu, preferably 1 atom. % To 20 atomic% Cu can be contained. In this case, it is particularly preferable that the entire MoX layer of the metal layer is composed of MoCu.

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is the elemental Ag, the MoAg layer containing 10 atomic% or more and 50 atomic% or less Ag, preferably 20 atomic% or more. It can contain up to 50 atom% of Ag. In this case, it is particularly preferable that the entire MoX layer of the metal layer is composed of MoAg.

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is the elemental Au and the MoAu metal layer may contain not less than 5 atom% and not more than 20 atom% Au. In this case, it is particularly preferable that the entire MoX layer of the metal layer is composed of MoAu.

In an exemplary embodiment of the component according to the invention, each MoX layer can have a layer resistance p of 200 micro-ohm cm or less, preferably 100 micro-ohm cm or less, particularly preferably 50 micro-ohm cm or less.

In an exemplary embodiment of the component according to the invention, at least one of the semiconducting or electrically insulating layers directly adjacent to the metal layer can be formed as a plurality of layers. Also, both the immediately adjacent layers or the electrically insulating layer can be formed as a plurality of layers.

In an exemplary embodiment of the component according to the invention, the metal layer may have a layer resistance p of a total of 50 micro-ohm cm or less, preferably 10 micro-ohm cm or less, particularly preferably 3.5 micro-ohm cm or less. ..

In the method according to the invention, at least one MoX layer is deposited containing from 0.5 atomic% to 50 atomic% of X, where X is one element selected from the group Cu, Ag, Au. .. In this case, the MoX layer can form or become part of the metal layer as defined in claim 2.

The deposition of the at least one MoX layer and/or the metal layer can be performed by various types of vapor deposition methods. For example, the deposition can be done by physical vapor deposition or chemical vapor deposition.

However, it is advantageous for the deposition of the at least one MoX layer and/or the metal layer to be carried out by PVD methods, in particular sputtering methods. The PVD method (physical vapor deposition) is known as a thin film coating technique. This technique converts particles of the coating material into the gas phase before depositing it on the substrate. By the PVD method, particularly uniform deposition can be achieved. The property is to deposit a coating that is equally isotropic over the coated surface. A further advantage of this method is the resulting low substrate temperature. Thus, for example, polymer coating is possible. Furthermore, the PVD layer excels in very good adhesion to the substrate.

It is particularly preferred when the MoX layer or the metal layer is deposited by sputtering (also called cathodic sputtering). The sputtering method is relatively cost-effective for mass production because it can be used relatively easily for large area uniform coatings.

It is highly preferred that the method according to the invention further comprises the step of providing a Mo-based target containing between 0.5 and 50 atomic% of X.

The Mo-based target containing between 0.5 and 50 atomic% of X is provided prior to the deposition of the at least one MoX layer and/or the at least one metal layer. Therefore, the MoX layer and/or the metal layer are deposited from the provided target.

In this case, the target is to be understood as the coating source of the coating device. In one preferred method, the target used is a sputtering target for a sputtering method.

The chemical composition of the coating is determined by the chemical composition of the target used. However, the deviation of the coating composition from the target composition can be caused by the slightly different sputtering behavior (sputtering yield) of the elements contained in the target.

For example, suitable sputtering of Cu from a MoCu target may slightly increase the Cu content in the deposited coating. For example, to form a coating containing 10 atomic% or more Cu, the corresponding target should also contain 10 atomic% or less Cu.

Alternatively, the metal layer can also be deposited by co-deposition from individual targets, preferably co-sputtering, to use only one target. In this case, the chemical composition of the coating can be further controlled by the choice of different targets.

The production of sputtering targets more suitable for the deposition of metal layers can be carried out, for example, by powder metallurgy.

Possible powder metallurgical methods for the production of sputtering targets are based on hot pressing methods such as hot pressing (HP) or spark plasma sintering (SPS). In both cases, the powder mixture is cast into a press mold, heated in the mold and sintered/packed at high compression pressure and temperature to a high density part. In this case, a homogeneous microstructure with uniform particles without preferential orientation (texture) results.

A similar powder metallurgical method for producing sputtering targets is hot isostatic pressing (HIP). In this case, the compacted material is poured into a deformable high density container (typically a metal can). In this case, the material can be a powder, a powder mixture or a green compact (in the form of a compressed powder). The material present in this vessel is sintered/compacted at high temperature in a pressurized in-vessel vessel under a protective gas (eg argon). This method is called isotropic pressurization because the gas pressure acts from all directions. Typical process parameters are, for example, a holding time of 3 hours at 1100° C. and 100 MPa. In this case, a homogeneous microstructure with uniform particles without preferential orientation (texture) results.

A further option for producing sputtering targets by powder metallurgical methods is sintering and subsequent shaping. In this case, the powder compact is sintered under hydrogen atmosphere or under vacuum. After sintering, a high relative density of more than 99% can be obtained by performing a forming process such as rolling or forging. In this case, a microstructure with elongated particles having a preferred orientation (texture) is produced. On any subsequent low-strength anneal or recrystallization anneal, uniform grains are produced, but the grains still have a homogeneous microstructure with a preferred orientation (texture).

A further option for the production of sputtering targets by powder metallurgical methods is to apply the powder or powder mixture onto the corresponding support structure, eg metal or tube, by means of the thermal spraying method, eg cold gas spraying or vacuum plasma spraying (VPS). Is.

In the following, the invention will be explained in more detail on the basis of exemplary embodiments and the drawings.

1 shows a schematic configuration of a uniaxial tensile test for measuring electric resistance used for critical breaking elongation ε _k measurement. 3 shows the R/R ₀ curves for Mo and MoCu alloys as a function of Cu content in the layer. The electron microscope photograph of the crack pattern of the Mo layer and the various MoCu layers after the maximum elongation of 15% is shown. 3 shows the R/R ₀ curves for Mo and MoAg alloys as a function of Ag content in the layer. The electron microscope photograph of the crack pattern of the Mo layer and the various MoAg layers after the maximum elongation of 15% is shown. 1 shows a cross section of a layered structure of a bottom gate type thin film transistor. Figure 3 shows a schematic block diagram (from above) of a system on panel display screen. 3 shows a detail of the system-on-panel display screen as seen from above the conductor path structure between the driver circuit and the TFT display screen area. 3 shows details of a TFT display screen structure (from above, top view) showing how the gate and source/drain electrodes of the TFT are connected to the gate and data lines. The cross section of the layered structure of a top gate type LTPS-TFT is shown. Figure 4 shows an X-ray diffractogram of a 500 nm thick MoCu thin film sputtered on a silicon wafer. Figure 3 shows an X-ray diffractogram of a 500 nm thick MoAg thin film sputtered on a silicon wafer.

Example 1
Various Mo-based metal layers were deposited on a polyimide substrate within a series of multiple experiments. In this case, layers having various chemical compositions were formed.

The composition of the Mo-based metal layer is summarized in Table 1.

[Table 1] Chemical composition of sputtered MoCu layer

Pure Mo was used as a reference material for the molybdenum-based alloy in the form of a molybdenum layer having a thickness of 50 nm.

All layers were deposited at room temperature on a 50 μm thick thin film of polyimide (PI, eg Kapton®). In this case, the process parameters were kept constant in order to eliminate the influence of different process conditions on the results as much as possible. The layer thickness was kept constant at 50 nm to avoid the influence of shape effects on the results.

The substrate surface was completely covered and no structures were produced, for example by etching.

A uniaxial tensile test was performed on the layer sample on the polyimide substrate using an MTS Tyron 250 (registered trademark) general purpose tester. The test setup is shown schematically in FIG. In this case, the substrate was elastically deformed to a maximum elongation ε of 15%. During the tensile test, the electrical resistance R of the layer was continuously recorded using the four-point method. The electrical resistance at the start of measurement is called R ₀ . In this case, the sample length (free length between the clamps) in the initial state was 20 mm, and the width was 5 mm.

The measurement setup is shown schematically in FIG. In this case, _Lconst indicates a fixed clamp length with no elongation. Here, the critical elongation is defined as the critical elongation ε _k . The electrical resistance R of the layer on the flexible substrate increased by 10% with respect to the initial state, R/R ₀ =1.1.

Table 2 shows the critical elongation ε _k obtained by this tensile test.

[Table 2] The critical elongation ε _{k of} the Mo and MoCu layers investigated and the difference from the reference sample consisting of pure Mo. Furthermore, it shows the layer resistance of a 500 nm thick layer on a non-conducting borosilicate glass (Corning Eagle XG®).

FIG. 2 shows the increase in electrical resistance versus initial resistance (R/R ₀ ) with elongation ε. The curve "theoretical" shows the increase in electrical resistance caused only by the change in shape of the sample. As is evident in the curves measured on the basis of the reference material, the electrical resistance increases very rapidly with increasing elongation.

After the tensile test described above, the layers tested were examined with a light microscope and a scanning electron microscope. In this case, the crack shape and the average distance between the cracks formed in the layer were determined.

For example, in a layer based on a brittle material such as pure Mo, when the sample is damaged under tensile stress, a cracking pattern characteristic of the behavior of the brittle material usually occurs. It is characterized by a network of linear, parallel-run cracks that form approximately perpendicular to the stress direction. Such a crack pattern can be seen, for example, in FIG. 3 (Mo, left). These linear cracks not only mostly run the entire width from one side of the sample to the other, but also run through the full thickness of the layer. Such a crack is also called a through crack (TTC). TTC significantly reduces the electrical conductivity of the layer. This is because, in the worst case, a continuous conductive connection no longer exists in the layer.

It can be seen from Table 2 that the critical elongation of failure criterion R/R ₀ =1.1 increases the ductility of the layer as the Cu content in the layer increases. It is speculated that this increase in ductility was caused by easy displacement movement within the material. This reduces the increase in critical elongation and the occurrence of TTC.

As an example, FIG. 2 shows the resistance curve R/R ₀ for the sample MoCu 7 atom %. The appearance pattern of cracks still corresponds to TTC, but the critical elongation ε _k has already increased significantly.

A further effect that can be observed in addition to the increase in the critical elongation ε _k is that the appearance pattern of cracks changes from the behavior of brittle materials to that of ductile materials. The cracks characteristic of the behavior of ductile materials are zigzag rather than straight cracks. Crack bending at the crack tip is a possible explanation for such crack behavior.

In FIG. 3 (center view, MoCu 18 atomic %), it can be seen that in the case of MoCu 18 atomic %, the cracks certainly run in parallel, but no longer linearly. In FIG. 3 (right diagram, MoCu 52 atom %), a ductile crack pattern has already occurred. Ductile cracks run largely through the full layer thickness, but not necessarily over the entire sample width, so that the conductive connection still remains in the material. In this case, as can be seen from FIG. 2, the slope of the R/R ₀ curve is small (the curve does not rise sharply).

Therefore, the critical elongation ε _k is significantly increased and crack initiation is reduced from the small Cu content in the Mo-based layer. As the Cu content increases further, the cracking behavior changes from brittle to ductile. Therefore, Cu as an additive to Mo is particularly advantageous in that the ductility of the Mo-based layer is significantly increased even if the addition is small, and Cu is relatively cost effective as a material.

FIG. 11 shows the X-ray diffractograms of two MoCu layers with a Cu content of 18 atom% and 34 atom %, respectively. A diffractogram of the pure Mo layer or Cu layer, respectively, is also included as reference material. All layers are deposited by DC sputtering on silicon wafers at room temperature (without heating the substrate) and have a thickness of 500 nm. The crystal structure was recorded with a Bruker-AXS D8 diffractometer equipped with a Cu-Kα X-ray source in the grazing incidence mode at an incident angle of 2°. As reference materials, the position of X-ray reflection of body-centered cubic (cl) molybdenum is shown as a vertical dotted line, and the reflection position of face-centered cubic (cF) copper is shown as a vertical broken line. The data was obtained from the ICDD (International Diffraction Data Center) database. As can be seen from FIG. 11, the two systems of MoCu 18 atom% and MoCu 34 atom% with a high copper content do not have another Cu phase because there is no corresponding reflection in the diffractogram. Therefore, it can be estimated that Cu is forcedly dissolved in molybdenum in the form of a mixed crystal, that is, copper atoms occupy the molybdenum space lattice. Copper atoms thus cause the strain of the Mo lattice. Since the Cu atom (atomic radius 128 pm) is smaller than the Mo atom (140 pm), there are two Mo(110) reflections deviating to a larger refraction angle (2θ) and a larger refraction angle (2θ) than the undistorted reference material. The Mo(200) reflection also shows a distorted Mo lattice.

Furthermore, in the last column of Table 2, the layer resistance ρ (micro ohm cm) of various Mo thin films or MoCu thin films is shown (layer thickness of 500 nm on the insulating glass substrate). For the measurement, the surface specific resistance R _s (ohm/sheet) was measured by the four-point method and multiplied by the layer thickness. The layer resistance of the MoCu layer increases to a Cu content of 34 atomic% and then decreases again with increasing Cu content. All MoCu layers have a layer resistance of 150 micro ohm cm or less.

In the case of multilayers consisting of MoCu/Cu or MoCu/Al, the layer resistance along the long conductor tracks is determined by the material Cu or Al, which has a particularly good conductivity. A bilayer of 50 nm MoCu 34 atomic% and 300 nm Cu formed thereon (deposited on a non-conducting glass substrate) has a layer resistance of 2.0 micro ohm cm. A bilayer of 50 nm MoCu 34 atomic% and 300 nm Al above it has a layer resistance of 3.1 micro-ohm cm.

It is speculated that the mechanical properties of the investigated layers can be further optimized. Therefore, the targeted heat treatment may further optimize the microstructure and internal stress state of the deposited Mo-based layer. It is also very likely that the setting for deposition conditions will also deliberately influence layer growth and further increase ductility.

Example 2
Within a series of multiple experiments, various Mo-based metal layers were deposited on polyimide substrates. In this case, layers having various chemical compositions were formed.

The composition of the Mo-based metal layer is summarized in Table 3.

Table 3 Chemical composition of sputtered MoAg layers

Pure Mo having a thickness of 50 nm was used in the form of a molybdenum layer as a reference material for the molybdenum based alloy.

All layers were deposited at room temperature on a 50 μm thick thin film of polyimide (PI, eg Kapton®). In this case, the process parameters were kept constant in order to eliminate the influence of different process conditions on the results as much as possible. The layer thickness was kept constant at 50 nm to avoid geometrical effects on the results.

The substrate surface was completely covered and, for example, the etching method did not produce any small structures.

Table 4 shows the critical elongation ε _k obtained by the tensile test as described in Example 1.

[Table 4] The critical elongation ε _{k of} the Mo and MoAg layers investigated and the difference from the reference sample consisting of pure Mo. Furthermore, it shows the layer resistance of a 500 nm thick layer on a non-conducting borosilicate glass (Corning Eagle XG).

After the tensile test described above, the layers tested were examined with a light microscope and a scanning electron microscope. In this case, the shape of the cracks and the average distance between the cracks formed in the layer were determined.

For example, in layers based on brittle materials such as pure Mo, when the sample is damaged under tensile stress, a crack pattern that is characteristic of the behavior of the brittle material is usually produced. It is characterized by a network of parallel, linear cracks that form approximately perpendicular to the stress direction. The crack pattern described above can be seen, for example, in FIG. 5 (Mo, left). Most of these linear cracks run not only across the entire width of one side of the sample to the other, but also through the full thickness of the layer. Such a crack is also called a through crack (TTC). In the worst case, the continuous conductive connection no longer exists in the layer, so that the TTC significantly reduces the electrical conductivity of the layer. As is evident in the curves measured on the basis of the reference material, the electrical resistance increases very rapidly with increasing elongation.

It can be deduced from FIG. 4 which shows the increase in electrical resistance versus initial resistance (R/R ₀ ) with respect to the elongation ε.

The critical elongation of failure criterion R/R ₀ =1.1 which can be inferred from Table 4 shows that the ductility of the layer is significantly large, as is clear from FIG. 4 and Table 4, from the critical Ag content in the layer larger than 18 atomic %. It has been shown to increase. It is speculated that this increase in ductility is caused by easy displacement movement within the material. As a result, the critical elongation is increased and the TTC generation is reduced. Therefore, Ag as an additive to Mo is particularly excellent in that the ductility of the Mo-based layer increases significantly when the amount of addition is large.

As an example, FIG. 4 shows the resistance curves R/R ₀ of various MoAg samples. As is clear from FIG. 5 (upper right), the appearance pattern of cracks still corresponds to TTC, but the critical elongation ε _k has already increased significantly.

A further effect that can be observed in addition to the increase in the critical elongation ε _k is that the crack initiation can change from the behavior of brittle materials to that of ductile materials. It can be seen that the cracks characteristic of the behavior of ductile materials are no longer straight, but rather zigzag. Bending of the crack at the crack tip is a possible explanation for the above crack behavior.

In FIG. 5 (MoAg 44 atomic %), it can be seen that in the case of MoAg 44 atomic %, the cracks certainly run in parallel but no longer linearly. FIG. 5 (MoAg 52 atomic %) already clearly shows many ductile crack patterns. Cracks with many ductile properties run through the entire layer thickness, but not necessarily over the entire sample width, so that the conductive connection still remains in the material. In this case, as can be seen from FIG. 4, the slope of the R/R ₀ curve is small (the curve does not rise sharply).

From the critical Ag content in the Mo-based layer of 18 atomic %, the critical elongation ε _k increases significantly and the crack initiation decreases. As the Ag content increases further, the cracking behavior changes from ductile direction to brittle.

FIG. 12 shows the X-ray diffractogram of the deposited MoAg layer. The layer deposition and analysis of the crystal structure was performed as in the MoCu system (FIG. 11). As a reference material, the diffractogram of the pure Mo or Ag layer is also included. In FIG. 12, the X-ray reflection position of body-centered cubic (cl) molybdenum is shown as a vertical dotted line and the reflection position of face-centered cubic (cF) silver is shown as a vertical broken line as reference materials. The data was obtained from the ICDD (International Diffraction Data Center) database. As shown in FIG. 12, the MoAg system does not have another Ag phase up to a silver content of 44 atomic% because there is no corresponding reflected light in the diffractogram. Therefore, it should be assumed that Ag is forced to dissolve in molybdenum in the form of mixed crystals, ie silver atoms occupy the molybdenum spatial lattice. In the silver atom, the distortion of the Mo lattice occurs in this way. Two Mo(110) and Mo(200) reflected lights that are shifted to a lower refraction angle (2θ) compared to the undistorted reference material also show a distorted Mo lattice. Because the Ag atoms (atomic radius 165 pm) are larger than the Mo atoms (140 pm), as shown by the layer of Mo(220)Ag 52 at% indicating the initial precipitation of another silver phase in the molybdenum chloride matrix, Only silver reflection is observed.

Therefore, in the MoCu thin film or the MoAg thin film, copper or silver (element X) is forcibly dissolved in the molybdenum oxide lattice. The crystal structure of pure gold (Au) is the same as that of Cu and Ag (Fm-3m space group). All three elements belong to the same subgroup (11) of the periodic system of chemical elements and exhibit similar chemical and physical behavior in many respects. Therefore, it should be assumed that even sputtered MoAu thin films with an Au content of 40 atomic% or less are present in the form of mixed crystals with gold atoms forcedly dissolved in the molybdenum oxide matrix.

Furthermore, in the last column of Table 4, the layer resistance ρ (micro ohm cm) of various Mo thin films or MoAg thin films is shown (layer thickness of 500 nm on the insulating glass substrate). For the measurement, the surface resistivity R _s (ohm/sheet) was measured by the four-point method and multiplied by the layer thickness. The layer resistance of the MoAg layer increases up to 31 atomic% Ag content and then decreases again with increasing Ag content. All MoAg layers have a layer resistance of 150 micro ohm cm or less.

In the case of multilayers consisting of MoAg/Cu or MoAg/Al, the layer resistance along the long conductor tracks is determined by the good conductive material Cu or Al, respectively. A bilayer of 50 nm MoAg 31 at% and 300 nm Cu (deposited on a non-conducting glass substrate) formed thereon has a layer resistance of 2.0 micro ohm cm. A bilayer of 50 nm MoAg 31 at% and 300 nm Al formed thereon has a layer resistance of 3.1 micro-ohm cm.

One or more metal layers as defined in claim 2 and one of its dependent claims can be part of a thin film transistor (TFT). The layered structure of the above insulating thin film component is shown in cross section in FIG. The TFT includes a semiconductor layer 150, a gate electrode 120, a source electrode 170a, and a drain electrode 170b, and at least one of these three metal conductive electrode layers is a metal layer according to the present invention. The gate electrode 120 and the semiconductor layer 150 are separated by an electrically insulating layer (gate insulator, gate dielectric) 140. The source electrode 170a and the drain electrode 170b are separated by the electrically insulating protective layer 180. Further, the protective layer 180 separates the source/drain electrodes 170a/170b from the pixel electrode layer 190 (excluding the contact holes described below).

Hereinafter, a general layered structure of the bottom gate type TFT as shown in one embodiment of FIG. 6 will be described. The TFT layered structure is disposed on the flexible substrate 100. First, irregularities in the upper part of the flexible substrate 100 can be compensated or unwanted impurities can be prevented from entering the semiconductor layer 150, for example by diffusion or penetration. A buffer layer 110 that covers the entire substrate 100 may be disposed on the flexible substrate 100. The buffer layer can be composed of one or a plurality of layers containing, for example, silicon oxide or silicon nitride. The gate electrode 120 is arranged on the buffer layer 110. By applying a voltage, a conductive channel that conductively connects the source electrode 170a to the drain electrode 170b can be formed by a field effect in the semiconductor layer 150. The gate electrode 120 may be a metal layer according to the present invention, or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the conventional technology. The metallization may be composed of one or more layers containing (W), titanium (Ti), chromium (Cr), niobium (Nb) and tantalum (Ta).

An electrically insulating layer (gate dielectric) 140 is disposed on the gate electrode 120. The electrically insulating layer 140 can include, for example, a layer of silicon oxide, silicon nitride, aluminum oxide, or an organic insulating material such as benzocyclobutene (BCB) or an acrylic-containing material.

The semiconductor layer 150 is adjacent to the electrically insulating layer (gate dielectric) 140, and is made of, for example, a metal oxide semiconductor such as amorphous silicon (a-Si), polysilicon, or indium gallium zinc oxide (IGZO), or an organic semiconductor. Can be included. In the case of a semiconductor layer 150a containing a-Si, for example, an n+ doped semiconductor layer 150b containing phosphorus-doped a-Si can be arranged on this layer. In the case of the semiconductor layer 150a containing a metal oxide semiconductor such as IGZO, the doped semiconductor layer 150b is generally omitted.

The source and drain electrode layers 170a and 170b are provided over the semiconductor layer 150. These layers are the metal layers according to the invention or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the prior art. The metallization may be composed of one or more layers containing (W), titanium (Ti), chromium (Cr), niobium (Nb) and tantalum (Ta).

The protective layer 180 is disposed on the semiconductor layer 150 and the source/drain electrode layers 170a/170b. The electrical insulation protection layer 180 can include, for example, a layer of silicon oxide, silicon nitride, aluminum oxide, or an organic insulating material such as benzocyclobutene (BCB) or an acrylic containing material.

The protective layer 180 is separated by a contact hole that electrically connects the pixel electrode layer 190 and the drain electrode 170b adjacent to each other. The pixel electrode layer 190 is electrically conductive, can be formed as a light transmissive layer or a light reflective layer, and can be composed of one or more layers. When the pixel electrode layer 190 is formed as a light transmissive layer, the layer may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum zinc oxide (AZO). Can be included. When the pixel electrode layer 190 is formed as a light reflecting layer, the layer is not only a light reflecting layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, but also indium tin oxide ( A layer of ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO) can be included.

The TFTs described herein can be part of a flexible TFT liquid crystal display screen or organic EL display screen.

One or more metal layers as defined in claim 2 and one of its dependent claims provide a system on panel (SOP) system in which a TFT active matrix display is arranged on a substrate together with a peripheral electronic control unit. Can be part. The SOP is shown in FIG. The display unit 1 includes, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or an electrophoretic display screen (“E-Ink (registered trademark)”, “electronic paper”). Can consist of The display unit 1 shows the actual visible part of the display screen on which the image content is displayed. Although some driver and control circuitry is located around this area, they are typically hidden behind the light-tight portion of the housing and are not visible to the user. In principle, one or more of the electronic circuits described below can be located on the SOP. The description here is not exhaustive and still requires additional circuits for control depending on the display device used.

In order to control the display unit 1, a horizontal data driver circuit (column driver) 2a/b can be arranged on the substrate, and the circuit includes a source/drain electrode 170a of the TFT via a data line (not shown). /B (not shown). For controlling the gate electrode 120, a gate driver structure (row driver) 3 connected to the gate electrode 120 (not shown) of the TFT via a gate line (not shown) can be arranged on the substrate.

Furthermore, a DC-DC converter 4 for converting a low input voltage to a high output voltage can be arranged in the peripheral region, and for controlling the TFT-LCD display screen, for example, a voltage of +3.3V to +5.0V is used. Can be applied to the input and its voltage is converted to a high output voltage in the range of −40V to +40V required for controlling the liquid crystal display (“charge pump”).

Furthermore, an electric circuit 5 for supplying a reference voltage (Vcom, for example +5V for the LCD display screen) for the display unit 1 can be arranged on the SOP.

Further, the timing control circuit (TCon) 6, the digital-analog conversion circuit 7, the discharging unit 8, and the Vcom buffer circuit 9 can be arranged on the substrate.

The SOP is connected to the rest of the display screen control electronics or graphics card via the contact area 10. The peripheral circuits 2-9 are interconnected with the display unit 1 and the contact areas (“conductor pads”) 10 by means of a metal layer (not shown) according to the invention.

As an example, the contact of the display unit 1 is shown in FIG. The row driver 3 is connected to the display unit 1 via an electrical conductor path 20, and the column driver 2b is connected to the display unit 1 via an electrical conductor path 21. One or both of the conductor tracks 20 or 21 can consist of a metal layer according to the invention as defined in claim 2 and one of its dependent claims.

FIG. 9 shows a contact between a thin film transistor (TFT) and a gate line and a data line. The gate conductor track 20 has an extension in the TFT region which forms the gate electrode 120 of the TFT. In the area of the TFT, the data conductor path 21 includes an extension portion that forms the source electrode 170a of the TFT, and an area that forms the drain electrode 170b of the TFT and is divided by the source electrode connected to the pixel electrode 190. Have. One or both of the conductor tracks 20 or 21 and/or the TFT electrodes 120, 170a/b can consist of a metal layer according to the invention as defined in claim 2 and one of its dependent claims.

Furthermore, the layered structure of one or more metal layers defined in claim 2 and one of its dependent claims is, for example, part of a low temperature polysilicon (LTPS) thin film transistor (TFT) shown in FIG. Can become Compared to the TFT structure of FIG. 6, in this case the top gate type TFT, ie the gate electrode 240, is arranged above, not below, the semiconductor layer 220. The LTPS-TFT is preferably configured as a top gate type TFT. LTPS semiconductor, as compared to amorphous silicon ^{(0.5cm 2 /Vs~1.5cm 2 / Vs)} , has a significantly higher charge carrier mobility ^{(50cm 2 / Vs~200cm 2 / Vs} ). Therefore, the above-mentioned TFT can be used for controlling a current drive type display device such as an OLED or a micro LED.

The layered structure of the top gate type LTPS TFT will be described below as an example. The LTPS-TFT is arranged on the flexible substrate 200. First, the irregularities on the flexible substrate 200 are compensated, or into the semiconductor layer 220 or into the doped semiconductor regions 221 (source electrode) and 222 (drain electrode), for example by diffusion or A buffer layer 210 that covers the entire substrate 200 may be disposed on the flexible substrate 200 to prevent unnecessary impurities from entering due to permeation. The buffer layer 210 can be composed of one or a plurality of layers containing, for example, silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer may be omitted depending on the composition of the substrate.

A semiconductor layer 220, which can be composed of undoped polycrystalline silicon, is arranged on the buffer layer 210. Adjacent to this layer 220 (also called the "channel region") is a source electrode 221 on one side and a drain electrode 222 on the other side. Each of these electrodes can be composed of doped polysilicon. Doping can be performed, for example, by ion implantation, and p-doping can be performed, for example, by using boron (B) or B ₂ H ₆ . Depending on the TFT embodiment, the type of doping (p or n) and/or the type of dopant can of course vary.

The gate insulator layer 230 is disposed on the semiconductor layers 220, 221 and 222. The gate insulator layer 230 can be composed of, for example, silicon nitride or silicon oxide. The gate electrode 240 is arranged on the gate insulator layer 230 so that the gate electrode has at least an overlap region (in the vertical direction) which is a channel region (semiconductor layer 220). The gate electrode 240 may be a metal layer according to the present invention, or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the conventional technology. The metallization may be composed of one or more layers containing (W), titanium (Ti), chromium (Cr), niobium (Nb) and tantalum (Ta). The gate electrode 240 is connected via a gate line (not shown) to control electronics (not shown), in particular a row driver.

On the gate electrode 240 or the gate insulator layer 230, an insulating layer 250, which can be composed of the same material as the gate insulator layer 230, for example, silicon nitride or silicon oxide, is applied. The insulating layer 250 and the gate insulator layer 230 are provided with through holes (“through holes”) that allow the source and drain electrodes 221/222 to (electrically) access the semiconductor layers.

The control and/or source contact electrode layer 260 and/or the control and/or contact drain electrode layer 270 are disposed on the insulating layer 250 and connected to the semiconductor source electrode/drain electrodes 221/222 through the through holes. Has been done. The control and/or source/drain electrode layer 260/270 may be a metal layer according to the present invention, or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt) corresponding to the prior art. ), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), niobium (Nb), and tantalum (Ta). The control and/or contact source electrode layer 260 is connected via data lines (signal lines; not shown) to control electronics, in particular column drivers (not shown).

The thin film transistor is formed of the semiconductor layer 220, the gate electrode 240, and the control and/or contact source/drain electrode layer 260/270. However, the TFT configuration is not limited to the exemplary embodiments described above, but rather may have numerous alternative configurations that can be easily implemented by one of ordinary skill in the art.

A planarization layer 280 may also be disposed on the TFT structure, especially if a further light emitting layer, such as an OLED layer (not shown), is disposed on the TFT. The planarization layer 280 can include, for example, polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The planarization layer 280 is provided with through holes that allow access to the control and/or contact drain electrode layer 270 regions.

In FIG. 10, a pixel electrode layer 290 is also shown as an example, and the pixel electrode layer 290 is formed on the planarization layer 280 and is conductively connected to the control and/or contact drain electrode layer 270 through the through hole. Has been done. In the case of an LTPS-OLED display screen, the pixel electrode layer 290 forms the first electrode of the light emitting structure (typically the anode in the upward emitting structure). When the pixel electrode layer 290 is formed as a light transmissive layer, the layer may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO). Can be included.

When the pixel electrode layer 290 is formed as a light transmissive layer, the layer is not only a reflective layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, but also indium tin oxide ( A layer containing ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or zinc aluminum oxide (AZO) can also be included.

It is speculated that the mechanical properties of the investigated layers can be even further optimized. Thus, the targeted heat treatment could further optimize the microstructure and internal stress states of the deposited molybdenum-based layer. It is also very possible that the setting of the deposition conditions can also have a deliberate effect on the growth of the layer and further increase the ductility.

Electric resistance of R layer R ₀ Electric resistance at the start of measurement R ₀ Surface specific resistance ε Maximum elongation ε _k Critical elongation L _const Fixed clamp length without elongation ρ Layer resistance 1 Display device 2a/b Data driver circuit (row) driver)
3 Gate driver structure (row driver)
4 DC-DC conversion circuit 5 Electric circuit 6 Timing control circuit (TCon)
7 Digital-Analog Converter Circuit 8 Discharge Section 9 Buffer Circuit 10 Contact Area ("Conductor Pad")
20 electrical conductor path 21 electrical conductor path 100 flexible substrate 110 buffer layer 120 gate electrode 140 insulating layer (gate insulator, gate dielectric)
150 semiconductor layer 170a source electrode 170b drain electrode 180 insulating protective layer 190 pixel electrode layer 200 flexible substrate 210 buffer layer 220 semiconductor layer 221 doped semiconductor region (source electrode)
222 Doped semiconductor region (drain electrode)
230 gate insulator layer 240 gate electrode 250 insulating layer 260 control and/or contact source electrode layer 270 control and/or contact drain electrode layer 280 planarization layer 290 pixel electrode layer

Claims (21)

Electricity of Mo-based layers in a layer plane applied directly or via one or more intermediate layers on a flexible substrate (100, 200) subjected to one or repeated bending, tensile and/or torsional stresses Use of an additive for maintaining conductivity, said additive being Cu, Ag, Au, or a mixture thereof, use. Flexible substrate (100, 200),
Directly or via one or more intermediate layers disposed on the flexible substrate (100, 200), having directly adjacent semiconductor layers or electrically insulating layers on one side, and directly adjacent to each other. A flexible coated substrate comprising: a semiconductor layer or at least one layered structure having a metal layer having an electrically insulating layer on the other side,
The metal layer is
Single layer structure composed of MoX,
A two-layer structure composed of a combination of MoX and a Cu-based layer or a combination of MoX and an Al-based layer, or
A three-layer structure composed of two MoX layers and a Cu-based layer interposed therebetween or two MoX layers and an Al-based layer interposed therebetween,
Here, X is one or more elements selected from the group of Cu, Ag, and Au, wherein the flexible coated substrate is characterized. The flexible coated substrate according to claim 2, wherein in at least one MoX layer, X is elemental Cu, and the MoCu layer contains 0.5 atomic% or more and 50 atomic% or less Cu. The flexible coated substrate according to claim 2 or 3, wherein in at least one MoX layer, X is an elemental Ag, and the MoAg layer contains Ag of 10 atomic% or more and 50 atomic% or less. The flexible coating according to any one of claims 2 to 4, wherein in at least one MoX layer, X is an elemental Au and the MoAu metal layer contains 5 atomic% or more and 20 atomic% or less Au. substrate. The flexible coated substrate according to any one of claims 2 to 5, wherein X in the Mo layer is formed by dissolving in a mixed crystal form. The flexible coated substrate according to any one of claims 2 to 6, wherein each of the MoX layers has a layer resistance ρ of 200 micro ohm cm or less. The component according to any one of claims 2 to 7, wherein the flexible substrate (100, 200) is formed separately from the electrically insulating layer. The flexible coated substrate according to any one of claims 1 to 7, wherein the flexible substrate (100, 200) is formed by one of a semiconductor layer or an electrically insulating layer that is directly adjacent to the metal layer. .. At least one of a semiconductor layer or an electrically insulating layer directly adjacent to the metal layer is formed as a plurality of layers (140, 150, 220, 250). The flexible coated substrate described. The flexible coated substrate according to claim 2, wherein the metal layer has a thickness of 1 μm or less, preferably 500 nm or less, preferably 5 nm to 100 nm. The flexible coated substrate according to any one of claims 2 to 11, wherein the flexible substrate (100, 200) is transparent. 13. The flexible coated substrate according to claim 2, wherein the entire metal layer has a layer resistance ρ of 50 micro ohm cm or less. The flexible substrate (100, 200) is
Polymer,
Thin glass,
Metal foil,
Mineral materials,
The flexible coated substrate according to any one of claims 2 to 13, comprising at least one material selected from the group consisting of: The metal layer has a ratio (R/R ₀ ) of an electric resistance (R) to an electric resistance (R ₀ ) at the start of measurement of 1.2% or less at an elastic elongation (ε) of 2%. 15. The flexible coated substrate according to any one of 1 to 14. The flexible coated substrate (100, 200) has at least one conductor track structure, and is preferably formed such that the metal layer is part of the at least one conductor track structure. 16. The flexible coated substrate according to any one of items 1 to 15. The flexible coated substrate according to claim 2, wherein the metal layer is a part of a TFT structure. The flexible coated substrate according to claim 2, wherein the metal layer is part of an active matrix structure. The flexible coated substrate is a group of flexible liquid crystal display screen, flexible organic EL display screen, flexible electrophoretic display screen (electronic paper, E-Ink (registered trademark)), flexible solar cell, electrochromic flexible film, flexible thin film battery. The flexible coated substrate according to any one of claims 2 to 18, which is a component to be selected. A step of preparing a flexible substrate (100, 200),
Coating the flexible substrate (100, 200) by deposition of at least one MoX layer, either directly or via one or more intermediate layers, and
In particular, a method for producing a flexible coated substrate according to any one of claims 2 to 19, particularly a flexible coated substrate used by using the additive according to claim 1.
The MoX layer contains 0.5 atomic% or more of X,
Here, X is one or more elements selected from the group consisting of Cu, Ag, and Au. The method for manufacturing a flexible coated substrate according to claim 20, wherein the at least one metal layer is deposited by a PVD method.