CN115714128A - Array substrate, preparation method thereof, display panel and display device - Google Patents
Array substrate, preparation method thereof, display panel and display device Download PDFInfo
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Abstract
The embodiment of the invention discloses an array substrate, which comprises: a substrate; a first buffer layer on one side of the substrate, the first buffer layer comprising silicon nitride; the second buffer layer is positioned on one side, far away from the substrate, of the first buffer layer and comprises silicon oxide; the polycrystalline silicon active layer is positioned on one side, far away from the substrate, of the second buffer layer, and a plurality of bulges are formed on the surface of one side, far away from the substrate, of the polycrystalline silicon active layer; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate. Because the rapid change of heat can generate the bulge to cause the threshold voltage drift in the preparation process of the polycrystalline silicon active layer, the array substrate provided by the embodiment of the invention avoids the rapid change of heat in the preparation process of the polycrystalline silicon active layer by arranging the buffer layers comprising the first buffer layer and the second buffer layer which are arranged in a laminated manner, can reduce the height of the bulge, can improve the drift of the threshold voltage and has the effect of improving the short-time residual image.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof, a display panel and a display device.
Background
Organic Light-Emitting diodes (OLEDs) have advantages of small size, simple structure, self-emission, high brightness, good picture quality, large viewing angle, low power consumption, short response time, etc., and thus have attracted much attention and are likely to become a next-generation display technology replacing liquid crystals.
However, when the display screen of the OLED is switched to a picture, and the bright area and the dark area are switched to the same gray scale, the brightness is not uniform in a short time due to the electric hysteresis of the transistor, and the image sticking phenomenon is easily caused, thereby seriously affecting the display effect.
Disclosure of Invention
In view of this, embodiments of the present invention provide an array substrate, a method for manufacturing the array substrate, a display panel and a display device. By reducing the height of the protrusion on the surface of the polysilicon active layer, the drift of threshold voltage is improved, and the short-time ghost phenomenon is improved.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
a substrate;
a first buffer layer on one side of the substrate, the first buffer layer comprising silicon nitride;
a second buffer layer located on a side of the first buffer layer away from the substrate, the second buffer layer comprising silicon oxide;
the polycrystalline silicon active layer is positioned on one side, far away from the substrate, of the second buffer layer, and a plurality of bulges are formed on the surface of the polycrystalline silicon active layer, far away from the substrate; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate.
Optionally, in the array substrate, along the first direction, the thickness H3 of the first buffer layer satisfies that H3 is greater than or equal to 50nm and less than or equal to 400nm;
along the first direction, the thickness H4 of the second buffer layer is equal to or more than 50nm and equal to or less than H4 and equal to or less than 400nm.
Optionally, the array substrate further includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer on the side of the polysilicon active layer away from the substrate;
the array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor;
the first metal layer comprises a grid electrode of the thin film transistor and a first polar plate of the capacitor;
the second metal layer comprises a second plate of the capacitor;
the third metal layer includes a source and a drain of the thin film transistor.
In a second aspect, an embodiment of the present invention provides a method for preparing an array substrate, where the method is used to prepare the array substrate in a first direction, and the method includes:
providing a substrate;
preparing a first buffer layer on one side of the substrate, wherein the first buffer layer comprises silicon nitride;
preparing a second buffer layer on one side of the first buffer layer far away from the substrate, wherein the second buffer layer comprises silicon oxide;
preparing a polysilicon active layer on one side of the second buffer layer, which is far away from the substrate, wherein a plurality of bulges are formed on the surface of the polysilicon on one side, which is far away from the substrate; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate.
Optionally, preparing a first buffer layer on one side of the substrate includes:
inputting NH according to a preset gas flow proportion 3 And SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein, the NH 3 And the SiH 4 The gas flow ratio of (5-20) to 1.
Optionally, preparing a second buffer layer on a side of the first buffer layer away from the substrate includes:
inputting N according to a preset gas flow proportion 2 O and SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein, the N is 2 O and the SiH 4 The gas flow ratio of (20-60) to (1).
Optionally, preparing a polysilicon active layer on a side of the second buffer layer away from the substrate includes:
preparing an amorphous silicon layer on one side of the second buffer far away from the substrate;
crystallizing the amorphous silicon by adopting an excimer laser process to obtain a polycrystalline silicon layer;
and carrying out laser annealing on the polycrystalline silicon layer to obtain a polycrystalline silicon active layer.
Optionally, the preparation method further comprises:
preparing a first insulating layer on one side of the polycrystalline silicon active layer far away from the substrate;
preparing a first metal layer on one side of the first insulating layer far away from the substrate;
preparing a second insulating layer on one side of the first metal layer far away from the substrate;
preparing a second metal layer on one side of the second insulating layer far away from the substrate;
preparing a third insulating layer on one side of the second metal layer far away from the substrate;
preparing a third metal layer on one side of the third insulating layer far away from the substrate;
the array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor;
preparing a first metal layer on one side of the first insulating layer far away from the substrate, wherein the first metal layer comprises:
preparing a grid electrode of the thin film transistor and a first polar plate of the capacitor on one side of the first insulating layer, which is far away from the substrate;
preparing a second metal layer on one side of the second insulating layer far away from the substrate, wherein the second metal layer comprises:
preparing a second polar plate of the capacitor on one side of the second insulating layer far away from the substrate;
preparing a third metal layer on one side of the third insulating layer far away from the substrate, wherein the third metal layer comprises:
and preparing a source electrode and a drain electrode of the thin film transistor on one side of the third insulating layer far away from the substrate.
In a third aspect, an embodiment of the present invention provides a display panel, including the array substrate of the first aspect, and further including an opposite substrate;
the counter substrate is disposed opposite to the array substrate.
In a fourth aspect, an embodiment of the present invention provides a display device, including the display panel described in the third aspect.
According to the array substrate provided by the embodiment of the invention, the buffer layers are arranged on the substrate and comprise the first buffer layer and the second buffer layer which are arranged in a laminated manner, the first buffer layer is further arranged and comprises silicon nitride, the second buffer layer comprises silicon oxide, and the surface type of the polycrystalline silicon active layer is adjusted by adjusting the film layer structure and the film material of the buffer layers, so that the height of the bulge in the upper surface of the polycrystalline silicon active layer is reduced, the quantity of charges captured by the bulge is reduced, the drift of threshold voltage is reduced, and the phenomenon of afterimage in a short time is improved; furthermore, the protruding height of the surface of the polycrystalline silicon active layer is smaller than half of the thickness of the polycrystalline silicon active layer, so that the drift of threshold voltage can be obviously reduced, the threshold consistency of the thin film transistor in the array substrate is ensured, and the good display effect of the display panel is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It is clear that the described figures are only figures of a part of the embodiments of the invention to be described, not all figures, and that for a person skilled in the art, without inventive effort, other figures can also be derived from them.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a polysilicon active layer according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a polysilicon active layer according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, an array substrate 100 according to an embodiment of the present invention may include:
a substrate 110;
a first buffer layer 120 on one side of the substrate 110, the first buffer layer 120 including silicon nitride;
a second buffer layer 130 on a side of the first buffer layer 120 away from the substrate 110, the second buffer layer 130 including silicon oxide;
the polysilicon active layer 140 is positioned on one side of the second buffer layer 130, which is far away from the substrate 110, and a plurality of protrusions A are formed on the surface of the polysilicon active layer 140, which is far away from the substrate 110; along the first direction X, the height of the protrusion a is H1, and the thickness of the polysilicon active layer 140 is H2, wherein H1 is not more than H2/2; the first direction X is perpendicular to the plane of the substrate 110.
The substrate 110 may be a rigid substrate or a flexible substrate, such as glass or polyimide, for example, and the specific type of the substrate 110 is not limited by the embodiments of the present invention. . In the embodiment of the present invention, the materials of the first buffer layer 120 and the second buffer layer 130 are different, the first buffer layer 120 includes silicon nitride, and the second buffer layer 130 includes silicon oxide. Meanwhile, when the polysilicon active layer 140 is prepared, the temperature may be drastically changed due to the change of the polysilicon crystal, and the protrusion a is generated at the grain boundary.
Specifically, the buffer layers include a first buffer layer 120 and a second buffer layer 130, the first buffer layer 120 is located on one side of the substrate 110, the second buffer layer 130 is located on one side of the first buffer layer 120 away from the substrate 110, the polysilicon active layer 140 is located on one side of the second buffer layer 130 away from the substrate 110, and the first buffer layer 120 and the second buffer layer 130 serve to bond the polysilicon active layer 140 to be grown next. Because the preparation of the polysilicon is obtained by carrying out crystallization treatment on the amorphous silicon, and a high-temperature process is required in the crystallization process, the first buffer layer 120 comprises silicon nitride, the second buffer layer 130 comprises silicon oxide, and the film structure of the buffer layers and the film materials of the buffer layers are reasonably arranged, so that the violent temperature change of the first buffer layer 120 and the second buffer layer 130 during the preparation of the polysilicon active layer 140 can be relieved, the height of the protrusion A generated on the surface of the polysilicon active layer 140 is reduced, and if the quantity of charges captured by the protrusion A can be reduced, the drift of the threshold voltage is reduced, and the short-time ghost phenomenon is improved.
Specifically, along the first direction X perpendicular to the plane of the substrate 110, the height of the protrusion a is H1, and the thickness of the polysilicon active layer 140 is H2, where H1 is less than or equal to H2/2. Experiments show that the height H1 of the protrusion A and the thickness H2 of the polysilicon active layer 140 satisfy that H1 is less than or equal to H2/2, so that the quantity of charges trapped by the protrusion A can be obviously reduced, and the drift of the threshold voltage can be obviously reduced.
Specifically, when the array substrate 100 is used for display operation, the charge transition occurs when the bright area is switched to the gray scale and the dark area is switched to the gray scale, and the charge transition is captured by the protrusion a at the grain boundary. Since the height of the protrusion a is reduced, the number of charge traps is reduced, and the drift of the threshold voltage is reduced, thereby improving the afterimage effect for a short time.
In summary, in the array substrate provided by the embodiment of the present invention, the buffer layers are disposed on the substrate and include the first buffer layer and the second buffer layer which are stacked, the first buffer layer is further disposed and includes silicon nitride, the second buffer layer includes silicon oxide, and the surface morphology of the polysilicon active layer is adjusted by adjusting the film structure and the film material of the buffer layer, so as to reduce the height of the protrusions in the upper surface of the polysilicon active layer, reduce the number of charges captured by the protrusions, reduce the drift of the threshold voltage, and thereby improve the image sticking phenomenon in a short time; furthermore, the protruding height of the surface of the polycrystalline silicon active layer is smaller than half of the thickness of the polycrystalline silicon active layer, so that the drift of threshold voltage can be obviously reduced, the threshold consistency of the thin film transistor in the array substrate is ensured, and the good display effect of the display panel is ensured.
With reference to fig. 1, in the array substrate 100 according to the embodiment of the invention, along the first direction X, the thickness H3 of the first buffer layer 120 is equal to or greater than 50nm and equal to or less than H3 and equal to or less than 400nm;
the thickness H4 of the second buffer layer 130 satisfies 50nm ≦ H4 ≦ 400nm along the first direction X.
Illustratively, through a great deal of research by the inventors, the thicknesses of the first buffer layer 120 and the second buffer layer 130 have an important role in alleviating the drastic temperature change during the preparation of the polysilicon active layer 140, and in the embodiment of the present invention, by setting the thickness H3 of the first buffer layer 120 along the first direction X to satisfy 50nm ≦ H3 ≦ 400nm, and setting the thickness H4 of the second buffer layer 130 to satisfy 50nm ≦ H3 ≦ 400nm, it is ensured that the height of the protrusion a on the surface of the polysilicon active layer 140 can be effectively reduced, and the threshold voltage drift and the short-time afterimage effect can be improved.
Specifically, the thickness H3 of the first buffer layer 120 satisfies 50nm ≦ H3 ≦ 400nm, and may be H3=50nm, H3=400nm, or any value between 50nm and 400nm of the thickness of H3 in the first direction X. Further, the thickness H4 of the second buffer layer 130 satisfies 50nm ≦ H4 ≦ 400nm, and may be H4=50nm, H4=400nm, or any value between 50nm and 400nm of the thickness of H4 in the first direction X. The specific thicknesses of the first buffer layer 120 and the second buffer layer 130 are not limited in the embodiments of the present invention.
With reference to fig. 1, the array substrate 100 according to the embodiment of the present invention further includes a first insulating layer N1, a first metal layer M1, a second insulating layer N2, a second metal layer M2, a third insulating layer N3, and a third metal layer M3 on a side of the polysilicon active layer 140 away from the substrate 110;
the array substrate 100 further includes a driving circuit 150, wherein the driving circuit 150 includes a thin film transistor 151 and a capacitor 152;
the first metal layer M1 includes a gate 1511 of the thin film transistor 151 and a first plate 1521 of the capacitor 152;
the second metal layer M2 includes a second plate 1522 of the capacitor 152;
the third metal layer M3 includes a source 1512 and a drain 1513 of the thin film transistor 151.
As shown in fig. 1, the array substrate 100 further includes a first insulating layer N1, a first metal layer M1, a second insulating layer N2, a second metal layer M2, a third insulating layer N3 and a third metal layer M3 sequentially disposed on a side of the polysilicon active layer 140 away from the substrate 110. The material of the first insulating layer N1, the second insulating layer N2, and the third insulating layer N3 may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide, and the first insulating layer N1 may have, for example, a single-layer structure of silicon nitride, a single-layer structure of silicon oxide, or a multilayer structure of silicon nitride layer, silicon oxide layer, aluminum oxide, or hafnium oxide. The materials of the first metal layer M1, the second metal layer M2, and the third metal layer M3 may be conductive metals or alloys.
Further, the array substrate 100 further includes a driving circuit 150, and the driving circuit 150 includes a thin film transistor 151 and a capacitor 152. The thin film transistor 151 includes a gate 1511, a source 1512, and a drain 1513. The capacitor 152 includes a first plate 1521 and a second plate 1522. Specifically, as shown in fig. 1, the first metal layer M1 includes a gate 1511 of the thin film transistor 151 and a first plate 1521 of the capacitor 152. The gate 1511 and the first electrode plate 1521 of the capacitor 152 are arranged on the same layer and are prepared from the same material in the same process, so that the arrangement mode of the driving circuit is simple, and the structure of the film layer of the array substrate is simple. Illustratively, the first metal layer M1 material may include at least one of Au, ag, cu, ni, pt, pd, al, mo, W, and Ti, or may be formed using a metal alloy such as Al — Nd alloy and Mo — W alloy, but is not limited thereto. While it may be formed using various materials in consideration of properties or characteristics such as adhesion to an adjacent layer, planarization, resistance, or formability, the material of the first metal layer M1 is not limited by the embodiment of the present invention. The second metal layer M2 includes a second plate 1522 of the capacitor 152, and the first plate 1521 and the second plate 1522 form the capacitor 152 to maintain the gate voltage of the driving transistor in the driving circuit stable. The third metal layer M3 includes a source 1512 and a drain 1513 of the tft 151, and the source 1512 and the drain 1513 are disposed on the same layer. Exemplary materials of the source electrode 1512 and the drain electrode 1513 may be conductive materials, for example, metals such as Cr, pt, ru, au, ag, mo, al, W, cu, and/or AlNd, or alloys including Ti — Al — Ti, which is not limited in this embodiment of the present invention.
Based on the same inventive concept, the embodiment of the invention also provides a preparation method of the array substrate, which is used for preparing the array substrate described in the embodiment. Fig. 3 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention, and as shown in fig. 3, the method for manufacturing an array substrate according to the embodiment of the present invention includes:
s110, providing a substrate;
the material of the substrate may be a rigid substrate or a flexible substrate, such as glass or polyimide, for example, and the specific type of the substrate is not limited by the embodiment of the present invention.
S120, preparing a first buffer layer on one side of the substrate, wherein the first buffer layer comprises silicon nitride.
Illustratively, a first buffer layer is prepared on the substrate, the first buffer layer comprising silicon nitride. The first buffer layer may be prepared by depositing a material of the first buffer layer on the substrate by physical vapor deposition, vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like.
S130, preparing a second buffer layer on one side, far away from the substrate, of the first buffer layer, wherein the second buffer layer comprises silicon oxide.
Illustratively, a second buffer layer is prepared on a side of the first buffer layer remote from the substrate, the second buffer layer comprising silicon oxide. The buffer layer may be prepared by depositing the first buffer layer material on the substrate by physical vapor deposition, vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like.
S140, preparing a polycrystalline silicon active layer on one side, far away from the substrate, of the second buffer layer, wherein a plurality of bulges are formed on the surface of the polycrystalline silicon on one side, far away from the substrate; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate.
Illustratively, the polysilicon active layer is prepared on a side of the second buffer layer remote from the substrate. Polycrystalline silicon can be obtained by converting amorphous silicon into polycrystalline silicon by a laser melting technique. When the polycrystalline silicon active layer is prepared, a plurality of bulges are formed on the surface of the polycrystalline silicon active layer on the side far away from the substrate. And controlling the thickness H1 of the protrusion and the thickness H2 of the polysilicon active layer along the first direction X to satisfy that H1 is less than or equal to H2/2.
In summary, the first buffer layer and the second buffer layer which are stacked are prepared on the substrate, the first buffer layer is further arranged to comprise silicon nitride, the second buffer layer comprises silicon oxide, and the surface type of the polycrystalline silicon active layer is adjusted by adjusting the film layer structure and the film material of the buffer layer, so that the height of the protrusion in the upper surface of the polycrystalline silicon active layer is reduced, the quantity of charges captured by the protrusion is reduced, the drift of threshold voltage is reduced, and the short-time afterimage phenomenon is improved; furthermore, the protruding height of the surface of the polysilicon active layer is smaller than half of the thickness of the polysilicon active layer, so that the drift of threshold voltage can be obviously reduced, the threshold consistency of the thin film transistor in the array substrate is ensured, and the good display effect of the display panel is ensured.
Optionally, preparing a first buffer layer on one side of the substrate includes:
inputting NH according to a preset gas flow proportion 3 And SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein NH 3 And SiH 4 The gas flow ratio of (5-20) to (1).
Illustratively, the first buffer layer is supplied with NH according to a predetermined gas flow rate ratio during the preparation process 3 And SiH 4 Wherein NH 3 And SiH 4 The gas flow rate ratio of (5-20) to 1, for example, NH 3 And SiH 4 The gas flow ratio of (2) is 5 3 And SiH 4 The gas flow ratio of (1) is 20 3 And SiH 4 The gas flow ratio of (a) is Y:1 (Y is any of 5 to 20). Exemplary, when NH 3 And SiH 4 When the gas flow ratio of (2) is 5 3 Gas of (2) is introduced into the gas passage of 10000m -3 At/min, siH 4 Gas introduction of 2000m -3 /min。
Further, by reasonably setting NH 3 And SiH 4 The thickness of the first buffer layer may be adjusted, for example, the thickness of the first buffer layer may be 50nm to 400nm.
Optionally, preparing a second buffer layer on a side of the first buffer layer away from the substrate includes:
inputting N according to a preset gas flow proportion 2 O and SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein N is 2 O and SiH 4 The gas flow ratio of (20-60): 1.
Illustratively, the second buffer layer is fed with N according to a predetermined gas flow ratio during the preparation process 2 O and SiH 4 Wherein N is 2 O and SiH 4 The gas flow ratio of (20-60) to 1, for example, N 2 O and SiH 4 The gas flow ratio of (2) is 20 2 O and SiH 4 The gas flow ratio of (1) or (N) is 60 2 O and SiH 4 The gas flow ratio of (a) is Z:1 (Z is any of values from 20 to 60). Exemplary, when N 2 O and SiH 4 NH is 20 3 Gas of (2) is introduced into the gas passage of 10000m -3 At/min, siH 4 Gas (2) is introduced into the furnace at a distance of 500m -3 /min。
Further, by reasonably setting N 2 O and SiH 4 The thickness of the second buffer layer may be adjusted, for example, the thickness of the second buffer layer may be 50nm to 400nm.
Optionally, preparing a polysilicon active layer on a side of the second buffer layer away from the substrate includes:
preparing an amorphous silicon layer on one side of the second buffer far away from the substrate;
crystallizing the amorphous silicon by adopting an excimer laser process to obtain a polycrystalline silicon layer;
and carrying out laser annealing on the polycrystalline silicon layer to obtain a polycrystalline silicon active layer.
For example, the polysilicon active layer is prepared on the side of the second buffer layer away from the substrate, and an amorphous silicon layer is first prepared on the side of the second buffer layer away from the substrate, and then the amorphous silicon layer may be crystallized by an excimer laser process to obtain the polysilicon layer. And finally, carrying out laser annealing treatment on the polycrystalline silicon layer to prepare a polycrystalline silicon oxide layer, so as to ensure the stable performance of the polycrystalline active layer.
Optionally, the preparation method of the array substrate further includes:
preparing a first insulating layer on one side of the polycrystalline silicon active layer far away from the substrate;
preparing a first metal layer on one side of the first insulating layer far away from the substrate;
preparing a second insulating layer on one side of the first metal layer far away from the substrate;
preparing a second metal layer on one side of the second insulating layer, which is far away from the substrate;
preparing a third insulating layer on one side of the second metal layer far away from the substrate;
preparing a third metal layer on one side of the third insulating layer far away from the substrate;
the array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor;
further, preparing a first metal layer on the side of the first insulating layer away from the substrate includes:
preparing a grid electrode of the thin film transistor and a first polar plate of the capacitor on one side of the first insulating layer, which is far away from the substrate;
preparing a second metal layer on one side of the second insulating layer far away from the substrate, wherein the second metal layer comprises:
preparing a second plate of the capacitor on one side of the second insulating layer far away from the substrate;
preparing a third metal layer on the side of the third insulating layer far away from the substrate, wherein the third metal layer comprises:
and preparing a source electrode and a drain electrode of the thin film transistor on the side of the third insulating layer far away from the substrate.
Illustratively, the insulating layer and the metal layer are prepared layer by layer on the side of the polysilicon active layer away from the substrate. The insulating layer may have a single-layer structure of silicon nitride, a single-layer structure of silicon oxide, or a multilayer structure of a silicon nitride layer, a silicon oxide layer, aluminum oxide, hafnium oxide, or the like. The metal layer can be made of a material with good conductivity.
The array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor. And thin film transistor and capacitor structures can be formed between different metal layers. For example, the first metal layer comprises a grid electrode of a thin film transistor and a first plate of a capacitor; the second metal layer comprises a second plate of the capacitor; the third metal layer includes a source and a drain of the thin film transistor.
Based on the same inventive concept, the embodiment of the invention further provides a display panel, and the display panel comprises the array substrate described in the embodiment. Specifically, fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 4, the display panel includes an array substrate 100 and an opposite substrate 200;
the counter substrate 200 is disposed opposite to the array substrate 100.
The display panel 10 includes an array substrate 100 and an opposite substrate 200. The counter substrate 200 is disposed opposite to the array substrate 100. Therefore, the array substrate 100 included in the display panel 10 provided in the embodiment of the invention also has the beneficial effects described in the array substrate 100, and details are not repeated herein.
The display panel 10 further includes a light emitting element located on a side of the third metal layer M3 away from the substrate 110, and the light emitting element may specifically include an anode 160 located on a side of the third metal layer M3 away from the substrate 110, a light emitting layer 170 located on a side of the anode 160 away from the substrate 110, and a cathode 180 located on a side of the light emitting layer 170 away from the substrate 110.
The opposite substrate 200 further includes at least one spacer 210 on a side of the opposite substrate 200 adjacent to the array substrate 100 for supporting the opposite substrate 200.
Based on the same inventive concept, the embodiment of the invention also provides a display device, and the display device comprises the display panel described in the embodiment. Specifically, fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 5, a display device 1 includes a display panel 10.
Therefore, the display device 1 provided in the embodiment of the present invention has the technical effects of the technical solutions in any of the embodiments, and the structures and terms identical to or corresponding to those in the embodiments are not repeated herein. The display device 1 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 5, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display device comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited to this. .
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that the features of the various embodiments of the invention may be partially or fully coupled to each other or combined and may be capable of cooperating with each other in various ways and of being technically driven. Numerous variations, rearrangements, combinations, and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
a first buffer layer on one side of the substrate, the first buffer layer comprising silicon nitride;
a second buffer layer located on one side of the first buffer layer far away from the substrate, wherein the second buffer layer comprises silicon oxide;
the polycrystalline silicon active layer is positioned on one side, far away from the substrate, of the second buffer layer, and a plurality of bulges are formed on the surface of the polycrystalline silicon active layer, far away from the substrate; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate.
2. The array substrate of claim 1, wherein a thickness H3 of the first buffer layer along the first direction satisfies 50nm ≦ H3 ≦ 400nm;
along the first direction, the thickness H4 of the second buffer layer is equal to or more than 50nm and equal to or less than H4 and equal to or less than 400nm.
3. The array substrate of claim 1, further comprising a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer on the side of the polysilicon active layer away from the substrate;
the array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor;
the first metal layer comprises a grid electrode of the thin film transistor and a first polar plate of the capacitor;
the second metal layer comprises a second plate of the capacitor;
the third metal layer includes a source and a drain of the thin film transistor.
4. A method for preparing an array substrate according to any one of claims 1 to 3, the method comprising:
providing a substrate;
preparing a first buffer layer on one side of the substrate, wherein the first buffer layer comprises silicon nitride;
preparing a second buffer layer on one side of the first buffer layer far away from the substrate, wherein the second buffer layer comprises silicon oxide;
preparing a polysilicon active layer on one side of the second buffer layer, which is far away from the substrate, wherein a plurality of bulges are formed on the surface of the polysilicon on one side, which is far away from the substrate; along the first direction, the height of the protrusion is H1, the thickness of the polycrystalline silicon active layer is H2, wherein H1 is less than or equal to H2/2; the first direction is perpendicular to the plane of the substrate.
5. The method of claim 4, wherein preparing a first buffer layer on the substrate side comprises:
inputting NH according to a preset gas flow proportion 3 And SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein, the NH 3 And the SiH 4 The gas flow ratio of (5-20) to (1).
6. The method according to claim 4, wherein preparing a second buffer layer on a side of the first buffer layer away from the substrate comprises:
inputting N according to a preset gas flow proportion 2 O and SiH 4 So as to deposit silicon nitride on one side of the substrate; wherein, the N is 2 O and the SiH 4 The gas flow ratio of (20-60) to (1).
7. The method according to claim 4, wherein preparing the polysilicon active layer on the side of the second buffer layer away from the substrate comprises:
preparing an amorphous silicon layer on one side of the second buffer far away from the substrate;
crystallizing the amorphous silicon by adopting an excimer laser process to obtain a polycrystalline silicon layer;
and carrying out laser annealing on the polycrystalline silicon layer to obtain a polycrystalline silicon active layer.
8. The method of manufacturing according to claim 4, further comprising:
preparing a first insulating layer on one side of the polycrystalline silicon active layer far away from the substrate;
preparing a first metal layer on one side of the first insulating layer far away from the substrate;
preparing a second insulating layer on one side of the first metal layer far away from the substrate;
preparing a second metal layer on one side of the second insulating layer far away from the substrate;
preparing a third insulating layer on one side of the second metal layer far away from the substrate;
preparing a third metal layer on one side of the third insulating layer far away from the substrate;
the array substrate further comprises a driving circuit, and the driving circuit comprises a thin film transistor and a capacitor;
preparing a first metal layer on the side of the first insulating layer far away from the substrate, wherein the first metal layer comprises:
preparing a grid electrode of the thin film transistor and a first plate electrode of the capacitor on one side, far away from the substrate, of the first insulating layer;
preparing a second metal layer on one side of the second insulating layer far away from the substrate, wherein the second metal layer comprises:
preparing a second polar plate of the capacitor on one side of the second insulating layer far away from the substrate;
preparing a third metal layer on one side of the third insulating layer far away from the substrate, wherein the third metal layer comprises:
and preparing a source electrode and a drain electrode of the thin film transistor on one side of the third insulating layer far away from the substrate.
9. A display panel comprising the array substrate according to any one of claims 1 to 3, and further comprising an opposite substrate;
the opposite substrate is arranged opposite to the array substrate.
10. A display device characterized by comprising the display panel according to claim 9.
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| CN202110954414.8A CN115714128A (en) | 2021-08-19 | 2021-08-19 | Array substrate, preparation method thereof, display panel and display device |
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| CN202110954414.8A CN115714128A (en) | 2021-08-19 | 2021-08-19 | Array substrate, preparation method thereof, display panel and display device |
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