JP7282688B2 - Flexible part with layered structure with metal layers - Google Patents

Description

The present invention relates to the use of an additive for maintaining the electrical conductivity in the layer plane of the Mo-based layer having the features of the preamble of claim 1, the flexible coated component having the features of the preamble of claim 2, and It relates to a method for manufacturing a flexible sheath component having the features of the preamble of claim 20.

Technological advances in the field of flexible components are closely related to advances in the field of thin film materials. In particular, this progress is due to electronics, in particular electronics (display screens), such as liquid crystal displays (liquid crystal display screens: TFT-LCD), AM-OLED (active matrix organic light emitting diode) or micro LED (light emitting diode) displays. It allows further development in the field of thin film components, for example thin film transistors (TFTs), as part of the structure (active matrix) for the active control of screens. Active matrix structures can also be used in other applications, such as sensor arrays for X-ray radiation. In these applications, the conductor paths are arranged in a matrix in rows (“gate lines”, “rows”) and columns (“signal lines”, “row lines”, “data lines”). An electrical conductor path provides a conductive path for the transmission of electrical signals, currents or voltages from one point to another.

Each active matrix row or column consists of long, thin conductor tracks (e.g., lengths from a few centimeters to just under two meters, widths from a few micrometers to tens of micrometers, and tens of nanometers to hundreds of nanometers). ), which form the gate electrode (“control electrode”) or the source/drain electrode (“inflow electrode” and “outflow electrode”) of the TFT in the thin film transistor area, respectively. It has one or more extensions. These conductor tracks are the gate electrodes or source/drain electrodes of the TFTs and contact areas ("contact pads") for external contact or gate driver structures and data driver structures (row drivers and column drivers) for display screen control. ) are located on the peripheral area of the substrate.

With active matrix control, the brightness of each individual picture element (pixel) can be individually adjusted across a single TFT (eg TFT-LCD) or multiple TFTs (eg AM-OLED display screen). In this case, it is important that the voltage drop along long gate conductor tracks and signal conductor tracks is as low as possible. This is because unnecessary length-dependent luminance differences will occur in pixels (the human eye is very sensitive to luminance differences).

In the case of active matrix structures arranged on flexible, flexible or pivotable substrates, in particular long row and column conductor tracks are subject to high deformation and/or bending and/or torsion stresses. I am receiving . This stress is very large because the spatial extent of the gate and source /drain electrodes in the TFT structure is much smaller (generally rectangular areas with side lengths of a few micrometers up to tens of micrometers). becomes smaller. Especially when the conductor track material is brittle, this stress quickly leads to an increase in the electrical resistance by many orders of magnitude. As a result , the TFTs arranged along the conductor path are not uniformly supplied with a defined voltage , and in the case of display screen applications , length-dependent luminance differences may occur. In extreme cases, the conductor track may completely lose its electrical conductivity, resulting in total fall of the pixel.

Especially in the case of display screens for mobile applications, e.g. mobile phones, tablet PCs, PDAs (Personal Digital Assistants), on the display screen substrate, besides the actual unit for the display of the image content, there are further peripherals. An electrical circuit is implemented. It is, for example, a circuit for controlling gate electrodes (gate driver), a control circuit for source/drain electrodes (data driver), a DC-DC converter, a digital-analog converter, a timing controller, or a buffer circuit and an interface circuit. The combination of such a display screen and its control unit can be System on Panel (SOP) (system mounted on display screen panel) or System on Glass (SOG) if the substrate is made of glass (mounted on glass). system). It is advantageous to place the peripheral electrical circuitry for display screen control directly on the substrate instead of implementing it as an external integrated circuit (IC) that includes a separate housing. The basic advantages are low manufacturing costs, low current consumption, small space requirements and high reliability. System-on-panel display screens are often realized with low temperature poly-Silicon (LTPS) technology, but other semiconductors such as amorphous silicon or metal oxides are also possible. Some of the peripheral circuits arranged on the substrate are connected to the TFTs of individual pixels via electrical conductor paths, gate lines and signal lines, the length of which varies from a few millimeters to several millimeters depending on the size of the display screen. Up to 200 cm. Changes in the resistance of conductor tracks under deformation, bending or torsional stresses may be used to prevent the extinguishing of individual pixels or entire rows or columns of the display screen, or to unwanted differences in luminance or color ("mura") of the display screen. should be as small as possible to prevent

Flexible contact sensors (eg, resistive or capacitive sensors) also use matrix-arranged x- and y-electrodes, but generally do not have an active TFT structure. For larger sensors, from a few centimeters to several meters, very long and narrow conductor track structures are used, for example with lengths of 10 cm to 100 cm and widths of 5 μm to 50 μm. For this application, too, the resistance change (increase) of the conductor tracks subjected to deformation, bending or torsion stress should be as small as possible. Otherwise, sensor failure (eg, due to reduced signal-to-noise ratio) may occur.

In U.S. Pat. No. 6,300,000 (FIG. 7), non-linear, e.g., sinusoidal, wavy, rectangular, serpentine or saw-tooth conductor tracks are used to reduce mechanical stress in conductor tracks under bending stress. structure is proposed. To prevent crack propagation, a bifurcated and recombined conductor track structure (FIG. 8c in the above document) has been proposed. However, all these structures require more space than a simple straight conductor track, and the current must travel an overall longer path between two points, resulting in additional voltage drop or signal-to-noise ratio. may decline.

Furthermore, advances in the development of new integration techniques have made it possible to combine electronic devices with flexible substrates and, as a result, manufacture more flexible electronic components. A prior art of this kind in question is formed by US Pat. For more information on the prior art, please refer to this document.

WO2016/032175 Austrian Utility Model No. 15048

It is an object of the present invention to maintain the electrical conductivity of metal layers applied on flexible substrates that are subjected to single or repeated bending, tensile and/or torsional stresses. In particular, the object of the invention is an electrical conductor track (metal layer) on a flexible substrate. The electrical resistance of the conductor track along the conductor track, ie in the layer plane, changes only slightly, in particular less than 10%, when subjected to deformation, bending or torsion stress.

The object is solved by the use of an additive according to claim 1, a flexible coated part according to claim 2 and a method for producing a flexible coated part with the features of claim 20. Preferred embodiments of the invention are defined in the dependent claims.

According to the invention, the electrical stability in the layer plane of the Mo-based (molybdenum-based) or metal layers when subjected to single or repeated bending stresses and/or tensile stresses and/or torsional stresses of the flexible part. Ensures conductivity maintenance. This is achieved by increasing the ductility of the flexible part.

As defined in claim 2, multiple metal layers may be provided on the flexible substrate. In this case, it is said that each metal layer is directly adjoined on both sides by a semiconductor layer or an electrically insulating layer, and the metal layer itself is formed as a single-layer structure, a two-layer structure or a three-layer structure according to claim 2. restrictions are added.

The Mo-based layer or MoX layer contains at least 50% by weight Mo, in particular at least 60% by weight Mo.

The MoX layer can consist of multiple MoX sublayers with another X-containing MoX sublayer.

Besides maintaining electrical conductivity, increased ductility increases mechanical damage tolerance. For example, it reduces the risk of delamination of multilayer composites.

Of course, the Mo-based layer (MoX layer) does not have to be pure Mo, except for the additive X, but rather impurities, especially the PVD (Physical Vapor Deposition) method, especially the sputtering method (cathode sputtering). Impurities (eg, Ar, O, N, C) may be present from the process atmosphere of . However, metal impurities should be less than 0.5 atomic percent.

Among the above elements Cu, Ag, and Au, Cu is particularly preferred. A lower atomic % is sufficient here to achieve the desired effect. Furthermore, Cu is more cost effective than Ag and Au.

According to the invention, the layered structure comprises a metal layer with a semiconducting or electrically insulating layer directly adjacent on one side and a semiconducting or electrically insulating layer directly adjacent to the metal layer on the other side. layer. These properties are met at least in some areas of the flexible covering component (but not necessarily in all areas of the flexible component, especially the flexible electronic component). Further possible adjacent layers are described in detail below. In this case, "electrically insulating" should be understood to mean an electrical resistance greater than 1 megohm.

As used herein, flexibility and "flexible" should be understood as the property of absorbing and/or withstanding bending stresses without adversely affecting the properties associated with the use of the part. That is, fully flexible parts also have significantly improved ductility.

Significantly increased ductility in the sense of the invention means that the component and/or of course also the included layer or layers have a high resistance to crack initiation and crack growth up to the elongation at which cracking occurs. It should be understood to mean no formation, or formation only at greater elongation, or a change in crack progression.

Critical elongation is used within the scope of the present invention to describe ductility and resulting flexibility. The critical elongation is defined as the elongation ε _k at which the electrical resistance R of a layer or layers on a flexible substrate increases by 10% relative to the initial state (R/R ₀ =1.1) . be done. In flexible parts of sufficiently high height , the critical elongation ε _k increases significantly and the conductivity of one or more layers remains significantly longer.

A flexible substrate, within the scope of the present invention, is to be understood as a substrate on which the layer or layers (coatings) deposited thereon undergo an elongation ε when subjected to a bending stress. If one or more layers are much thinner than the substrate, the elongation is approximately described by ε=ds/2R, where ds is the thickness of the substrate and R is the bend radius. If the layer or layers are very thin compared to the substrate, the elongation in the layer or layers can be set approximately equal to only tensile or compressive stress. For example, flexible substrates can be composed of one or more polymeric materials such as polyimides, polycarbonates, polyethylene terephthalates, polyethylene naphthalates, polyethersulfones, polyarylates, or polycyclic olefins. Most flexible substrates based on one or more polymeric materials have elastic moduli of 8 GPa or less. Thin glass (glass having a thickness of 1 mm or less), metal sheets having a thickness of 1 mm or less, such as steel sheets, aluminum foils, copper sheets or titanium foils having a thickness of 1 mm or less, or mineral materials such as mica. are also flexible substrates suitable for flexible components according to the present invention.

Flexible substrates suitable for the present invention can likewise be composed of one or more layers and/or one or more materials. Such substrates can already be completely or only partially pre-coated with one or more layers of other materials.

This part is preferably a flexible cover part. Flexible coated electronic components have at least one current-conducting layer, compared to flexible coated components such as, for example, packaging films with metallic moisture barriers or optical layers. This includes, for example, flexible circuits, flexible display screens, flexible sensor elements, flexible thin-film capacitors, flexible thin-film batteries or simple conductive thin-films, such as flexible printed circuit boards. Examples of such flexible electronic components that can be constructed in accordance with the present invention were described earlier in this specification.

The metal layer of the flexible jacket according to the invention preferably has a thickness of 1 μm or less. The metal layer preferably has a minimum thickness of 5 nm, more preferably at least 10 nm. Also, a thickness of 5 nm to 300 nm, even more preferably a thickness of 5 nm to 100 nm. The layer thicknesses mentioned are particularly advantageous when the metal layer is used as an adhesion structure layer or as a diffusion barrier layer. Alternatively, a thickness range of 150 nm to 400 nm is advantageous. A layer thickness of 150 nm to 400 nm is particularly well suited for using the coated flexible parts according to the invention in display screens, for example as gate electrode layers.

The metal layer or layers defined in claim 2 or one of its dependent claims can be part of a thin film transistor (TFT).

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is elemental Cu, said MoCu layer containing ≦0.5 atomic % to ≦50 atomic % Cu, preferably 1 atomic % to 20 atomic % or less of Cu. In this case, it is particularly preferred for the entire MoX layer of the metal layer to consist of MoCu.

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is the element Ag, the MoAg layer containing >10 to <50 atomic % Ag, preferably >20 atomic % It can contain Ag up to ˜50 atomic %. In this case, it is particularly preferred that the entire MoX layer of the metal layer consists of MoAg.

In an exemplary embodiment of the component according to the invention, in at least one MoX layer, X is the element Au, and this MoAu metal layer may contain ≧5 atomic % and ≦20 atomic % Au. In this case, it is particularly preferred that the entire MoX layer of the metal layer consists of MoAu.

In exemplary embodiments of the component according to the invention, each MoX layer can have a layer resistance ρ of 200 micro-Ohm cm or less, preferably 100 micro-Ohm cm or less, particularly preferably 50 micro-Ohm cm or less.

In exemplary embodiments of the component according to the invention, at least one of the semiconductor layer or the electrically insulating layer directly adjacent to the metal layer can be formed as a plurality of layers. Also, both the immediately adjacent layers or the electrically insulating layers can be formed as multiple layers.

In an exemplary embodiment of the component according to the invention, the metal layers in total can have a layer resistance ρ of 50 micro-Ohm cm or less, preferably of 10 micro-Ohm cm or less, particularly preferably of 3.5 micro-Ohm cm or less. .

In the method according to the present invention, at least one MoX layer is deposited containing ≧0.5 atomic % and ≦50 atomic % of X, where X is one element selected from the group of Cu, Ag, Au. . In this case, the MoX layer can form or be part of the metal layer as defined in claim 2 .

Deposition of the at least one MoX layer and/or metal layer can be done by various types of vapor deposition methods. For example, the deposition can be by physical vapor deposition or chemical vapor deposition.

However, it is advantageous if the deposition of at least one MoX layer and/or metal layer is performed by a PVD method, in particular a sputtering method. PVD (Physical Vapor Deposition) is known as thin film coating technology. This technique converts particles of the coating material into the gas phase before depositing them on the substrate. Deposition by the PVD method allows a particularly uniform deposition. Its properties allow it to deposit a coating that is equally isotropic over the entire coated surface. A further advantage of this method is the low substrate temperature that can be achieved as a result. Thus, for example, polymer coatings are possible. Moreover, the PVD layer is distinguished by very good adhesion to the substrate.

It is particularly preferred if the MoX layer or metal layer is deposited by a sputtering method (also called cathode sputtering method). Sputtering methods are relatively easy to use for uniform coating of large areas, making them cost effective for mass production.

It is highly preferred that the method according to the invention further comprises the step of providing a Mo-based target containing between 0.5 atomic % and up to 50 atomic % of X.

A Mo-based target containing between 0.5 atomic % and up to 50 atomic % of X is provided prior to the deposition of the at least one MoX layer and/or the at least one metal layer. Thus, MoX layers and/or metal layers are deposited from the targets provided.

In this case, the target should be understood as the coating source of the coating device. In one preferred method, the target used is a sputtering target for sputtering processes.

The chemical composition of the coating is determined by the chemical composition of the target used . However , slight differences in the sputtering behavior (sputtering yield) of the elements contained in the target can cause the composition of the coating to deviate from the target composition .

For example, preferential sputtering of Cu from a MoCu target may slightly increase the Cu content in the deposited coating. For example, to form a coating containing 10 atomic % or more Cu, the corresponding target can contain 10 atomic % or less Cu.

Instead of using a single target, the metal layers can also be deposited by co-deposition, preferably co-sputtering , from separate targets. In this case, the chemical composition of the coating can be further controlled by selection of different targets.

The manufacture of sputtering targets, which are more suitable for depositing metal layers, can be carried out, for example, by powder metallurgy.

Possible powder metallurgical methods for the production of sputtering targets are based on hot pressing methods such as hot pressing (HP) or spark plasma sintering (SPS). In both cases, the powder mixture is filled into a press die, heated in the die and sintered/ compacted at high compaction pressure and temperature into a dense part. In this case, a homogeneous microstructure with uniform grains without preferential orientation (texture) results.

A similar powder metallurgical method for sputtering target manufacture is hot isostatic pressing (HIP). In this case, the material to be compressed is packed into a deformable high-density container (usually a metal can). In this case, this material can be a powder, a powder mixture or a compact (in the form of compacted powder). The material present in this container is sintered at high temperature and pressure in a pressurized container under protective gas (eg argon). This method is called isostatic pressurization because the gas pressure acts from all directions. Typical process parameters are, for example, 1100° C. and 100 MPa with a hold time of 3 hours. In this case, a homogeneous microstructure with uniform grains without preferential orientation (texture) results.

A further option for manufacturing sputtering targets by powder metallurgical methods is sintering followed by shaping. In this case, the powder compact is sintered at high temperature in a hydrogen atmosphere or under vacuum. After sintering, a forming step such as rolling or forging, for example, results in high relative densities of over 99%. In this case, a microstructure with elongated grains with preferential orientation (texture) results. In the case of an optional subsequent low tension anneal or recrystallization anneal, a homogeneous microstructure with uniform grains is obtained , but still with preferred orientation (texture).

A further option for sputtering target manufacture by powder metallurgical methods is to apply the powder or powder mixture onto a corresponding support structure, such as a metal or tube , by thermal spraying methods, such as cold gas spraying or vacuum plasma spraying (VPS). is.

The invention is explained in more detail below on the basis of exemplary embodiments and drawings.

Schematic configuration of a uniaxial tensile test for electrical resistance measurement used for critical elongation at break ε _k measurement is shown. Figure 2 shows the R/ _R0 curves of Mo and MoCu alloys as a function of Cu content in the layer. Figure 2 shows electron micrographs of crack patterns of Mo and various MoCu layers after a maximum elongation of 15%. Figure 2 shows R/R ₀ curves for Mo and MoAg alloys as a function of Ag content in the layer. Figure 2 shows electron micrographs of crack patterns of Mo and various MoAg layers after a maximum elongation of 15%. 1 shows a cross section of a layered structure of a bottom gate thin film transistor. Fig. 2 shows a schematic block diagram (from above) of a system on-panel display screen; Figure 2 shows a detail of the system-on-panel display screen with a top view of the conductor track structure between the driver circuit and the TFT display screen area; Figure 2 shows a detail of the TFT display screen structure (from top, plan view) showing how the gate and source/drain electrodes of the TFTs and the gate and data lines are connected. 1 shows a cross-section of a layered structure of a top-gate LTPS-TFT. Figure 2 shows the X-ray diffraction pattern of a sputtered 500 nm thick MoCu thin film on a silicon wafer. FIG. 2 shows an X-ray diffraction diagram of a sputtered 500 nm thick MoAg thin film on a silicon wafer.

Example 1
Within a series of experiments, various Mo-based metal layers were deposited on polyimide substrates. In this case, layers with different chemical compositions were formed.

The compositions of the Mo-based metal layers are summarized in Table 1.

Table 1 Chemical Composition of Sputtered MoCu Layers

As a reference material for molybdenum-based alloys, pure Mo was used in the form of a molybdenum layer with a thickness of 50 nm.

All layers were deposited at room temperature on 50 μm thick thin films of polyimide (PI, eg Kapton®). In this case the process parameters were kept constant in order to eliminate as much as possible the influence of different process conditions on the results. The layer thickness was kept constant at 50 nm to avoid shape effects on the results.

The substrate surface was completely covered , and no fine structure was formed by etching or the like .

Uniaxial tensile tests were performed on layer samples on polyimide substrates using an MTS Tyron 250® general purpose testing machine. The test setup is shown schematically in FIG. In this case, the substrate was elastically deformed up to a maximum elongation ε of 15%. During the tensile test, the electrical resistance R of the layer was continuously recorded using the 4-point method. The electrical resistance at the start of measurement is called _R0 . In this case, the sample length (free length between clamps) in the initial state was 20 mm and the width was 5 mm.

The measurement setup is shown schematically in FIG. In this case, Lconst denotes the fixed clamping length without elongation. Here, the elongation at which the electrical resistance R of the layer on the flexible substrate increases by 10% relative to the initial state, ie, R/R ₀ =1.1, was defined as the critical elongation ε _k .

Table 2 shows the critical elongation ε _k determined by this tensile test.

Table 2 Critical elongation ε _k of the investigated Mo and MoCu layers and their difference from the reference sample consisting of pure Mo. Furthermore, the layer resistance of a 500 nm thick layer on non-conductive borosilicate glass (Corning Eagle XG®) is shown.

FIG. 2 shows the increase in electrical resistance versus initial resistance (R/R ₀ ) with elongation ε. The curve "Theoretical" shows the increase in electrical resistance caused only by the shape change of the sample. As is evident in the curves measured on the reference material, the electrical resistance increases very sharply with increasing elongation.

After the tensile tests described above, the tested layers were examined with an optical microscope and a scanning electron microscope. In this case, the shape of cracks in the layer and the average distance between cracks were determined.

For example, in layers based on brittle materials such as pure Mo , cracking patterns characteristic of the behavior of brittle materials usually occur when the specimen is damaged under tensile stress. It is characterized by a network of straight parallel cracks formed approximately perpendicular to the stress direction. Such a crack pattern is seen, for example, in FIG. 3 (Mo, left). These linear cracks mostly run the full width of the sample from one side to the other, as well as through the full thickness of the layer. Such cracks are also called through cracks (TTC). TTC significantly reduces the electrical conductivity of the layer. This is because in the worst case there is no longer a continuous conductive connection in the layers.

The critical elongation at failure criterion R/R0=1.1 inferred from Table 2 indicates that the ductility of the layer increases with increasing Cu content in the layer. It is speculated that this increase in ductility was caused by enhanced dislocation movement within the material. This increases the critical elongation and reduces the occurrence of TTC.

As an example, FIG. 2 shows the resistance curve R/R ₀ for a sample MoCu 7 atomic %. The crack appearance pattern still corresponds to TTC, but the critical elongation ε _k has already increased significantly.

A further effect that can be observed in addition to the increase in the critical elongation ε _k is that the crack appearance pattern changes from brittle to ductile material behavior. A characteristic of ductile material behavior is that cracks are no longer straight, but rather zig-zag. Crack bending at the crack tip is a possible explanation for such crack behavior.

In FIG. 3 (middle diagram, 18 at. % MoCu) it can be seen that the cracks do indeed run approximately parallel in the case of 18 at. % MoCu, but no longer run straight. In FIG. 3 (right panel, MoCu 52 atomic %), a ductile crack pattern has already occurred. The ductile crack runs mostly through the entire layer thickness, but not necessarily over the entire sample width, so that a conductive connection still exists in the material. In this case, as can be seen from FIG. 2, the slope of the R/R ₀ curve is small (the curve does not rise sharply).

Therefore, the critical elongation ε _k is greatly increased and crack initiation is reduced from the small Cu content in the Mo-based layer. As the Cu content is further increased, the cracking behavior changes from brittle to ductile. Therefore, Cu as an additive to Mo is particularly good in that it significantly increases the ductility of Mo-based layers even at low additions and in that Cu is a relatively cost-effective material.

FIG. 11 shows the X-ray diffractograms of two MoCu layers with Cu contents of 18 atomic % and 34 atomic %, respectively. Diffractograms of pure Mo or Cu layers, respectively, are also included as reference material. All layers were deposited by DC sputtering on silicon wafers at room temperature (without heating the substrate) and have a thickness of 500 nm. The crystal structure was recorded using a Bruker-AXS D8 diffractometer equipped with a Cu—K α X- ray source in the low-angle incidence mode at an angle of incidence of 2°. For reference , the positions of the X-ray reflections of body-centered cubic ( bcc ) molybdenum (space group Im-3m) are shown as vertical dashed lines and face-centered cubic ( fcc ) copper (space group Fm-3m), respectively. is shown as a vertical dashed line. Data were obtained from the ICDD (International Diffraction Data Center) database. As can be seen from FIG. 11, the two high copper content MoCu 18 atomic % and MoCu 34 atomic % systems have no corresponding reflections in the diffractograms and do not have separate Cu phases. Therefore, it can be assumed that Cu is forced to dissolve in molybdenum in the form of a solid solution , ie copper atoms occupy the molybdenum space lattice. The copper atoms thus strain the Mo lattice . The distorted Mo lattice is also shown by two reflections of Mo(110) and Mo(200), which indicate that the Cu atoms (atomic radius 128 pm) are smaller than the Mo atoms (140 pm) . , there is a shift to higher diffraction angles (2θ) compared to the undistorted reference .

Furthermore, the last column of Table 2 gives the layer resistance ρ (micro-ohm cm) of various Mo or MoCu thin films (500 nm layer thickness on an insulating glass substrate). For the measurements, the surface specific resistivity Rs (ohms/sheet) was measured by the four-point method and multiplied by the layer thickness. After increasing up to a Cu content of 34 atomic %, the layer resistance of the MoCu layers decreases again with increasing Cu content. All MoCu layers have layer resistances below 150 micro-ohm cm.

In the case of multilayers of MoCu/Cu or MoCu/Al, the layer resistance along long conductor tracks is determined by the materials Cu or Al, respectively, which have particularly good electrical conductivity. A two-layer coating consisting of 50 nm MoCu 34 atomic % and 300 nm Cu on top (deposited on a non-conductive glass substrate) has a layer resistance of 2.0 micro-ohm cm. A two-layer coating consisting of 50 nm MoCu 34 atomic % and 300 nm Al on top has a layer resistance of 3.1 micro-ohm cm.

It is assumed that the mechanical properties of the investigated layers can be optimized even further. Therefore, a targeted heat treatment may allow further optimization of the microstructure and internal stress state of the deposited Mo-based layer. It is also very likely that the targeted setting of the deposition conditions can also deliberately influence the layer growth to further increase ductility.

Example 2
Within a series of experiments, various Mo-based metal layers were deposited on polyimide substrates. In this case, layers with different chemical compositions were formed.

The compositions of the Mo-based metal layers are summarized in Table 3.

Table 3 Chemical Composition of Sputtered MoAg Layers

As a reference material for molybdenum-based alloys, pure Mo with a thickness of 50 nm was used in the form of a molybdenum layer.

All layers were deposited at room temperature on 50 μm thick films of polyimide (PI, eg Kapton®). In this case the process parameters were kept constant in order to eliminate as much as possible the influence of different process conditions on the results. The layer thickness was kept constant at 50 nm to avoid geometrical effects on the results.

The substrate surface was completely covered and was not microstructured, for example by etching .

The critical elongations ε _k determined by tensile tests as described in Example 1 are shown in Table 4.

Table 4 Critical elongation ε _k of the Mo and MoAg layers investigated and their difference from the reference consisting of pure Mo. Furthermore, the layer resistance of a 500 nm thick layer on non-conducting borosilicate glass (Corning Eagle XG) is shown.

After the tensile tests described above, the tested layers were examined with an optical microscope and a scanning electron microscope. In this case, the shape of the cracks and the average distance between cracks in the layers were determined.

For example, in layers based on brittle materials such as pure Mo, cracking patterns characteristic of brittle material behavior usually occur when the specimen is damaged under tensile stress. It is characterized by a network of parallel-running linear cracks formed approximately perpendicular to the stress direction. The above crack pattern can be seen, for example, in FIG. 5 (Mo, left). These linear cracks mostly run the full width of the sample from one side to the other, as well as through the full thickness of the layer. Such cracks are also called through cracks (TTC). In the worst case, TTC significantly reduces the electrical conductivity of the layer, since there is no longer a continuous conductive connection in the layer. As is evident in the curves measured on the reference material, the electrical resistance increases very sharply with increasing elongation.

It can be deduced from FIG. 4, which shows the increase in electrical resistance versus initial resistance (R/R ₀ ) with elongation ε.

The critical elongation for the failure criterion R/R ₀ =1.1, which can be deduced from Table 4, is that the critical Ag content in the layer greater than 18 at. It shows that it increases to It is speculated that this increase in ductility is caused by the easy movement of dislocations within the material. As a result, the critical elongation is increased and the occurrence of TTC is reduced. Ag as an additive to Mo is therefore superior, especially in that higher additions greatly increase the ductility of the Mo-based layer.

As an example, FIG. 4 shows resistance curves R/R ₀ for various MoAg samples. As is evident from FIG. 5 (upper right), the crack appearance pattern still corresponds to TTC, but the critical elongation ε _k has already increased significantly.

A further effect that can be observed in addition to the increase in the critical elongation ε _k is that crack initiation can change from brittle material behavior to ductile material behavior. It can be seen that the cracks characteristic of ductile material behavior are no longer straight, but rather zig-zag. Crack bending at the crack tip is a possible explanation for the above crack behavior.

In FIG. 5 (diagram for 44 at. % MoAg) it can be seen that the cracks do indeed run approximately parallel in the case of 44 at. % MoAg, but no longer run straight. Many ductile cracking patterns are already clearly shown in FIG. 5 (MoAg 52 atomic %). Many ductile cracks run through the entire layer thickness, but not necessarily across the entire sample width, so that conductive connections still exist within the material. In this case, as can be seen from FIG. 4, the slope of the R/R ₀ curve is small (the curve does not rise sharply).

From the critical Ag content in the Mo-based layer of 18 atomic %, the critical elongation ε _k is greatly increased and crack initiation is reduced. As the Ag content is further increased, the cracking behavior changes from ductile to brittle.

FIG. 12 shows the X-ray diffractogram of the deposited MoAg layer. Layer deposition and analysis of the crystal structure were performed as for the MoCu system (Fig. 11). Diffractograms of pure Mo or Ag layers are also included for reference . In FIG. 12, as a reference , the position of the X-ray reflection of body-centered cubic ( bcc ) molybdenum (space group Im-3m) is indicated by a vertical dotted line, and face-centered cubic ( fcc ) silver (space group Fm- 3m) reflection positions are shown as vertical dashed lines. Data were obtained from the ICDD (International Diffraction Data Center) database. As shown in FIG. 12, the MoAg system has no corresponding reflected light in the diffractogram and no separate Ag phase up to 44 atomic % silver content. It should therefore be assumed that Ag is forced to dissolve in molybdenum in the form of a solid solution , ie silver atoms occupy the molybdenum space lattice. The silver atoms thus introduce strain into the Mo lattice. The distorted Mo lattice is also indicated by two reflections of Mo(110) and Mo(200), which are due to the larger Ag atoms (atomic radius 165 pm) than Mo atoms (140 pm). , is shifted to lower refraction angles (2θ) compared to the undistorted reference . Only for the 52 atomic % MoAg layer was evidence of (220) silver reflections, indicating the initiation of precipitation of another silver phase in the bcc molybdenum matrix.

Therefore, in the MoCu thin film or MoAg thin film, copper or silver (element X) is forced into solid solution in the bcc molybdenum lattice. The crystal structure of pure gold (Au) is the same as that of Cu and Ag (space group Fm-3m) . All three elements belong to the same subfamily (11) of the periodic system of chemical elements and exhibit similar chemical and physical behavior in many aspects. Therefore, it is assumed that sputtered MoAu thin films with Au content of 40 at.% or less also exist in the form of a solid solution in which the gold atoms are forced dissolved in the bcc molybdenum matrix.

In addition, the last column of Table 4 gives the layer resistance ρ (micro-ohm cm) of various Mo or MoAg thin films (500 nm layer thickness on an insulating glass substrate). For the measurements, the surface resistivity Rs (ohms/sheet) was measured by the four-point method and multiplied by the layer thickness. The layer resistance of the MoAg layer increases up to an Ag content of 31 atomic % and then decreases again with increasing Ag content. All MoAg layers have layer resistances below 150 micro-ohm cm.

In the case of multilayers of MoAg/Cu or MoAg/Al, the layer resistance along long conductor tracks is primarily determined by the well-conducting Cu or Al , respectively . A bilayer film of 50 nm MoAg 31 atomic % and 300 nm Cu formed thereon (deposited on a non-conductive glass substrate) has a layer resistance of 2.0 micro-ohm cm. A two-layer film of 50 nm MoAg 31 atomic % and 300 nm Al deposited thereon has a layer resistance of 3.1 micro-ohm cm.

One or more metal layers as defined in claim 2 and one of its dependent claims can be part of a thin film transistor (TFT). FIG. 6 shows a cross section of the layered structure of the insulating thin film component described above. The TFT consists of a semiconductor layer 150, a gate electrode 120, a source electrode 170a and a drain electrode 170b, at least one of these three metal conductive electrode layers consisting of a metal layer according to the invention. The gate electrode 120 and the semiconductor layer 150 are separated by an electrically insulating layer (gate insulator, gate dielectric) 140 . The source electrode 170a and drain electrode 170b are separated by an electrically insulating protective layer 180 . In addition, this protective layer 180 separates the source/drain electrodes 170a/170b from the pixel electrode layer 190 (
(excluding contact holes listed below).

The following describes the general layered structure of a bottom-gate TFT, as shown in one embodiment of FIG. A TFT layered structure is disposed on a flexible substrate 100 . First , on the flexible substrate 100, a substrate is deposited to compensate for irregularities in the top surface of the flexible substrate 100 or to prevent unwanted impurities from entering the semiconductor layer 150 by diffusion or penetration, for example . A buffer layer 110 may be placed over the entire 100 . The buffer layer can consist of one or more layers comprising, for example, silicon oxide or silicon nitride. A gate electrode 120 is disposed on the buffer layer 110 . By applying a voltage, field effects in the semiconductor layer 150 can form a conductive channel electrically connecting the source electrode 170a to the drain electrode 170b. The gate electrode 120 is a metal layer according to the invention or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the prior art. (W), titanium (Ti), chromium (Cr), niobium (Nb), and tantalum (Ta).

An electrically insulating layer (gate dielectric) 140 is disposed over the gate electrode 120 . This electrically insulating layer 140 may comprise, for example, a layer of silicon oxide, silicon nitride, aluminum oxide, or an organic insulating material such as, for example, benzocyclobutene (BCB) or an acrylic-containing material.

The semiconductor layer 150 is adjacent to an electrically insulating layer (gate dielectric) 140 and is composed of, for example, amorphous silicon (a-Si), polysilicon, a metal oxide semiconductor such as indium gallium zinc oxide (IGZO), or an organic semiconductor. can contain. In the case of a semiconductor layer 150a comprising a-Si, an n+ doped semiconductor layer 150b comprising , for example, phosphorous-doped a-Si can be arranged on this layer. In the case of semiconductor layer 150a comprising a metal oxide semiconductor such as IGZO, doped semiconductor layer 150b is generally omitted.

A source electrode layer and a drain electrode layer 170 a and 170 b are arranged over the semiconductor layer 150 . These layers may be metal layers according to the invention or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the prior art. (W), titanium (Ti), chromium (Cr), niobium (Nb), and tantalum (Ta).

A protective layer 180 is disposed over the semiconductor layer 150 and the source/drain electrode layers 170a/170b. This electrically insulating protective layer 180 can comprise a layer of, for example, silicon oxide, silicon nitride, aluminum oxide, or an organic insulating material such as, for example, benzocyclobutene (BCB) or an acrylic-containing material.

A contact hole that electrically connects the adjacent pixel electrode layer 190 and the drain electrode 170b penetrates the protective layer 180 . The pixel electrode layer 190 is electrically conductive, can be formed as a light transmissive layer or a light reflective layer, and can consist of one or more layers. If the pixel electrode layer 190 is formed as a light-transmissive layer, it may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO). can contain. When the pixel electrode layer 190 is formed as a light-reflecting layer, the layer can be a light-reflecting layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, as well as indium tin oxide ( ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO).

The TFTs described herein can be part of a flexible TFT liquid crystal display screen or an organic EL display screen.

The one or more metal layers defined in claim 2 and one of its dependent claims is for a system on panel (SOP) system in which a TFT active matrix display is arranged on a substrate together with a peripheral electronic control unit. can be a part of The SOP is shown in FIG. The display unit 1 may, for example, be a liquid crystal display (LCD), an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or an electrophoretic display screen (“E-Ink®”, “electronic paper”). can become Display unit 1 represents the actual visible part of the display screen on which the image content is displayed. Some driver and control circuits are located around this area, but they are generally hidden behind a light-tight portion of the housing and are not visible to the user. In principle, one or more of the electronic circuits described below can be placed on the SOP. The description here is not exhaustive and still further circuitry is required for control depending on the display used.

In order to control the display unit 1, horizontal data driver circuits (column drivers) 2a/b can be arranged on the substrate, which circuits connect to the source/drain electrodes 170a of the TFTs via data lines (not shown). /b (not shown). For control of the gate electrodes 120, a gate driver structure (row driver) 3 can be arranged on the substrate, which is connected to the gate electrodes 120 (not shown) of the TFTs via gate lines (not shown).

Furthermore, in the peripheral area a DC-DC converter 4 can be arranged for converting a low input voltage to a high output voltage, for example a voltage of +3.3V to +5.0V for the control of a TFT-LCD display screen. can be applied to the input, which voltage is converted (“charge pump”) to the high output voltage in the range of −40 V to +40 V required for the control of the liquid crystal display.

Furthermore, an electrical circuit 5 for supplying the reference voltage for the display unit 1 (Vcom, eg +5 V for LCD display screens) can be arranged on the SOP.

Furthermore, a timing control circuit (TCon) 6, a digital-analog conversion circuit 7, a discharge section 8, and a Vcom buffer circuit 9 can be arranged on the substrate.

The SOP is connected via a contact area 10 to the display screen control electronics or the rest of the graphics card. The peripheral circuits 2-9 are interconnected with the display unit 1 and the contact areas (“contact pads”) 10 using metal layers (not shown) according to the invention.

As an example, contacting the display unit 1 is shown in FIG. The row driver 3 is connected to the display unit 1 via electrical conductor tracks 20 and the column driver 2b is connected to the display unit 1 via electrical conductor tracks 21 . One or both conductor tracks 20 or 21 can consist of a metal layer according to the invention as defined in claim 2 and one of its dependent claims.

FIG. 9 shows contact between thin film transistors (TFTs) and gate lines and data lines. The gate conductor 20 has an extension in the TFT area that forms the gate electrode 120 of the TFT. In the region of the TFT, the data conductor 21 has an extension forming the source electrode 170a of the TFT and a region separated by said source electrode forming the drain electrode 170b of the TFT and connected to the pixel electrode 190. , have One or both conductor tracks 20 or 21 and/or TFT electrodes 120, 170a/b can consist of a metal layer according to the invention as defined in claim 2 and one of its dependent claims.

Furthermore, the one or more metal layers as defined in claim 2 and one of its dependent claims, the layered structure of which is part of a low temperature polysilicon (LTPS) thin film transistor (TFT), for example shown in FIG. can be Compared to the TFT structure of FIG. 6, in this case the top-gate TFT, ie the gate electrode 240 is located above the semiconductor layer 220 instead of below it. The LTPS-TFT is preferably configured as a top-gate TFT. LTPS semiconductors have significantly higher charge carrier mobilities (50 cm ² /Vs to 200 cm 2 /Vs) compared to amorphous silicon (0.5 cm ^{2 /} Vs to 1.5 cm ² /Vs). Therefore, the above TFTs can be used, for example, to control current-driven display devices such as OLEDs or micro-LEDs.

In the following, the layered structure of a top-gate LTPS TFT is described as an example. LTPS-TFTs are arranged on a flexible substrate 200 . First, to compensate for irregularities on the flexible substrate 200 or into the semiconductor layer 220 or into the doped semiconductor regions 221 (source electrode) and 222 (drain electrode), e.g. A buffer layer 210 that covers the entire substrate 200 can be placed on the flexible substrate 200 to prevent unwanted impurities from entering through permeation. Buffer layer 210 can be composed of one or more layers including, for example, silicon oxide, silicon nitride, or silicon oxynitride. Depending on the composition of the substrate, the buffer layer can also be omitted.

A semiconductor layer 220 , which may be composed of undoped polycrystalline silicon, is disposed over the buffer layer 210 . Adjacent to this layer 220 (also called the "channel region") is a source electrode 221 on one side and a drain electrode 222 on the other side. Each of these electrodes can consist of doped polysilicon. Doping can be done, for example, by ion implantation, and p-doping can be done, for example, by using boron (B) or B ₂ H ₆ . Depending on the TFT embodiment, the doping type (p or n) and/or dopant type may of course vary.

A gate insulator layer 230 is disposed over the semiconductor layers 220 , 221 and 222 . This gate insulator layer 230 may comprise, for example, silicon nitride or silicon oxide. Gate electrode 240 is disposed on gate insulator layer 230 such that the gate electrode has an overlap region (vertically) that is at least the channel region (semiconductor layer 220). Gate electrode 240 is a metal layer according to the present invention or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten corresponding to the prior art. (W), titanium (Ti), chromium (Cr), niobium (Nb), and tantalum (Ta). The gate electrode 240 is connected via gate lines (not shown) to control electronics (not shown), in particular row drivers.

Overlying the gate electrode 240 or the gate insulator layer 230 is an insulating layer 250 which can consist of the same material as the gate insulator layer 230, for example silicon nitride or silicon oxide. The insulating layer 250 and the gate insulator layer 230 are provided with through holes (“through holes”) that allow the source and drain electrodes 221/222 to be (electrically) accessible to the semiconductor layers.

A control and/or source contact electrode layer 260 and/or a control and/or contact drain electrode layer 270 are disposed on the insulating layer 250 and connected to the semiconductor source/drain electrodes 221/222 through the through holes described above. It is The control and/or source/drain electrode layers 260/270 may be metal layers according to the invention or at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt) corresponding to the prior art. ), Molybdenum (Mo), Tungsten (W), Titanium (Ti), Chromium (Cr), Niobium (Nb), Tantalum ( Ta). The control and/or contact source electrode layer 260 is connected via data lines (signal lines; not shown) to control electronics, in particular column drivers (not shown).

A thin film transistor is formed from a semiconductor layer 220, a gate electrode 240, control and/or contact source/drain electrode layers 260/270. However, the TFT configuration is not limited to the exemplary embodiments described above, but rather can have many other configurations that can be readily implemented by those skilled in the art.

A planarization layer 280 may also be disposed over the TFT structure, particularly if a further light-emitting layer, eg, an OLED layer (not shown) is disposed over the TFT. The planarizing layer 280 can include, for example, polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). The planarization layer 280 is provided with through holes to allow access to the control and/or contact drain electrode layer 270 regions.

FIG. 10 also shows, by way of example, a pixel electrode layer 290 formed on the planarization layer 280 and in conductive connection with the control and/or contact drain electrode layer 270 through through holes. It is In the case of an LTPS-OLED display screen, the pixel electrode layer 290 forms the first electrode of the light emitting structure (generally the anode in upward emitting structures). If the pixel electrode layer 290 is formed as a light-transmissive layer, it may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO). can contain.

When the pixel electrode layer 290 is formed as an optical reflective layer , it can be a reflective layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, as well as indium tin oxide (ITO ), indium zinc oxide (IZO), zinc oxide (ZnO) or aluminum zinc oxide (AZO).

It is assumed that the mechanical properties of the investigated layers can be optimized even further. Thus, a targeted heat treatment could further optimize the microstructure and internal stress state of the deposited molybdenum-based layer. It is also very likely that the targeted setting of deposition conditions can also deliberately influence layer growth to further increase ductility.

R electrical resistance of the layer _R0 electrical resistance at the start of the measurement _R0 surface specific resistance ε maximum elongation ε _k critical elongation Lconst fixed clamp length without elongation ρ layer resistance 1 display device 2a/b data driver circuit (column driver )
3 Gate driver structure (row driver)
4 DC-DC conversion circuit 5 electric circuit 6 timing control circuit (TCon)
7 digital-to-analog conversion circuit 8 discharge section 9 buffer circuit 10 contact area (“contact pad”)
20 electrical conductor track 21 electrical conductor track 100 flexible substrate 110 buffer layer 120 gate electrode 140 insulating layer (gate insulator, gate dielectric)
150 semiconductor layer 170a source electrode 170b drain electrode 180 insulating protective layer 190 pixel electrode layer 200 flexible substrate 210 buffer layer 220 semiconductor layer 221 doped semiconductor region (source electrode)
222 doped semiconductor region (drain electrode)
230 gate insulator layer 240 gate electrode 250 insulating layer 260 control and/or contact source electrode layer 270 control and/or contact drain electrode layer 280 planarization layer 290 pixel electrode layer

Claims (20)

In the layer plane of a Mo -based layer disposed directly or via one or more intermediate layers on a flexible substrate (100, 200) subjected to one or more bending, tensile, and/or torsional stresses The use of additives to maintain electrical conductivity, comprising:
The Mo-based layer contains at least 50 wt% Mo,
the additive is Cu, Ag, Au, or a mixture thereof;
Use of an additive, characterized in that the additive is present in the form of a solid solution in the Mo-based layer . a flexible substrate (100, 200);
directly or via one or more intermediate layers on said flexible substrate (100, 200) having on one side and directly adjacent a directly adjacent semiconducting layer or electrically insulating layer at least one layered structure having a metal layer with an electrically insulating layer on the other side;
A flexible coated substrate comprising:
The metal layer is
A single layer structure consisting of a MoX layer, or a two-layer structure consisting of a combination of a MoX layer and a Cu-based layer or a combination of a MoX layer and an Al-based layer, or
A three-layer structure consisting of two MoX layers and a Cu-based layer interposed therebetween or two MoX layers and an Al-based layer interposed therebetween,
is one of
wherein said MoX layer comprises at least 50 wt% Mo,
X is one or more elements selected from the group of Cu, Ag, Au;
A flexible coated substrate , wherein said X is present in the form of a solid solution in said MoX layer . 3. The flexible coated substrate of claim 2, wherein in at least one MoX layer, X is elemental Cu, and the MoCu layer contains more than 0.5 atomic % and less than 50 atomic % Cu. 3. The flexible coated substrate of claim 2, wherein in at least one MoX layer, X is elemental Ag, and the MoAg layer contains more than 10 atomic % and less than 50 atomic % Ag. 3. The flexible coated substrate of claim 2, wherein in at least one MoX layer, X is elemental Au, and the MoAu metal layer contains more than 5 atomic % and less than 20 atomic % Au. A flexible coated substrate according to any one of claims 2 to 5 , wherein each MoX layer has a layer resistance ρ of less than 200 micro-ohm cm. Flexible coated substrate according to any one of claims 2 to 6 , wherein said flexible substrate (100, 200) is formed separately from said electrically insulating layer. Flexible coated substrate according to any one of claims 2 to 6 , wherein the flexible substrate (100, 200) is formed by one of the electrically insulating layers directly adjoining the metal layer. 9. The method according to any one of claims 2 to 8 , wherein at least one of the semiconducting or electrically insulating layers directly adjacent to the metal layer is formed as a plurality of layers (140, 150, 220, 250). A flexible coated substrate as described. A flexible coated substrate according to any one of claims 2 to 9 , wherein the metal layer has a thickness of less than 1 µm. Flexible coated substrate according to any one of claims 2 to 10 , wherein said flexible substrate (100, 200) is transparent. A flexible coated substrate according to any one of claims 2 to 11 , wherein the entire metal layer has a layer resistance ρ of less than 50 micro-ohm cm. The flexible substrate (100, 200) is
a polymer;
thin glass and
metal foil;
a mineral material;
Flexible coated substrate according to any one of claims 2 to 12 , comprising at least one material selected from the group consisting of: Claims 2 to 1, wherein the metal layer has a ratio (R/R0) of an electrical resistance (R) to an electrical resistance (R0) at the start of measurement of less than 1.2 at an elastic elongation (ε) of 2%. 4. The flexible coated substrate according to any one of 3 . Claims 2-, wherein said flexible substrate (100, 200) has at least one conductor track structure and said metal layer is preferably formed to be part of said at least one conductor track structure. 14. The flexible coated substrate according to any one of 14 . The flexible coated substrate according to any one of claims 2-15 , wherein said metal layer is part of a TFT structure. A flexible coated substrate according to any one of claims 2 to 16 , wherein said metal layer is part of an active matrix structure. 18. The flexible coated substrate according to any one of claims 2 to 17 , wherein the flexible coated substrate is a component selected from the group of flexible liquid crystal display screens, flexible organic EL display screens, flexible electrophoretic display screens , flexible thin film batteries. flexible coated substrate. A method of manufacturing a flexible coated substrate, comprising the steps of:
preparing a flexible substrate (100, 200);
covering said flexible substrate (100, 200) by deposition of at least one MoX layer, either directly or via one or more intermediate layers;
including at least
said MoX layer comprises at least 50% by weight Mo;
the MoX layer contains more than 0.5 atomic % of X;
Here, X is one or more elements selected from the group consisting of Cu, Ag, Au,
A method for producing a flexible coated substrate , wherein the X exists in the form of a solid solution in the MoX layer . 20. The method of manufacturing a flexible coated substrate according to claim 19 , wherein said at least one MoX layer is deposited by PVD method.

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